Integrated device based on third-generation semiconductor, and manufacturing method therefor

Abstract

Provided in the present application is an integrated device based on a third-generation semiconductor, and a manufacturing method therefor. The integrated device at least comprises an SiC substrate, a buffer layer, a GaN thin film layer and a piezoelectric material layer, wherein the SiC substrate comprises a first buffer layer stacked on a first SiC substrate and a second buffer layer stacked on a second SiC substrate; the GaN thin film layer at least comprises a first GaN thin film layer stacked on the first buffer layer and a second GaN thin film layer stacked on the second buffer layer; and the first SiC substrate, the first buffer layer, the first GaN thin film layer and the piezoelectric material layer which are stacked are used for forming a multilayer piezoelectric film, and the multilayer piezoelectric film is used for forming an SAW filter. The integrated device prepared by using the technical solution of the present application has a simple structure, greatly reduces the processing cost, can optimize the performance of SAW filters, significantly increases the use frequency of SAWs, and improves the electromechanical coupling coefficients of the SAW filters.

Description

An integrated device based on third-generation semiconductors and a method for manufacturing the same

[0001] This application claims priority to Chinese invention patent application number CN 202311835589.2, filed on December 28, 2023, entitled “An integrated device based on third-generation semiconductors and its manufacturing method”, which is incorporated herein by reference in its entirety. Technical Field

[0002] The present application relates to the technical field of electronic information materials, and in particular to an integrated device based on third-generation semiconductors and a method for manufacturing the same. Background Art

[0003] Surface acoustic wave (SAW) filters are currently the preferred filtering technology for RF applications due to their small size, low price, and simple manufacturing process. However, 5G communications impose high frequency, wide bandwidth, high power, and low loss requirements on filter performance, far exceeding the achievable limits of SAW technology. A major bottleneck is the insufficient electromechanical coupling coefficient and quality factor of commercial piezoelectric materials (lithium tantalate and lithium niobate), which cannot support the high-bandwidth and low-loss communication requirements. Furthermore, increased input power causes heat to accumulate on the chip, potentially damaging the device. Designing new piezoelectric materials to enable SAW technology to scale to 5G is a key technical challenge in the RF field.

[0004] In order to solve the above problems, Japanese researchers Takai et al. first proposed to bond a hundred-nanometer piezoelectric film to a silicon substrate with a higher sound velocity to form a piezoelectric multilayer film (LiTaO3 / SiO2 / AlN / Si), so that the sound waves can be more confined to the substrate surface, greatly improving the electromechanical coupling ability and quality factor of the device, and using the thermal conductivity of silicon to enhance the cooling ability of the device under high input power. However, the silicon substrate is still a conventional semiconductor substrate material, and its limitations in sound velocity and thermal conductivity still cannot meet the device performance requirements of 5G communications. For example, the integrated device manufacturing method and related products disclosed in Chinese invention patent CN111682860A use a buffer layer to reduce the lattice mismatch caused by heteroepitaxial growth of SiC and GaN, but perform wafer bonding for filters, power amplifiers and initial wafers. However, since the patent is mainly used for bulk acoustic wave (BAW) filters, it is necessary to complete the back-side process to obtain a complete integrated device.

[0005] Therefore, in order to realize the application of SAW technology in 5G, it is urgent to develop piezoelectric multilayer films with high electromechanical coupling and promote the integration of filters and other RF devices.

[0006] Summary of the Invention

[0007] In view of this, in order to solve the above problems, the present application provides an integrated device based on third-generation semiconductors and a manufacturing method thereof, which can not only integrate SAW filters and RF devices into one device, but also the introduction of the GAN thin film layer can optimize the device performance.

[0008] To achieve the above objectives, the present application provides an integrated device based on a third-generation semiconductor, the integrated device comprising at least:

[0009] The SiC substrate comprises a first SiC substrate and a second SiC substrate arranged along a specified direction;

[0010] a buffer layer, comprising a first buffer layer stacked on the first SiC substrate and a second buffer layer stacked on the second SiC substrate;

[0011] The GaN thin film layer includes a first GaN thin film layer stacked on the first buffer layer and a second GaN thin film layer stacked on the second buffer layer; the first GaN thin film layer is disposed on the first buffer layer, and the second GaN thin film layer is disposed on the second buffer layer;

[0012] a piezoelectric material layer, stacked on the first GaN thin film layer;

[0013] The stacked first SiC substrate, the first buffer layer, the first GaN thin film layer, and the piezoelectric material layer are used to form a piezoelectric multilayer film, and the piezoelectric multilayer film is used to form a SAW filter.

[0014] Preferably, the piezoelectric material layer is directly grown on the surface of the first GaN thin film layer, or the piezoelectric material layer is bonded to the surface of the first GaN thin film layer.

[0015] Preferably, the thickness of the GaN thin film layer is 50 to 5000 nm.

[0016] Preferably, the thickness of the GaN thin film layer is 200-400 nm.

[0017] More preferably, the thickness of the GaN thin film layer is 400 nm.

[0018] Preferably, the integrated device further includes a functional layer, which is stacked on the first GaN thin film layer; the piezoelectric material layer is stacked on the functional layer; and the piezoelectric multilayer film includes the first SiC substrate, the first buffer layer, the first GaN thin film layer, the functional layer and the piezoelectric material layer, which are stacked.

[0019] Preferably, the piezoelectric material layer is directly grown on the surface of the functional layer, or the piezoelectric material layer is bonded to the surface of the functional layer.

[0020] Preferably, the material of the functional layer includes SiO2, Si3N4, T e Any one or more combinations of O2.

[0021] Preferably, the thickness of the functional layer is 50 to 3000 nm.

[0022] Preferably, the second SiC substrate, the second buffer layer and the second GaN thin film layer that are stacked are used to form a radio frequency device; the thickness of the SiC substrate is 50 to 500 μm.

[0023] Preferably, the radio frequency device is a power amplifier.

[0024] Preferably, the SiC substrate is a wafer-level substrate.

[0025] Preferably, the buffer layer has a thickness of 50 to 2000 nm.

[0026] Preferably, the buffer layer is made of AlN.

[0027] Preferably, the material of the piezoelectric material layer includes any one or more combinations of lithium niobate, lithium tantalate, quartz, lanthanum gallium silicate, potassium niobate, lead magnesium niobate-lead titanate, bismuth germanate, and zinc oxide single crystal.

[0028] Preferably, the piezoelectric material layer has a thickness of 50 to 3000 nm.

[0029] In a preferred embodiment, the piezoelectric single crystal thin film is directly grown on the surface of the GaN thin film layer, or the piezoelectric single crystal thin film is bonded to the surface of the GaN thin film layer.

[0030] Preferably, the SiC substrate has a thickness of 50 to 500 μm.

[0031] Furthermore, the SiC substrate is a wafer-level substrate and includes a c-plane, a-plane or r-plane cut type.

[0032] Compared with existing SAW filters, the technical solution provided in this application fully utilizes the material advantages of third-generation semiconductors. The high sound velocity of SiC will greatly increase the operating frequency of SAW, and through the waveguide effect, SAW will be confined to the surface of the piezoelectric single crystal film, thereby improving the electromechanical coupling coefficient and quality factor of the SAW filter.

[0033] In order to achieve another object, the present application also provides a method for manufacturing the above-mentioned integrated device, specifically comprising the following steps:

[0034] The integrated device includes an integrated device SAW filter, the SAW filter includes a piezoelectric multilayer film, and the manufacturing method includes the following steps:

[0035] Providing a SiC substrate; wherein the SiC substrate includes a first SiC substrate and a second SiC substrate arranged along a specified direction;

[0036] Growing GaN thin film layers on the first SiC substrate and the second SiC substrate; wherein the GaN thin film layers at least include a first GaN thin film layer stacked on the first SiC substrate and a second GaN thin film layer stacked on the second SiC substrate;

[0037] growing a piezoelectric material layer on the first GaN thin film layer;

[0038] The piezoelectric multilayer film includes the first SiC substrate, the first GaN thin film layer and the piezoelectric material layer which are stacked.

[0039] As a preferred embodiment, the manufacturing method of the above integrated device further comprises: directly growing a piezoelectric multilayer film on the first GaN thin film layer.

[0040] As a preferred embodiment, a piezoelectric single crystal film with a damaged layer formed therein is bonded to the GaN thin film layer, and then the piezoelectric single crystal film is dissociated along the damaged layer to obtain a piezoelectric material layer bonded to the GaN thin film layer.

[0041] As a preferred embodiment, at least the portion of the piezoelectric material layer stacked on the second surface area of ​​the GaN thin film layer is removed to expose the second surface area of ​​the GaN thin film layer, while the portion of the piezoelectric material layer stacked on the first surface area of ​​the GaN thin film layer is retained.

[0042] Preferably, a buffer layer, the GaN thin film layer and a functional layer are grown in sequence on the SiC substrate.

[0043] Preferably, the piezoelectric material layer is grown on the functional layer.

[0044] Preferably, under the first setting conditions, a damaged layer is formed in the piezoelectric single crystal thin film by an ion implantation process, wherein the ions used in the ion implantation process include hydrogen ions and / or helium ions; the energy of the ion implantation is 1 to 2000 keV, and the dose is 1×10 16 ~1.5×10 17 cm -2 The first setting conditions include a temperature of 20 to 150 ° C and a vacuum degree of less than 10 -4 Pa, pressure is 70~1000N.

[0045] Preferably, under the second setting condition, the piezoelectric single crystal film is dissociated along the damaged layer through an annealing peeling process; the second setting condition includes an annealing temperature of 300-700° C. and a time of 0.1-5 h.

[0046] Preferably, under the third setting conditions, the piezoelectric single crystal film is grown by magnetron sputtering, wherein the magnetron sputtering source used is a planar target magnetron sputtering source; the third setting conditions include a power of 10 to 1000 W, a temperature of 20 to 700°C, a pressure of 0.5 to 1.2 Pa, and a distance between the target material and the substrate of 60 to 80 mm.

[0047] Preferably, a mask is used to etch at least a portion of the piezoelectric single crystal film until the surface of the second GaN thin film layer is exposed, forming two parts: an etched second region and an unetched first region; the obtained second region can be used to prepare a radio frequency device, and integrated with the SAW filter formed in the unetched first region, which can be completed in one go and does not require a back-side process.

[0048] Preferably, the etching method includes dry etching and / or wet etching.

[0049] The integrated device provided by the above technical solution is applied to SAW filters. The SAW filters can achieve frequencies above 5.8 GHz and an electromechanical coupling coefficient of more than 20%. The introduction of the GaN thin film layer can effectively suppress parasitic modes, especially when the thickness is 200 to 400 nm. A burr-free admittance response can be obtained, which is suitable for the requirements of 5G large bandwidth and low loss filtering. It is expected to be applicable to 5G communication frequency bands such as n77 and n78 and / or to sub-6G frequency bands.

[0050] The beneficial technical effects achieved by this application are as follows:

[0051] 1. Compared with existing SAW filters, the technical solution provided in this application fully utilizes the material advantages of third-generation semiconductors. The high sound velocity of SiC will greatly increase the operating frequency of SAW, and the surface acoustic wave will be confined to the surface of the piezoelectric single crystal film through the waveguide effect, which can improve the electromechanical coupling coefficient and quality factor of the SAW filter; in addition, the GaN thin film layer epitaxially grown on the SiC substrate is conducive to the integration of SAW filters and RF devices on the same wafer through planar technology, thereby improving the preparation process of integrated devices.

[0052] 2. The piezoelectric multilayer film prepared using the technical solution of this application has a simple structure, and the preparation method can be combined with the semiconductor processing technology in the existing technology. The materials are simple, which greatly reduces the processing cost, and can obtain piezoelectric materials with a high electromechanical coupling coefficient. It can be directly applied to surface acoustic wave devices and is suitable for the requirements of 5G large-bandwidth filtering.

[0053] 3. The piezoelectric multilayer film provided by this application, the GaN thin film layer introduced in this structure can regulate and optimize the performance of the SAW filter, especially in terms of parasitic mode suppression. Compared with the Bulk Acoustic Wave (BAW) technology, the technical solution of this application does not require a back-side manufacturing process, and the LN used in the SAW technology has a higher electromechanical coupling coefficient than the AlN used in BAW, which is more suitable for the needs of 5G large-bandwidth filtering.

[0054] 4. The present application directly epitaxially grows a GaN thin film layer after growing a buffer layer on the surface of the SiC substrate. The technical solution is simple, reduces the number of layers in the material structure, and also reduces the thickness of the overall piezoelectric multilayer film.

[0055] 5. The technical solution of this application combines the use of integrated technology with ion implantation-bonding-annealing peeling process, does not require back-side processing, and can obtain a piezoelectric single crystal film with a thickness of less than 300nm by thinning the thickness of the piezoelectric single crystal film on one side. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] FIG1 is a schematic structural diagram of an integrated device based on third-generation semiconductors in Example 1 of the present application.

[0057] FIG2 is an admittance curve of the SAW filter in Example 1 of the present application.

[0058] FIG3 is a schematic structural diagram of an integrated device based on third-generation semiconductors in Example 2 of the present application.

[0059] FIG4 is a process flow chart for preparing a piezoelectric material layer in Example 2 of the present application.

[0060] FIG5 is the admittance curves of the SAW filters in Examples 2-9 and Comparative Example 1 of the present application.

[0061] FIG6 is an admittance curve of the SAW filter in Comparative Example 2-9 of the present application.

[0062] The symbols in the figure are: 10-SAW filter; 11-first SiC substrate; 12-first buffer layer; 13-first GaN thin film layer; 14-functional layer; 15-piezoelectric material layer; 16-damaged layer; 17-peeling layer; 20-RF device; 21-second SiC substrate; 22-second buffer layer; 23-second GaN thin film layer. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0064] The present application provides an integrated device based on a third-generation semiconductor. The integrated device includes two functional areas, a first area and a second area, and can integrate devices with two different functions.

[0065] In some preferred embodiments, the integrated device includes a SAW filter and a power amplifier.

[0066] The integrated device at least includes a SiC substrate, a buffer layer, a GaN thin film layer and a piezoelectric material layer.

[0067] The SiC substrate includes a first SiC substrate and a second SiC substrate arranged along a specified direction; the first SiC substrate and the second SiC substrate are placed parallel to or side by side along the specified direction, or a whole substrate material of a suitable size is selected to divide two areas, respectively serving as the first SiC substrate and the second SiC substrate.

[0068] Preferably, the thickness of the SiC substrate is 50-500 μm, and the SiC substrate may be a wafer-level substrate, that is, the SiC material in the SiC substrate is a wafer-level material, including any one of c-plane, a-plane, r-plane or special cuts.

[0069] The buffer layer includes a first buffer layer stacked on the first SiC substrate and a second buffer layer stacked on the second SiC substrate; specifically, the buffer layer has a thickness of 50 to 2000 nm, and the material of the buffer layer includes AlN.

[0070] The GaN thin film layer includes a first GaN thin film layer stacked on the first buffer layer and a second GaN thin film layer stacked on the second buffer layer; specifically, the GaN thin film layer has a wafer-level size.

[0071] The piezoelectric material layer is stacked on the first GaN thin film layer.

[0072] Specifically, the material of the piezoelectric material layer includes any one or more combinations of lithium niobate, lithium tantalate, quartz, lanthanum gallium silicate, potassium niobate, lead magnesium niobate-lead titanate, bismuth germanate, and zinc oxide single crystal; the thickness of the piezoelectric material layer is 50 to 3000 nm; and the piezoelectric material layer has a wafer-level size.

[0073] Furthermore, the SAW filter includes a piezoelectric multilayer film, which includes a first SiC substrate, a first buffer layer, a first GaN thin film layer and a piezoelectric material layer that are stacked together, that is, the piezoelectric multilayer film has a first SiC substrate, a first buffer layer, a first GaN thin film layer and a piezoelectric material layer from bottom to top; the area where the SAW filter is located is recorded as the first area.

[0074] The stacked second SiC substrate, second buffer layer and second GaN thin film layer are used to form a radio frequency device, that is, the radio frequency device has a second SiC substrate, a second buffer layer and a second GaN thin film layer from bottom to top; the area where the radio frequency device is located is recorded as the second area; the radio frequency device can be a power amplifier.

[0075] In some preferred embodiments, the integrated device further includes a functional layer, which is stacked on the first GaN thin film layer; and the piezoelectric material layer is stacked on the functional layer.

[0076] Specifically, the materials of the functional layer include SiO2, Si3N4, T e Any one or more combinations of O2; the thickness of the functional layer is 50 to 3000 nm.

[0077] In some preferred embodiments, the piezoelectric material layer is directly grown on the surface of the first GaN thin film layer; or, the piezoelectric material layer is directly grown on the surface of the functional layer.

[0078] Furthermore, the piezoelectric material layer is a piezoelectric single crystal thin film, which can be directly grown on the functional layer or the GaN thin film layer by magnetron sputtering. The growth conditions include: the magnetron sputtering source is a planar target magnetron sputtering source; the power is 10 to 1000 W; the temperature is 20 to 700°C; the pressure of the system is 0.5 to 1.2 Pa; and the distance between the target material and the substrate is 60 to 80 mm.

[0079] In some preferred embodiments, the functional layer is grown on the GaN thin film layer, and the thickness of the functional layer is 50 to 2000 nm. The piezoelectric material layer is bonded to the surface of the functional layer, for example, the piezoelectric material layer is bonded to the functional layer via a first bonding layer.

[0080] Alternatively, the piezoelectric material layer is bonded to the surface of the first GaN thin film layer, for example, the piezoelectric material layer is bonded to the first GaN thin film layer via a second bonding layer.

[0081] Furthermore, the piezoelectric material layer is a piezoelectric single crystal thin film. After the piezoelectric single crystal thin film is grown on the functional layer, a photoresist is coated on the piezoelectric material layer. The photoresist is exposed and developed using a mask. The remaining area between the piezoelectric single crystal thin film and the functional layer (referred to as the etched area) is then etched to expose the GaN thin film layer, while the remaining area is protected by the photoresist. Specifically, the remaining area is used to prepare a SAW filter, while the etched area is used to prepare a radio frequency device, thereby integrating the SAW filter and the radio frequency device into a single device.

[0082] Preferably, the etching method includes dry etching or wet etching, such as argon ion etching, reactive ion etching (RIE) or inductively coupled plasma (ICP) etching, etc.

[0083] It can be understood that the bonding of the piezoelectric material layer includes but is not limited to direct bonding or polymer bonding, or any bonding method that can be used in the prior art.

[0084] In some preferred embodiments, the piezoelectric multilayer film is derived from a piezoelectric single crystal thin film via an ion implantation-bonding-annealing debonding process, with the piezoelectric material layer bonded to the surface of the functional layer or GaN thin film layer. The piezoelectric material layer acts as an acoustic-to-electric converter, capable of stimulating one or more of Rayleigh waves, leaky longitudinal waves, and horizontal shear waves, with the specific configuration determined by the subsequent electrode layout and material type.

[0085] Specifically, ion implantation is performed on the process surface of the piezoelectric single crystal film to form a damage layer at a set thickness of the piezoelectric single crystal film body; the process surface of the piezoelectric single crystal film is bonded to the surface of the functional layer or the GaN thin film layer to form a bonding structure; the bonding structure is subjected to an annealing peeling process to dissociate the piezoelectric single crystal film along the damage layer, thereby obtaining a bonding structure that remains bonded to the surface of the functional layer or the GaN thin film layer; and the dissociated surface of the piezoelectric single crystal film is flattened to obtain a piezoelectric material layer.

[0086] In some preferred embodiments, in the above process (i.e., ion implantation-bonding-annealing and stripping), under the first set conditions, a damaged layer is formed in the piezoelectric single crystal thin film by an ion implantation process, the ions used include hydrogen ions and / or helium ions, the implantation energy is 1 to 2000 keV, and the dose is 1×10 16 ~1.5×10 17 cm -2 Preferably, the first setting conditions include a temperature of 20 to 150°C and a vacuum degree of less than 10 -4 Pa, pressure is 70~1000N.

[0087] In some preferred embodiments, under the second set condition, the piezoelectric single crystal film is dissociated along the damaged layer through an annealing peeling process; preferably, the second set condition includes an annealing temperature of 300-700° C. and a time of 0.1-5 h.

[0088] Under the third setting conditions, the piezoelectric single crystal film is grown by magnetron sputtering, wherein the magnetron sputtering source used is a planar target magnetron sputtering source; preferably, the third setting conditions include a power of 10 to 1000 W, a temperature of 20 to 700°C, a pressure of 0.5 to 1.2 Pa, and a distance between the target material and the substrate of 60 to 80 mm.

[0089] In some preferred embodiments, portions of the piezoelectric material layer and the functional layer are etched until the second GaN thin film layer is exposed. This etching results in two functional regions, a first region and a second region, with different stacked structures and functions. This allows the SAW filter and RF device to be integrated into a single device, significantly reducing device size and improving performance while enabling the integration of both RF devices on the same wafer, significantly reducing RF front-end manufacturing costs.

[0090] The technical solution of the present application is described in detail below through specific embodiments.

[0091] Example 1

[0092] The integrated device prepared in this embodiment is shown in Figure 1. The integrated device includes two functional regions, a first region and a second region, having different stacking structures and different functions. The first region is used to prepare a SAW filter 10, and the second region is used to prepare a radio frequency device 20. Preferably, the radio frequency device in this embodiment is a power amplifier.

[0093] The SAW filter 10 sequentially includes a first SiC substrate 11 , a first buffer layer 12 , a first GaN thin film layer 13 , and a piezoelectric material layer 15 . The piezoelectric material layer 15 is grown by magnetron sputtering.

[0094] In this embodiment, the material of the first buffer layer 12 is AlN; and the piezoelectric material layer 15 is a zinc oxide piezoelectric film.

[0095] The method for preparing the above integrated device comprises the following steps:

[0096] (1) The first SiC substrate 11 was ultrasonically cleaned in acetone and alcohol in sequence; cleaned with the first mixed solution at 60°C for 5 minutes; soaked in the second mixed solution for 1 minute, rinsed with deionized water, and placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber.

[0097] The first mixed solution includes HCl, H2O2 and H2O, and the volume ratio of HCl:H2O2:H2O is 5:3:3. The second mixed solution includes hydrofluoric acid:H2O in a volume ratio of 1:10.

[0098] (2) First, hydrogen gas is introduced into the MOCVD reaction chamber, and the first SiC substrate 11 is pretreated at a high temperature to remove adsorbents on the surface of the first SiC substrate 11; then, an AlN thin film is grown on the surface of the first SiC substrate 11 at 950°C to obtain a first buffer layer 12 with a thickness of 60 nm; finally, the temperature in the MOCVD reaction chamber is increased to 1040°C, and a first GaN thin film layer 13 with a thickness of 400 nm is grown on the surface of the first buffer layer 12.

[0099] When growing the first GaN thin film layer 13 , the gallium source is trimethylgallium, the nitrogen source is high-purity ammonia, and the carrier gas is purified hydrogen. By providing the first GaN thin film layer 13 , the lattice mismatch problem can be alleviated.

[0100] (3) A zinc oxide single crystal thin film is grown on the first GaN thin film layer 13 by magnetron sputtering to obtain a piezoelectric material layer 15, thereby obtaining a piezoelectric multilayer film with a thickness of 400 nm. Then, nitrogen is filled into the MOCVD reaction chamber until the pressure in the MOCVD reaction chamber reaches atmospheric pressure, and the chamber is opened to remove the piezoelectric multilayer film.

[0101] The piezoelectric multilayer film obtained through the above steps includes, from top to bottom, a first SiC substrate 11 , a first buffer layer 12 , a first GaN thin film layer 13 and a piezoelectric material layer 15 stacked one on top of the other.

[0102] Furthermore, the process parameters of the magnetron sputtering method include a zinc target power of 100 W, an argon flow rate of 18 sccm, an oxygen flow rate of 12 sccm, a gas pressure of 0.8 Pa, and a deposition thickness of 300 nm.

[0103] (4) Covering the areas not to be etched with a mask, photolithography is performed. After photolithography, the zinc oxide piezoelectric film is etched with hydrochloric acid until the first GaN film layer is exposed. Finally, the photoresist is washed away with acetone.

[0104] A photoresist is applied to the surface of the piezoelectric material layer; the photoresist is exposed and developed using a mask; then, the portion of the piezoelectric material layer and the functional layer that needs to be etched (referred to as the etched area) is etched to expose the first GaN thin film layer, while the remaining area is protected by the photoresist. Specifically, the remaining area is used to form the SAW filter 10, and the etched area is used to form the power amplifier 20, thereby integrating the SAW filter 10 and the power amplifier 20 into a single device.

[0105] Simulation tests of the technical solution employed in this embodiment yielded the admittance curve shown in Figure 2. In the test, the SAW filter's electrode material was Al, with a thickness of 80 nm. The SAW filter's frequency was 4997 MHz, and the electromechanical coupling coefficient was 4.15%. Sputtering zinc oxide piezoelectric thin films is relatively inexpensive, significantly reducing production costs and making them applicable even in scenarios where high-bandwidth communications are not required.

[0106] In addition, by using the above steps, the SAW filter prepared in the first area and the RF device (the power amplifier 20 in this embodiment) prepared in the second area are integrated into one device, which greatly reduces the size of the device and improves the performance. The integration of two RF devices on the same wafer can significantly reduce the manufacturing cost of the RF front-end process.

[0107] Example 2

[0108] Referring to Figure 3 , the integrated device fabricated in this embodiment includes an integrated device structure integrating a SAW filter 10 and a radio frequency device 20. The SAW filter 10 fabricated in the first region includes a stacked first SiC substrate 11, a first buffer layer 12, a first GaN thin film layer 13, a functional layer 14, and a piezoelectric material layer 15 (transferred by ion implantation and annealing). The power amplifier 20 fabricated in the second region includes a stacked second SiC substrate 21, a second buffer layer 22, and a second GaN thin film layer 23.

[0109] The piezoelectric material layer 15 of this embodiment is transferred by ion implantation-bonding-annealing peeling process. Specifically, the preparation method of the integrated device includes the following steps:

[0110] (1) The first SiC substrate 11 was ultrasonically cleaned in acetone and alcohol in sequence; cleaned with the first mixed solution at 60°C for 5 minutes; soaked in the second mixed solution for 1 minute, rinsed with deionized water, and placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber.

[0111] The first mixed solution includes HCl, H2O2 and H2O, and the volume ratio of HCl:H2O2:H2O is 5:3:3. The second mixed solution includes hydrofluoric acid:H2O in a volume ratio of 1:10.

[0112] (2) First, hydrogen gas is introduced into the MOCVD reaction chamber, and the first SiC substrate 11 is pretreated at high temperature to remove adsorbents on the surface of the first SiC substrate 11; then, an AlN thin film is grown on the surface of the first SiC substrate 11 at 950°C to obtain a second buffer layer 12 with a thickness of 60 nm; finally, the temperature in the MOCVD reaction chamber is increased to 1040°C, and a GaN thin film layer 13 with a thickness of 400 nm is grown on the surface of the first buffer layer 12.

[0113] When growing the GaN thin film layer 13 , the gallium source is trimethylgallium, the nitrogen source is high-purity ammonia, and the carrier gas is purified hydrogen. By providing the GaN thin film layer 13 , the lattice mismatch problem can be alleviated.

[0114] (3) The wafer on which the GaN thin film layer 13 has been grown is placed in a magnetron sputtering chamber, and SiO 2 is grown on the surface of the GaN thin film layer 13 as the functional layer 14 .

[0115] The thickness of the functional layer 14 is 400 nm. The RF sputtering mode is selected for the growth of the functional layer 14. The power is set to 1000 W, the argon flow rate is set to 18 mL / min, the oxygen flow rate is 12 mL / min, the gas pressure is stabilized at 0.5 Pa, and the deposition is 150 nm.

[0116] (4) In order to obtain a piezoelectric multilayer film of precise thickness, an ion implantation-bonding-annealing peeling process is used to take a four-inch X-40°Y tangential LiNbO3 piezoelectric single crystal film and implant ions from its process surface, thereby forming a damaged layer 16 with a thickness of approximately 500 nm in the piezoelectric single crystal film.

[0117] The ion type is hydrogen ion and / or helium ion, the implantation energy is 75keV, and the dose is 9×10 16 cm -2 , the temperature is 25℃.

[0118] (5) Bonding the processed surface of the injected piezoelectric single crystal film to the GaN / SiC wafer on which SiO2 is grown to obtain a multilayer structure.

[0119] The bonding process follows the following conditions: vacuum degree is 8.0×10 -5 Pa, pressure is 800N.

[0120] (6) The multilayer structure obtained in step (5) is then placed in an annealing furnace for annealing, so that the piezoelectric single crystal film is separated from the piezoelectric single crystal film along the damaged layer 16.

[0121] The annealing temperature used was 200°C and the time was 3 h.

[0122] In one embodiment, referring to FIG4 , FIG4 is a schematic diagram of a process for preparing a piezoelectric multilayer through ion implantation-bonding-annealing and peeling processes in steps (4)-(6), which sequentially includes the piezoelectric single crystal film undergoing ion implantation ( FIG4 (a) )-bonding ( FIG4 (b) )-annealing and peeling ( FIG4 (c) ) to finally obtain a piezoelectric multilayer film.

[0123] Specifically, Figure 4(a) is a schematic diagram of the structure corresponding to the ion implantation process in step (4), in which ions are implanted along the process surface of the piezoelectric single crystal film to form a damaged layer 16, and the piezoelectric single crystal film separated by the damaged layer 16 is respectively recorded as a peeling layer 17 and a piezoelectric material layer 15. Figure 4(b) is a schematic diagram of the structure corresponding to the bonding process in step (5), in which the piezoelectric material layer 15 is bonded to the surface of the functional layer 14 to obtain a multilayer structure. Figure 4(c) is a schematic diagram of the structure corresponding to the annealing peeling process in step (6), in which the multilayer structure obtained in step (4) is peeled along the damaged layer 16 to achieve bonding of the piezoelectric material layer 15 to the surface of the functional layer 14.

[0124] (7) The piezoelectric material layer 15 is thinned to 400 nm by chemical mechanical polishing, and the surface of the piezoelectric material layer 15 is made flat to obtain a piezoelectric multilayer film.

[0125] At this point, the obtained piezoelectric multilayer film includes, from top to bottom, the stacked first SiC substrate 11 , the first buffer layer 12 , the GaN thin film layer 13 , the functional layer 14 and the piezoelectric material layer 15 .

[0126] (8) Cover the positions that do not need to be etched with photoresist and perform photolithography. After the photolithography is completed, the piezoelectric material layer 15 and the functional layer 14 are etched by the ICP process until the GaN thin film layer 13 is exposed.

[0127] The etching parameters may be: power of 100 W, SF6 flow rate of 40 sccm, and gas pressure of 1 Pa.

[0128] After the etching process is completed, nitrogen is introduced into the etcher until the pressure reaches atmospheric pressure. The etched wafer is taken out and placed in acetone to remove the adhesive.

[0129] After etching a part of the area in step (8), the second SiC substrate 21, the second buffer layer 22, and the second GaN thin film layer 23 shown in the second area shown in Figure 3 are obtained, which can be used to prepare the power amplifier 20; and the piezoelectric multilayer film in the first area, which includes the first SiC substrate 11, the second buffer layer 12, the second GaN thin film layer 13, the functional layer 14 and the piezoelectric material layer 15, which can be used to prepare the SAW filter 10.

[0130] The SAW filter 10 and the power amplifier 20 are prepared through the above steps, and the two different devices are integrated into an integrated structure. That is, the above process can be used to integrate the SAW filter and the RF device into one device, which greatly reduces the size of the device and improves the performance. The integration of two RF devices on the same wafer can greatly reduce the manufacturing cost of the front-end process of the RF device.

[0131] By conducting simulation tests on the technical solution adopted in this embodiment, the admittance curve shown in Figure 5 can be obtained; in the test, the electrode material of the SAW filter is Al, and the thickness is 80nm; after testing, it is found that the frequency of the SAW filter is approximately 5.8GHz, and the electromechanical coupling coefficient is greater than 20%, which is greater than the electromechanical coupling coefficient of the SAW filter prepared according to Example 1, indicating that in this embodiment, when the thickness of the GaN thin film layer is 400nm, the parasitic mode can be effectively suppressed to obtain a glitch-free response, which is suitable for the requirements of 5G large bandwidth and low loss filtering, and meets the application requirements of 5G communication frequency bands such as n77, n78 and / or sub-6G frequency bands.

[0132] Example 3

[0133] Example 3 is similar to Example 2, with the only difference being that the thickness of the GaN thin film layer in step (2) is 100 nm. Other details are the same and will not be described again.

[0134] Example 4

[0135] Example 4 is similar to Example 2, with the only difference being that the thickness of the GaN thin film layer in step (2) is 200 nm. Other details are the same and will not be described again.

[0136] Example 5

[0137] Example 5 is similar to Example 2, with the only difference being that the thickness of the GaN thin film layer in step (2) is 300 nm. Other details are the same and will not be described again.

[0138] Example 6

[0139] Example 6 is similar to Example 2, with the only difference being that the thickness of the GaN thin film layer in step (2) is 500 nm. The rest are the same and will not be described again.

[0140] Example 7

[0141] Example 7 is similar to Example 2, with the only difference being that the thickness of the GaN thin film layer in step (2) is 600 nm. The rest are the same and will not be described again.

[0142] Example 8

[0143] Example 8 is similar to Example 2, with the only difference being that the thickness of the GaN thin film layer in step (2) is 700 nm. The rest are the same and will not be described again here.

[0144] Example 9

[0145] Example 9 is similar to Example 2, with the only difference being that the thickness of the GaN thin film layer in step (2) is 800 nm. Other details are the same and will not be described again.

[0146] Comparative Example 1

[0147] Comparative Example 1 is similar to Example 2, except that: Comparative Example 1 does not include a GaN thin film layer, that is, in this comparative example, the functional layer 14 is directly grown on the surface of the first buffer layer 12 by sputtering, and the rest are the same.

[0148] Comparative Example 2

[0149] Comparative Example 2 is similar to Example 2, except that the GaN thin film layer is replaced by an AlN thin film layer. Specifically, the piezoelectric multilayer film includes a LiNbO3 layer, a SiO2 buffer layer, an AlN thin film layer, and a SiC substrate stacked from top to bottom, with the AlN thin film layer having a thickness of 100 nm. The remaining preparation processes are the same as those in Example 2 and are not described here. This comparative example is similar to the LiTaO3 / SiO2 / AlN / Si structure reported by T. Takai in the prior art (only the substrate material is different).

[0150] Comparative Example 3

[0151] Comparative Example 3 is similar to Example 2, except that the GaN thin film layer is replaced with an AlN thin film layer. Specifically, the piezoelectric multilayer film includes a LiNbO3 layer, a SiO2 buffer layer, an AlN thin film layer, and a SiC substrate stacked from top to bottom. The AlN thin film layer has a thickness of 200 nm. The remaining preparation processes are the same as those in Example 2 and are not further described here.

[0152] Comparative Example 4

[0153] Comparative Example 4 is similar to Example 2, except that the GaN thin film layer is replaced with an AlN thin film layer. Specifically, the piezoelectric multilayer film includes a LiNbO3 layer, a SiO2 buffer layer, an AlN thin film layer, and a SiC substrate stacked from top to bottom. The AlN thin film layer has a thickness of 300 nm. The remaining preparation processes are the same as those in Example 2 and are not further described here.

[0154] Comparative Example 5

[0155] Comparative Example 5 is similar to Example 2, except that the GaN thin film layer is replaced with an AlN thin film layer. Specifically, the piezoelectric multilayer film includes a LiNbO3 layer, a SiO2 buffer layer, an AlN thin film layer, and a SiC substrate stacked from top to bottom. The AlN thin film layer has a thickness of 400 nm. The remaining preparation processes are the same as those in Example 2 and are not further described here.

[0156] Comparative Example 6

[0157] Comparative Example 6 is similar to Example 2, except that the GaN thin film layer is replaced with an AlN thin film layer. Specifically, the piezoelectric multilayer film includes a LiNbO3 layer, a SiO2 buffer layer, an AlN thin film layer, and a SiC substrate stacked from top to bottom. The AlN thin film layer has a thickness of 500 nm. The remaining preparation processes are the same as those in Example 2 and are not further described here.

[0158] Comparative Example 7

[0159] Comparative Example 7 is similar to Example 2, except that the GaN thin film layer is replaced with an AlN thin film layer. Specifically, the piezoelectric multilayer film includes a LiNbO3 layer, a buffer layer, an AlN thin film layer, and a SiC substrate stacked from top to bottom. The AlN thin film layer has a thickness of 600 nm. The remaining preparation processes are the same as those in Example 2 and are not further described here.

[0160] Comparative Example 8

[0161] Comparative Example 8 is similar to Example 2, except that the GaN thin film layer is replaced with an AlN thin film layer. Specifically, the piezoelectric multilayer film includes a LiNbO3 layer, a SiO2 buffer layer, an AlN thin film layer, and a SiC substrate stacked from top to bottom. The AlN thin film layer has a thickness of 700 nm. The remaining preparation processes are the same as those in Example 2 and are not further described here.

[0162] Performance characterization:

[0163] In order to verify the effectiveness of the technical solution provided in this application, Example 2 is compared with the solution provided in Comparative Example 1. In Example 2, the thickness of the LiNbO3 piezoelectric material layer is 400nm, the thickness of the buffer layer is 60nm, the thickness of the GaN thin film layer is 400nm, and the device structure is X-40°Y LN / SiO2 / GaN / AlN / SiC (piezoelectric material layer-functional layer-GaN thin film layer-buffer layer-SiC substrate); on this basis, the technical solutions adopted in Examples 2-9 are simulated and tested to obtain the admittance curves corresponding to GaN thin film layers of different thicknesses. The electrode material used in the test is Al with a thickness of 80nm. Simulation tests are performed on the GaN thin film layer with a thickness of 0nm (Comparative Example 1), 100nm (Example 3), 200nm (Example 4), 300nm (Example 5), 400nm (Example 2), 500nm (Example 6), 600nm (Example 7), 700nm (Example 8) and 800nm ​​(Example 9), respectively, to obtain the admittance curves shown in Figure 5.

[0164] As can be seen from Figure 5, when the integrated device does not include a GaN thin film layer, the functional layer is grown directly on the AlN buffer layer, that is, the device structure is X-40°Y LN / SiO2 / AlN / SiC (piezoelectric material layer-functional layer-buffer layer-SiC substrate). The main acoustic wave operating mode of the integrated device is leaky longitudinal wave, with a resonant frequency of around 5.8 GHz, and an obvious noise will appear at a frequency of 6.5 GHz. The appearance of noise will reduce the flatness of the SAW filter and lead to increased loss.

[0165] When the thickness of the GaN thin film layer is between 200 and 400 nm, the device admittance is almost free of noise in the frequency range of 5 to 7 GHz. In particular, when the GaN thickness is 400 nm, the device admittance is very clean in the frequency range of 5 to 7 GHz, thus achieving the most effective suppression of parasitic modes.

[0166] Obviously, by adopting the technical solution of the present application, the filter and the power amplifier can be integrated into one device, and after integration, it can be used without the need for back-side processing, which simplifies the manufacturing process; and from Examples 2-9, it can be found that the introduction of the GaN thin film layer can regulate and optimize the intrinsic performance of the SAW.

[0167] Furthermore, the present application also uses an AlN thin film layer instead of a GaN thin film layer, and the device structure obtained is X-40° YLN / SiO2 / AlN / AlN / SiC (piezoelectric material layer-functional layer-buffer layer-AlN thin film layer-SiC substrate). When the AlN thin film layer is located between the AlN buffer layer and the SiC substrate, simulation tests are performed on the AlN thin film layer with thicknesses of 100nm (Comparative Example 2), 200nm (Comparative Example 3), 300nm (Comparative Example 4), 400nm (Comparative Example 5), 500nm (Comparative Example 6), 600nm (Comparative Example 7), and 700nm (Comparative Example 8), respectively, and the admittance curve shown in Figure 6 is obtained.

[0168] As shown in FIG6 , when the thickness of the AlN thin film layer is in the range of 100 to 700 nm, the SAW filter cannot obtain a clean admittance response. The AlN thin film layer cannot achieve the technical effects brought by the GaN thin film layer in Example 2 in terms of suppressing and regulating the propagation law of sound waves and suppressing parasitic modes.

[0169] In summary, in the technical solution of this application, GaN materials play an important role in suppressing and regulating the propagation laws of sound waves and suppressing parasitic modes.

[0170] The above are merely preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. Persons skilled in the art will readily appreciate that the present application may be modified and altered in various ways. Any changes, modifications, substitutions, integrations, or parameter changes to these embodiments, which fall within the spirit and principles of the present application and achieve the same functionality through conventional substitutions, without departing from the principles and spirit of the present application, fall within the scope of protection of the present application.

Claims

1. An integrated device based on third-generation semiconductors, characterized in that, The integrated device at least includes: An SiC substrate, including a first SiC substrate and a second SiC substrate arranged along a specified direction; A buffer layer, including a first buffer layer stacked on the first SiC substrate and a second buffer layer stacked on the second SiC substrate; A GaN thin film layer, including a first GaN thin film layer stacked on the first buffer layer and a second GaN thin film layer stacked on the second buffer layer; the first GaN thin film layer is disposed on the first buffer layer, and the second GaN thin film layer is disposed on the second buffer layer; A functional layer, the functional layer is stacked on the first GaN thin film layer; A piezoelectric material layer, stacked on the functional layer; Wherein, the stacked first SiC substrate, the first buffer layer, the first GaN thin film layer, the functional layer and the piezoelectric material layer are used to form a piezoelectric multi-layer film, and the piezoelectric multi-layer film is used to form a SAW filter; The material of the functional layer includes any one or a combination of SiO2, Si3N4, and TeO2.

2. The integrated device based on the third-generation semiconductor according to claim 1, wherein: The thickness of the GaN thin film layer is 50 - 5000 nm.

3. The integrated device based on third-generation semiconductors according to claim 1, characterized in that: The piezoelectric multi-layer film includes the stacked first SiC substrate, the first buffer layer, the first GaN thin film layer, the functional layer and the piezoelectric material layer.

4. The integrated device based on third-generation semiconductors according to claim 3, characterized in that: The thickness of the functional layer is 50 - 3000 nm.

5. The integrated device based on the third-generation semiconductor according to claim 1, characterized in that: The stacked second SiC substrate, the second buffer layer and the second GaN thin film layer are used to form a radio frequency device; the thickness of the SiC substrate is 50 - 500 μm; The SiC substrate is a wafer-level substrate; The thickness of the buffer layer is 50 - 2000 nm; The material of the buffer layer includes AlN; The material of the piezoelectric material layer includes any one or a combination of lithium niobate, lithium tantalate, quartz, lanthanum gallium silicate, potassium niobate, lead magnesium niobate-lead titanate, bismuth germanate, zinc oxide single crystal; The thickness of the piezoelectric material layer is 50 - 3000 nm.

6. A method for manufacturing an integrated device based on a third-generation semiconductor according to any one of claims 1-5, characterized in that, The integrated device includes an integrated device SAW filter, and the SAW filter includes a piezoelectric multi-layer film; the manufacturing method includes the following steps: Provide an SiC substrate; wherein, the SiC substrate includes a first SiC substrate and a second SiC substrate arranged along a specified direction; Grow a GaN thin film layer on the first SiC substrate and the second SiC substrate; wherein, the GaN thin film layer at least includes a first GaN thin film layer stacked on the first SiC substrate and a second GaN thin film layer stacked on the second SiC substrate; Grow a functional layer on the first GaN thin film layer; Grow a piezoelectric material layer on the functional layer; Wherein, the piezoelectric multi-layer film includes the stacked first SiC substrate, the first GaN thin film layer, the functional layer and the piezoelectric material layer.

7. The manufacturing method of the integrated device according to claim 6, characterized in that, Specifically include: Grow the functional layer on the first GaN thin film layer; Bond a piezoelectric single crystal thin film with an internal damage layer to the functional layer, and dissociate the piezoelectric single crystal thin film along the damage layer to obtain a piezoelectric material layer disposed on the functional layer.

8. The method for manufacturing an integrated device according to claim 6, wherein, Specifically include: A buffer layer, the GaN thin film layer, and the functional layer are sequentially grown on the SiC substrate.

9. The manufacturing method of the integrated device according to any one of claims 6-8, characterized in that, Specifically, it includes: Under the first set of conditions, a damaged layer is formed in the piezoelectric single-crystal thin film through an ion implantation process. The ions used in the ion implantation process include hydrogen ions and / or helium ions, with an implantation energy of 1 to 2000 keV and a dose of 1×10 16 ~1.5×10 17 cm -2 ; the first set of conditions includes a temperature of 20 to 150 °C, a vacuum degree less than 10 -4 Pa, and a pressure of 70 to 1000 N; Under a second set of conditions, the piezoelectric single crystal thin film is dissociated along the damaged layer through an annealing and peeling process, where the second set of conditions includes an annealing temperature of 300 - 700 °C and a time of 0.1 - 5 h; Under a third set of conditions, the piezoelectric material layer is grown by magnetron sputtering, where the magnetron sputtering source is a planar target magnetron sputtering source, and the third set of conditions includes a power of 10 - 1000 W, a temperature of 20 - 700 °C, a pressure of 0.5 - 1.2 Pa, and a distance between the target and the substrate of 60 - 80 mm.

10. The manufacturing method according to claim 8, characterized in that, The manufacturing method further includes: Etching a partial region of the piezoelectric material layer and the functional layer until the second GaN thin film layer is exposed.

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