Laterally diffused metal-oxide-semiconductor device and preparation method therefor

Abstract

The present application relates to a laterally diffused metal-oxide-semiconductor device and a preparation method therefor. The laterally diffused metal-oxide-semiconductor device comprises: a substrate structure 11; a first doped region 111, which is arranged in the substrate structure 11; a first well region 115 and a drain region 113, which are arranged in the first doped region 111 at intervals; a source region 112, which is arranged in the first well region 115; a variable-K dielectric layer 12, which is embedded in the first doped region 111 and is located between the first well region 115 and the drain region 113, wherein in a direction from a front surface of the substrate structure 11 to a back surface of the substrate structure 11, a dielectric constant of the variable-K dielectric layer 12 gradually increases; and a super-junction structure 13, which is arranged in the first doped region 111 on the side of the variable-K dielectric layer 12 that is close to the back surface of the substrate structure 11.

Description

Laterally diffused metal oxide semiconductor device and preparation method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2023118315077, filed on December 27, 2023, entitled “Laterally Diffused Metal Oxide Semiconductor Device and Method for Preparing the Same,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal oxide semiconductor device and a method for preparing the same. Background Art

[0004] With the continuous advancement of semiconductor technology, the application of lateral double-diffuse MOS (LDMOS) devices has become increasingly widespread, placing higher demands on their performance. In related LDMOS technology, trenches are added to the drift region to lengthen the drift region, improving device withstand voltage and reducing device surface area. However, the electric field at the tip of the trench corner is too concentrated, which is detrimental to device performance.

[0005] Summary of the Invention

[0006] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor device and a method for preparing the same to address the above problems.

[0007] In a first aspect, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device, comprising:

[0008] Substrate structure;

[0009] A first doped region is provided in the substrate structure;

[0010] A first well region and a drain region are alternately arranged in the first doped region;

[0011] a source region, disposed in the first well region;

[0012] a variable-K dielectric layer embedded in the first doped region and located between the first well region and the drain region; the dielectric constant of the variable-K dielectric layer gradually increases from the front side of the substrate structure to the back side of the substrate structure;

[0013] The super junction structure is provided in the first doping region on the side of the variable-K dielectric layer close to the back surface of the substrate structure.

[0014] In one embodiment, the variable-K dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the dielectric constant of the first sub-dielectric layer is smaller than the dielectric constant of the second sub-dielectric layer;

[0015] The first sub-dielectric layer is located on a side of the second sub-dielectric layer close to the front surface of the substrate structure.

[0016] In one embodiment, the variable-K dielectric layer further includes a third sub-dielectric layer, the dielectric constant of the third sub-dielectric layer is greater than the dielectric constant of the second sub-dielectric layer; the third sub-dielectric layer is located on a side of the second sub-dielectric layer close to the back side of the substrate structure.

[0017] In one embodiment, the super junction structure is adjacent to the variable-K dielectric layer.

[0018] In one embodiment, the super junction structure includes a first charge balance region and a second charge balance region, wherein the first charge balance region is located between the second charge balance region and the variable-K dielectric layer;

[0019] The doping type of the first charge balance region is opposite to that of the first doping region, and the doping type of the second charge balance region is the same as that of the first doping region.

[0020] In one embodiment, a second doping region is disposed on at least a portion of the periphery of the variable-K dielectric layer, and the doping type of the second doping region is the same as the doping type of the first doping region.

[0021] In one embodiment, the drain region and the source region are spaced apart along a first direction, and the first direction is perpendicular to a thickness direction of the substrate structure; the second doped region is provided at both ends of the variable-K dielectric layer along the first direction.

[0022] In one embodiment, the second doped region is disposed around the outer periphery of the variable-K dielectric layer.

[0023] In one embodiment, the second doped region is adjacent to the variable-K dielectric layer.

[0024] In one embodiment, the variable-K dielectric layer includes a high-K portion and a low-K portion, and the second doped region is disposed on at least a portion of the periphery of the high-K portion.

[0025] In one embodiment, side edges of the super junction structure protrude beyond sidewalls of the variable-K dielectric layer.

[0026] In one embodiment, the second doped region is adjacent to the super junction structure.

[0027] In one embodiment, the variable-K dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the dielectric constant of the first sub-dielectric layer is smaller than the dielectric constant of the second sub-dielectric layer, and the first sub-dielectric layer is located on a side of the second sub-dielectric layer close to the front surface of the substrate structure; the first sub-dielectric layer is the low-K portion, the second sub-dielectric layer is the high-K portion, and the height of the second doped region is not less than the thickness of the second sub-dielectric layer;

[0028] Alternatively, the variable-K dielectric layer includes a first sub-dielectric layer, a second sub-dielectric layer, and a third sub-dielectric layer, the dielectric constant of the first sub-dielectric layer is smaller than the dielectric constant of the second sub-dielectric layer, the first sub-dielectric layer is located on a side of the second sub-dielectric layer close to the front surface of the substrate structure, the dielectric constant of the third sub-dielectric layer is larger than the dielectric constant of the second sub-dielectric layer, and the third sub-dielectric layer is located on a side of the second sub-dielectric layer close to the back surface of the substrate structure; the first sub-dielectric layer is the low-K portion, the third sub-dielectric layer is the high-K portion, and the height of the second doped region is not less than the thickness of the third sub-dielectric layer.

[0029] In one embodiment, the laterally diffused metal oxide semiconductor device further comprises:

[0030] a second well region, disposed in the first doped region and spaced apart from the first well region; and the drain region being disposed in the second well region;

[0031] a body lead region, disposed in the first well region,

[0032] A gate is arranged on the surface of the substrate structure and covers at least a portion of the first well region and a portion of the first doped region.

[0033] In a second aspect, an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device, comprising:

[0034] providing a substrate structure;

[0035] forming a first doped region in the substrate structure, and forming a first well region in the first doped region;

[0036] forming a super junction structure in the first doped region;

[0037] forming a variable-K dielectric layer in the first doped region, wherein the superjunction structure is located on a side of the variable-K dielectric layer close to the back surface of the substrate structure, and the dielectric constant of the variable-K dielectric layer gradually increases from the front surface of the substrate structure to the back surface of the substrate structure;

[0038] A drain region spaced apart from the first well region is formed in the first doped region, and a source region is formed in the first well region, with the variable-K dielectric layer located between the first well region and the drain region.

[0039] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0041] FIG1 is a schematic diagram of a partial structure of a laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0042] FIG2 is a schematic diagram of a partial structure of another laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0043] FIG3 is a schematic flow chart of a method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0044] Description of reference numerals:

[0045] 1. Laterally diffused metal oxide semiconductor device; 11. Substrate structure; 11a. Base; 11b. Buried layer; 11c. Top silicon layer; 111. First doped region; 112. Source region; 113. Drain region; 114. Second doped region; 115. First well region; 116. Second well region; 117. Body lead region; 118. Trench; 12. Variable-K dielectric layer; 121. First sub-dielectric layer; 122. Second sub-dielectric layer; 123. Third sub-dielectric layer; 13. Superjunction structure; 131. First charge balance region; 132. Second charge balance region; 14. Gate; 141. Gate dielectric layer; 142. Gate conductive layer. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0048] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0049] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0050] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] Embodiments of the application are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0052] As described in the background technology, in the related LDMOS technology, trenches are set in the drift region to lengthen the drift region to improve the device's withstand voltage and shorten the device's surface area. However, the electric field peak along the trench surface is low, and the electric field at the tip of the trench corner is too concentrated, which is not conducive to improving device performance.

[0053] In view of the above problems, the embodiments of the present application provide a laterally diffused metal oxide semiconductor device and a method for fabricating the same, which comprises disposing a variable-K dielectric layer and a superjunction structure at the bottom of the variable-K dielectric layer within a first doped region. This allows, on the one hand, an electric field peak to be introduced at the sidewalls of the variable-K dielectric layer, thereby increasing the average field in the withstand voltage region and weakening the electric field concentrated at the corners of the variable-K dielectric layer, that is, weakening the electric field concentrated at the corners of the trench, thereby improving the withstand voltage of the device without increasing the on-resistance of the device. On the other hand, the use of a low-K dielectric on the device surface can increase the surface withstand voltage capability of the device, while the use of a high-K dielectric within the device body can assist in depleting the charge within the device body. Furthermore, by introducing a superjunction structure, in the off state, the superjunction structure and the drift region mutually deplete each other, thereby optimizing the electric field and increasing the doping concentration of the drift region, thereby reducing the on-resistance in the on state.

[0054] In a first aspect, as shown in FIG1 and FIG2 , an embodiment of the present application provides a LDMOS device 1. Taking an N-type LDMOS device 1 as an example, the LDMOS device 1 has a first doping type of P-type and a second doping type of N-type. In other embodiments, the LDMOS device 1 may also be a P-type LDMOS device 1, with the first doping type of N-type and the second doping type of P-type.

[0055] Specifically, the laterally diffused metal oxide semiconductor device 1 includes: a substrate structure 11, a first doped region 111, a source region 112, a drain region 113, a first well region 115, a variable-K dielectric layer 12, and a superjunction structure 13. The first doped region 111 is disposed within the substrate structure 11; the first well region 115 and the drain region 113 are alternately arranged within the first doped region 111, and the source region 112 is disposed within the first well region 115; the variable-K dielectric layer 12 is embedded within the first doped region 111 and located between the first well region 115 and the drain region 113; the dielectric constant of the variable-K dielectric layer 12 gradually increases from the front side of the substrate structure 11 to the back side of the substrate structure 11; and the superjunction structure 13 is disposed within the first doped region 111 on the side of the variable-K dielectric layer 12 near the back side of the substrate structure 11, that is, the superjunction structure 13 is disposed within the first doped region 111 at the bottom of the variable-K dielectric layer 12.

[0056] It is understood that a trench 118 is provided in the first doped region 111 and the variable-K dielectric layer 12 is provided in the trench 118. The trench 118 is located between the source region 112 and the drain region 113 and opens from the surface of the first doped region 111 and extends along the thickness direction of the substrate structure 11.

[0057] In one embodiment, the substrate structure 11 includes a stacked base 11a, a buried layer 11b, and a top silicon layer 11c. For example, the base 11a and the top silicon layer 11c may be made of single crystal silicon, polycrystalline silicon, amorphous silicon, a silicon germanium compound, or low-temperature polysilicon (LTPS), or other materials known to those skilled in the art. The buried layer 11b may be made of silicon oxide, silicon nitride, silicon oxyfluoride, or a dielectric material having a dielectric constant lower than that of silicon oxide.

[0058] In the embodiment of the present application, the substrate 11 a , the top silicon layer 11 c and the first well region 115 are of the first doping type, and the first doping region 111 , the source region 112 and the drain region 113 are of the second doping type.

[0059] The laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application comprises a variable-K dielectric layer 12 and a superjunction structure 13 located at the bottom of the variable-K dielectric layer 12 disposed within the first doped region 111. This allows, on the one hand, an electric field peak to be introduced on the sidewalls of the variable-K dielectric layer 12 (or trench 118), thereby increasing the average field in the withstand voltage region and weakening the concentrated electric field at the corners of the variable-K dielectric layer 12, that is, weakening the concentrated electric field at the corners of the trench 118, thereby improving the withstand voltage of the device without increasing the on-resistance of the device. Furthermore, the use of a low-K dielectric on the device surface can increase the withstand voltage capability of the device surface, while the use of a high-K dielectric within the device body can assist in depleting charge within the device body. Furthermore, by introducing the superjunction structure 13, in the off state, the superjunction structure 13 and the drift region mutually deplete each other, thereby optimizing the electric field and increasing the doping concentration of the drift region, thereby reducing the on-resistance in the on state.

[0060] In one embodiment, as shown in FIG1 , the variable-K dielectric layer 12 includes a first sub-dielectric layer 121 and a second sub-dielectric layer 122. The dielectric constant of the first sub-dielectric layer 121 is smaller than that of the second sub-dielectric layer 122. The first sub-dielectric layer 121 is located on a side of the second sub-dielectric layer 122 that is closer to the front surface of the substrate structure 11. That is, the first sub-dielectric layer 121 is located on a side of the second sub-dielectric layer 122 that is closer to the opening of the trench 118. Thus, by forming the variable-K dielectric layer 12 using two sub-dielectric layers with different dielectric constants, the difficulty of manufacturing the variable-K dielectric layer 12 can be reduced.

[0061] In the embodiment of the present application, by providing the first sub-dielectric layer 121 and the second sub-dielectric layer 122, it can be seen from the continuity of the electric flux that additional electric field peaks will be formed on the side walls of the trench 118, which can increase the average field in the voltage-resistant area and weaken the electric field concentrated at the corners of the trench 118, thereby further improving the device voltage resistance without increasing the device on-resistance.

[0062] In one embodiment, as shown in FIG2 , the variable-K dielectric layer 12 further includes a third sub-dielectric layer 123. The dielectric constant of the third sub-dielectric layer 123 is greater than the dielectric constant of the second sub-dielectric layer 122. The third sub-dielectric layer 123 is located on the side of the second sub-dielectric layer 122 that is closer to the back surface of the substrate structure 11. That is, the third sub-dielectric layer 123 is located on the side of the second sub-dielectric layer 122 that is away from the opening of the trench 118. Thus, by forming the variable-K dielectric layer 12 using three sub-dielectric layers with different dielectric constants, the difficulty of manufacturing the variable-K dielectric layer 12 can be reduced.

[0063] In the embodiment of the present application, by providing the first sub-dielectric layer 121, the second sub-dielectric layer 122 and the third sub-dielectric layer 123, it can be seen from the continuity of the electric flux that two additional electric field peaks are formed on the sidewalls of the trench 118, which can effectively increase the average field in the voltage-resistant area and weaken the electric field concentrated at the corners of the trench 118, thereby further improving the device voltage resistance without increasing the device on-resistance.

[0064] In one embodiment, the second sub-dielectric layer 122 is an oxide dielectric layer. Exemplarily, the second sub-dielectric layer 122 is made of silicon oxide. Thus, using the dielectric constant of the oxide dielectric layer as a reference, a sub-dielectric layer with a greater dielectric constant than the oxide dielectric layer is a high-K dielectric layer, which is disposed at the bottom of the second sub-dielectric layer 122. A sub-dielectric layer with a smaller dielectric constant than the oxide dielectric layer is a low-K dielectric layer, which is disposed on top of the second sub-dielectric layer 122.

[0065] In one embodiment, as shown in FIG1 , when the variable-K dielectric layer 12 includes only a first sub-dielectric layer 121 and a second sub-dielectric layer 122 , the first sub-dielectric layer 121 may be made of silicon oxide, and the second sub-dielectric layer 122 may be made of a material having a dielectric constant greater than that of silicon oxide.

[0066] In one embodiment, the super junction structure 13 is adjacent to the variable-K dielectric layer 12 , that is, the super junction structure 13 is adjacent to the trench 118 , which is beneficial for reducing the electric field peak at the corner of the trench 118 .

[0067] It should be noted that the super junction structure 13 and the variable-K dielectric layer 12 may not be adjacent to each other, that is, the super junction structure 13 and the trench 118 are separated by a small distance. For example, the distance between the super junction structure 13 and the trench 118 is no more than 0.5 μm.

[0068] In one embodiment, the super junction structure 13 includes a first charge balance region 131 and a second charge balance region 132. The first charge balance region 131 is located between the second charge balance region 132 and the trench 118. The doping type of the first charge balance region 131 is opposite to the doping type of the first doping region 111, and the doping type of the second charge balance region 132 is the same as the doping type of the first doping region 111. That is, the first charge balance region 131 is of the first doping type, and the second charge balance region 132 is of the second doping type.

[0069] In this way, on the one hand, the first charge balance region 131 of the first doping type can reduce the electric field peak at the corner of the trench 118; on the other hand, the second charge balance region 132 of the second doping type can be closer to the bottom of the trench 118, which is beneficial to reducing the on-resistance.

[0070] It is understood that, in another embodiment, the doping type of the first charge balancing region 131 may be the same as the doping type of the first doping region 111, and the doping type of the second charge balancing region 132 may be different from the doping type of the first doping region 111. The embodiment of the present application does not limit the doping type of the first charge balancing region 131 and the second charge balancing region 132.

[0071] It is understood that the first charge balance region 131 and the second charge balance region 132 may be adjacent to each other or spaced apart. If the first charge balance region 131 and the second charge balance region 132 are spaced apart, the distance between them may be less than or equal to 0.5 μm.

[0072] In one embodiment, as shown in Figures 1 and 2, a second doped region 114 is provided on at least a portion of the outer periphery of the variable-K dielectric layer 12, that is, the second doped region 114 is provided on at least a portion of the outer periphery of the trench 118. Here, at least a portion of the outer periphery of the variable-K dielectric layer 12 refers to at least a portion of the outer periphery of the variable-K dielectric layer 12. The doping type of the second doped region 114 is the same as the doping type of the first doped region 111. This is equivalent to forming a superjunction structure of the second doped region 114 and the variable-K dielectric layer 12 on the sidewalls of the trench 118. This not only helps to weaken the electric field peak at the bottom corner of the trench 118, thereby increasing the breakdown voltage, but also effectively reduces the on-resistance.

[0073] In one embodiment, the drain region 113 and the source region 112 are arranged at intervals along a first direction X, and the first direction X is perpendicular to the thickness direction of the substrate structure 11; the second doped region 114 is provided at both ends of the variable-K dielectric layer 12 along the first direction X, that is, the second doped region 114 is provided at both ends of the trench 118 along the first direction X.

[0074] In one embodiment, the second doped region 114 is disposed around the outer periphery of the variable-K dielectric layer 12. This not only effectively weakens the electric field peak at the bottom corner of the trench 118 and increases the breakdown voltage, but also effectively reduces the on-resistance.

[0075] In one embodiment, the second doped region 114 is adjacent to the variable-K dielectric layer 12, that is, the second doped region 114 is adjacent to the trench 118. This facilitates the formation of a superjunction structure between the second doped region 114 and the variable-K dielectric layer 12, thereby reducing the electric field peak at the bottom corner of the trench 118.

[0076] It is understood that a small distance may be provided between the second doped region 114 and the variable-K dielectric layer 12. For example, the distance between the second doped region 114 and the variable-K dielectric layer 12 is less than or equal to 0.5 μm. This allows the second doped region 114 and the variable-K dielectric layer 12 to form a superjunction structure, thereby optimizing the electric field lines at the bottom corner of the trench 118.

[0077] In one embodiment, the variable-K dielectric layer 12 includes a high-K portion and a low-K portion, with a second doped region 114 disposed at least partially around the periphery of the high-K portion. This, on the one hand, forms a superjunction structure 13 of the second doped region 114 and the high-K sub-dielectric layer on the sidewalls of the trench 118, thereby reducing the electric field peak at the bottom corner of the trench 118; on the other hand, it helps reduce the difficulty and cost of device manufacturing.

[0078] It will be understood that in the device shown in FIG1 , the low-K portion is the first sub-dielectric layer 121, and the high-K portion is the second sub-dielectric layer 122. In the device shown in FIG2 , the low-K portion is the first sub-dielectric layer 121, and the high-K portion may include only the third sub-dielectric layer 123, or may include both the second sub-dielectric layer 122 and the third sub-dielectric layer 123.

[0079] It should be noted that the second doped region 114 may also extend to the outer periphery of the low-K portion, which is beneficial for reducing the on-resistance of the device.

[0080] In one embodiment, in the device shown in FIG1 , second doped regions 114 are provided at both ends of the second sub-dielectric layer 122 along the first direction X. The height of the second doped regions 114 is no less than the thickness of the second sub-dielectric layer 122. Here, the height of the second doped regions 114 refers to the dimension of the second doped regions 114 along the thickness direction of the substrate structure 11, and the thickness of the second sub-dielectric layer 122 refers to the dimension of the second sub-dielectric layer 122 along the thickness direction of the substrate structure 11. This is equivalent to forming a second doped region 114-high-K sub-dielectric layer superjunction structure 13 on the sidewalls of the trench 118, thereby facilitating the reduction of the electric field peak at the bottom corner of the trench 118.

[0081] In a preferred embodiment, the height of the second doped region 114 is equal to the thickness of the second sub-dielectric layer 122. It is understood that when the height of the second doped region 114 is greater than the thickness of the second sub-dielectric layer 122, the depletion effect of the protruding portion is relatively limited. Therefore, by making the height of the second doped region 114 equal to the thickness of the second sub-dielectric layer 122, the height of the second doped region 114 can be reduced while ensuring the desired effect, thereby reducing the difficulty and cost of manufacturing the device.

[0082] In one embodiment, in the device shown in FIG. 2 , second doped regions 114 are provided at both ends of the third sub-dielectric layer 123 along the first direction X. The height of the second doped regions 114 is no less than the thickness of the third sub-dielectric layer 123. Here, the height of the second doped regions 114 refers to the dimension of the second doped regions 114 along the thickness direction of the substrate structure 11, and the thickness of the third sub-dielectric layer 123 refers to the dimension of the third sub-dielectric layer 123 along the thickness direction of the substrate structure 11. This is equivalent to forming a second doped region 114-high-K sub-dielectric layer superjunction structure 13 on the sidewalls of the trench 118, thereby facilitating the reduction of the electric field peak at the bottom corner of the trench 118.

[0083] In a preferred embodiment, the height of the second doped region 114 is equal to the thickness of the third sub-dielectric layer 123. It is understood that when the height of the second doped region 114 is greater than the thickness of the third sub-dielectric layer 123, the depletion effect of the protruding portion is relatively limited. Therefore, by making the height of the second doped region 114 equal to the thickness of the third sub-dielectric layer 123, the height of the second doped region 114 can be reduced while ensuring the desired effect, thereby reducing the difficulty and cost of manufacturing the device.

[0084] In one embodiment, the side edges of the superjunction structure 13 protrude beyond the sidewalls of the variable-K dielectric layer 12, that is, the side edges of the superjunction structure 13 protrude beyond the sidewalls of the trench 118. This facilitates the formation of the second doped region 114 above the superjunction structure 13 and also allows the second doped region 114 to form a superjunction structure with the first charge balance region 131, thereby improving device performance.

[0085] In one embodiment, the edge of the superjunction structure 13 along the first direction X protrudes beyond the sidewalls of the variable-K dielectric layer 12. That is, the edge of the superjunction structure 13 along the first direction X protrudes beyond the sidewalls of the trench 118. This facilitates the formation of the second doped region 114 above the superjunction structure 13. Furthermore, it allows the second doped region 114 to form a superjunction structure with the first charge balance region 131, thereby improving device performance.

[0086] In one embodiment, the second doped region 114 is adjacent to the super junction structure 13. This helps to reduce the electric field peak at the bottom corner of the trench 118 without affecting the current path.

[0087] It is understood that there may be a distance between the second doping region 114 and the super junction structure 13. The embodiment of the present application does not limit the positional relationship between the second doping region 114 and the super junction structure 13.

[0088] In one embodiment, the LDMOS device 1 further includes a second well region 116 , a body tie-out region 117 and a gate 14 .

[0089] The body lead region 117 is of the first doping type, and the second well region 116 is of the second doping type. The first well region 115 and the second well region 116 are spaced apart within the first doped region 111. The body lead region 117 is disposed within the first well region 115, and the drain region 113 is disposed within the second well region 116. The gate 14 is disposed on the surface of the substrate structure 11 and covers at least a portion of the first well region 115 and a portion of the first doped region 111.

[0090] In one embodiment, the gate 14 includes a gate conductive layer 142 and a gate dielectric layer 141 . The gate dielectric layer 141 is disposed on a surface of the substrate structure 11 , and the gate conductive layer 142 is disposed on a side of the gate dielectric layer 141 away from the substrate structure 11 .

[0091] In one embodiment, the first doped region 111 is an N-type drift region, the first well region 115 is a P-well, and the second well region 116 is an N-well.

[0092] In a second aspect, as shown in FIG3 , an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device, which specifically includes the following steps:

[0093] S100: Providing a substrate structure. Exemplarily, the substrate structure includes a base, a buried layer, and a top silicon layer stacked in layers.

[0094] S200: Forming a first doped region within the substrate structure and a first well region within the first doped region. Exemplarily, the first doped region can be formed within the top silicon layer by an ion implantation process. It is understood that a second well region can be formed simultaneously during this step.

[0095] S300: forming a super junction structure in the first doping region.

[0096] S400: forming a variable-K dielectric layer in the first doped region, and the superjunction structure is located on the side of the variable-K dielectric layer close to the back of the substrate structure. The dielectric constant of the variable-K dielectric layer gradually increases from the front side of the substrate structure to the back side of the substrate structure.

[0097] S500: forming a drain region spaced apart from the first well region in the first doped region, and forming a source region in the first well region, with a variable-K dielectric layer located between the first well region and the drain region. It is understood that a body tie region may be formed simultaneously in this step.

[0098] The method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application comprises disposing a variable-K dielectric layer and a superjunction structure at the bottom of the variable-K dielectric layer within a first doped region. This, on the one hand, can introduce an electric field peak on the sidewalls of the variable-K dielectric layer, thereby increasing the average field in the withstand voltage region and weakening the electric field concentrated at the corners of the variable-K dielectric layer, that is, weakening the electric field concentrated at the corners of the trench, thereby improving the withstand voltage of the device without increasing the on-resistance of the device. On the other hand, the use of a low-K dielectric on the device surface can increase the surface withstand voltage capability of the device, and the use of a high-K dielectric within the device body can assist in depleting the charge within the device body. Furthermore, by introducing the superjunction structure, in the off state, the superjunction structure and the drift region mutually deplete each other, thereby optimizing the electric field and increasing the doping concentration of the drift region, thereby reducing the on-resistance in the on state.

[0099] It should be noted that ion implantation damages the substrate structure, significantly reducing the mobility and lifetime of electron-hole pairs. Furthermore, most implanted ions are not placed in substitutional positions in the lattice. To activate the ions and restore their original mobility, the substrate structure must be annealed at an appropriate temperature. Annealing repairs lattice defects and allows impurity atoms to migrate to lattice sites, activating the impurities. Generally, lattice defect repair requires approximately 450-550°C, while impurity activation requires 900-1000°C. Impurity activation is time- and temperature-dependent: longer time and higher temperature lead to more complete impurity activation. Common annealing methods for substrate structures include high-temperature thermal annealing and rapid thermal annealing (RTA). For example, a high-temperature thermal annealing process can be used. Specifically, a high-temperature furnace is used to heat the silicon wafer to 800-1000°C and maintain this temperature for 20-40 minutes. It is understandable that a rapid thermal annealing process can also be used for annealing. Compared with a high-temperature thermal annealing process, the rapid thermal annealing process has a shorter annealing time, can avoid the diffusion of doped ions caused by long-term high temperature, and reduce the instantaneous enhanced diffusion of doped ions.

[0100] In one embodiment, S300 specifically includes the following steps:

[0101] S310: forming a mask layer on the front surface of the substrate structure.

[0102] S320: performing patterning on the mask layer to obtain a patterned mask layer, wherein the patterned mask layer has an opening, and the opening exposes the substrate structure and defines the shape and position of the trench.

[0103] S330: etching the substrate structure based on the patterned mask layer to form a trench in the substrate structure.

[0104] S340: removing the patterned mask layer.

[0105] S350: A superjunction structure is formed in the first doped region at the bottom of the trench. Exemplarily, high-energy implantation is performed to form the first charge balance region and the second charge balance region. It should be noted that in S350, the second doped region may also be formed simultaneously. Exemplarily, after the first and second charge balance regions are formed, the second doped region is formed by ion implantation.

[0106] In one embodiment, S400 specifically includes the following steps:

[0107] S420: forming a second sub-dielectric layer in the trench.

[0108] S430: forming a first sub-dielectric layer on the second sub-dielectric layer, wherein the dielectric constant of the first sub-dielectric layer is smaller than the dielectric constant of the second sub-dielectric layer.

[0109] In one embodiment, the following steps are included before S420:

[0110] S410: forming a third sub-dielectric layer in the trench, wherein the dielectric constant of the third sub-dielectric layer is greater than the dielectric constant of the second sub-dielectric layer.

[0111] In one embodiment, the following steps are further included before S500:

[0112] S440: forming a gate on the substrate structure.

[0113] It should be understood that, in the embodiments of the present application, although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0114] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A lateral diffused metal oxide semiconductor device, wherein, Including: A substrate structure; A first doped region disposed within the substrate structure; A first well region and a drain region arranged at intervals within the first doped region; A source region disposed within the first well region; A variable-K dielectric layer embedded within the first doped region and located between the first well region and the drain region, and in the direction from the front surface to the back surface of the substrate structure, the dielectric constant of the variable-K dielectric layer gradually increases; A superjunction structure disposed within the first doped region on the side of the variable-K dielectric layer close to the back surface of the substrate structure.

2. The lateral diffusion metal oxide semiconductor device according to claim 1, wherein, The variable-K dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the dielectric constant of the first sub-dielectric layer is less than that of the second sub-dielectric layer; The first sub-dielectric layer is located on the side of the second sub-dielectric layer close to the front surface of the substrate structure.

3. The lateral diffusion metal oxide semiconductor device according to claim 2, wherein, The variable-K dielectric layer further includes a third sub-dielectric layer, and the dielectric constant of the third sub-dielectric layer is greater than that of the second sub-dielectric layer; the third sub-dielectric layer is located on the side of the second sub-dielectric layer close to the back surface of the substrate structure.

4. The lateral diffused metal oxide semiconductor device according to claim 1, wherein, The superjunction structure is adjacent to the variable-K dielectric layer.

5. The lateral diffused metal oxide semiconductor device according to claim 4, wherein, The superjunction structure includes a first charge balance region and a second charge balance region, and the first charge balance region is located between the second charge balance region and the variable-K dielectric layer; The doping type of the first charge balance region is opposite to that of the first doped region, and the doping type of the second charge balance region is the same as that of the first doped region.

6. The lateral diffused metal oxide semiconductor device according to any one of claims 1-5, wherein, At least a part of the outer periphery of the variable-K dielectric layer is provided with a second doped region, and the doping type of the second doped region is the same as that of the first doped region.

7. The lateral diffused metal oxide semiconductor device according to claim 6, wherein, The drain region and the source region are arranged at intervals along a first direction, and the first direction is perpendicular to the thickness direction of the substrate structure; Both ends of the variable-K dielectric layer along the first direction are provided with the second doped region.

8. The lateral diffusion metal oxide semiconductor device according to claim 6, wherein, The entire circumferential outer periphery of the variable-K dielectric layer is provided with the second doped region.

9. The lateral diffused metal oxide semiconductor device according to claim 6, wherein, The second doped region is adjacent to the variable-K dielectric layer.

10. The lateral diffusion metal oxide semiconductor device according to claim 6, wherein, The variable-K dielectric layer includes a high-K part and a low-K part, and at least a part of the outer periphery of the high-K part is provided with the second doped region.

11. The lateral diffusion metal oxide semiconductor device according to claim 6, wherein, The side edge of the superjunction structure protrudes from the side wall of the variable-K dielectric layer.

12. The lateral diffused metal oxide semiconductor device according to claim 11, wherein, The second doped region is adjacent to the superjunction structure.

13. The lateral diffused metal oxide semiconductor device according to claim 10, wherein, The variable-K dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, the dielectric constant of the first sub-dielectric layer is less than that of the second sub-dielectric layer, and the first sub-dielectric layer is located on the side of the second sub-dielectric layer close to the front surface of the substrate structure; the first sub-dielectric layer is the low-K part, the second sub-dielectric layer is the high-K part, and the height of the second doped region is not less than the thickness of the second sub-dielectric layer; Alternatively, the variable-K dielectric layer includes a first sub-dielectric layer, a second sub-dielectric layer, and a third sub-dielectric layer. The dielectric constant of the first sub-dielectric layer is less than that of the second sub-dielectric layer. The first sub-dielectric layer is located on the side of the second sub-dielectric layer closer to the front surface of the substrate structure. The dielectric constant of the third sub-dielectric layer is greater than that of the second sub-dielectric layer. The third sub-dielectric layer is located on the side of the second sub-dielectric layer closer to the back surface of the substrate structure. The first sub-dielectric layer is the low-K part, the third sub-dielectric layer is the high-K part, and the height of the second doped region is not less than the thickness of the third sub-dielectric layer.

14. The lateral diffused metal oxide semiconductor device according to any one of claims 1-5, wherein, The lateral diffusion metal oxide semiconductor device further includes: a second well region, which is disposed in the first doped region and is spaced apart from the first well region; the drain region is disposed in the second well region; a body extraction region, which is disposed in the first well region, a gate, which is disposed on the surface of the substrate structure and covers at least a part of the first well region and a part of the first doped region.

15. A method for manufacturing a lateral diffused metal oxide semiconductor device, wherein, including: providing a substrate structure; forming a first doped region in the substrate structure and forming a first well region in the first doped region; forming a superjunction structure in the first doped region; forming a variable-K dielectric layer in the first doped region, and the superjunction structure is located on the side of the variable-K dielectric layer closer to the back surface of the substrate structure. In the direction from the front surface of the substrate structure to the back surface of the substrate structure, the dielectric constant of the variable-K dielectric layer gradually increases; forming a drain region spaced apart from the first well region in the first doped region and forming a source region in the first well region, and the variable-K dielectric layer is located between the first well region and the drain region.

Images