Time synchronization method and apparatus, base station circuit, integrated circuit, device, and medium

Abstract

A time synchronization method and apparatus, a base station circuit, an integrated circuit, a device, and a medium. The method is executed in coordination by a main control board and multiple radio frequency sub-boards in a base station, and comprises: by means of a first transmission board, sending interrupt signals to the remaining multiple boards in the base station at regular time intervals; by means of the main control board, determining a timestamp on the basis of the interrupt signals, and sending communication data carrying the timestamp to the multiple radio frequency sub-boards in the base station; and by means of a radio frequency sub-board, performing time alignment with the remaining multiple radio frequency sub-boards on the basis of the time point at which each interrupt signal occurs, and, upon confirming receipt of a valid timestamp sent by the main control board, using the valid timestamp to perform absolute time calibration on the time point at which a previous interrupt signal occurred.

Description

Time synchronization method, device, base station circuit, integrated circuit, equipment and medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311848373.X. The entire contents of this application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, for example, to time synchronization methods, devices, base station circuits, integrated circuits, equipment and media. Background Art

[0003] In modern communication systems, especially large-scale device networks such as electronic price tag communication systems, multiple RF daughter boards are generally required to send data alternately. Therefore, strict time synchronization between multiple RF daughter boards within the base station is key to ensuring efficient system operation.

[0004] However, each RF sub-board in the base station may be affected by various factors such as temperature, which may cause deviations in the internal clock timing of each RF sub-board.

[0005] In related technologies, the current time message can be sent to each RF sub-board through the main control board of the base station. After parsing the current time message, each RF sub-board uses the current time message to update the internal clock of each RF sub-board. However, since the transmission and parsing of the time message require a certain amount of time, the actual time may not match the current time message obtained by parsing, and the time between each RF sub-board cannot be accurately aligned. Summary of the Invention

[0006] The present application provides a time synchronization method, apparatus, base station circuit, integrated circuit, equipment and medium, which can realize time synchronization of multiple RF sub-boards in a base station, solve the problem of large time calibration errors in related technologies, and effectively improve the time calibration accuracy.

[0007] According to one aspect of the present application, a time synchronization method for a base station radio frequency sub-board is provided, which is performed by a main control board in the base station in cooperation with multiple radio frequency sub-boards, including:

[0008] Periodically sending an interrupt signal to the remaining multiple boards in the base station through a first sending board; wherein the first sending board is a main control board or a pre-designated radio frequency sub-board;

[0009] Determine the timestamp according to the interrupt signal through the main control board, and send the communication data carrying the timestamp to multiple radio frequency sub-boards in the base station;

[0010] Through the RF daughter board, time alignment is performed with the other multiple RF daughter boards according to the time point when each interrupt signal occurs. After determining that a legal timestamp sent by the main control board has been received, the legal timestamp is used to perform absolute time calibration on the time point when the last interrupt signal occurred.

[0011] According to another aspect of the present application, a time synchronization device for a base station radio frequency sub-board is provided, comprising:

[0012] An interrupt signal sending module is configured to periodically send an interrupt signal to the remaining multiple boards in the base station through a first sending board; wherein the first sending board is a main control board in the base station or a radio frequency sub-board in a pre-designated multiple radio frequency sub-boards in the base station;

[0013] a communication data sending module, configured to determine a timestamp according to the interrupt signal through the main control board, and send communication data carrying the timestamp to multiple radio frequency sub-boards in the base station;

[0014] The time synchronization module is configured to align the time with the other multiple RF sub-boards according to the time point of each interrupt signal through the RF sub-board, and after determining that a legitimate timestamp sent by the main control board is received, use the legitimate timestamp to perform absolute time calibration on the time point of the last interrupt signal.

[0015] According to another aspect of the present application, a base station circuit is provided, comprising a main control chip and a plurality of radio frequency chips; a target chip is pre-selected from the main control chip and the plurality of radio frequency chips as a first transmitting chip;

[0016] The first transmitting chip is configured to periodically transmit an interrupt signal to the remaining multiple chips in the base station circuit;

[0017] The main control chip is configured to determine a timestamp according to the interrupt signal and send communication data carrying the timestamp to multiple radio frequency chips in the base station circuit;

[0018] The radio frequency chip is configured to perform time alignment with the remaining multiple radio frequency chips based on the time point at which each interrupt signal occurs, and after determining that a legitimate timestamp sent by the main control chip has been received, use the legitimate timestamp to perform absolute time calibration on the time point at which the last interrupt signal occurred.

[0019] According to another aspect of the present application, an integrated circuit is provided, comprising a main control module and a plurality of radio frequency modules; a target module is pre-selected from the main control module and the plurality of radio frequency modules as a first sending module;

[0020] The first sending module is configured to periodically send an interrupt signal to the remaining multiple modules in the integrated circuit;

[0021] The main control module is configured to determine a timestamp according to the interrupt signal and send communication data carrying the timestamp to multiple radio frequency modules in the integrated circuit;

[0022] The radio frequency module is configured to perform time alignment with the remaining multiple radio frequency modules based on the time point of each interrupt signal occurrence, and after determining that a legitimate timestamp sent by the main control module has been received, use the legitimate timestamp to perform absolute time calibration on the time point of the last interrupt signal occurrence.

[0023] According to another aspect of the present application, an electronic device is provided, comprising:

[0024] at least one processor; and

[0025] a memory communicatively connected to the at least one processor; wherein,

[0026] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the time synchronization method of the base station radio frequency sub-board described in any embodiment of the present application.

[0027] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the time synchronization method of the base station radio frequency sub-board described in any embodiment of the present application when executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a flow chart of a method for synchronizing a base station radio frequency sub-board according to an embodiment of the present application;

[0029] FIG2 is a schematic diagram of the internal structure of a base station according to an embodiment of the present application;

[0030] FIG3 is a flowchart of another method for synchronizing a base station radio frequency sub-board according to an embodiment of the present application;

[0031] FIG4 is a flowchart of another method for synchronizing a base station radio frequency sub-board according to an embodiment of the present application;

[0032] FIG5 is a schematic structural diagram of a base station circuit according to an embodiment of the present application;

[0033] FIG6 is a schematic structural diagram of another base station circuit provided according to an embodiment of the present application;

[0034] FIG7 is a schematic diagram of the structure of an integrated circuit provided according to an embodiment of the present application;

[0035] FIG8 is a schematic structural diagram of a time synchronization device for a base station radio frequency sub-board according to an embodiment of the present application;

[0036] FIG9 is a schematic structural diagram of an electronic device for implementing the time synchronization method of the base station radio frequency sub-board according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Figure 1 is a flow chart of a method for synchronizing a base station RF sub-board time according to an embodiment of the present application. This embodiment is applicable to situations where multiple RF sub-boards in a base station are synchronized with a main control board. The method can be executed by a time synchronization device for a base station RF sub-board. The time synchronization device for the base station RF sub-board can be implemented in the form of hardware and / or software and can be configured in a base station with data communication and data processing functions. As shown in Figure 1, the method includes:

[0039] S110 , periodically sending an interrupt signal to the remaining multiple boards in the base station through the first sending board.

[0040] The first sending board is a main control board or a pre-designated radio frequency sub-board.

[0041] It can be understood that the base station includes a main control board and multiple RF sub-boards. The main control board is the core control module of the base station equipment, which is mainly responsible for the management and control of the base station equipment. The RF sub-board can be used for transmitting and receiving wireless signals. The main control board can send various information such as configuration information, monitoring information, control information and data information to the RF sub-board. Through data transmission and processing between the main control board and the RF sub-board, the base station can ensure efficient and stable provision of wireless services.

[0042] Optionally, in an embodiment of the present application, multiple RF sub-boards can be independent chips with RF functions, or multiple different RF modules in the same chip. Some RF sub-boards can be independent chips, and some RF sub-boards can be integrated in the same chip.

[0043] Optionally, when the first sending board is the main control board, the main control board can send interrupt signals to multiple RF sub-boards. When the first sending board is a pre-designated RF sub-board, the pre-designated RF sub-board can serve as the base station main sub-board. At this time, the remaining RF sub-boards in the base station can serve as base station auxiliary sub-boards. Interrupt signals can be sent to multiple base station auxiliary sub-boards through the base station main sub-board, and the base station main sub-board can also send interrupt signals to the main control board.

[0044] Optionally, the first sending board can use the general purpose input and output (GPIO) port to send an interrupt signal. GPIO is a hardware connection port that can be used to control and monitor digital signals. In the base station, the first sending board can be connected to the remaining multiple boards in the base station through a GPIO communication line.

[0045] Figure 2 is a schematic diagram of an optional internal structure of a base station, primarily illustrating the sending of interrupt signals to multiple other boards within the base station via a pre-designated RF sub-board, namely, the base station master sub-board. As shown in Figure 2, the base station master sub-board can send interrupt signals to multiple base station auxiliary sub-boards and the main control board via a GPIO output port, and the multiple base station auxiliary sub-boards and the main control board can receive interrupt signals via their respective GPIO input ports.

[0046] The number of RF sub-boards in Figure 2 is not fixed. The actual number of RF sub-boards inside the base station can be set according to actual needs, and the connection method between the first sending board and the remaining boards in the base station can also be set according to actual needs.

[0047] Optionally, the advantage of using GPIO is that the time delay of transmitting interrupt signals through GPIO is smaller than that of traditional data transmission. Traditional data transmission may be subject to various restrictions such as traffic and parsing time. The time difference between multiple RF sub-boards in obtaining parsed data is large. However, by transmitting interrupt signals through GPIO, multiple RF sub-boards can feel the fluctuation of the interrupt signal at the same time, and then multiple RF sub-boards can determine the occurrence time of the interrupt signal as almost the same time point, thereby realizing time alignment between multiple RF sub-boards and ensuring the accuracy of time alignment.

[0048] Optionally, the first sending board can send the interrupt signal regularly according to a predetermined interrupt signal sending cycle, for example, it can send it once every 1 second, once every 5 seconds, etc. The timing duration here can be set according to actual needs.

[0049] S120 , determining a timestamp according to the interrupt signal through the main control board, and sending communication data carrying the timestamp to multiple radio frequency sub-boards in the base station.

[0050] Optionally, the main control board may send communication data to the multiple radio frequency daughter boards via a serial peripheral interface (SPI), or may send communication data via other data transmission methods.

[0051] Optionally, when the main control board needs to send communication data, it can determine the current timestamp according to the clock in the main control board, and send the current timestamp and the communication data together to the radio frequency sub-board.

[0052] Optionally, when the main control board sends communication data, it may send the communication data with a timestamp to each RF daughter board at the same time, or send it to at least one designated RF daughter board according to the receiver information of the communication data.

[0053] Optionally, the timestamp is a number representing a specific time point. For example, the main control board can determine the time point when any interrupt signal occurs as the timing starting point according to actual usage requirements. The clock in the main control board can record the current time as the specific second from the timing starting point. In one embodiment, the main control board can use the time point when the 10th interrupt signal is sent and received as the timing starting point when determining that the 10th interrupt signal is sent and received, and use 30 seconds as a timestamp and send it to the RF sub-board at the 30th second calculated from the timing starting point.

[0054] Optionally, in actual use, the data interaction between the main control board and the RF sub-board is relatively frequent. Therefore, generally within a short time range, multiple RF sub-boards in the base station can receive the communication data with timestamps sent by the main control board.

[0055] S130. The RF sub-board is time-aligned with the remaining multiple RF sub-boards according to the time point at which each interrupt signal occurs. After determining that a legitimate timestamp sent by the main control board is received, the legitimate timestamp is used to perform absolute time calibration on the time point at which the last interrupt signal occurred.

[0056] It is understandable that due to the good performance of GPIO in transmitting interrupt signals, multiple RF sub-boards can receive interrupt signals at almost the same time point. If the first sending board is a designated RF sub-board, the time point when the RF sub-board sends the interrupt signal and the time points when the other multiple RF sub-boards receive the interrupt signal are also within a relatively small time range, such as 100 microseconds. Therefore, the time points when the interrupt signals occur determined by multiple RF sub-boards are almost the same time point, and the error is negligible.

[0057] Optionally, after the multiple RF daughter boards determine the time point at which the same interrupt signal occurs, the multiple RF daughter boards may use the time point at which the interrupt signal occurs as the starting point of this timing cycle.

[0058] In an optional example, if the interrupt signal sending period of the first sending board is 5 seconds, then after determining the time point when the interrupt signal occurs, the multiple RF sub-boards can use the time point as the timing starting point of the current 5-second timing period.

[0059] Optionally, when multiple RF sub-boards determine the same time point as the timing starting point of the same timing cycle, it is equivalent to completing time alignment between these RF sub-boards, and the time alignment can provide a benchmark reference for subsequent absolute time calibration.

[0060] Optionally, considering that it takes a certain amount of time for the main control board to send communication data and for multiple RF sub-boards to parse the communication data, it may not be as accurate as the GPIO transmission interrupt signal. If the main control board sends communication data at the end of the previous timing cycle, it is very likely that the RF sub-board will not receive it until the beginning of this timing cycle. Therefore, after receiving the communication data, multiple RF sub-boards need to judge the reception time of the communication data. If the reception time is within the legal range of the timing cycle, the timestamp carried in the communication data is determined to be a legal timestamp. Otherwise, the timestamp in the communication data is ignored, and the absolute time calibration is performed when the next timestamp is sent.

[0061] Optionally, the legal range of the timing cycle can be a predetermined time range. For example, the time range of 20%-80% of the current timing cycle can be determined as the legal range. In one embodiment, if the timing cycle is 5 seconds, then the 1st to 4th seconds after the start of the timing cycle can be determined as the legal range. However, the legal range of the above timing cycle and other examples are only used for illustration.

[0062] Optionally, after determining that the timestamp sent by the main control board is a legal timestamp, the RF sub-board can use the legal timestamp as the absolute time of the time point when the last interrupt signal occurred, that is, the legal timestamp can be used as the absolute time of the timing starting point of this timing cycle.

[0063] In an embodiment of the present application, an interrupt signal is periodically sent to the remaining multiple boards in the base station through the first sending board, and communication data carrying time stamps are sent to multiple RF sub-boards in the base station through the main control board. Through the RF sub-board, time alignment and absolute time calibration are performed according to the reception and transmission of the interrupt signal and the legal time stamp. On the basis of time synchronization of multiple RF sub-boards in the base station, absolute time calibration can be performed, which effectively compensates for the problem of insufficient accuracy of absolute time in traditional synchronization schemes, effectively improves the time calibration accuracy, thereby ensuring data synchronization of multiple RF sub-boards during signal reception and transmission, and thus effectively improving the communication efficiency of the base station.

[0064] FIG3 is a flow chart of another method for synchronizing a base station radio frequency sub-board according to an embodiment of the present application. This embodiment, based on the above embodiment, specifically describes the method for synchronizing a base station radio frequency sub-board. As shown in FIG3 , the method includes:

[0065] S210 : The first sending board sends an interrupt signal to the remaining boards in the base station by using GPIO whenever it is determined that a standard timing cycle has started.

[0066] Optionally, the standard timing cycle may be a predetermined timing cycle, such as 1 second, 5 seconds, etc. Whenever a new standard timing cycle begins, the first sending board may use GPIO to send an interrupt signal to the remaining boards in the base station.

[0067] S220. Whenever the main control board sends communication data to multiple RF sub-boards, the main control board determines the current timestamp according to the reception and transmission of the interrupt signal and the time definition rules in the main control board, and sends the communication data carrying the current timestamp to the multiple RF sub-boards.

[0068] Optionally, the time definition rule can be a pre-set rule. For example, after receiving a certain interrupt signal, it is determined to be the first second of the clock in the main control board, thereby determining the current timestamp. However, the time definition rule can be set according to actual needs, and the timestamp in the main control board can be determined in any way.

[0069] S230 : Whenever an interrupt signal is detected by the RF daughter board, the time point at which the interrupt signal occurs is used as the timing starting point of the standard timing cycle.

[0070] S240. When receiving the communication data sent by the main control board through the RF sub-board, whether the reception time of the communication data is within the legal time range is determined according to the reception and transmission of the interrupt signal; in response to the reception time of the communication data being within the legal time range, the current timestamp is determined as the legal timestamp, and S250 is executed; in response to the reception time of the communication data not being within the legal time range, the current timestamp is ignored.

[0071] S250 : In response to determining that the current timestamp is a valid timestamp, the RF daughter board modifies the clock count value at the time point when the last interrupt signal occurred according to the valid timestamp.

[0072] In an embodiment of the present application, through the first sending board, GPIO is used to periodically send interrupt signals to the remaining multiple boards in the base station, and the main control board is used to send communication data carrying timestamps to multiple RF sub-boards in the base station. Through the RF sub-board, time alignment and absolute time calibration are performed according to the reception and transmission of the interrupt signal and the legal timestamp. On the basis of time synchronization of multiple RF sub-boards in the base station, absolute time calibration can be performed, which effectively compensates for the problem of insufficient accuracy of absolute time in traditional synchronization schemes, effectively improves the time calibration accuracy, thereby ensuring data synchronization of multiple RF sub-boards during signal reception and transmission, and thus effectively improving the communication efficiency of the base station.

[0073] In some embodiments, the time synchronization method of the base station radio frequency subboard may further include:

[0074] Through the main control board, in response to determining that the timing calibration conditions are met, the legal sending time point of the calibration timestamp is determined according to the sending and receiving conditions of the interrupt signal, and when the legal sending time point is reached, the calibration timestamp is sent to multiple radio frequency sub-boards, so that the multiple radio frequency sub-boards perform absolute time calibration according to the calibration timestamp.

[0075] It is understandable that in order to avoid situations where the time when the main control board sends communication data does not fall within the legal time range, the main control board can not only randomly send timestamps with communication data, but also send timestamps regularly, thereby achieving absolute time calibration of the RF sub-board timing.

[0076] Optionally, the timing calibration condition may be that when a specified timing calibration time point is reached, it is determined that the timing calibration condition is satisfied.

[0077] Optionally, the legal sending time point can be determined based on factors such as the legal time range and the standard time for data transmission, leaving a reserved time amount for the data transmission time. The communication data sent at the legal sending time point can generally ensure that the radio frequency sub-board receives the communication data within the legal time range.

[0078] Figure 4 is a flow chart of another method for synchronizing a base station radio frequency sub-board according to an embodiment of the present application. This embodiment, based on the above embodiment, specifically describes a method for synchronizing a base station radio frequency sub-board in seconds. As shown in Figure 4, the method includes:

[0079] S310 , continuously sending second pulses to the remaining multiple boards in the base station through the first sending board.

[0080] S320. Whenever the main control board sends communication data to multiple RF sub-boards, the current second count value is determined according to the reception and transmission of the interrupt signal and the time definition rules in the main control board, and the communication data carrying the current second count value is sent to the multiple RF sub-boards.

[0081] S330. Through the RF sub-board, whenever a rising edge of a second pulse is detected, the current moment is used as the timing starting point of the current second. In response to receiving communication data sent by the main control board within the legal time range of the current second, the second clock of the timing starting point of the current second is modified according to the current second count value in the communication data.

[0082] In one embodiment, the first sending board continuously sends second pulses to the remaining multiple boards in the base station through GPIO. Multiple RF sub-boards can detect the rising edge of the second pulse once every 1 second. Multiple RF sub-boards use the detection time of the rising edge as the starting point of the current second. That is, multiple RF sub-boards perform time alignment every second. When the main control board determines that it has reached the 10th second pulse transmission and reception, it uses the time of the occurrence of the 10th second pulse rising edge as the first second of the clock timing in the main control board. When sending communication data, it obtains the current second count value in the clock, for example, the 30th second, and carries the second count value in the communication data and sends it to multiple RF sub-boards. After receiving the communication data within the legal time range, the multiple RF sub-boards use the second count value in the communication data to modify the second clock of the starting point of the current second. That is, multiple RF sub-boards all determine that the starting point of the current second is the 30th second, thereby achieving time synchronization of multiple RF sub-boards. In the above example, the method for determining the clock timing in the main control board and the second count value selected in the main control board are both exemplary.

[0083] In an embodiment of the present application, through the first sending board, GPIO is used to continuously send second pulses to the remaining multiple boards in the base station, and the main control board is used to send communication data carrying the current second count value to the multiple RF sub-boards in the base station. Through the RF sub-board, time alignment and absolute time calibration are performed according to the reception and transmission of the interrupt signal and the current second count value. On the basis of time synchronization of multiple RF sub-boards in the base station, absolute time calibration can be performed, which effectively makes up for the problem of insufficient accuracy of absolute time in traditional synchronization schemes, effectively improves the time calibration accuracy, thereby ensuring data synchronization of multiple RF sub-boards during signal reception and transmission, and thus effectively improving the communication efficiency of the base station.

[0084] FIG5 is a schematic diagram of a base station circuit according to an embodiment of the present invention. As shown in FIG5 , the base station circuit includes a main control chip 410 and multiple radio frequency chips 420 .

[0085] A target chip is pre-selected from the main control chip 410 and the plurality of radio frequency chips 420 as the first transmitting chip.

[0086] The first sending chip is configured to periodically send an interrupt signal to the remaining multiple chips in the base station circuit.

[0087] The main control chip 410 is configured to determine a timestamp according to the interrupt signal and send communication data carrying the timestamp to multiple radio frequency chips 420 in the base station circuit.

[0088] The RF chip 420 is configured to perform time alignment with the other multiple RF chips 420 based on the time point when each interrupt signal occurs, and after determining that a valid timestamp sent by the main control chip 410 is received, use the valid timestamp to perform absolute time calibration on the time point when the last interrupt signal occurred.

[0089] Optionally, the first transmitting chip can be pre-selected from the main control chip 410 and multiple RF chips 420. The main control chip 410 can be selected as the first transmitting chip and perform the function of the first transmitting chip, or any RF chip 420 can be selected as the first transmitting chip and perform the function of the first transmitting chip. However, it should be noted that even if the main control chip 410 or the RF chip 420 is used as the first transmitting chip, it can still perform the function of the main control chip 410 or the RF chip 420.

[0090] Optionally, the first transmitting chip can be connected to the remaining multiple chips in the base station circuit through a GPIO, that is, at least one general output port is set in the first transmitting chip, and at least one general input port is set in the remaining multiple chips in the base station circuit; the first transmitting chip can also be connected to the remaining multiple chips in the base station circuit through multiple GPIOs, that is, when the base station circuit includes n chips in addition to the first transmitting chip, n general output ports are set in the first transmitting chip, each general output port is connected to one GPIO, and each GPIO is connected to a designated chip in the base station circuit.

[0091] In the example shown in FIG5 , a radio frequency chip 420 is pre-selected as the first transmitting chip. A general output port is provided in the first transmitting chip. The first transmitting chip is connected to the main control chip 410 and the remaining radio frequency chips 420 via a GPIO.

[0092] Figure 6 is a schematic diagram of the structure of another base station circuit provided by an embodiment of the present application. As shown in Figure 6, a main control chip 410 is pre-selected as the first transmitting chip. The base station circuit also includes four radio frequency chips 420. The main control chip 410 is connected to multiple radio frequency chips 420 via four GPIOs.

[0093] It can be understood that the examples shown in Figures 5 and 6 are only for illustrating the selection method of the first transmitting chip and the connection method between the first transmitting chip and the remaining multiple chips. For example, when the first transmitting chip is the RF chip 420, the RF chip 420 can also be connected to the remaining multiple chips through multiple GPIOs. It is only necessary to ensure that the selection method of the first transmitting chip and the connection method between the first transmitting chip and the remaining multiple chips meet the rules. The specific number of RF chips 420 shown in Figures 5 and 6 is only used as an example. The number of RF chips 420 in the base station circuit can be set according to actual needs.

[0094] Optionally, the first sending chip may be configured to send an interrupt signal to the remaining chips in the base station circuit via GPIO whenever it is determined that a standard timing cycle has started.

[0095] Optionally, the radio frequency chip 420 may be configured to use the time point at which an interrupt signal occurs as the timing starting point of a standard timing cycle whenever an interrupt signal is detected.

[0096] Optionally, the main control chip 410 can be set to: whenever communication data is sent to multiple RF chips 420, the current timestamp is determined according to the reception and transmission of the interrupt signal and the time definition rules in the main control chip 410, and the communication data carrying the current timestamp is sent to the multiple RF chips 420.

[0097] Optionally, the radio frequency chip 420 may also be configured as:

[0098] When receiving communication data sent by the main control chip 410, judging whether the reception time of the communication data is within the legal time range according to the transmission and reception of the interrupt signal; in response to the reception time of the communication data being within the legal time range, determining the current timestamp as the legal timestamp; in response to the reception time of the communication data not being within the legal time range, ignoring the current timestamp;

[0099] In response to determining that the current timestamp is a valid timestamp, the clock count value at the time point when the last interrupt signal occurred is modified according to the valid timestamp.

[0100] Optionally, the main control chip 410 may also be configured as:

[0101] In response to determining that the timing calibration conditions are met, the legal sending time point of the calibration timestamp is determined based on the sending and receiving conditions of the interrupt signal, and when the legal sending time point is reached, the calibration timestamp is sent to multiple RF chips 420 so that multiple RF chips 420 can perform absolute time calibration based on the calibration timestamp.

[0102] In an embodiment of the present application, a main control chip and multiple RF chips are configured in the base station circuit, and a target chip is pre-selected as the first sending chip among the main control chip and the multiple RF chips. The first sending chip periodically sends an interrupt signal to the remaining multiple chips in the base station circuit, and the main control chip sends communication data with timestamps to the multiple RF chips in the base station circuit. The RF chips perform time alignment and absolute time calibration based on the reception and transmission of the interrupt signal and the legal timestamp. On the basis of time synchronization of multiple RF chips in the base station circuit, absolute time calibration can be performed, which effectively compensates for the problem of insufficient accuracy of absolute time in traditional synchronization schemes, effectively improves the time calibration accuracy, thereby ensuring data synchronization of multiple RF chips during signal reception and transmission, and thus effectively improving the communication efficiency of the base station circuit.

[0103] FIG7 is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application. As shown in FIG7 , the integrated circuit includes a main control module 510 and multiple radio frequency modules 520 .

[0104] A target module is pre-selected in the main control module 510 and the plurality of radio frequency modules 520 as the first sending module.

[0105] The first sending module is configured to periodically send an interrupt signal to the remaining multiple modules in the integrated circuit.

[0106] The main control module 510 is configured to determine a timestamp according to the interrupt signal and send communication data carrying the timestamp to the multiple radio frequency modules 520 in the integrated circuit.

[0107] Optionally, Figure 7 shows an internal architecture diagram of an integrated circuit, in which the main control module 510 and multiple RF modules 520 are all internal structures of the same integrated circuit. Four RF modules 520 are shown in Figure 7, but in actual integrated circuit design, the number of RF modules 520 can be set according to actual needs.

[0108] The RF module 520 is configured to perform time alignment with the other multiple RF modules 520 based on the time point when each interrupt signal occurs, and after determining that a valid timestamp sent by the main control module 510 has been received, use the valid timestamp to perform absolute time calibration on the time point when the previous interrupt signal occurred.

[0109] Optionally, the integrated circuit may be equivalent to a chip, and the main control module 510 and the radio frequency module 520 are different functional modules in the same chip.

[0110] Optionally, the first sending module can be pre-selected from the main control module 510 and multiple RF modules 520. The main control module 510 can be selected as the first sending module and perform the functions of the first sending module. Any RF module 520 can also be selected as the first sending module and perform the functions of the first sending module. Even if the main control module 510 or the RF module 520 is used as the first sending module, it can still perform the functions of the main control module 510 or the RF module 520.

[0111] Optionally, the first sending module can be connected to the remaining modules in the integrated circuit through a signal line, that is, at least one universal output port is set in the first sending module, and at least one universal input port is set in the remaining modules in the integrated circuit; the first sending module can also be connected to the remaining modules in the integrated circuit through multiple signal lines, that is, when the integrated circuit includes n modules in addition to the first sending module, n universal output ports are set in the first sending module, each universal output port is connected to one signal line, and each signal line is connected to a designated module in the integrated circuit.

[0112] Optionally, the first sending module may be configured to send an interrupt signal to the remaining modules in the integrated circuit via a signal line whenever a standard timing cycle is determined to start.

[0113] Optionally, the radio frequency module 520 may be configured to use the time point at which the interrupt signal occurs as the timing starting point of the standard timing period whenever an interrupt signal is detected.

[0114] Optionally, the main control module 510 can be configured to: whenever communication data is sent to multiple RF modules 520, determine the current timestamp based on the reception and transmission of the interrupt signal and the time definition rules in the main control module 510, and send the communication data carrying the current timestamp to the multiple RF modules 520.

[0115] Optionally, the radio frequency module 520 may also be configured as:

[0116] Upon receiving the communication data sent by the main control module 510, determining whether the reception time of the communication data is within a legal time range according to the transmission and reception of the interrupt signal; in response to the reception time of the communication data being within the legal time range, determining the current timestamp as a legal timestamp; in response to the reception time of the communication data not being within the legal time range, ignoring the current timestamp;

[0117] In response to determining that the current timestamp is a valid timestamp, the clock count value at the time point when the last interrupt signal occurred is modified according to the valid timestamp.

[0118] Optionally, the main control module 510 may also be configured as:

[0119] In response to determining that the timing calibration conditions are met, the legal sending time point of the calibration timestamp is determined based on the sending and receiving conditions of the interrupt signal, and when the legal sending time point is reached, the calibration timestamp is sent to multiple RF modules 520 so that the multiple RF modules 520 can perform absolute time calibration based on the calibration timestamp.

[0120] In an embodiment of the present application, a main control module and multiple RF modules are configured in an integrated circuit, and a target module is pre-selected in the main control module and the multiple RF modules as the first sending module. The first sending module periodically sends an interrupt signal to the remaining multiple modules in the integrated circuit, and the main control module sends communication data carrying a timestamp to the multiple RF modules in the integrated circuit. The RF module performs time alignment and absolute time calibration based on the reception and transmission of the interrupt signal and the legal timestamp. On the basis of time synchronization of multiple RF modules in the integrated circuit, absolute time calibration can be performed, which effectively compensates for the problem of insufficient accuracy of absolute time in traditional synchronization schemes, effectively improves the time calibration accuracy, thereby ensuring data synchronization of multiple RF modules during signal transmission and reception, and thus effectively improving the communication efficiency of the integrated circuit.

[0121] FIG8 is a schematic diagram of the structure of a time synchronization device for a base station radio frequency sub-board according to an embodiment of the present application. As shown in FIG8 , the device includes: an interrupt signal sending module 610 , a communication data sending module 620 , and a time synchronization module 630 .

[0122] The interrupt signal sending module 610 is configured to periodically send an interrupt signal to the remaining multiple boards in the base station through a first sending board; wherein the first sending board is a main control board or a pre-designated radio frequency sub-board.

[0123] The communication data sending module 620 is configured to determine a timestamp according to the interrupt signal through the main control board, and send communication data carrying the timestamp to multiple radio frequency sub-boards in the base station.

[0124] The time synchronization module 630 is configured to align the time with the other multiple RF sub-boards based on the time point of each interrupt signal through the RF sub-board, and after determining that a valid timestamp sent by the main control board is received, use the valid timestamp to perform absolute time calibration on the time point of the last interrupt signal.

[0125] In an embodiment of the present application, an interrupt signal is periodically sent to the remaining multiple boards in the base station through the first sending board, and communication data carrying time stamps are sent to multiple RF sub-boards in the base station through the main control board. Through the RF sub-board, time alignment and absolute time calibration are performed according to the reception and transmission of the interrupt signal and the legal time stamp. On the basis of time synchronization of multiple RF sub-boards in the base station, absolute time calibration can be performed, which effectively compensates for the problem of insufficient accuracy of absolute time in traditional synchronization schemes, effectively improves the time calibration accuracy, thereby ensuring data synchronization of multiple RF sub-boards during signal reception and transmission, and thus effectively improving the communication efficiency of the base station.

[0126] Based on the above embodiments, the interrupt signal sending module 610 may be configured as follows:

[0127] The first sending board sends an interrupt signal to the remaining boards in the base station by using GPIO whenever it is determined that a standard timing cycle has started.

[0128] Based on the above embodiments, the time synchronization module 630 may include a time alignment unit and a time calibration unit;

[0129] The time alignment unit can be set to:

[0130] Through the RF daughter board, whenever an interrupt signal is detected, the time point when the interrupt signal occurs is used as the timing starting point of the standard timing cycle.

[0131] Based on the above embodiments, the communication data sending module 620 may be configured as follows:

[0132] Whenever communication data is sent to multiple RF sub-boards through the main control board, the current timestamp is determined according to the reception and transmission of the interrupt signal and the time definition rules in the main control board, and the communication data carrying the current timestamp is sent to the multiple RF sub-boards.

[0133] Based on the above embodiments, the time calibration unit may be configured as follows:

[0134] When receiving communication data sent by the main control board, the radio frequency sub-board determines whether the reception time of the communication data is within a legal time range according to the transmission and reception of the interrupt signal; in response to the reception time of the communication data being within the legal time range, the current timestamp is determined as a legal timestamp; in response to the reception time of the communication data not being within the legal time range, the current timestamp is ignored;

[0135] By the radio frequency daughter board, in response to determining that the current timestamp is a legal timestamp, the clock count value at the time point when the last interrupt signal occurred is modified according to the legal timestamp.

[0136] Based on the above embodiments, the interrupt signal sending module 610 may also be configured as follows:

[0137] When the first sending board is a pre-designated radio frequency sub-board, an interrupt signal is periodically sent to the main control board via the first sending board using GPIO.

[0138] Based on the above embodiments, a timing calibration module may be further included, configured to:

[0139] Through the main control board, in response to determining that the timing calibration conditions are met, the legal sending time point of the calibration timestamp is determined according to the sending and receiving conditions of the interrupt signal, and when the legal sending time point is reached, the calibration timestamp is sent to multiple radio frequency sub-boards, so that the multiple radio frequency sub-boards perform absolute time calibration according to the calibration timestamp.

[0140] On the basis of the above embodiments, the interrupt signal sending module 610 may be configured to: continuously send second pulses to the remaining multiple boards in the base station by using GPIO via the first sending board;

[0141] The communication data sending module 620 may be configured to determine the current second count value based on the reception and transmission of the interrupt signal and the time definition rules in the main control board whenever sending communication data to the multiple RF sub-boards through the main control board, and send the communication data carrying the current second count value to the multiple RF sub-boards;

[0142] The time synchronization module 630 can be configured to: through the RF sub-board, whenever the rising edge of the second pulse is detected, the current moment is used as the timing starting point of the current second; and, in response to receiving communication data sent by the main control board within the legal time range of the current second, the second clock of the timing starting point of the current second is modified according to the current second count value in the communication data.

[0143] The time synchronization device of the base station radio frequency sub-board provided in the embodiment of the present application can execute the time synchronization method of the base station radio frequency sub-board provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method.

[0144] FIG9 shows a block diagram of an electronic device 10 that can be used to implement an embodiment of the present application. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only provided as examples.

[0145] As shown in Figure 9, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the ROM 12 or the computer program loaded from the storage unit 18 into the RAM 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12 and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0146] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0147] The processor 11 can be various general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors that run machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The processor 11 performs the various methods and processes described above, such as the time synchronization method of the base station radio frequency sub-board as described in the embodiment of the present application. That is:

[0148] Periodically sending an interrupt signal to the remaining multiple boards in the base station through a first sending board; wherein the first sending board is a main control board or a pre-designated radio frequency sub-board;

[0149] Determine the timestamp according to the interrupt signal through the main control board, and send the communication data carrying the timestamp to multiple radio frequency sub-boards in the base station;

[0150] Through the RF daughter board, time alignment is performed with the other multiple RF daughter boards according to the time point when each interrupt signal occurs. After determining that a legal timestamp sent by the main control board has been received, the legal timestamp is used to perform absolute time calibration on the time point when the last interrupt signal occurred.

[0151] In some embodiments, the time synchronization method of the base station radio frequency daughter board can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the time synchronization method of the base station radio frequency daughter board described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the time synchronization method of the base station radio frequency daughter board by any other appropriate means (for example, by means of firmware).

[0152] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0153] Computer programs for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0154] In the context of the present application, computer-readable storage medium can be a tangible medium that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage medium can include electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage medium can be a machine-readable signal medium. Machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, RAM, ROM, an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device or any suitable combination of the foregoing.

[0155] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0156] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0157] A computing system may include a client and a server. The client and server are generally remote from each other and typically interact via a communication network. The client-server relationship arises through computer programs running on the respective computers and establishing a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, a host product within a cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosts and virtual private server (VPS) services.

[0158] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of this application can be achieved.

Claims

1. A time synchronization method for a base station radio frequency sub-board, which is executed by a main control board and multiple radio frequency sub-boards in the base station. The method includes: Timing and sending an interrupt signal to the remaining multiple boards in the base station through a first sending board; wherein, the first sending board is the main control board or a pre-specified radio frequency sub-board; Determining a timestamp according to the interrupt signal through the main control board, and sending communication data carrying the timestamp to multiple radio frequency sub-boards in the base station; Aligning the time with the remaining multiple radio frequency sub-boards according to the time point when each interrupt signal occurs through the radio frequency sub-board, and, after determining that a legal timestamp sent by the main control board is received, performing absolute time calibration on the time point when the previous interrupt signal occurred by using the legal timestamp.

2. The method according to claim 1, wherein, Timing and sending an interrupt signal to the remaining multiple boards in the base station through the first sending board, including: Whenever it is determined that the standard timing period starts through the first sending board, using the General-Purpose Input / Output (GPIO) to send an interrupt signal to the remaining multiple boards in the base station.

3. The method according to claim 2, wherein Aligning the time with the remaining multiple radio frequency sub-boards according to the time point when each interrupt signal occurs through the radio frequency sub-board, including: Whenever the radio frequency sub-board detects an interrupt signal, taking the time point when the interrupt signal occurs as the timing start point of the standard timing period.

4. The method according to claim 1, wherein Determining a timestamp according to the interrupt signal through the main control board, and sending communication data carrying the timestamp to multiple radio frequency sub-boards in the base station, including: Whenever the main control board sends communication data to multiple radio frequency sub-boards, determining the current timestamp according to the sending and receiving situation of the interrupt signal and the time definition rule in the main control board, and sending the communication data carrying the current timestamp to multiple radio frequency sub-boards.

5. The method according to claim 4, wherein, After determining that a legal timestamp sent by the main control board is received, performing absolute time calibration on the time point when the previous interrupt signal occurred by using the legal timestamp through the radio frequency sub-board, including: When the radio frequency sub-board receives the communication data sent by the main control board, judging whether the receiving time of the communication data is within the legal time range according to the sending and receiving situation of the interrupt signal; in response to the receiving time of the communication data being within the legal time range, determining the current timestamp as the legal timestamp; in response to the receiving time of the communication data not being within the legal time range, ignoring the current timestamp; In response to determining that the current timestamp is the legal timestamp, modifying the clock count value of the time point when the previous interrupt signal occurred through the radio frequency sub-board.

6. The method according to claim 1, further including: In response to determining that the timing calibration condition is met through the main control board, determining the legal sending time point of the calibration timestamp according to the sending and receiving situation of the interrupt signal, and when the legal sending time point is reached, sending the calibration timestamp to multiple radio frequency sub-boards for the multiple radio frequency sub-boards to perform absolute time calibration according to the calibration timestamp.

7. The method according to claim 1, further including: Continuously sending a second pulse to the remaining multiple boards in the base station through the first sending board by using GPIO; Through the main control board, whenever communication data is sent to multiple radio frequency sub-boards, the current second count value is determined according to the transceiver situation of the interrupt signal and the time definition rule in the main control board, and the communication data carrying the current second count value is sent to the multiple radio frequency sub-boards; Through the radio frequency sub-board, whenever the rising edge of the second pulse is detected, the current moment is used as the starting point for timing the current second, and in response to receiving the communication data sent by the main control board within the legal time range of the current second, the second clock of the starting point for timing the current second is modified according to the current second count value in the communication data.

8. A time synchronization device for a base station radio frequency sub-board, comprising: An interrupt signal sending module, configured to regularly send interrupt signals to the remaining multiple boards in the base station through a first sending board; wherein, the first sending board is the main control board in the base station or one of the multiple radio frequency sub-boards in the base station designated in advance; A communication data sending module, configured to determine a timestamp according to the interrupt signal through the main control board, and send the communication data carrying the timestamp to the multiple radio frequency sub-boards in the base station; A time synchronization module, configured to align the time with the remaining multiple radio frequency sub-boards according to the time point when each interrupt signal occurs through the radio frequency sub-board, and after determining that a legal timestamp sent by the main control board is received, perform absolute time calibration on the time point when the previous interrupt signal occurred by using the legal timestamp.

9. A base station circuit, comprising a main control chip and multiple radio frequency chips; a target chip is pre-selected as the first sending chip from the main control chip and the multiple radio frequency chips; The first sending chip is configured to regularly send interrupt signals to the remaining multiple chips in the base station circuit; The main control chip is configured to determine a timestamp according to the interrupt signal, and send the communication data carrying the timestamp to the multiple radio frequency chips in the base station circuit; The radio frequency chip is configured to align the time with the remaining multiple radio frequency chips according to the time point when each interrupt signal occurs, and after determining that a legal timestamp sent by the main control chip is received, perform absolute time calibration on the time point when the previous interrupt signal occurred by using the legal timestamp.

10. An integrated circuit, comprising a main control module and multiple radio frequency modules; a target module is pre-selected as the first sending module from the main control module and the multiple radio frequency modules; The first sending module is configured to regularly send interrupt signals to the remaining multiple modules in the integrated circuit; The main control module is configured to determine a timestamp according to the interrupt signal, and send the communication data carrying the timestamp to the multiple radio frequency modules in the integrated circuit; The radio frequency module is configured to align the time with the remaining multiple radio frequency modules according to the time point when each interrupt signal occurs, and after determining that a legal timestamp sent by the main control module is received, perform absolute time calibration on the time point when the previous interrupt signal occurred by using the legal timestamp.

11. An electronic device, the electronic device comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and when the computer program is executed by the at least one processor, enables the at least one processor to execute the time synchronization method for the base station radio frequency daughter board according to any one of claims 1-7.

12. A computer-readable storage medium storing computer instructions for implementing the time synchronization method for the base station radio frequency daughter board according to any one of claims 1-7 when the computer instructions are executed by a processor.

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