Display panel, display module, and display apparatus

Abstract

A display panel, a display module, and a display apparatus. The display panel has a display area and a light transmission area located at at least one side of the display area, where the light transmission area emits light of one color within one light emission period. The display panel comprises a first substrate and a second substrate which are arranged opposite each other, and a first pixel circuit, a second pixel circuit, a liquid crystal layer, and a frame sealing portion which are arranged between the first substrate and the second substrate. The frame sealing portion is arranged around the liquid crystal layer, an inner side wall of the frame sealing portion is used for defining a liquid crystal sealing area, and the display area and the light transmission area are both located within the liquid crystal sealing area. The first pixel circuit is located within the display area and comprises a first pixel electrode and a first common electrode, and the first pixel electrode and the first common electrode are configured to drive liquid crystal molecules in the liquid crystal layer to move. The second pixel circuit is located within the light transmission area and comprises a second pixel electrode and a second common electrode, and the second pixel electrode and the second common electrode are configured to drive liquid crystal molecules in the liquid crystal layer to move.

Description

Display panel, display module, display device

[0001] This application claims priority to Chinese patent application No. 202311869296.6, filed on December 29, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel, a display module, and a display device. Background Art

[0003] In some liquid crystal display panels, a liquid crystal layer is used in a display area to realize image display, and a light emitting diode is used as a light emitting device in an indicator area outside the boundary of the display area to realize light emission in the indicator area. Summary of the Invention

[0004] In one aspect, a display panel is provided. The display panel comprises a display area and a light-transmitting area located on at least one side of the display area, wherein the light-transmitting area emits light of one color during one light-emitting cycle. The display panel comprises a first substrate and a second substrate disposed opposite to each other, and a first pixel circuit, a second pixel circuit, a liquid crystal layer, and a sealing frame disposed between the first substrate and the second substrate. The sealing frame is disposed around the liquid crystal layer, and the inner sidewalls of the sealing frame are used to define a liquid crystal sealing area, wherein both the display area and the light-transmitting area are located within the liquid crystal sealing area. The first pixel circuit is located within the display area and comprises a first pixel electrode and a first common electrode, wherein the first pixel electrode and the first common electrode are configured to drive the movement of liquid crystal molecules in the liquid crystal layer. The second pixel circuit is located within the light-transmitting area and comprises a second pixel electrode and a second common electrode, wherein the second pixel electrode and the second common electrode are configured to drive the movement of liquid crystal molecules in the liquid crystal layer.

[0005] In some embodiments, the display panel further includes: a circuit structure located outside the display area, and the circuit structure and the light-transmitting area are arranged side by side along an extension direction of at least one side boundary of the display area.

[0006] In some embodiments, the circuit structure includes a portion of a first common electrode line, and the first common electrode line is electrically connected to the first common electrode.

[0007] In some embodiments, the first common electrode line is electrically connected to the second common electrode.

[0008] In some embodiments, the first common electrode line and the second common electrode are disposed in the same layer with a gap therebetween. The display panel further includes a connecting line located on a side of the second common electrode that is close to or away from the first substrate, with the connecting line crossing the gap. The first common electrode line is electrically connected to the second common electrode via the connecting line.

[0009] In some embodiments, the connecting line extends to the area where the first common electrode line is located, and is electrically connected to the first common electrode line through multiple connection points in the area where the first common electrode line is located; and / or, the display panel includes multiple second common electrodes, the multiple second common electrodes are connected into an integrated structure, the connecting line extends to the light-transmitting area, and is electrically connected to the integrated structure through multiple connection points in the light-transmitting area.

[0010] In some embodiments, the display panel further includes a second common electrode line, the second common electrode line being electrically connected to the first common electrode, and the first common electrode line being wider than the second common electrode line.

[0011] In some embodiments, the display panel further includes an electrostatic protection circuit. The circuit structure includes a portion of a ground line, the ground line is electrically connected to the electrostatic protection circuit, the ground line is electrically insulated from the first common electrode, and the ground line is electrically insulated from the second common electrode.

[0012] In some embodiments, the ground line and the second common electrode are disposed in the same layer with a gap therebetween.

[0013] In some embodiments, the circuit structure includes: a third pixel circuit located outside the display area and the light-transmitting area. The third pixel circuit includes a third pixel electrode and a third common electrode, the third pixel electrode being disposed in the same layer as the first pixel electrode, and the third common electrode and the first common electrode forming an integral structure.

[0014] In some embodiments, the first common electrode and the second common electrode are disposed in the same layer.

[0015] In some embodiments, the first pixel electrode and the second pixel electrode are disposed in the same layer and made of the same material.

[0016] In some embodiments, the area defined by the first pixel circuit is a first sub-pixel region, the display area includes multiple first sub-pixel regions, the first sub-pixel regions are configured to emit light of a single color, and at least two of the multiple first sub-pixel regions emit light of different colors. The area defined by the second pixel circuit is a second sub-pixel region, the light-transmitting area includes one or more second sub-pixel regions, and the second sub-pixel regions are configured to emit light of a single color. At least two of the multiple second sub-pixel regions emit light of different colors, or the multiple second sub-pixel regions all emit the same color.

[0017] In some embodiments, the display panel further includes a color filter layer including a plurality of first filter portions located in the display area, the plurality of first filter portions being arranged corresponding to the plurality of first sub-pixel areas, and the plurality of first filter portions including filter portions of at least two filtering colors.

[0018] The thickness of the color filter layer in the area corresponding to the second sub-pixel area is 0; or, the color filter layer also includes: one or more second filter parts located in the light-transmitting area, each second filter part is arranged corresponding to a second sub-pixel area; the multiple second filter parts include filter parts of at least one filtering color.

[0019] In some embodiments, filter portions with the same filter color are disposed in the same layer.

[0020] In some embodiments, the display panel further includes a black matrix layer having a plurality of first openings located in the display area, the first openings being arranged corresponding to the first pixel electrodes. Along the arrangement direction of the light-transmitting area and the display area, a distance q is defined between two adjacent first openings.

[0021] The black matrix layer further has a second opening having the same size as the light-transmitting area, and the distance between the first opening and the second opening closest to each other is w, 0.5q≤w≤1.5q, or w>1.5q.

[0022] Alternatively, the black matrix layer further has a plurality of third openings located in the light-transmitting area, the third openings are arranged corresponding to the second pixel electrodes, and the distance between the closest first opening and the third opening is r, 0.5q≤r≤1.5q, or r>1.5q.

[0023] In some embodiments, the display panel further includes a sensor area located on one side of the display area, the sensor area being located within the liquid crystal sealing area, and the thickness of the black matrix layer in the area corresponding to the sensor area is zero.

[0024] In some embodiments, in an orthographic projection onto the first substrate, a boundary line of the black matrix layer surrounds the sensor area, and the black matrix layer has a fourth opening corresponding to the sensor area; or, in an orthographic projection onto the first substrate, the sensor area is outside the boundary line of the black matrix layer.

[0025] In another aspect, a display module is provided. The display module includes: a display panel according to any of the aforementioned embodiments; and a circuit board. The circuit board is electrically connected to the display panel and configured to send a drive signal to the display panel.

[0026] In some embodiments, the display module further comprises: a sensor disposed in the sensor area. The light-transmitting area is configured to change the color of the emitted light according to a change in the working state of the sensor.

[0027] In another aspect, a display device is provided. The display device includes a backlight module and a display module disposed on the light-emitting side of the backlight module. The backlight module has a first backlight region and a second backlight region. The display region of the display module, as projected by the backlight module, is within the range of the first backlight region, and the light-transmitting region of the display module, as projected by the backlight module, is within the range of the second backlight region.

[0028] In some embodiments, the first backlight area and the second backlight area can be independently controlled to be turned on and off. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0030] FIG1 is a planar structural diagram of a display device according to some embodiments;

[0031] FIG2 is a cross-sectional structural diagram obtained along the cross-sectional line G1-G1 in FIG1 ;

[0032] FIG3 is a structural diagram of a display module according to some embodiments;

[0033] FIG4 is a planar structural diagram of a display panel according to some embodiments;

[0034] FIG5 is a planar structural diagram of a display panel according to some other embodiments;

[0035] FIG6 is a planar structural diagram of a display panel according to yet other embodiments;

[0036] FIG7 is a planar structural diagram of a display panel according to still other embodiments;

[0037] FIG8 is an enlarged structural diagram of region V1 in FIG1 ;

[0038] FIG9 is an enlarged structural diagram of region V2 in FIG2 ;

[0039] FIG10 is a cross-sectional structural diagram obtained along the cross-sectional line G2-G2 in FIG8;

[0040] FIG11 is a cross-sectional structural diagram obtained along the cross-sectional line G3-G3 in FIG8 ;

[0041] FIG12 is an enlarged structural diagram of region V1 in FIG1 ;

[0042] FIG13 is an enlarged structural diagram of a first common electrode and a second common electrode according to some embodiments;

[0043] FIG14 is another enlarged structural diagram of the first common electrode and the second common electrode according to some embodiments;

[0044] FIG15 is a flowchart of preparing an array substrate according to some embodiments;

[0045] FIG16 is a planar structural diagram of a display panel according to some embodiments;

[0046] FIG17 is an enlarged structural diagram of area V3 in FIG16 ;

[0047] FIG18 is a planar structural diagram of a display panel according to some other embodiments;

[0048] FIG19 is another enlarged structural diagram of region V3 in FIG16 ;

[0049] FIG20 is a timing diagram of a second gate line in a light emitting period according to some embodiments;

[0050] FIG21 is another timing diagram of the second gate line in a light emitting period according to some embodiments;

[0051] FIG22 is another enlarged structural diagram of region V3 in FIG16 ;

[0052] FIG23 is an enlarged structural diagram of area V1 in FIG1 ;

[0053] FIG24 is another enlarged structural diagram of region V1 in FIG1 ;

[0054] FIG25 is another enlarged structural diagram of area V1 in FIG1 ;

[0055] FIG26 is another enlarged structural diagram of the area V1 in FIG1 ;

[0056] FIG27 is an equivalent circuit diagram of a first pixel circuit in a display panel according to some embodiments;

[0057] FIG28 is a partially enlarged structural diagram of a display panel according to some embodiments;

[0058] FIG29 is an equivalent circuit diagram of a second pixel circuit in a display panel according to some embodiments;

[0059] FIG30 is a timing diagram of a second pixel circuit in a light emitting phase according to some embodiments;

[0060] FIG31 is an equivalent circuit diagram of a first pixel circuit and a second pixel circuit in a display panel according to some embodiments;

[0061] FIG32 is an equivalent circuit diagram of a first pixel circuit and a second pixel circuit in a display panel according to some other embodiments;

[0062] FIG33 is a timing diagram of a second pixel circuit in a light emitting phase according to some embodiments;

[0063] FIG34 is a structural diagram of a first gate driving circuit according to some embodiments;

[0064] FIG35 is a structural diagram of a first shift register according to some embodiments;

[0065] FIG36 is an equivalent circuit diagram of a first shift register according to some embodiments;

[0066] FIG37 is a structural diagram of a second shift register according to some embodiments;

[0067] FIG38 is an equivalent circuit diagram of a second shift register according to some embodiments;

[0068] FIG39 is an electrical equivalent circuit diagram of a light emitting data driving circuit according to some embodiments;

[0069] FIG40 is an equivalent circuit diagram of a light emitting data driving circuit according to some other embodiments;

[0070] FIG41 is an equivalent circuit diagram of a light emitting data driving circuit according to yet other embodiments;

[0071] FIG42 is an equivalent circuit diagram of a light emitting data driving circuit according to still other embodiments;

[0072] FIG43 is a timing diagram of a light-emitting data driving circuit in a light-emitting phase according to some embodiments;

[0073] FIG44 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0074] FIG45 is a partially enlarged structural diagram of a display panel according to some embodiments;

[0075] FIG46 is an enlarged structural diagram of V4 in FIG45 ;

[0076] FIG47 is a cross-sectional structural diagram obtained based on the cross-sectional line G4-G4 in FIG46. DETAILED DESCRIPTION

[0077] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0078] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0079] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0080] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0081] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0082] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0083] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0084] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0085] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0086] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0087] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0088] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0089] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0090] In an embodiment of the present disclosure, FIG1 is a planar structural diagram of a display device 10000. To clearly describe the structure of the display device 10000, only a portion of the first sub-pixel regions P1 is shown in the figure, and the number of the first sub-pixel regions P1 is not limited to that shown in the figure.

[0091] As shown in Figures 1 and 2, some embodiments of the present disclosure provide a display device 10000. The display device 10000 can be any device that displays any image, whether in motion (e.g., video), stationary (e.g., still image), text, or text. More specifically, it is contemplated that the embodiments described herein can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0092] In some embodiments, as shown in FIG1 and FIG2 , the display device 10000 includes a display module 1000 and a backlight module 2000 , wherein the display module 1000 is disposed on the light-emitting side of the backlight module 2000 . The backlight module 2000 is configured to provide backlight to the display module 1000 .

[0093] The display module 1000 also has a display area AA and a light-transmitting area BB located on at least one side of the display area AA. The backlight module 2000 has a first backlight area BG1 and a second backlight area BG2. The display area AA of the display module 1000 is projected onto the backlight module 2000 as an orthographic projection within the first backlight area BG1, while the light-transmitting area BB of the display module 1000 is projected onto the backlight module 2000 as an orthographic projection within the second backlight area BG2.

[0094] For example, the first backlight area BG1 and the second backlight area BG2 can be independently controlled to be turned on and off.

[0095] Based on this, when the display area AA does not display an image, the first backlight area BG1 is turned off, and the second backlight area BG2 can be turned on, so that the light-transmitting area BB can also emit light when the display module 1000 does not display an image.

[0096] For example, the backlight module 2000 may be a direct-lit backlight module or an edge-lit backlight module, and may be adaptively designed as needed, which is not limited in the present disclosure.

[0097] For example, the display device 10000 may further include a sensor 300 disposed in the sensor area CC. The sensor includes but is not limited to at least one of a camera module, a fingerprint recognition module, a light sensor, and a microphone module.

[0098] For example, the display device 10000 may further include a frame and other electronic components, etc. The display module 1000 may be disposed within the frame, for example.

[0099] As shown in Figure 3, the display module 1000 includes a display panel 100 and a circuit board 200. The circuit board 200 is electrically connected to the display panel 100. The circuit board 200 is configured to send drive signals to the display panel 100. The drive signals include, but are not limited to, display drive signals and / or touch drive signals. Driven by the circuit board 200, the display panel 100 displays images and / or responds to touch operations.

[0100] The circuit board 200 includes but is not limited to a PCB (Printed Circuit Board) or an FPC (Flexible Printed Circuit).

[0101] Figures 4 to 7 are planar structural diagrams of the display panel 100. To clearly illustrate the configuration of the light-transmitting area BB, the figures only illustrate the positional relationship between the display area AA, the light-transmitting area BB, and the sensor area CC of the display panel 100. It is understood that the display panel 100 also includes other structures.

[0102] In some embodiments, as shown in FIG. 1 and FIG. 4 to FIG. 7 , the display panel 100 has a display area AA and a light-transmitting area BB located on at least one side (one side or at least two sides) of the display area AA.

[0103] The sensor area CC can be located within the display area AA or on at least one side of the display area AA, which is not limited in this disclosure. The light-transmitting area BB can emit light of at least one (one or at least two) colors, including but not limited to at least one of red, green, blue, orange, or white.

[0104] In some examples, the light-transmitting area is configured to change the color of the emitted light based on the operating state of the camera module sensor. The light-transmitting area BB is configured to change the color of the emitted light based on the operating state of the sensor 300 within the sensor area CC. The operating states of the sensor 300 include an on state and an off state. The light-transmitting area BB is configured to emit light of one color in response to the on state of the sensor 300, and to emit light of a different color or no light in response to the off state of the sensor 300.

[0105] When the sensor 300 is in the off state, the light-transmitting area BB does not emit light. When the sensor 300 is in the working state, the light-transmitting area BB may emit green light, red light, blue light, orange light or white light.

[0106] When the light-transmitting area BB emits light both when the sensor 300 is in the on state and in the off state, the light-transmitting area BB may emit green light when the sensor 300 is in the on state, and emit red light when the sensor 300 is in the off state; or the light-transmitting area BB may emit blue light when the sensor 300 is in the on state, and emit orange light when the sensor 300 is in the off state.

[0107] The specific adaptive design can be carried out according to actual needs, which is only used as an example and not as a limitation to the present disclosure.

[0108] For example, when the sensor 300 is in the on state, the light-transmitting area BB may emit light of different colors depending on the operating state of the sensor 300. For example, when the sensor 300 is in the first operating state, the light-transmitting area BB emits light of a first color; when the sensor 300 is in the second operating state, the light-transmitting area BB emits light of a second color. The first and second colors may be the same color or different colors, which is not limited in this disclosure.

[0109] Based on this, when the sensor 300 is a camera module, when the camera module is in the state of taking pictures, the light-transmitting area BB emits the first color light; when the camera module is in the state of recording videos, the light-transmitting area BB emits the second color light.

[0110] For example, the number of sensors 300 may be one or more.

[0111] When the display module 1000 includes one sensor 300 , the sensor 300 is disposed in one sensor region CC.

[0112] When the display module 1000 includes multiple sensors 300, the multiple sensors 300 can be respectively arranged in multiple sensor zones CC, that is, one sensor 300 is arranged in each sensor zone CC; or, the multiple sensors 300 are arranged in the same sensor zone CC, that is, multiple sensors 300 are arranged in one sensor zone CC.

[0113] The number of sensors 300 and the specific implementation of the sensors 300 can be adaptively designed according to actual needs. This is only used as an example and not as a limitation to the present disclosure.

[0114] In some embodiments, the display module 1000 may include one sensor 300 and one light-transmitting area BB. In this case, the light-transmitting area BB changes its luminous color based on changes in the operating state of the sensor 300. Alternatively, the display module 1000 may include one sensor 300 and multiple light-transmitting areas BB. In this case, at least one of the multiple light-transmitting areas BB changes its luminous color based on the operating state of the sensor 300.

[0115] The light-transmitting area BB may change its luminous color according to the operating state of the sensor 300. When the sensor 300 is in the operating state, the light-transmitting area BB emits light of one color. When the sensor 300 is in the non-operating state, the light-transmitting area BB emits light of another color. The difference in luminous color of the light-transmitting area BB can be used to distinguish whether the sensor 300 is in the operating state.

[0116] Alternatively, the light-transmitting area BB may change its luminous color by emitting or not emitting light in accordance with the operating state of the sensor 300. For example, when the sensor 300 is in the operating state, the light-transmitting area BB associated with the sensor 300 emits light, while when the sensor 300 is in the non-operating state, the light-transmitting area BB does not emit light. Whether the sensor 300 is in the operating state is determined by whether the light-transmitting area BB associated with the sensor 300 emits light.

[0117] The display module 1000 may also include a plurality of sensors 300 and a light-transmitting area BB. In this case, the light-transmitting area BB emits light of a color according to a change in the operating state of at least one of the plurality of sensors 300.

[0118] For example, when all of the plurality of sensors 300 are in a non-operating state, the light-transmitting area BB does not emit light or emits light of a first color; when at least one of the plurality of sensors 300 is in an operating state, the light-transmitting area BB emits light of a second color, and the color of the emitted light of the second color is different from the color of the emitted light of the first color.

[0119] The display module 1000 may also include a plurality of sensors 300 and a plurality of light-transmitting areas BB, and each light-transmitting area BB is correspondingly arranged with one sensor 300. In this case, each light-transmitting area BB changes the color of the emitted light according to a change in the operating state of the sensor 300 associated therewith.

[0120] Exemplarily, the number of the light-transmitting areas BB is greater than or equal to 1. The shape of the light-transmitting area BB includes but is not limited to at least one of a circle, an ellipse, a square, a rhombus, a rectangle, an L shape, a "匚" shape or a "囗" shape.

[0121] When the display panel 100 includes one light-transmitting area BB, the light-transmitting area BB may be located on at least one side of the display area AA. Exemplarily, the light-transmitting area BB is located on any one side of the display area AA (for example, on the upper side of the display area AA), and its shape may be a circle (as shown in FIG. 1), an ellipse, a square, a rhombus or a rectangle. Another exemplarily, the light-transmitting area BB may be located on at least two sides of the display area. For example, as shown in FIG. 4, the light-transmitting area BB is located on two sides of the display area, forming an L shape; another example, as shown in FIG. 5, the light-transmitting area BB is located on three sides of the display area, forming a "匚" shape; another example, as shown in FIG. 6, the light-transmitting area BB is located on four sides of the display area, forming a "囗" shape.

[0122] As shown in FIG. 7, when the display panel 100 includes a plurality of light-transmitting areas BB, each light-transmitting area BB may be located on at least one side of the display area AA. Exemplarily, each light-transmitting area BB is located on one side of the display area AA; the plurality of light-transmitting areas BB may be all arranged on the same side of the display area AA or respectively arranged on different sides of the display area AA. For example, the display panel 100 includes M1 (M1≥2) light-transmitting areas BB1, and the M1 light-transmitting areas BB1 are located on the same side of the display area AA, and the M1 light-transmitting areas BB1 are arranged along the extending direction of the edge of the display area. Another example, the display panel 100 includes M2 (M2≥2) light-transmitting areas BB2, and the M2 light-transmitting areas BB2 are located on the same side of the display area AA, and the M1 light-transmitting areas BB2 are arranged along the direction perpendicular to the edge of the display area AA.

[0123] The light-transmitting area BB is located outside the display area AA of the display panel 100. Therefore, the light-transmitting area BB does not affect the normal display of the display. There are no fixed requirements for the number, shape, size, luminous color, and setting position of the light-transmitting area BB. It can be adaptively designed according to actual needs, increasing the design flexibility of the display panel 100.

[0124] In some embodiments, as shown in FIG1 , the display area AA of the display panel 100 is configured to display an image under the drive of the circuit board 200. One frame of image is displayed in one display frame of the display area AA. The refresh rate of the display panel 100 may be 60 Hz or 120 Hz, etc. For example, the refresh rate of the display panel 100 is 60 Hz; that is, within 1 second, a continuous plurality of frames (for example, 60 frames) of images can be displayed in the display area AA, and the continuous plurality of frames of images may be the same image or may be non-completely the same image. Then, the length of one display frame is Ts, and Ts is 1 / 60 second.

[0125] As shown in FIG1 , the display area AA of the display panel 100 includes a plurality of first sub-pixel areas P1 , each of which is configured to emit light of one color, and at least two of the plurality of first sub-pixel areas P1 emit light of different colors.

[0126] The plurality of first sub-pixel regions P1 may include, for example, a red light first sub-pixel region P1(R) emitting red light, a green light first sub-pixel region P1(G) emitting green light, and a blue light first sub-pixel region P1(B) emitting blue light. The plurality of first sub-pixel regions P1 may also include a white light first sub-pixel region P1(W) emitting white light.

[0127] 1 , the display panel 100 includes a light-transmitting area BB configured to emit light of one color within a light-emitting period Tf of the light-transmitting area BB. The light-transmitting areas BB may emit light of the same color or light of different colors within two adjacent light-emitting periods Tf.

[0128] FIG8 is an enlarged structural diagram of the region V1 in FIG1 , which only shows a portion of the first sub-pixel region P1 and a portion of the second sub-pixel region P2 . The number of the first sub-pixel region P1 and the portion of the second sub-pixel region P2 is not limited to that shown in the figure.

[0129] As shown in FIG8 , the light-transmitting area BB of the display panel 100 includes one or more second sub-pixel areas P2, each of which is configured to emit light of a single color. At least two of the plurality of second sub-pixel areas P2 emit light of different colors, or all of the plurality of second sub-pixel areas P2 emit light of the same color.

[0130] When the light-transmitting area BB includes second sub-pixel areas P2 of multiple (two or more) light-emitting colors, the light-transmitting area BB includes at least one (or more) light-transmitting units (also referred to as repeating minimum units or pixel units), each of which includes a second sub-pixel area P2 of a different light-emitting color. The light-transmitting area BB emitting light of one color during a light-emitting period Tf means that all light-transmitting units within the light-transmitting area BB emit light of the same color during the light-emitting period Tf.

[0131] For example, the light-transmitting area BB includes a plurality of light-transmitting units, each of which includes a red second sub-pixel area P2(R) and a green second sub-pixel area P2(G). During a light-emitting period Tf, the red second sub-pixel area P2(R) emits red light, and the green second sub-pixel area P2(G) does not emit light. In this case, each light-transmitting unit emits red light, and the light-transmitting area BB emits red light. Alternatively, during a light-emitting period Tf, the red second sub-pixel area P2(R) emits red light, and the green second sub-pixel area P2(G) emits green light. In this case, each light-transmitting unit simultaneously emits red light and green light, which are mixed to form yellow light, and the light-transmitting area BB emits yellow light.

[0132] For another example, the light-transmitting area BB includes multiple light-transmitting units, each of which includes a red second sub-pixel area P2(R), a green second sub-pixel area P2(G), and a blue second sub-pixel area P2(B). During a light-emitting period Tf, the red second sub-pixel area P2(R) emits red light, while the green second sub-pixel area P2(G) and the blue second sub-pixel area P2(B) do not emit light. In this case, each light-transmitting unit emits red light, and the light-transmitting area BB emits red light. Alternatively, during a light-emitting period Tf, the red second sub-pixel area P2(R) emits red light, the green second sub-pixel area P2(G) emits green light, and the blue second sub-pixel area P2(B) emits blue light. In this case, each light-transmitting unit simultaneously emits red light, green light, and blue light, which are mixed to form white light, and the light-transmitting area BB emits white light.

[0133] For another example, the light-transmitting area BB includes multiple light-transmitting units, each of which includes a white-light second sub-pixel region P2(W). During a light-emitting period Tf, the multiple white-light second sub-pixel regions P2(W) emit white light. In this case, each light-transmitting unit emits white light, and the light-transmitting area BB emits white light.

[0134] Of course, the light-transmitting area BB may also include only one light-transmitting unit, which includes a red second sub-pixel area P2(R), a green second sub-pixel area P2(G), and a blue second sub-pixel area P2(B). During a light-emitting period Tf, the red second sub-pixel area P2(R) emits red light, while the green second sub-pixel area P2(G) and the blue second sub-pixel area P2(B) do not emit light. In this case, each light-transmitting unit emits red light, and the light-transmitting area BB emits red light. Alternatively, during a light-emitting period Tf, the red second sub-pixel area P2(R) emits red light, the green second sub-pixel area P2(G) emits green light, and the blue second sub-pixel area P2(B) emits blue light. In this case, the light-transmitting unit simultaneously emits red light, green light, and blue light, which are mixed to form white light, and the light-transmitting area BB emits white light.

[0135] The duration during which all the second sub-pixel regions P2 emitting light of the same color are driven to emit light each time may be referred to as a light-emitting period Tf.

[0136] When the light-transmitting area BB includes a second sub-pixel area P2, the light-emitting color of the second sub-pixel area P2 can be any color, such as any one of red, green, blue, orange and white. In this case, the duration of each driving of the second sub-pixel area P2 to emit light is referred to as a light-emitting period Tf.

[0137] When the light-transmitting area BB includes multiple second sub-pixel areas P2, the multiple second sub-pixel areas P2 can all be any color, such as any one of red, green, blue, orange, and white. For example, the multiple second sub-pixel areas P2 emit light of the same color. In this case, the duration of each drive of all the second sub-pixel areas P2 to emit light can be referred to as a light-emitting period Tf. For another example, if at least two of the multiple second sub-pixel areas P2 emit light of different colors, in this case, the duration of each drive of all the second sub-pixel areas P2 to initially emit light of the same color can be referred to as a light-emitting period Tf.

[0138] For example, the plurality of second sub-pixel regions P2 may include a red second sub-pixel region P2 (R) emitting red light, and a green second sub-pixel region P2 (G) emitting green light.

[0139] At this time, the duration of driving all the red second sub-pixel regions P2 to emit light once is one lighting cycle Tf, and the duration of driving all the green second sub-pixel regions P2 to emit light once is also one lighting cycle Tf.

[0140] During the same light-emitting period Tf, the light-transmitting area BB of the display panel 100 emits light of the same color. For example, the light-transmitting area BB of the display panel 100 can emit red light during at least one (one or multiple) light-emitting periods Tf, and can emit green light during another at least one (one or multiple) light-emitting periods Tf.

[0141] For another example, the plurality of second sub-pixel regions P2 further include a blue second sub-pixel region P2 (B) emitting blue light.

[0142] At this time, the time it takes to drive all the red light second sub-pixel areas P2(R) to emit light once is one light-emitting period Tf, the time it takes to drive all the green light second sub-pixel areas P2(G) to emit light once is also one light-emitting period Tf, and the time it takes to drive all the blue light second sub-pixel areas P2(B) to emit light once is also one light-emitting period Tf.

[0143] During a light-emitting period Tf, the light-transmitting area BB of the display panel 100 emits light of at least two colors. For example, during at least one (one or multiple consecutive) light-emitting period Tf, the red second sub-pixel area P2(R), the green second sub-pixel area P2(G), and the blue second sub-pixel area P2(B) all emit light; and during at least one (one or multiple consecutive) light-emitting period Tf, the red second sub-pixel area P2(R), the green second sub-pixel area P2(G), and the blue second sub-pixel area P2(B) do not emit light.

[0144] In this way, the light emitted by the red second sub-pixel region P2(R), the green second sub-pixel region P2(G), and the blue second sub-pixel region P2(B) is mixed, allowing the light-transmitting area BB of the display panel 100 to emit white light during at least one (one or multiple) light-emitting periods Tf. The red second sub-pixel region P2(R), the green second sub-pixel region P2(G), and the blue second sub-pixel region P2(B) do not emit light, and the light-transmitting area BB of the display panel 100 can also not emit light during at least one (one or multiple) light-emitting periods Tf.

[0145] For another example, the plurality of second sub-pixel regions P2 are all white light second sub-pixel regions P2 (W) emitting white light.

[0146] At this time, the duration of driving all the second white light sub-pixel regions P2 to emit light once is one light emitting period Tf.

[0147] In this way, the light-transmitting area BB of the display panel 100 can emit white light in at least one (one or multiple consecutive) light-emitting period Tf, and the light-transmitting area BB of the display panel 100 can not emit light in another at least one (one or multiple consecutive) light-emitting period Tf.

[0148] The colors of the light emitted from the first sub-pixel region P1 and the second sub-pixel region P2 can be adaptively designed according to actual needs. This is an exemplary description and is not intended to limit the present disclosure.

[0149] In some application scenarios, the light-transmitting area BB may serve as an ambient light or a “breathing light” of the display panel 100 , and the light-transmitting area BB may emit light of different colors statically or dynamically.

[0150] A light-emitting phase of the light-transmitting area BB includes multiple consecutive light-emitting periods Tf, and the light-transmitting area BB emits light in these multiple consecutive light-emitting periods Tf. When two adjacent light-emitting periods Tf of the light-transmitting area BB are discontinuous, these two adjacent light-emitting periods Tf belong to different light-emitting phases.

[0151] Based on this, the term "statically emitting light of different colors from the light-transmitting area BB" herein refers to the light-transmitting area BB emitting light of the same color within the same lighting phase. The term "dynamically emitting light of different colors from the light-transmitting area BB" refers to the light-transmitting area BB emitting light of the same or different colors within multiple consecutive lighting cycles Tf, and the light-transmitting area BB can emit light of different colors within the same lighting phase.

[0152] In some embodiments, the structure of the display panel 100 described above is described in detail. The display panel 100 may be a liquid crystal display (LCD) panel. The display panel 100 includes: a first substrate 1 and a second substrate 6 disposed opposite each other; a liquid crystal layer 4 disposed between the first substrate 1 and the second substrate 6; and a sealing frame 5 disposed between the first substrate 1 and the second substrate 6. The sealing frame 5 surrounds the liquid crystal layer 4, and the inner sidewalls of the sealing frame 5 define a liquid crystal sealing area SA. The display area AA, the light-transmitting area BB, and the sensor area CC are all located within the liquid crystal sealing area SA.

[0153] When the display panel 100 is an LCD display panel, in some embodiments of the present disclosure, both the display area AA and the light-transmitting area BB utilize the liquid crystal layer 4 to emit light, thereby improving the utilization rate of the liquid crystal layer 4. In some embodiments of the present disclosure, light-emitting display in the light-transmitting area BB can be achieved without the need for additional light-emitting devices (e.g., light-emitting diodes). Compared to technical solutions that utilize light-emitting devices within the light-transmitting area BB to achieve light-emitting display, the structure of the display panel 100 can be simplified and the number of steps required to manufacture the display panel 100 can be reduced.

[0154] Furthermore, to ensure normal display of the display area AA, the coverage of the liquid crystal layer 4 is larger than the display area AA. In other words, the display area AA is within the edge (outer contour) of the liquid crystal layer 4. For example, in an orthographic projection onto the first substrate 1, the liquid crystal layer 4 surrounds the display area AA.

[0155] In some embodiments of the present disclosure, the light-transmitting area BB also facilitates the emission of light from the liquid crystal layer 4. For example, the light-transmitting area BB is located within the liquid crystal layer 4, that is, within the edge (outer contour) of the liquid crystal layer 4. Compared to solutions that place light-emitting devices within the light-transmitting area BB to achieve emission, where the light-emitting devices need to be located outside the liquid crystal layer 4, this embodiment can reduce the width of the bezel AN of the display panel 100, thereby increasing the screen-to-body ratio of the display panel 100.

[0156] Figure 9 is an enlarged structural diagram of region V2 in Figure 2. Figure 10 is a cross-sectional structural diagram of the display panel taken along the cross-sectional line G2G2 in Figure 8. For the purpose of illustrating the positional relationship between the first sub-pixel region P1 and the second sub-pixel region P2, which are closest to each other, only a portion of the second sub-pixel region P2 and a portion of the first sub-pixel region P1 are shown in the figure.

[0157] In some embodiments, as shown in Figures 9 and 10, the display panel 100 further includes: a first pixel circuit 2 and a second pixel circuit 3 disposed between the first substrate 1 and the second substrate 6. The first pixel circuit 2 is located in the display area AA, and the second pixel circuit 3 is located in the light-transmitting area BB. The area defined by a single first pixel circuit 2 is a first sub-pixel area P1, and the area defined by a single second pixel circuit 3 is a second sub-pixel area P2.

[0158] The first pixel circuit 2 includes a first pixel electrode 21 and a first common electrode 22 . The first pixel electrode 21 and the first common electrode 22 are configured to drive the movement of liquid crystal molecules in the area defined by the first pixel circuit 2 in the liquid crystal layer 4 .

[0159] The second pixel circuit 3 includes a second pixel electrode 31 and a second common electrode 32 . The second pixel electrode 31 and the second common electrode 32 are configured to drive the movement of liquid crystal molecules in the area defined by the second pixel circuit 3 in the liquid crystal layer 4 .

[0160] The display area AA includes multiple first sub-pixel areas P1, and the light-transmitting area BB includes one or more second sub-pixel areas P2. The first sub-pixel area P1 and the second sub-pixel area P2 are both liquid crystal display areas. The display panel 100 also includes a pixel circuit for driving the movement of liquid crystal molecules in the corresponding areas of the display area AA and the light-transmitting area BB. The pixel circuit drives the deflection of the liquid crystal molecules to control the transmittance of the light emitted by the backlight module 2000, thereby realizing image display on the display module 1000.

[0161] The backlight module 2000 emits light of one color. To enable the display module 1000 to achieve color display, in some embodiments, as shown in FIG9 and FIG10 , the display panel 100 further includes a color filter layer CF. The color filter layer CF includes a plurality of filter portions G.

[0162] The plurality of filter portions G at least include a plurality of first filter portions G1 located in the display area AA. The plurality of first filter portions G1 are correspondingly disposed to the plurality of first sub-pixel areas P1. The plurality of first filter portions G1 include filter portions G of at least two filtering colors.

[0163] Exemplarily, the at least two filter color filter portions G are at least two of the first color filter portion G, the second color filter portion G, and the third color filter portion G. The first color, the second color, and the third color may be three primary colors, such as red, green, and blue.

[0164] Based on this, the first filter G1 includes but is not limited to a red filter G, a green filter G, and a blue filter G. The filters G of different colors are configured to pass light within a set wavelength range and block light of other wavelengths.

[0165] For example, the backlight module 2000 may emit white light, and the wavelength range of the light emitted by the backlight module 2000 is, for example, 390 nm to 780 nm.

[0166] When the light emitted by the backlight module 2000 passes through the red light filter, the light with a wavelength range of 625nm to 740nm can pass through the red light filter and be emitted, while the light with other wavelengths will be blocked by the red light filter and cannot be emitted, thereby ensuring that the light emitted through the red light filter is red light.

[0167] When the light emitted by the backlight module 2000 passes through the green light filter, the light with a wavelength range of 500nm to 570nm can pass through the green light filter and be emitted, while the light with other wavelengths will be blocked by the green light filter and cannot be emitted, thereby ensuring that the light emitted through the green light filter is green light.

[0168] When the light emitted by the backlight module 2000 passes through the blue light filter, the light with a wavelength range of 450nm to 490nm can pass through the blue light filter and be emitted, while the light with other wavelengths will be blocked by the blue light filter and cannot be emitted, thereby ensuring that the light emitted through the blue light filter is blue light.

[0169] In some embodiments, the at least one second sub-pixel region P2 included in the light-transmitting area BB is configured to emit light of the same color, and the light emitted by the light-transmitting area BB has the same color as the light emitted by the backlight module 2000 .

[0170] Based on this, the light emitted by the backlight module 2000 can be emitted directly after passing through the display module 1000 without changing the luminous color, that is, the color filter layer CF can be provided with the filter part G in the area corresponding to the second sub-pixel area P2. In this case, the thickness of the color filter layer CF in the area corresponding to the second sub-pixel area P2 is 0.

[0171] In some other embodiments, as shown in FIG. 10 , the light-transmitting area BB includes at least one of the second sub-pixel regions P2 , and the light emitted by the light source is different in color from the light emitted by the backlight module 2000 .

[0172] Based on this, as shown in Figure 10, the color filter layer CF further includes: one or more second filter portions G2 located in the light-transmitting area BB, each second filter portion G2 being corresponding to a second sub-pixel area P2. The plurality of second filter portions G2 include filter portions G of at least one filtering color.

[0173] In the case where the light-transmitting area BB may include one or more second sub-pixel areas P2, the color filter layer CF may include a second filter portion G2, which is disposed corresponding to the light-transmitting area BB. A single second filter portion G2 may be disposed corresponding to one or more second sub-pixel areas P2. Alternatively, the color filter layer CF may include multiple second filter portions G2, each of which is disposed corresponding to a second sub-pixel area P2.

[0174] In some embodiments, as shown in FIG9 and FIG10 , the color filter layer CF includes a first filter portion G1 and a second filter portion G2 , and the first filter portion G1 and the second filter portion G2 are disposed in the same layer.

[0175] It should be noted that the term "same layer" as used in this disclosure refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then using the same mask through a single patterning process. Alternatively, different film-forming processes may be used to form the same film layer structure. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, or may include an evaporation process. The specific patterns in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0176] The first filter portion G1 and the second filter portion G2 may be disposed in different film layer structures or in the same film layer structure. When the first filter portion G1 and the second filter portion G2 are disposed in the same layer, they may be formed in the same process step, thereby reducing the number of steps in manufacturing the display panel 100.

[0177] In some embodiments, the filter portions G having the same filter color are disposed in the same layer.

[0178] The filter portions of the same color can be formed simultaneously in the same process step, thereby reducing the number of steps in manufacturing the display panel 100 .

[0179] In the case where the color filter layer CF includes only the first filter portion G1, the first filter portion G1, for example, includes multiple first color light filter portions, multiple second color light filter portions, and multiple third color light filter portions. The multiple first color light filter portions are arranged on the same layer and can be formed in the same process step, the multiple second color light filter portions are arranged on the same layer and can be formed in the same process step, and the multiple third color light filter portions are arranged on the same layer and can be formed in the same process step, thereby reducing the preparation steps of the display panel 100.

[0180] Based on this, the plurality of first color light filters, the plurality of second color light filters, and the plurality of third color light filters can be arranged in the same layer, which is conducive to achieving a lightweight and thin design of the display panel 100 compared to the layered arrangement of the filter portions G of different filter colors.

[0181] When the color filter layer CF includes a first filter portion G1 and a second filter portion G2, the first filter portion G1, for example, includes multiple first color light filter portions, multiple second color light filter portions, and multiple third color light filter portions, and the second filter portion G2, for example, includes at least one first color light filter portion. The second filter portion G2 is arranged on the same layer as the first color light filter portion included in the first filter portion G1 and can be formed in the same process step.

[0182] In this way, compared with the layered arrangement of the first filter portion G1 and the second filter portion G2 , the number of manufacturing steps of the display panel 100 is reduced, and a lightweight and thin design of the display panel 100 is also achieved.

[0183] 9 , the display panel 100 further includes a black matrix layer BM configured to block light emitted between adjacent first sub-pixel regions P1 to prevent color mixing in the display area AA.

[0184] For example, the boundary line of the black matrix layer BM is located outside the boundary line of the liquid crystal sealing area SA, so as to avoid light leakage problem of the display panel 100.

[0185] 9 , the black matrix layer BM has a plurality of first openings K1 located in the display area AA, and the first openings K1 are arranged corresponding to the first pixel electrodes 21. Along the arrangement direction of the light-transmitting area BB and the display area AA, the distance between two adjacent first openings K1 is q.

[0186] As shown in FIG. 1 , the light-transmitting area BB is located on one side of the display area AA along the first direction X. The arrangement direction of the light-transmitting area BB and the display area AA is the first direction X shown in FIG. 1 .

[0187] For example, each first filter portion G1 may be disposed in one first opening K1 . In this way, the first filter portion G1 and the black matrix layer BM are disposed in the same layer, which is conducive to achieving a lighter and thinner display panel 100 .

[0188] In some embodiments, as shown in FIG. 10 , the black matrix layer BM further has a second opening K2 located in the light-transmitting area BB. The second opening K2 is as large as the light-transmitting area BB.

[0189] In this case, the light-transmitting area BB may include a second sub-pixel area P2 . The second opening K2 may be provided with any one of the second filter portion G2 , the transparent filling portion, and the scattering particle portion.

[0190] When the second filter portion G1 is disposed in the second opening K2 , the second filter portion G2 is disposed on the same layer as the black matrix layer BM, which is beneficial for achieving a lighter and thinner display panel 100 .

[0191] In some embodiments, the display area AA is adjacent to the light-transmitting area BB. As shown in Figure 9, each first sub-pixel area P1 is located within a first opening K1 of the black matrix layer BM. Adjacent first sub-pixel areas P1 are separated by the black matrix layer BM to prevent color mixing of light emitted from adjacent first sub-pixel areas P1, thereby ensuring that each first sub-pixel area P1 only emits light of one color. Therefore, there is a spacing of q (the distance between two adjacent first openings K1) between two adjacent first sub-pixel areas P1. Based on this, when the display area AA is adjacent to the light-transmitting area BB, the boundary of the first sub-pixel area P1 closest to the light-transmitting area BB is also surrounded by the black matrix layer BM, and there is also a spacing between the first sub-pixel area P1 and the second sub-pixel area P2 that are closest to each other.

[0192] In this case, the interval between the adjacent first sub-pixel area P1 and the second sub-pixel area P2 is the distance w between the two adjacent first openings K1 and the second opening K2 along the arrangement direction of the light-transmitting area BB and the display area AA, and w may be smaller than the distance q between the two adjacent first openings K1.

[0193] For example, as shown in Figures 9 and 10, along the arrangement direction of the light-transmitting area BB and the display area AA, for example, the first direction X shown in Figure 10, the distance between the closest first opening K1 and the second opening K2 is w, and 0.5q≤w≤1.5q. The distance w between the closest first opening K1 and the second opening K2 can be 0.5q, q, 1.2q, or 1.5q, etc.

[0194] In other embodiments, as shown in Figures 2 and 8, the display area AA is spaced apart from the light-transmitting area BB. In this case, for example, as shown in Figures 9 and 10, along the arrangement direction of the light-transmitting area BB and the display area AA, for example, the first direction X shown in Figure 10, the distance between the closest first opening K1 and the second opening K2 is w, and w>1.5q. The distance w between the closest first opening K1 and the second opening K2 can be 1.65q, 6.5q, 8q, 15q, or 20q, etc.

[0195] In some other embodiments, as shown in FIG. 10 , the black matrix layer BM further has a plurality of third openings K3 located in the light-transmitting area BB, and the third openings K3 are disposed corresponding to the second pixel electrodes 31 .

[0196] In this case, the light-transmitting area BB may include multiple second sub-pixel areas P2. The black matrix layer BM is further configured to isolate light emitted between adjacent second sub-pixel areas P2 to prevent color mixing in the light-transmitting area BB. The third opening K3 may contain any of the second filter portion G2, a transparent filling portion, or a scattering particle portion.

[0197] When the second filter portion G1 is disposed in the third opening K3 , the second filter portion G2 is disposed on the same layer as the black matrix layer BM, which is beneficial for achieving a lightweight and thin display panel 100 .

[0198] For example, along the arrangement direction of the light-transmitting area BB and the display area AA, for example, the first direction X shown in FIG10 , the distance r between the closest first opening K1 and the closest third opening K3 is 0.5q≤r≤1.5q, or r>1.5q. In some examples, the distance r between the closest first opening K1 and the closest third opening K3 can be 0.5q, 1.2q, or 1.5q, etc. In other examples, the distance r between the closest first opening K1 and the closest third opening K3 can be 1.65q, 6.5q, 8q, 15q, or 20q, etc.

[0199] The arrangement of the light-transmitting area BB and the display area AA and the arrangement of the first opening K1 and the second opening K3 can be found in the above description of the first opening K1 and the second opening K2 and will not be repeated here.

[0200] Based on the above, by controlling the distance between the first opening K1 and the third opening K3 that are closest to each other, when the size of the light-transmitting area BB is the same, the smaller the distance between the first opening K1 and the third opening K3, as shown in FIG1 , the frame AN ​​of the display panel 100 along the arrangement direction of the light-transmitting area BB and the display area AA, for example, the dimension d4 along the first direction X shown in FIG1 can also be correspondingly smaller, which is conducive to realizing a narrow frame design of the display panel 100.

[0201] In some embodiments, as shown in FIG. 11 , the thickness of the black matrix layer BM in the region corresponding to the sensor region CC is 0.

[0202] Based on this, in some examples, the sensor region CC is outside the boundary line of the black matrix layer BM in an orthographic projection onto the first substrate 1. In other examples, as shown in FIG11 , in an orthographic projection onto the first substrate 1, the boundary line of the black matrix layer BM surrounds the sensor region CC, and the black matrix layer BM has a fourth opening K4 corresponding to the sensor region CC.

[0203] By not providing the black matrix layer BM in the area corresponding to the sensor region CC, the black matrix layer BM can be prevented from blocking light, thereby ensuring the light transmittance of the sensor region CC and ensuring the normal operation of the sensor.

[0204] In some embodiments, the display panel 100 has no conductive material within the sensor region CC.

[0205] No conductive material is provided in the sensor area CC, which can reduce the loss of light when entering the sensor area CC and increase the light transmittance in the sensor area CC.

[0206] Based on this, in some other embodiments, the display panel 100 does not have an interlayer insulating layer in the sensor region CC. An interlayer insulating layer is, for example, an insulating film layer between adjacent conductive film layers. If there is no conductive material in the sensor region CC, the interlayer insulating layer may not be provided in the sensor region CC. This can reduce light loss when entering the sensor region CC and increase light transmittance in the sensor region CC.

[0207] In some embodiments, the thickness of the first alignment layer Q1 and / or the second alignment layer Q2 within the area defined by the sensor region CC is zero.

[0208] The first alignment layer Q1 and / or the second alignment layer Q2 are made of a light-transmitting material. Without removing the first alignment layer Q1 and / or the second alignment layer Q2 within the area defined by the sensor region CC, the light transmittance of the sensor region CC meets design requirements. However, removing at least one of the first alignment layer Q1 and the second alignment layer Q2 within the area defined by the sensor region CC improves the light transmittance of the sensor region CC compared to the case where the first alignment layer Q1 and the second alignment layer Q2 are not removed.

[0209] In some embodiments, as shown in Figures 10 and 11, the first pixel electrode 21 is disposed on the first substrate 1, and the display panel 100 further includes: a first polarizer POL1 disposed on a side of the first substrate 1 away from the second substrate 6, and a second polarizer POL2 disposed on a side of the second substrate 6 away from the first substrate 1.

[0210] In the orthographic projection onto the first substrate 1 , the light-transmitting area BB overlaps with both the first polarizer POL1 and the second polarizer POL2 , and at least a portion of the sealing frame 5 is located outside the boundary of the first polarizer POL1 .

[0211] Exemplarily, the sealing frame portion 5 is made of sealant, for example. When forming the sealing frame portion 5 , the sealant is filled in a set position, and then the sealant is cured by light irradiation or other methods to form the sealing frame portion 5 .

[0212] The polarizer will block part of the light and convert it into linearly polarized light. Therefore, there will be a certain loss of light passing through the polarizer. By locating at least a portion of the sealing frame 5 outside the boundary of the first polarizer POL1, light can be directly irradiated on the sealant when curing the sealant, which is conducive to rapid curing of the sealant and improves the preparation efficiency of the display panel 100.

[0213] As shown in Figure 10, in the area corresponding to the sealing frame portion 5, a black matrix layer BM is further arranged between the second substrate 6 and the liquid crystal layer 4. In other embodiments, during the preparation of the display panel 100, light is irradiated from the side of the second substrate 6 to the sealant for light curing. In order to avoid the black matrix layer BM blocking the light, at least a portion of the sealing frame portion 5 is located outside the boundary of the black matrix layer BM, thereby ensuring that the light can be directed to the sealant.

[0214] Based on this, at least a portion of the sealing frame 5 is also located outside the boundary of the second polarizer POL2. In this way, when curing the sealant, light can directly irradiate the sealant, which is conducive to rapid curing of the sealant and improves the production efficiency of the display panel 100.

[0215] Figure 12 is an enlarged structural diagram of the display panel, based on region V1 in Figure 1. To clearly illustrate the positional relationship between the polarizer POL, support structure 10, light-transmitting area BB, and sensor area CC, the figure only shows the polarizer POL, support structure 10, light-transmitting area BB, and sensor area CC, without showing the remaining structures in the display panel.

[0216] In some embodiments, as shown in FIG. 12 , the sensor region CC is located outside the boundary of the first polarizer POL1 , and the second polarizer POL2 has a fifth opening K5 corresponding to the sensor region CC.

[0217] With this design, no polarizer POL is provided in the area corresponding to the sensor area CC, thereby ensuring the light transmittance of the sensor area CC.

[0218] In some embodiments, as shown in FIG. 12 , in an orthographic projection onto the first substrate 1 , the fifth opening K5 surrounds the sensor region CC.

[0219] Such a design can ensure that light can pass through the fifth opening K5 and enter the sensor region CC without being blocked by the second polarizer POL2 , thereby ensuring the light transmittance of the sensor region CC.

[0220] In some embodiments, as shown in FIG12 , in the orthographic projection onto the first substrate 1 , the display area AA and the light-transmitting area BB fall within the range of the first polarizer POL1 , and the minimum distance between the boundary of the first polarizer POL1 and the boundary of the display area AA and the light-transmitting area BB is d1 , 0<d1≤3 mm.

[0221] Any boundary of the first polarizer POL1 is located outside the boundary between the display area AA and the light-transmitting area BB. The distance between the boundary of the first polarizer POL1 and the boundary between the display area AA and the light-transmitting area BB can be 0.2 mm, 1 mm, 1.7 mm or 3 mm.

[0222] Parts of the edge of the polarizer POL may not effectively polarize light (the inactive area of ​​the polarizer POL). Furthermore, during assembly of the display panel 100, there may be some deviation between the actual coverage area of ​​the polarizer POL and the target coverage area. Therefore, the actual size of the polarizer POL should be larger than the size of the area it is required to cover, ensuring that the active area of ​​the polarizer POL fully covers the display area AA and the light-transmitting area BB.

[0223] In some embodiments, as shown in FIG12 , the display panel 100 further includes a support structure 10. In an orthographic projection onto the first substrate 1, the support structure 10 is located outside the boundary of the first polarizer POL1 and extends along the boundary of the first polarizer POL1; the support structure 10 avoids the sensor area CC.

[0224] Exemplarily, the support structure 10 and the first polarizer POL1 are arranged side by side along a plane parallel to the first substrate 1 , and the distances between the support structure 10 and the first polarizer POL1 and the first substrate 1 are the same or substantially the same.

[0225] The support structure 10 is, for example, disposed around a boundary line of the first polarizer POL1 .

[0226] By providing the support structure 10 to surround the first polarizer POL1, on the one hand, the edge portion of the first polarizer POL1 can be prevented from being damaged by bumps. On the other hand, by providing the support structure 10, the thickness of the portion outside the boundary line of the first polarizer POL1 is increased, and the thickness uniformity of the display panel 100 can be ensured.

[0227] For example, the support structure 10 can be made of foam tape. The foam tape is designed to avoid the sensor area CC and the light-transmitting area BB, thereby ensuring that the support structure 10 does not block the sensor area CC and the light-transmitting area BB, thereby ensuring the light transmittance of the sensor area CC and the luminous effect of the light-transmitting area BB.

[0228] In some embodiments, as shown in FIG12 , the minimum distance between the support structure 10 and the first polarizer POL1 is d2, d2 ≥ 6 μm. The distance d2 between the support structure 10 and the first polarizer POL1 can be 6 μm, 6.3 μm, or 8.5 μm.

[0229] During the manufacturing process of the display panel 100, the order of assembling the support structure 10 and the first polarizer POL1 is not limited. By controlling the minimum distance between the support structure 10 and the first polarizer POL1, it is possible to effectively avoid the situation in which the support structure 10 and the first polarizer POL1 affect each other during the manufacturing process of the display panel 100, causing the other to deviate from the set position, thereby ensuring that the support structure 10 and the first polarizer POL1 can be relatively accurately placed in the target area.

[0230] In some embodiments of the present disclosure, the first pixel electrode 21 and the first common electrode 22 may be disposed on the same side of the liquid crystal layer 4 , or may be disposed on two sides of the liquid crystal layer 4 .

[0231] In the case where the first pixel electrode 21 and the first common electrode 22 are both disposed on the same side of the liquid crystal layer 4, the first pixel electrode 21 and the first common electrode 22 may be both disposed between the liquid crystal layer 4 and the first substrate 1. Based on this, the first pixel electrode 21 and the first common electrode 22 may be disposed in the same layer, or they may be disposed in different layers.

[0232] For example, as shown in FIG10 , the first common electrode 22 is disposed on a side of the first pixel electrode 21 away from the first substrate 1. In this case, the display panel 100 further includes a first spacer layer 31 (e.g., an insulating layer) disposed between the first pixel electrode 21 and the first common electrode 22. Of course, the first common electrode 22 may also be disposed on a side of the first pixel electrode 21 close to the first substrate 1.

[0233] 10 , some embodiments of the present disclosure will be described below by taking an example where both the first pixel electrode 21 and the first common electrode 22 are disposed between the liquid crystal layer 4 and the first substrate 1 .

[0234] In some embodiments of the present disclosure, the second pixel electrode 31 and the second common electrode 32 may be disposed on the same side of the liquid crystal layer 4 , or may be disposed on two sides of the liquid crystal layer 4 .

[0235] When the display panel 100 includes multiple second pixel circuits 3 , for example, the second common electrodes 32 of the multiple second pixel circuits 3 may be an integrated structure, and the portion of the second common electrode layer corresponding to the area defined by each second pixel circuit 3 is one second common electrode 32 .

[0236] For another example, the multiple second common electrodes 32 are spaced apart from each other. Thus, compared to multiple second pixel circuits 3 sharing one second common electrode 32, the second common electrode 32 independently provided for each second pixel circuit 3 has a smaller area and lower resistance, and accordingly, the power consumption of the second pixel circuit 3 is lower. In this case, the multiple second common electrodes 32 can also be connected to each other via connecting wires, which can be provided in the same layer as the multiple second common electrodes 32, or provided on a side of the film layer where the multiple second common electrodes 32 are located that is closer to / farther from the first substrate 1.

[0237] The above is merely an illustrative description of some possible implementations of the present disclosure and is not intended to limit the present disclosure.

[0238] In the case where the second pixel electrode 31 and the second common electrode 32 are both disposed on the same side of the liquid crystal layer 4, the second pixel electrode 31 and the second common electrode 32 may be both disposed between the liquid crystal layer 4 and the first substrate 1. Based on this, the second pixel electrode 31 and the second common electrode 32 may be disposed in the same layer, or they may be disposed in different layers.

[0239] For example, as shown in FIG10 , the second common electrode 32 is disposed on a side of the second pixel electrode 31 away from the first substrate 1. In this case, the display panel 100 further includes a second spacer layer 32 (e.g., an insulating layer) disposed between the second pixel electrode 31 and the second common electrode 32. Of course, the second common electrode 32 is disposed on a side of the second pixel electrode 31 close to the first substrate 1.

[0240] 10 , some embodiments of the present disclosure will be described below by taking an example in which both the second pixel electrode 31 and the second common electrode 32 are disposed between the liquid crystal layer 4 and the first substrate 1 .

[0241] In some embodiments, as shown in FIG10 , the first pixel electrode 21 and the second pixel electrode 31 are disposed in the same layer.

[0242] In some examples, the first pixel electrode 21 and the second pixel electrode 31 are made of the same material. For example, both are made of a transparent conductive material, wherein the transparent conductive material may be ITO or IZO.

[0243] When the first pixel electrode 21 and the second pixel electrode 31 are made of the same material, the first pixel electrode 21 and the second pixel electrode 31 may be formed simultaneously through a single manufacturing process, thereby reducing the number of manufacturing steps for the display panel 100 .

[0244] In other examples, the first pixel electrode 21 and the second pixel electrode 31 are made of different materials. In the case where the first pixel electrode 21 and the second pixel electrode 31 are made of different materials, the first pixel electrode 21 and the second pixel electrode 31 can be formed separately and disposed on the same insulating material layer.

[0245] In some embodiments, as shown in FIG. 10 , the first common electrode 22 and the second common electrode 32 are disposed in the same layer.

[0246] The first common electrode 22 and the second common electrode may be formed of the same material. For example, both are made of a transparent conductive material, wherein the transparent conductive material may be ITO (indium tin oxide) or IZO (indium zinc oxide).

[0247] When the first common electrode 22 and the second common electrode 32 are made of the same material, they can be formed simultaneously in a single manufacturing process, thereby reducing the number of manufacturing steps for the display panel 100. Furthermore, the first common electrode 22 and the second common electrode 32 can be a single film structure or independently provided.

[0248] In some embodiments, as shown in FIG. 9 and FIG. 10 , the first spacer layer 23 and the second spacer layer 33 are disposed on the same layer.

[0249] The first spacer layer 23 and the second spacer layer 33 disposed in the same layer may be formed simultaneously through a single manufacturing process, thereby reducing the number of manufacturing steps for the display panel 100 .

[0250] Exemplarily, the first spacer layer 23 and the second spacer layer 33 are made of insulating material.

[0251] The materials of the first spacer layer 23 and the second spacer layer 33 include, but are not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like.

[0252] In some embodiments, as shown in FIG10 , the display panel 100 further includes: a first alignment layer Q1 disposed on a side of the liquid crystal layer 4 close to the first substrate 1 , and a second alignment layer Q2 disposed on a side of the liquid crystal layer 4 close to the second substrate 6 .

[0253] By providing a first alignment layer Q1 and a second alignment layer Q2, the liquid crystal molecules in the liquid crystal layer 4 are initially aligned, thereby determining the direction in which the liquid crystal molecules align when no electric field is applied. Therefore, the first alignment layer Q1 and the second alignment layer Q2 are provided on opposite sides of the liquid crystal layer 4 and in contact with the liquid crystal layer 4.

[0254] Figures 13 and 14 are enlarged structural diagrams of the first common electrode and the second common electrode. To facilitate a clear description of the structure of the first common electrode and the second common electrode, only a portion of the first common electrode and the second common electrode are shown in the figures. The number of first common electrodes and second common electrodes in the display panel is not limited to that shown in the figures.

[0255] In some embodiments, as shown in FIG. 13 , the first common electrode 22 has a first slit 221 , and the second common electrode 32 has a second slit 321 .

[0256] The first slits 221 can reduce the sheet resistance of the first common electrode 22, thereby reducing the power consumption of the display panel 100. The second slits 321 can reduce the sheet resistance of the second common electrode 32, thereby reducing the power consumption of the display panel 100.

[0257] The plurality of first slits 221 may constitute at least one slit group XF1', each slit group XF1' may be disposed corresponding to a first sub-pixel region P1. The plurality of second slits 321 may constitute at least one slit group XF1, each slit group XF1 may be disposed corresponding to a second sub-pixel region P2.

[0258] There is no limitation on the number and shape of the first slits 221 and the second slits 321 , and they can be arbitrarily set as needed.

[0259] The following description will be made by taking the shapes of the first slit 221 and the second slit 321 as “<” or “>” as an example.

[0260] In some embodiments, both the first alignment layer Q1 and the second alignment layer Q2 are rubbed alignment layers. As shown in FIG. 13 , the first slit 221 and the second slit 321 have the same shape.

[0261] In other embodiments, both the first alignment layer Q1 and the second alignment layer Q2 are photo-alignment layers, as shown in FIG. 13 or FIG. 14 , and the shapes of the first slit 221 and the second slit 321 are the same or different.

[0262] The above-mentioned same or different shapes of the first slit 221 and the second slit 321 refer to the same or different bending directions of the first slit 221 and the second slit 321. The preparation methods of the first alignment layer Q1 and the second alignment layer Q2 are described below.

[0263] In some embodiments, as shown in FIG15 , a method for preparing an array substrate includes the following steps.

[0264] S1. Form a first alignment layer Q1 on a first substrate 1; the first substrate 1 has a display area AA and a light-transmitting area BB located on at least one side of the display area AA.

[0265] S2. Form a first common electrode 22 and a second common electrode 32 on the first alignment layer Q1; the first common electrode 22 is located in the display area AA, and the second common electrode 32 is located in the light-transmitting area BB; the first common electrode 22 has a plurality of first slits 221 , and the second common electrode 32 has a plurality of second slits 321 .

[0266] The first and second alignment layers Q1 and Q2 are formed by a rubbing alignment process, and the first and second slits 221 and 321 have the same shape; or, the first and second alignment layers Q1 and Q2 are formed by a photoalignment process, and the first and second slits 221 and 321 have the same or different shapes.

[0267] When the first alignment layer Q1 and the second alignment layer Q2 are formed by a rubbing alignment process, the orientation directions of the orientation grooves formed in the first alignment layer Q1 in the areas corresponding to the display area AA and the light-transmitting area BB are the same. Accordingly, the directions of the first slits 221 on the first common electrode 22 and the second slits 321 on the second common electrode 32 need to be consistent, thereby ensuring the display effect of the display panel 100.

[0268] When the first alignment layer Q1 and the second alignment layer Q2 are formed by a photo-alignment process, the orientation directions of the orientation grooves formed in the first alignment layer Q1 in the areas corresponding to the display area AA and the light-transmitting area BB can be the same or different. Accordingly, the first slit 221 on the first common electrode 22 and the second slit 321 on the second common electrode 32 can be the same or different.

[0269] Figures 16 and 18 are planar structural diagrams of the display panel 100. To clearly illustrate the positional relationship between the circuit structure 7 and the light-transmitting area BB, Figure 16 only shows the sealing frame 5, the circuit structure 7, and a portion of the first common electrode 22, while Figure 18 only shows the sealing frame 5, the circuit structure 7, the first common electrode line COM1, the common electrode sub-line Vcom, and a portion of the first common electrode 22. It will be understood that the display panel 100 also includes other structures besides those shown in Figures 16 and 18.

[0270] In some embodiments, as shown in FIG16 , the display panel 100 further includes a circuit structure 7 outside the display area AA. The circuit structure 7 and the light-transmitting area BB are arranged side by side along at least one side boundary of the display area AA.

[0271] As shown in Figures 7 and 16, when the display panel 100 includes one or more (two or more) light-transmitting areas BB located on one side of the display area AA, the circuit structure 7 can be arranged side by side with the light-transmitting area BB along the extension direction of one side boundary of the display area AA.

[0272] As shown in FIG4 , when the display panel 100 includes at least one light-transmitting area BB located on both sides of the display area AA, the circuit structure 7 may also be arranged side by side along the extension direction of multiple sides (two sides or more) of the boundary of the display area AA.

[0273] The circuit structure 7 only needs to include a conductive pattern. In the display panel 100 , the circuit structure 7 can be powered, but cannot be unpowered. The circuit structure 7 includes, for example, at least one of a common electrode line COM, a ground line GND, and a third pixel circuit 8 .

[0274] As shown in Figures 16 and 17, this embodiment adopts a design in which the circuit structure 7 and the light-transmitting area BB are arranged side by side along the boundary extension direction of the display area AA. Compared with the design in which the light-transmitting area BB is located on the side of the circuit structure 7 away from the display area AA, or the light-transmitting area BB is located between the circuit structure 7 and the light-transmitting area BB, since in this embodiment, the light-transmitting area BB occupies a part of the position of the original circuit structure 7, there is no need to provide additional layout space for the light-transmitting area BB in the width direction of the frame AN ​​of the display panel 100. Therefore, the dimension d4 in the width direction of the frame AN ​​of the display panel 100 can also be correspondingly smaller, which is conducive to realizing the narrow frame design of the display panel 100.

[0275] As shown in FIG. 17 , there may be a gap d5 between the circuit structure 7 and the light-transmitting area BB. The gap d5 is smaller than or equal to the outer dimensions of the light-transmitting area BB, for example, the dimension of the light-transmitting area BB along the second direction Y.

[0276] For example, d5≥6 μm. The interval d5 between the circuit structure 7 and the light-transmitting area BB may be 6 μm, 6.3 μm, or 8.5 μm.

[0277] Specifically, the circuit structure 7 includes a conductive pattern provided in the same layer as the second common electrode 32 , and a gap d5 is formed between the conductive pattern and the second common electrode 32 .

[0278] In some embodiments, as shown in FIG. 18 , the display panel 100 further includes a bonding area BA located on one side of the display area AA, and the circuit board 200 is electrically connected to the circuit board 200 in the bonding area BA.

[0279] Exemplarily, at least one second pixel circuit 3 is provided in the light-transmitting area BB. As shown in Figures 19 and 22 , a plurality of second pixel circuits 3 are provided in the light-transmitting area BB, and the plurality of second pixel circuits 3 are arranged in a plurality of rows and a plurality of columns.

[0280] Each row of second pixel circuits 3 is coupled to a second gate line GL2, for example, as shown in Figures 19 and 22. The second gate line GL2 is, for example, led out from the gap between the second common electrode 32 and the circuit structure 7, and is led out from the side of the second common electrode 22 and the circuit structure 7 close to the display area AA to the binding area BA.

[0281] In this case, as shown in FIG19 , multiple rows of second pixel circuits 3 are respectively coupled to multiple second gate lines GL2. Of course, as shown in FIG22 , multiple rows of second pixel circuits 3 can also be coupled to the same second gate line GL2. In this case, as shown in FIG20 and FIG21 , one light emission period Tf of the light-transmitting area BB refers to the duration during which all second gate lines GL2 provide one operating level to the second pixel circuits 3 coupled thereto.

[0282] For example, as shown in FIG19 , each row of second pixel circuits 3 is coupled to one second gate line GL2, and multiple rows of second pixel circuits 3 are respectively coupled to multiple second gate lines GL2. The multiple second gate lines GL2 may provide operating levels to the multiple rows of second pixel circuits 3 simultaneously, or sequentially provide operating levels to each row of second pixel circuits 3. In this case, one light-emitting period Tf of the light-transmitting area BB refers to the duration during which the multiple second gate lines GL2 provide one operating level to the multiple rows of second pixel circuits 3.

[0283] For another example, as shown in FIG22 , multiple rows of second pixel circuits 3 are coupled to the same second gate line GL2 , and the second gate line GL2 provides a working level to the multiple rows of second pixel circuits 3 for a duration of one light emitting period Tf.

[0284] Each column of the second pixel circuits 3 is coupled to, for example, a second data line DL2 . The second data line DL2 is, for example, led from the second common electrode 22 and the circuit structure 7 on a side close to the display area AA to the binding area BA.

[0285] In some embodiments, the circuit structure 7 includes a portion of the first common electrode line COM1. For example, as shown in FIG18 , the first common electrode line COM1 may have one end proximate to the light-transmitting area BB and the other end extending along the boundary of the display area AA to the binding area BA. Thus, a portion of the first common electrode line COM1 is arranged side by side with the light-transmitting area BB, while another portion extends into the binding area BA and is not arranged side by side with the light-transmitting area BB. The circuit structure 7 includes the portion of the first common electrode line COM1 arranged side by side with the light-transmitting area BB.

[0286] As shown in FIG. 18 , the first common electrode line COM1 is electrically connected to the first common electrode 22 .

[0287] The first common electrode line COM1 and the first common electrode may be formed in the same process step. Such a design is advantageous for simplifying the manufacturing steps of the display panel 100 .

[0288] 18 , the display panel 100 further includes a plurality of common electrode sub-lines Vcom, at least portions of which are located within the display area AA and electrically connected to the second common electrode 22 within the display area AA. At least one end of the common electrode sub-line Vcom extends outside the display area AA and is electrically connected to the first common electrode line COM1.

[0289] Based on this, the first common electrode line COM1 and the first common electrode 22 may be electrically connected through the common electrode sub-line Vcom.

[0290] The first common electrode line COM1 and the first common electrode 22 may be provided in the same layer, or they may be provided in different layers.

[0291] In the case that the first common electrode line COM1 and the first common electrode 22 are provided in the same layer, the common electrode sub-line Vcom may be provided in the same layer as the first common electrode 22 , or the two may be provided in different layers.

[0292] In the case that the common electrode sub-line Vcom and the first common electrode 22 are provided in different layers, the common electrode sub-line Vcom may be provided on a side of the first common electrode 22 close to or far away from the first substrate 1 .

[0293] In some embodiments, as shown in FIG. 20 and FIG. 22 , the first common electrode line COM1 is electrically connected to the second common electrode 32 .

[0294] In this embodiment, the second common electrode 32 occupies a portion of the original first common electrode line COM1, so there is no need to provide additional layout space for the second common electrode 32 in the width direction of the frame AN ​​of the display panel 100. Therefore, the dimension d4 in the width direction of the frame AN ​​of the display panel 100 can be correspondingly smaller, which is conducive to realizing the narrow frame design of the display panel 100.

[0295] In some embodiments, as shown in Figures 20 and 22 , the first common electrode line COM1 and the second common electrode 32 are disposed in the same layer with a gap g therebetween. The display panel 100 further includes a connecting line 9 , which is located on a side of the second common electrode 32 that is close to or away from the first substrate and spans the gap g. The first common electrode line COM1 is electrically connected to the second common electrode 32 via the connecting line 9 .

[0296] The first common electrode line COM1 and the second common electrode 32 transmit the same electrical signal, which is a common voltage signal. Therefore, the first common electrode line COM1 and the second common electrode 32 can be a single film structure. In this embodiment, by spacing the first common electrode line COM1 and the second common electrode 32 apart, the area of ​​the second common electrode 32 is smaller than if the first common electrode line COM1 and the second common electrode 32 were a single film structure. This reduces the resistance of the second common electrode 32, reduces the power consumption of the second pixel circuit 3, and thus reduces the power consumption of the display panel 100.

[0297] Exemplarily, the connection line 9 may be made of a conductive material such as a metal material or an alloy material. For example, the material of the connection line 9 includes but is not limited to at least one of gold, silver, copper, aluminum, nickel, or nickel-gold.

[0298] Exemplarily, the connection line 9 may be provided on a side of the second common electrode 32 close to or away from the first substrate 1 .

[0299] In some embodiments, the first common electrodes 22, the second common electrodes 32, and the common electrode lines COM are disposed in the same layer. Therefore, during the manufacturing process of the display panel 100, the first common electrodes 22, the second common electrodes 32, and the common electrode lines COM can be formed in the same process step, thereby reducing the number of manufacturing steps for the display panel 100.

[0300] The first common electrode 22, the second common electrode 32 and the common electrode line COM are designed to be spaced apart from each other. In this way, the first common electrode 22, the second common electrode 32 and the common electrode line COM are designed to be independently arranged. Compared with the design in which the first common electrode 22, the second common electrode 32 and the common electrode line COM are connected as a whole layer, the surface resistance of the first common electrode 22, the second common electrode 32 and the common electrode line COM can be reduced, thereby reducing the power consumption of the display panel 100.

[0301] Moreover, the first common electrode 22, the second common electrode 32 and the common electrode line COM can be connected to the same electrical signal. Therefore, by setting a connecting line 9, the independently separated first common electrode 22, the second common electrode 32 and the common electrode line COM can be connected to each other, thereby realizing the electrical connection between the first common electrode 22, the second common electrode 32 and the common electrode line COM.

[0302] In some embodiments, as shown in FIG19 , the first common electrode line COM1 has a plurality of first hollow portions 71. For example, the plurality of first hollow portions 71 may constitute at least one hollow group XF2, and each first hollow portion 71 in each hollow group XF2 may have the same or similar shape as a group of slits XF1 in a sub-pixel region (e.g., the second sub-pixel region P2) in the second common electrode 32.

[0303] During the manufacturing process of the display panel 100, when a plurality of second slits 321 are formed on the second common electrode, a conductive film layer may be formed entirely using the same film-forming process, and the conductive film layer may be subjected to a first patterning process to form the second slits 321 within the light-transmitting area BB. Subsequently, the conductive film layer may be subjected to a second patterning process to form the first common electrode lines COM1 and the second common electrodes 32 that are spaced apart. In this manner, due to process accuracy and other factors, during the second patterning process, one or more second pixel electrodes 32 formed within the light-transmitting area BB may not have the second slits 321, or the number of second slits 321 may be less than the designed number.

[0304] In this embodiment, a plurality of first hollow portions 71 are provided on the first common electrode line COM1. Thus, a plurality of second slits 321 and a plurality of first hollow portions 71 can be formed simultaneously in the first patterning process. Therefore, in the second patterning process, it can be ensured that the finally formed second common electrode 32 has a plurality of second slits 321.

[0305] In some embodiments, as shown in FIG. 23 , the connection line 9 extends to the area where the first common electrode line COM1 is located, and is electrically connected to the first common electrode line COM1 through a plurality of connection points in the area where the first common electrode line COM1 is located.

[0306] For example, in a direction perpendicular to the first substrate 1, when the connection line 9 and the first common electrode line COM1 are located in different conductive film layers, an insulating film layer is further provided between the conductive film layer where the connection line 9 is located and the conductive film layer where the first common electrode line COM1 is located. The connection point can be a connection hole penetrating the insulating film layer, and the conductive film layer where the connection line 9 is located and the conductive film layer where the first common electrode line COM1 is located are connected via the connection hole penetrating the insulating film layer. In this case, each connection hole serves as a connection point, and each first common electrode line COM1 is electrically connected to the first common electrode line COM1 via multiple connection holes.

[0307] Of course, in other embodiments, each first common electrode line COM1 may be electrically connected to the first common electrode line COM1 through a connection hole. In this case, the connection line 9 extends to the area where the first common electrode line COM1 is located, and is electrically connected to the first common electrode line COM1 through a connection point in the area where the first common electrode line COM1 is located.

[0308] In other embodiments, as shown in FIG23 , the display panel 100 includes a plurality of second common electrodes 32 , which are connected into an integral structure. The connecting line 9 extends to the light-transmitting area BB and is electrically connected to the integral structure through a plurality of connection points in the light-transmitting area BB.

[0309] By electrically connecting the connecting line 9 to the second common electrode 32 , the resistance of the second common electrode 32 can be reduced, thereby reducing the power consumption of the second pixel circuit 3 and further reducing the power consumption of the display panel 100 .

[0310] When the display panel 100 includes multiple (two or more) second common electrodes 32, the multiple second common electrodes 32 may be an integral structure formed integrally, or may be connected to each other via connecting wires to form an integral structure. The multiple second common electrodes 32 are connected to each other, so the connection points between the connecting wire 9 and the integral structure may be at least one (one or more) connection points corresponding to each second common electrode 32, or may be multiple connection points corresponding to one second common electrode 32.

[0311] In some other embodiments, as shown in Figure 23, one end of the connecting line 9 extends to the area where the first common electrode line COM1 is located, and is electrically connected to the first common electrode line COM1 through multiple connection points in the area where the first common electrode line COM1 is located; the other end of the connecting line 9 extends to the light-transmitting area BB, and is electrically connected to the integrated structure through multiple connection points in the light-transmitting area BB.

[0312] This embodiment can be a combination of the above two embodiments, and has the same structure and technical effects, which will not be described in detail here.

[0313] In this embodiment, by extending the connecting line 9 to the light-transmitting area BB and electrically connecting to the plurality of second common electrodes 32 , the resistance of the second common electrodes 32 can be better reduced, thereby facilitating a low-power design of the display panel 100 .

[0314] Moreover, in this embodiment, by setting the connecting line 9 to extend to the area where the first common electrode line COM1 is located and electrically connected to the first common electrode line COM1 through multiple connection points, compared with the case where the connecting line 9 is not set or the connecting line 9 is electrically connected to the first common electrode line COM1 through one connection point, the resistance value of the first common electrode line COM1 is lower, and thus the power consumption of the first common electrode line COM1 is lower, which is conducive to realizing a low-power design of the display panel 100.

[0315] In some embodiments, as shown in FIG. 23 and FIG. 24 , the display panel 100 further includes: a second common electrode line COM2 electrically connected to the first common electrode 22 ; and a width of the first common electrode line COM1 is greater than a width of the second common electrode line COM2 .

[0316] The display panel 100 includes multiple common electrode lines, and the second common electrode 22 occupies a portion of the wider one of the original multiple common electrode lines COM. Therefore, there is no need to provide additional layout space for the second common electrode 32 in the width direction of the frame AN ​​of the display panel 100. Therefore, the dimension d4 in the width direction of the frame AN ​​of the display panel 100 can be correspondingly smaller, which is conducive to realizing the narrow frame design of the display panel 100.

[0317] For example, as shown in Figures 23 and 24, the display panel 100 includes a first common electrode line COM1 and a second common electrode line COM2, and the width of the first common electrode line COM1 is greater than the width of the second common electrode line COM2. The wider one of the first common electrode line COM1 and the second common electrode line COM2 is arranged side by side with the light-transmitting area BB along the boundary extension direction of the display area AA, and the second common electrode 32 occupies part of the position of the original first common electrode line COM1.

[0318] As shown in Figures 23 and 24, the first common electrode line COM1 may be disposed on a side of the second common electrode line COM2 close to or away from the display area AA. Specific selections may be made based on design requirements and are not limited in this disclosure.

[0319] In some embodiments, as shown in FIG. 23 and FIG. 24 , the display panel 100 further includes at least one common electrode line COM, and the at least one common electrode line COM is electrically connected to the first common electrode 22 .

[0320] At least one common electrode line COM is electrically connected to the first common electrode 22, which means that when the display panel 100 includes one common electrode line COM, the common electrode line COM is electrically connected to the first common electrode 22; or, when the display panel 100 includes a first common electrode line COM1 and a second common electrode line COM2, at least one of the first common electrode line COM1 and the second common electrode line COM2 is electrically connected to the first common electrode 22.

[0321] When the display panel 100 includes a plurality of common electrode lines COM, the relative positional relationship of the plurality of common electrode lines COM along a direction perpendicular to the boundary of the display area AA is not limited. For example, the display panel 100 includes a first common electrode line COM1 and a second common electrode line COM2. As shown in FIG23 , the first common electrode line COM1 may be disposed on a side of the second common electrode line COM2 closer to the display area AA; or, as shown in FIG24 , the first common electrode line COM1 may be disposed on a side of the second common electrode line COM2 farther from the display area AA.

[0322] In some embodiments, as shown in FIG. 25 , the display panel 100 further includes an electrostatic discharge (ESD) protection circuit and a ground line GND. The ground line GND is electrically connected to the electrostatic discharge (ESD) protection circuit.

[0323] The electrostatic protection circuit ESD, for example, includes multiple protection transistors, the drains of which are electrically connected to the ground line GND, thereby conducting the static electricity in the display panel 100 through the ground line GND to form an electrostatic discharge channel, thereby preventing the static electricity from affecting the first pixel circuit 2 and the second pixel circuit 3.

[0324] Based on this, in some embodiments, as shown in FIG. 25 , the circuit structure 7 includes a portion of the ground line GND, the ground line GND is electrically insulated from the first common electrode 22 , and the ground line GND is electrically insulated from the second common electrode 32 .

[0325] The second common electrode 32 occupies a portion of the original ground line GND, so there is no need to provide additional space for the second common electrode 32 in the width direction of the frame AN ​​of the display panel 100. Therefore, the dimension d4 in the width direction of the frame AN ​​of the display panel 100 can be correspondingly smaller, which is conducive to realizing the narrow frame design of the display panel 100.

[0326] In some embodiments, the ground line GND and the second common electrode 32 are provided in the same layer with a gap therebetween; and / or the second common electrode 32 is electrically connected to one of the at least one common electrode line COM.

[0327] For example, the common electrode line COM is disposed outside the display area AA, and in an orthographic projection onto the first substrate 1, the common electrode line COM does not overlap with the light-transmitting area BB. In this case, the common electrode line COM can be made of a metal material. When the second common electrode 32 is made of a transparent conductive material, such as ITO, the resistance of the second common electrode 32 is relatively high. By electrically connecting the second common electrode 32 to the common electrode line COM made of a metal material, the resistance of the second common electrode 32 can be reduced, thereby reducing the power consumption of the display panel 100.

[0328] The second common electrode 32 can occupy a portion of at least one of the original common electrode line COM (for example, the first common electrode line COM1 and the second common electrode line COM2) and the ground line GND. There is no need to provide additional layout space for the second common electrode 32 in the width direction of the frame AN ​​of the display panel 100, which is conducive to realizing the narrow frame design of the display panel 100.

[0329] It should be noted that, in the direction along the extension direction perpendicular to the boundary line of the display area AA, the relative position relationship between the first common electrode line COM1, the second common electrode line COM2, the ground line GND and the electrostatic protection circuit ESD can be adaptively designed as needed. Figures 23, 24, 25 and 26 only show some possible relative position relationships between the first common electrode line COM1, the second common electrode line COM2, the ground line GND and the electrostatic protection circuit ESD, and do not serve as a limitation of the present disclosure.

[0330] To ensure the display quality of the display panel 100, the thickness of each film layer structure in the display area AA needs to be kept consistent, that is, in the multi-layer film layer structure arranged on the first substrate 1, the distance between each position on the same film layer structure and the first substrate 1 should be the same or approximately the same.

[0331] During the preparation of the display panel 100, in the process of forming multiple first pixel circuits 2 in the display area AA, taking the formation of the first pixel electrode 21 as an example, a conductive film layer can be first formed using a film forming process, and then the conductive film layer is patterned to form multiple first pixel electrodes 21.

[0332] When forming the conductive film layer, the thickness of the edge portion of the conductive film layer will be thinner than the thickness of the middle portion. In this way, the actual thickness of the first pixel electrodes 21 located at the periphery among the multiple first pixel electrodes 21 will be thinner than the required thickness. This may cause abnormal luminescence in the first sub-pixel area P1 corresponding to the peripheral first pixel electrodes 21.

[0333] Based on this, during the preparation of the display panel 100 , multiple third pixel circuits 8 can be formed simultaneously with the preparation of the first pixel circuit 2 . The third pixel circuits 8 are located outside the display area AA, and the areas defined by the third pixel circuits 8 do not emit light.

[0334] The plurality of third pixel circuits 8 may be arranged side by side along the extension direction of the boundary line of the display area AA. The third pixel circuit 8 includes a third pixel electrode 81 and a third common electrode 82. The third pixel electrode 81 is arranged in the same layer as the first pixel electrode 21, and the third common electrode 82 is an integral structure with the first common electrode 22.

[0335] In this way, the third pixel circuit 8 is formed at the same time as the first pixel circuit 2 is formed. In the process of forming the first pixel electrode 21 and the first common electrode 22, the first pixel electrode 21 and the first common electrode 22 obtained by patterning the conductive film layer have good thickness uniformity. The edge portion of the conductive film layer corresponds to the third pixel circuit 8. Since the third pixel circuit 8 is located outside the display area AA, it will not affect the picture display quality in the display area AA of the display panel 100.

[0336] Based on this, in some embodiments of the present disclosure, as shown in Figure 26, the display panel 100 also includes a third pixel circuit 8 located outside the display area AA. The third pixel circuit 8 can have the same structure as the first pixel circuit 2. For example, the third pixel circuit 8 includes a third pixel electrode 81 and a third common electrode 82.

[0337] Exemplarily, the third pixel circuit 8 is also located outside the light-transmitting area BB.

[0338] In some embodiments, the third pixel circuit 8 can be a dummy pixel circuit. Although it has the same structure as a normal display pixel circuit (e.g., the first pixel circuit 2), the circuit board 200 may not apply an electrical signal to the third pixel circuit 8. In this case, in a direction perpendicular to the first substrate 1, the third pixel circuit 8 is located within the range of the black matrix layer BM, and the light emitted from the area defined by the third pixel circuit 8 is blocked by the black matrix layer BM. By providing the third pixel circuit 8, no additional preparation steps are required for the display panel 100, and thickness differences caused by the preparation process can be avoided among the multiple first pixel electrodes 21 and the first common electrodes 22 in the display area AA.

[0339] In other embodiments, the circuit board 200 is further configured to apply an electrical signal to the third pixel circuit 8. The aforementioned light-transmitting area BB is referred to as the first light-transmitting area BB1. At least a portion of the third pixel circuit 8 is located in the second light-transmitting area BB2. The second light-transmitting area BB2 is located outside the display area AA and does not overlap with the first light-transmitting area BB1. In this case, the black matrix layer BM further includes an opening corresponding to the third pixel circuit 8 within the second light-transmitting area BB2 in a direction perpendicular to the first substrate 1. Light emitted from the area defined by the third pixel circuit 8 is not blocked by the black matrix layer BM.

[0340] Based on this, in some embodiments, the first common electrode line COM1 is provided on the same layer as the first common electrode 21. Based on this, the third common electrode 82 is provided on the same layer as the first common electrode line COM1. The third common electrode 82 and the first common electrode line COM1 can be an integral structure or have a gap between them.

[0341] Exemplarily, as shown in FIG. 26 , the third common electrode 82 and the first common electrode line COM1 are an integrated structure.

[0342] In some embodiments, as shown in FIG26 , the circuit structure 7 includes a third pixel circuit 8. The third pixel circuit 8 is located outside the display area AA. Therefore, the second common electrode 22 occupying at least a portion of the original third pixel circuit 8 does not affect the normal image display in the display area AA of the display panel 100, and facilitates the realization of a narrow-frame design for the display panel 100.

[0343] For example, the third common electrode 82 and the second common electrode 32 are provided in the same layer. Thus, the second common electrode 32 and the third common electrode 82 are simultaneously formed through a single film-forming process. The second common electrode 32 occupies a portion of the original third common electrode 82 . Therefore, there is no need to provide additional space for the second common electrode 32 in the width direction of the bezel AN of the display panel 100. Consequently, the dimension d4 of the display panel 100 in the width direction of the bezel AN can be correspondingly smaller, thereby facilitating a narrow-bezel design for the display panel 100.

[0344] For example, as shown in FIG26 , the third common electrode 82, the second common electrode 32, and the first common electrode line COM1 are disposed on the same layer. Thus, the second common electrode 32 occupies a portion of the original third common electrode 82 and the first common electrode line COM1. Therefore, there is no need to provide additional space for the second common electrode 32 in the width direction of the bezel AN of the display panel 100. Consequently, the dimension d4 in the width direction of the bezel AN of the display panel 100 can be correspondingly smaller, thereby facilitating a narrow bezel design for the display panel 100.

[0345] The specific structures of the first pixel circuit 2 and the second pixel circuit 3 are introduced below.

[0346] In some embodiments, as shown in Figures 27 and 28, the display panel 100 further includes a first gate line GL1, a first data line DL1, and a first transistor T1 located in the display area AA. The first gate line GL1 is electrically connected to the first transistor T1, and the first data line DL1 is coupled to the first pixel electrode 21 via the first transistor T1.

[0347] Exemplarily, as shown in FIG. 27 , the control electrode of the first transistor T1 is electrically connected to the first gate line GL1 , the first electrode of the first transistor T1 is electrically connected to the first data line DL1 , and the second electrode of the first transistor T1 is electrically connected to the first pixel electrode 21 .

[0348] The first transistor T1 is configured to transmit the first data signal provided by the first data line DL1 to the first pixel electrode 21 under the control of the voltage of the first gate line GL1 .

[0349] The display area AA includes multiple first sub-pixel regions P1, for example, arranged in an array. The first sub-pixel regions P1 of the same luminous color may be arranged in a row or in a column. Of course, the arrangement of the multiple first sub-pixel regions P1 within the display area AA is not limited to this. To facilitate the description of some embodiments of the present disclosure, the following describes some embodiments of the present disclosure using the example of first sub-pixel regions P1 of the same luminous color being arranged in a row.

[0350] Correspondingly, as shown in FIG. 28 , the plurality of first pixel circuits 2 in the display area AA are arranged in an array, for example.

[0351] As shown in Fig. 28, each first gate line GL1 is coupled to a row of first pixel circuits 2. As shown in Fig. 27 and Fig. 28, each first gate line GL1 is electrically connected to the control electrodes of a plurality of first transistors T1 arranged in a row.

[0352] In some embodiments, as shown in FIG28 , the display panel 100 further includes a first gate lines GL1 (m) and b first data lines DL1 (n), where a, b, m, and n are positive integers, and a≥m≥1, and b≥n≥1.

[0353] Exemplarily, as shown in FIG28 , the first pixel circuits 2 in the same column are coupled to the same first data line DL1 (n), and the first pixel circuits 2 in the same row are coupled to the same first gate line GL1 (m).

[0354] In this case, a plurality of first pixel circuits 2 are arranged in an array (a rows × b columns, a ≥ 2, b ≥ 2) within the display area AA, and the display area AA includes a plurality of first sub-pixel areas P1. Each first gate line GL1(m) provides a gate drive signal to the first pixel circuit 2 coupled thereto.

[0355] 28 and 29 , the display panel 100 further includes a second data line DL2 located in the light-transmitting area BB and coupled to the second pixel electrode 31 .

[0356] In some examples, as shown in FIG. 29 , the second data line DL2 is electrically connected to the second pixel electrode 31 .

[0357] As shown in Figures 29 and 30, in this case, the second sub-pixel region P2 emits light in response to the second data signal from the second data line DL2. When the second data signal is at an active level, the second sub-pixel region P2 is illuminated and the light-transmitting area BB is illuminated; when the second data signal is at an inactive level, the second sub-pixel region P2 does not emit light.

[0358] As shown in Figures 29 and 30, during the light-emitting phase of the light-transmitting area BB, the second data line DL2 transmits a second data signal to the second pixel electrode 31 to drive the light-transmitting area BB to emit light. The light-emitting phase of the light-transmitting area BB includes at least one light-emitting period Ts. During the non-light-emitting phase Toff of the light-transmitting area BB, the light-transmitting area BB does not emit light.

[0359] As shown in Figure 30, in order to avoid solidification of liquid crystal molecules in the liquid crystal layer 4, in the light-emitting stage of the light-transmitting area BB, the second data signal provided by the second data line DL2 is an electrical signal that alternates between positive and negative (for example, the voltage value corresponding to the second data signal alternates between +5V and -5V); in the non-light-emitting stage of the light-transmitting area BB, the second data line DL2 will also transmit an electrical signal that alternates between positive and negative to the second pixel electrode 31, but the light-transmitting area BB will not emit light.

[0360] It should be noted that when the second pixel electrode 31 is electrically connected to the second data line DL2 , the luminous state of the light-transmitting area BB may be related to or unrelated to the working state of the sensor 300 in the sensor area CC. Specific adaptive design can be performed as needed.

[0361] When the luminous state of the light-transmitting area BB is related to the operating state of the sensor 300 in the sensor area CC, the second data signal provided by the second data line DL2 can be a synchronous data signal of the operating state of the sensor. For example, when the sensor is in the operating state, the second data signal provided by the second data line DL2 is at an operating level, and the light-transmitting area BB is illuminated; when the sensor is in the non-operating state, the second data signal is at a non-operating level, and the light-transmitting area BB does not emit light.

[0362] In this way, whether the light-transmitting area BB emits light can be used to intuitively show whether the sensor 300 is in a working state. Of course, different colors of light emitted by the light-transmitting area BB can also correspond to different working states of the sensor 300.

[0363] The above is merely an exemplary description of some specific embodiments of the present disclosure. The data signal input terminal connected to the second pixel electrode 31 can be selected as needed. This is merely an exemplary description of some possible embodiments and does not limit the present disclosure.

[0364] In some other examples, as shown in FIG31 , the display panel 100 further includes a second transistor T2 , the second gate line GL2 is electrically connected to the second transistor T2 , and the second data line DL2 is coupled to the second pixel electrode 31 through the second transistor T2 .

[0365] Exemplarily, as shown in FIG31 , the control electrode of the second transistor T2 is electrically connected to the second gate line GL2 , the first electrode of the second transistor T2 is electrically connected to the second data line DL2 , and the second electrode of the second transistor T2 is electrically connected to the second pixel electrode 31 .

[0366] The second transistor T2 is configured to transmit the second data signal provided by the second data line DL2 to the second pixel electrode 31 under the control of the voltage of the second gate line GL2 .

[0367] As shown in Figures 31 and 32, when the voltage transmitted from the second gate line GL2 to the control electrode of the second transistor T2 is at an operating level, the second transistor T2 is turned on, and the second data signal provided by the second data line DL2 can be transmitted to the second pixel electrode 32 through the second transistor T2.

[0368] As shown in FIG31 , FIG32 and FIG33 , when the second gate line GL2 transmits the working level to the control electrode of the second transistor T2 and the second data line DL2 provides the second data signal at the working level, the light-transmitting area BB is illuminated.

[0369] In some embodiments, some of the first sub-pixel regions P1 and the second sub-pixel regions P2 included in the display panel 100 are arranged in a row.

[0370] As shown in Figures 31 and 32, when both the first pixel electrode 2 and the second pixel circuit 3 adopt an active drive mode (the display panel 100 includes a first transistor T1 and a second transistor T2), the first pixel electrode 21 and the second pixel electrode 31 arranged in a row can be coupled to the same data line DL or to different data lines DL. When at least one of the first pixel circuit 2 and the second pixel circuit 3 adopts a passive drive mode, the first pixel electrode 21 and the second pixel electrode 31 need to be coupled to different data lines DL, respectively.

[0371] In some embodiments, as shown in FIG31 , the display panel 100 includes a first transistor T1 and a second transistor T2, and the second data line DL2 is electrically connected to the first data line DL1. The first pixel electrode 21 and the second pixel electrode 31 in the same column can be considered to be coupled to the same data line DL, and the portion of the data line DL electrically connected to the first transistor T1 is the first data line DL1, and the portion electrically connected to the second transistor T2 is the second data line DL2.

[0372] One frame of the display panel 100 includes a picture display phase and a blanking phase, and one light-emitting period Tf of the light-transmitting area BB falls within one frame of the display panel 100. The first data line DL1 transmits a first data signal to the first pixel electrode 21 during the picture display phase, and transmits a second data signal to the second pixel electrode 31 during the light-emitting period Tf.

[0373] A frame of the display panel 100 is a frame of the display area AA. A frame of the display area AA is, for example, one of the display frames described above. During the display frame, the first pixel circuit 2 drives the liquid crystal molecules of the liquid crystal layer 4 within the area defined by the first pixel circuit 2 to move. The area defined by the first pixel circuit 2 is, for example, the first sub-pixel area P1 described above.

[0374] Each display frame includes at least: a data writing phase, a picture display phase and a blanking phase.

[0375] In the data writing phase, the first data line DL1 transmits a display data signal to the first pixel electrode 21 coupled thereto, so as to drive the first sub-pixel region P1 to emit light for display.

[0376] In the blanking phase, the first data line DL1 transmits the second data signal to the second pixel electrode 31 coupled thereto, so as to drive the second sub-pixel region P2 to emit light.

[0377] With this design, time-sharing multiplexing of the first data line DL1 is achieved. The same data line DL transmits electrical signals to the first pixel electrode 21 and the second pixel electrode 31 in a time-sharing manner, thereby reducing the number of data lines DL in the display panel 100 and simplifying the structure of the display panel 100.

[0378] Exemplarily, the light-emitting phase of the light-transmitting area BB includes at least one light-emitting period Tf. When the first pixel electrode 21 and the second pixel electrode 31 are coupled to the same data line DL, during the light-emitting phase of the light-transmitting area BB, the light-emitting period Tf of the light-transmitting area BB is shorter than the duration of the blanking phase of the display area AA.

[0379] The first data line DL1 transmits the second data signal to the second pixel electrode 31 during the blanking phase of the display area AA, and the light-emitting phase of the light-transmitting area BB includes at least one light-emitting period Tf. Therefore, the blanking phase of the display area AA is longer than the light-emitting period Tf.

[0380] For example, the first data line DL1 may transmit the second data signal to the second pixel electrode 31 during the blanking period of each frame in the display area AA, or may transmit the second data signal to the second pixel electrode 31 during the blanking period every k frames (k≥2).

[0381] As shown in Figures 31, 32, and 33, during the light-emitting period Tf, the duration during which the voltage of the second gate line GL2 is at the effective level is shorter than the duration of the light-emitting period Tf. Based on this, the first data line DL1 may continuously transmit the second data signal to the second pixel electrode 31 in the display area AA during the blanking phase, and the voltage of the second gate line GL2 may continuously be at the effective level or periodically be at the effective level during the blanking phase.

[0382] When the multiple rows of second pixel circuits 3 included in the display panel 100 are coupled to the same second gate line GL2 , the duration for the second gate line GL2 to provide a working level to the multiple rows of second pixel circuits 3 is one light emitting period Tf.

[0383] In the case where each second gate line GL2 is coupled to a row of second pixel circuits 3, multiple rows of second pixel circuits 3 are respectively coupled to multiple second gate lines GL2, and the multiple second gate lines GL2 may provide operating levels to the multiple rows of second pixel circuits 3 simultaneously, or the multiple second gate lines GL2 may provide operating levels to the multiple rows of second pixel circuits 3 in sequence. In this case, a light-emitting period Tf of the light-transmitting area BB refers to the total duration during which all second gate lines GL2 provide an operating level to the multiple rows of second pixel circuits 3.

[0384] In other embodiments, as shown in FIG32 , the display panel 100 includes a first transistor T1 and a second transistor T2 , the second data line DL2 is insulated from the first data line DL1 , and the first pixel electrode 21 and the second pixel electrode 31 in the same column are insulated from each other.

[0385] In some embodiments, as shown in FIG. 28 , FIG. 31 , and FIG. 32 , when the display panel 100 includes the first transistor T1 , the display panel 100 further includes: a first gate driving circuit 12 .

[0386] In some examples, as shown in FIG28 and FIG34 , the first gate driver circuit 12 includes a first shift register unit SR1(j), which is disposed outside the display area AA. A single first shift register unit SR1(j), for example, is coupled to a row of first pixel circuits 2. A single shift register SR1(j), for example, is coupled to at least one first gate line GL1(m).

[0387] The first shift register unit SR1(j) may be located in the liquid crystal sealing area SA.

[0388] In other examples, as shown in FIG28 and FIG34 , the gate driving circuit 12 includes k cascaded first shift registers SR1(j), and each shift register SR1(j) is coupled to at least one first gate line GL1(m). Here, k and j are positive integers, k≥j≥1, and m≥k≥2.

[0389] The following description takes an example where k cascaded shift registers SR1 (j) are each coupled to a first gate line GL1 (m), and each first gate line GL1 (m) is coupled to a row of first pixel circuits 2.

[0390] In some embodiments, as shown in Figure 34, the first shift register SR1(j) includes a signal input terminal IPT, a first signal output terminal GOUT1, a second signal output terminal OUTC and a reset signal terminal RST, the first signal output terminal GOUT1 of each level of shift register SR1(j) is coupled to the gate line G(m), the second signal output terminal OUTC of the j-th level shift register SR1(j) is coupled to the signal input terminal IPT of the j+1-th level shift register SR1(j+1), and the second signal output terminal OUTC of the j-th level shift register SR1(j) is coupled to the reset signal terminal RST of the j-1-th level shift register SR1(j-1).

[0391] Exemplarily, as shown in FIG34 , except for the first-stage first shift register SR1(1), the signal input terminal IPT of each stage first shift register SR1(j) is coupled to the second signal output terminal OUTC of its previous stage shift register SR1(j-1).

[0392] Except for the last first shift register SR1(k), the reset signal terminal RST of each first shift register SR1(j) is coupled to the second signal output terminal OUTC of the next shift register SR1(j+1).

[0393] It should be noted that the first-stage first shift register SR1 ( 1 ) and the last-stage first shift register SR1 ( k ) are relative, depending on the forward scanning and reverse scanning of the gate driving circuit 12 .

[0394] When the gate drive circuit 12 is used to perform forward scanning on the first gate line GL1(m), according to the scanning order of the first gate line GL1(m), the first first gate line GL1(1) is first input with a scanning signal. Therefore, the first shift register SR1(j) that provides the scanning signal to the first first gate line GL1(1) is the first-stage first shift register SR1(1); and the first shift register SR1(j) that provides the scanning signal to the last first gate line GL1(a) is the last-stage first shift register SR1(k).

[0395] The signal outputted by the second signal output terminal OUTC serves as the cascade signal of the gate drive circuit 12. The second signal output terminal OUTC of the j-th first shift register SR1(j) is coupled to the signal input terminal IPT of the j+1-th first shift register SR1(j+1), thereby triggering the j+1-th first shift register SR1(j+1). The second signal output terminal OUTC of the j-th first shift register SR1(j) is coupled to the reset signal terminal RST of the j-1-th first shift register SR1(j-1), thereby resetting the j-1-th first shift register SR1(j-1).

[0396] When the gate drive circuit 12 is used to reversely scan the first gate line GL1(m), according to the scanning order of the first gate line GL1(m), the last first gate line GL1(a) is first input with a scanning signal. Therefore, the first shift register SR1(j) that provides the scanning signal to the first gate line GL1(a) is the first-stage first shift register SR1(1); and the shift register that provides the scanning signal to the first first gate line GL1(1) is the last-stage first shift register SR1(k).

[0397] Based on the above, as shown in Figure 34, the signal input terminal IPT of the first-stage first shift register SR1(1) is coupled to the start signal terminal STV, for example, and the reset signal terminal RST of the last-stage first shift register SR1(k) is coupled to the above-mentioned start signal terminal STV, for example.

[0398] The start signal terminal STV is used to output a start signal. After receiving the start signal, the first shift register SR1 (1) of the first stage of the gate driving circuit 12 starts to scan the first gate line GL1 (m) line by line.

[0399] In this case, when the start signal of the start signal terminal STV is input to the signal input terminal IPT of the first-stage first shift register SR1(1), the reset signal terminal RST of the last-stage first shift register SR1(k) can use the start signal of the start signal terminal STV as a reset signal to reset the last-stage first shift register SR1(k).

[0400] Here, the reset signal terminal RST of the last stage first shift register SR1 (k) may also be independently provided with an initialization signal terminal, and the initialization signal terminal may transmit a reset signal to the reset signal terminal RST of the last stage first shift register SR1 (k).

[0401] In some embodiments, the gate driving circuit 12 further includes, for example, peripheral signal lines, which provide operating signals to the first shift register SR1 (j).

[0402] The first shift register SR1(j) is mainly composed of devices such as transistors and capacitors. During the operation of the first shift register SR1(j), the voltages of each node of the shift register (such as the first node PU1, the first pull-down point PD1 and the second pull-down node PD2) and the signal output terminal (such as the first signal output terminal GOUT1 and the second signal output terminal OUTC) are controlled through transistors and capacitors, thereby realizing the output of the signal.

[0403] For example, a single first shift register SR1 ( j ) transmits a signal to the first gate line GL1 ( m ) coupled thereto, and each first gate line GL1 ( m ) transmits the aforementioned electrical signal to a row of first pixel circuits 2 coupled thereto.

[0404] The signal output by a single first shift register SR1 (j) is transmitted to a row of first pixel circuits 2 through a first gate line GL1 (m), thereby controlling the brightness of the first sub-pixel regions P1 in the row to achieve color display.

[0405] Exemplarily, the transistors included in the first shift register SR1 (j) include but are not limited to thin film transistors or field effect transistors or other devices with the same characteristics.

[0406] The source (source electrode) of the transistor is called the first electrode, and the drain (drain electrode) is called the second electrode. Alternatively, the drain can be called the first electrode and the source can be called the second electrode. According to the form in the figure, the middle end of the transistor is defined as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain.

[0407] Exemplarily, the thin film transistors in the first shift register SR1 (j) are all oxide transistors. For example, the material of the active layers of the thin film transistors is all oxide.

[0408] The transistor used in the embodiments of the present disclosure can be a P-type switching transistor or an N-type switching transistor. The P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level; the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level.

[0409] It should be noted that, in the first shift register SR1(j) of the present embodiment, in actual use, the type of each transistor is not limited. Each transistor can be set as an N-type switching transistor or a P-type switching transistor as needed. When the transistors in the shift register are N-type transistors, the effective level of each transistor is a high-level signal.

[0410] The effective levels (also called working levels, working voltages, etc.) of the signal input terminal IPT, the first voltage signal terminal VDD1, the second voltage signal terminal VDD2, the third voltage signal terminal VGL, the fourth voltage signal terminal LVGL, the start signal terminal STV and the reset signal terminal RST are correspondingly set to high level signals.

[0411] It should be noted that Figure 34 shows an exemplary structure of the first shift register SR1(j) and the sub-circuits included therein. Those skilled in the art will understand that the first shift register SR1(j) and the sub-circuits included therein are not limited to the structure shown in Figure 34, as long as their functions can be achieved.

[0412] In addition, the voltages of multiple signals and nodes in various embodiments of the present disclosure correspond to operating levels and non-operating levels (also referred to as first voltage and second voltage, or first target voltage and second target voltage, etc.). The operating level and non-operating level only represent two different voltage state quantities of the signal, and do not mean that the operating level or non-operating level has a specific value in the entire text. In the embodiments of the present disclosure, the operating level (or high level, first voltage, first target voltage, etc.) is used as an example for explanation.

[0413] The first signal output terminal GOUT1 of each first shift register SR1(j) is coupled to a first gate line GL1(m) corresponding to a row of first pixel circuits 2, for example, to provide a gate driving signal to the first gate line GL1(m), thereby driving the display panel 100 to display.

[0414] Exemplarily, in the display stage of the display panel 100, when displaying each frame of the picture, the gate scanning signal is output to the first gate line GL1(m) corresponding to the first shift register SR1(j) step by step to complete the row-by-row scanning of multiple rows of first pixel circuits 2. While each row of first pixel circuits 2 is scanned, each data line DL(n) writes the data voltage signal into each first pixel circuit 2 of the row to light up each first sub-pixel area P1 of the row.

[0415] 35 , the first shift register SR1(j) includes an input sub-circuit 121, a first pull-up node PU1, and a first output sub-circuit 122. The input sub-circuit 121 is coupled to the input signal terminal IPT and the first pull-up node PU1.

[0416] The input sub-circuit 121 is configured to transmit the input signal from the input signal terminal IPT to the first pull-up node PU1 .

[0417] The first output sub-circuit 122 is coupled to the first pull-up node PU1, the clock signal terminal CLK, the first signal output terminal GOUT1 and the second signal output terminal OUTC. The first signal output terminal GOUT1 is coupled to the control electrode of the first transistor T1 through the first gate line GL1.

[0418] The first output sub-circuit 122 is configured to transmit the clock signal from the clock signal terminal CLK to the first signal output terminal GOUT1 under the control of the voltage of the first pull-up node PU1 .

[0419] The first output sub-circuit 122 is further configured to transmit the clock signal from the clock signal terminal CLK to the second signal output terminal OUTC under the control of the voltage of the first pull-up node PU1 .

[0420] Exemplarily, each first gate line GL1 (n) is electrically connected to the control electrodes of a plurality of first transistors T1 arranged in a row, and the first transistors T1 in the row are turned on under the control of the voltage of the first gate line GL1 (n) electrically connected thereto.

[0421] It should be noted that the above is merely an example of a possible operating mode of the input sub-circuit 121 and the first output sub-circuit 122 when operating in the first shift register SR1(j), and does not limit the specific operating mode of the input sub-circuit 121 and the first output sub-circuit 122 in the first shift register SR1(j). The above operating mode can be the operating mode of the input sub-circuit 121 and the first output sub-circuit 122 in any operating stage of the display device, such as the display stage.

[0422] In some embodiments, as shown in FIG. 36 , the first output sub-circuit 122 includes a third transistor M3 , a thirteenth transistor M13 , and a first capacitor C1 .

[0423] A control electrode of the third transistor M3 is electrically connected to the first pull-up node PU1 , a first electrode of the third transistor M3 is electrically connected to the clock signal terminal CLK, and a second electrode of the third transistor M3 is electrically connected to the first signal output terminal GOUT1 .

[0424] The third transistor M3 is configured to transmit the clock signal provided by the clock signal terminal CLK to the first signal output terminal GOUT1 under the control of the clock signal terminal CLK.

[0425] A first plate of the first capacitor C1 is electrically connected to the first pull-up node PU1 , and a second plate of the first capacitor C1 is electrically connected to the second electrode of the third transistor.

[0426] A control electrode of the thirteenth transistor M13 is electrically connected to the first pull-up node PU1 , a first electrode of the thirteenth transistor M13 is electrically connected to the clock signal terminal CLK, and a second electrode of the thirteenth transistor M13 is electrically connected to the second signal output terminal OUTC.

[0427] The thirteenth transistor M13 is configured to transmit the clock signal provided by the clock signal terminal CLK to the second signal output terminal OUTC under the control of the voltage of the first pull-up node PU1.

[0428] In some embodiments, as shown in FIG35 , the first shift register SR1(j) further includes a first control subcircuit 123. The first control subcircuit 123 is coupled to the first voltage signal terminal VDD1, the first pull-down node PD1, and the first pull-up node PU1.

[0429] The first control sub-circuit 123 is configured to pull up the first pull-down node PD1 under the control of the voltage of the first voltage signal terminal VDD1 , and pull down the first pull-up node PU1 in response to the high level of the first pull-down node PD1 .

[0430] The first control sub-circuit 123 is further configured to pull the first pull-down node PD1 low in response to a high level of the first pull-up node PU1 .

[0431] Exemplarily, as shown in FIG36 , the first shift register SR1 (j) further includes: a first pull-down control node PD-CN1 , and the first control sub-circuit 123 is further coupled to the first pull-down control node PD-CN1 .

[0432] The first control subcircuit 123 is configured to, under the control of the voltage of the first voltage signal terminal VDD1, transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the first pull-down control node PD-CN1 to pull the first pull-down control node PD-CN1 high.

[0433] The first control sub-circuit 123 is further configured to transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the first pull-down node PD1 under the control of the voltage of the first pull-down control node PD-CN1.

[0434] It should be noted that the above is merely an example of a possible operating mode of the first control sub-circuit 123 when operating in the first shift register SR1(j), and does not limit the specific operating mode of the first control sub-circuit 123 in the first shift register SR1(j). The above operating mode can be the operating mode of the first control sub-circuit 123 in any operating stage of the display device, such as the display stage.

[0435] In some embodiments, as shown in FIG. 36 , the first control sub-circuit 123 includes a fifth transistor M5 , a sixth transistor M6 , an eighth transistor M8 , a ninth transistor M9 , and a tenth transistor M10 .

[0436] The control electrode of the ninth transistor M9 is electrically connected to the first voltage signal terminal VDD1 , the first electrode of the ninth transistor M9 is electrically connected to the first voltage signal terminal VDD1 , and the second electrode of the ninth transistor M9 is electrically connected to the first pull-down control node PD-CN1 .

[0437] The ninth transistor M9 is configured to pull up the first pull-down control node PD-CN1 under the control of the first voltage signal terminal VDD1.

[0438] A control electrode of the eighth transistor M8 is electrically connected to the first pull-up node PU1 , a first electrode of the eighth transistor M8 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the eighth transistor M8 is electrically connected to the first pull-down control node PD-CN1 .

[0439] The eighth transistor M8 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-down control node PD-CN1 under the control of the voltage of the first pull-up node PU1.

[0440] The control electrode of the fifth transistor M5 is electrically connected to the first pull-down control node PD-CN1 , the first electrode of the fifth transistor M5 is electrically connected to the first voltage signal terminal VDD1 , and the second electrode of the fifth transistor M5 is electrically connected to the first pull-down node PD1 .

[0441] The fifth transistor M5 is configured to pull the first pull-down node PD1 high under the control of the voltage of the first pull-down control node PD-CN1.

[0442] A control electrode of the sixth transistor M6 is electrically connected to the first pull-up node PU1 , a first electrode of the sixth transistor M6 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the sixth transistor M6 is electrically connected to the first pull-down node PD1 .

[0443] The sixth transistor M6 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-down node PD1 under the control of the voltage of the first pull-up node PU1.

[0444] A control electrode of the tenth transistor M10 is electrically connected to the first pull-down node PD1 , a first electrode of the tenth transistor M10 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the tenth transistor M10 is electrically connected to the first pull-up node PU1 .

[0445] The tenth transistor M10 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the voltage of the first pull-down node PD1.

[0446] In some other embodiments, as shown in FIG35 , the first shift register SR1(j) further includes a second control subcircuit 123 ′. The second control subcircuit 123 ′ is coupled to the second voltage signal terminal VDD2 , the second pull-down node PD2 , and the first pull-up node PU1 .

[0447] The second control sub-circuit 123 ′ is configured to pull up the second pull-down node PD2 under the control of the voltage of the second voltage signal terminal VDD2 , and pull down the first pull-up node PU1 in response to the high level of the second pull-down node PD2 .

[0448] The second control sub-circuit 123 ′ is further configured to pull the second pull-down node PD2 low in response to the high level of the first pull-up node PU1 .

[0449] Exemplarily, as shown in FIG36 , the first shift register SR1 (j) further includes: a second pull-down control node PD-CN2, and the second control sub-circuit 123 ′ is further coupled to the second pull-down control node PD-CN2.

[0450] The second control sub-circuit 123 ′ is configured to, under the control of the voltage of the second voltage signal terminal VDD2 , transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the second pull-down control node PD-CN2 to pull the second pull-down control node PD-CN2 high.

[0451] The second control sub-circuit 123 ′ is further configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the second pull-down node PD2 under the control of the voltage of the second pull-down control node PD-CN2 .

[0452] It should be noted that the above is merely an example of a possible operating mode of the second control sub-circuit 123' when operating in the first shift register SR1(j), and does not limit the specific operating mode of the second control sub-circuit 123' in the first shift register SR1(j). The above operating mode can be the operating mode of the second control sub-circuit 123' in any operating stage of the display device, such as the display stage.

[0453] As a possible implementation, during the display phase of the display device 10000, the first control subcircuit 123 and the second control subcircuit 123' operate alternately. For example, when the first control subcircuit 123 is in operation, the second control subcircuit 123' is in non-operation.

[0454] In some embodiments, as shown in FIG. 36 , the second control sub-circuit 123 ′ includes a fifth transistor M5 ′, a sixth transistor M6 ′, an eighth transistor M8 ′, a ninth transistor M9 ′, and a tenth transistor M10 ′.

[0455] The control electrode of the ninth transistor M9 ′ is electrically connected to the second voltage signal terminal VDD2 , the first electrode of the ninth transistor M9 ′ is electrically connected to the second voltage signal terminal VDD2 , and the second electrode of the ninth transistor M9 ′ is electrically connected to the second pull-down control node PD-CN2 .

[0456] The ninth transistor M9 ′ is configured to pull up the second pull-down control node PD-CN2 under the control of the second voltage signal terminal VDD2 .

[0457] The control electrode of the eighth transistor M8' is electrically connected to the first pull-up node PU1, the first electrode of the eighth transistor M8' is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the eighth transistor M8' is electrically connected to the second pull-down control node PD-CN2.

[0458] The eighth transistor M8 ′ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull-down control node PD-CN2 under the control of the voltage of the first pull-up node PU1 .

[0459] The control electrode of the fifth transistor M5' is electrically connected to the second pull-down control node PD-CN2, the first electrode of the fifth transistor M5' is electrically connected to the second voltage signal terminal VDD2, and the second electrode of the fifth transistor M5' is electrically connected to the second pull-down node PD2.

[0460] The fifth transistor M5 ′ is configured to pull the second pull-down node PD2 high under the control of the voltage of the second pull-down control node PD-CN2 .

[0461] The control electrode of the sixth transistor M6 ′ is electrically connected to the first pull-up node PU1 , the first electrode of the sixth transistor M6 ′ is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the sixth transistor M6 ′ is electrically connected to the second pull-down node PD2 .

[0462] The sixth transistor M6 ′ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull-down node PD2 under the control of the voltage of the first pull-up node PU1 .

[0463] The control electrode of the tenth transistor M10 ′ is electrically connected to the second pull-down node PD2 , the first electrode of the tenth transistor M10 ′ is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the tenth transistor M10 ′ is electrically connected to the first pull-up node PU1 .

[0464] The tenth transistor M10 ′ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the voltage of the second pull-down node PD2 .

[0465] In some embodiments, as shown in FIG35 , the first shift register SR1(j) further includes a first denoising sub-circuit 127. The first denoising sub-circuit 127 is coupled to the input signal terminal IPT, the fourth voltage signal terminal LVGL, and the first pull-down node PD1. The first denoising sub-circuit 127 is configured to, under the control of the input signal terminal IPT, transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-down node PD1.

[0466] It should be noted that the above is merely an example of a possible operating mode of the first denoising sub-circuit 127 when operating in the first shift register SR1(j), and does not limit the specific operating mode of the first denoising sub-circuit 127 in the first shift register SR1(j). The above operating mode can be the operating mode of the first denoising sub-circuit 127 in any operating stage of the display device, such as the display stage.

[0467] 36 , the first denoising sub-circuit 127 includes a thirteenth transistor M13. A control electrode of the thirteenth transistor M13 is electrically connected to the input signal terminal IPT, a first electrode of the thirteenth transistor M13 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the thirteenth transistor M13 is electrically connected to the first pull-down node PD1.

[0468] The thirteenth transistor M13 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-down node PD1 under the control of the input signal terminal IPT.

[0469] In some embodiments, the first shift register SR1(j) further includes a second denoising sub-circuit 127', as shown in FIG35 . The second denoising sub-circuit 127' is coupled to the input signal terminal IPT, the fourth voltage signal terminal LVGL, and the second pull-down node PD2. The second denoising sub-circuit 127' is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second pull-down node PD2 under the control of the input signal terminal IPT.

[0470] It should be noted that the above is merely an example of a possible operating mode of the second denoising sub-circuit 127' when operating in the first shift register SR1(j), and does not limit the specific operating mode of the second denoising sub-circuit 127' in the first shift register SR1(j). The above operating mode can be the operating mode of the second denoising sub-circuit 127' in any operating stage of the display device, such as the display stage.

[0471] 36 , the second denoising sub-circuit 127 ′ includes a thirteenth transistor M13 ′. A control electrode of the thirteenth transistor M13 ′ is electrically connected to the input signal terminal IPT, a first electrode of the thirteenth transistor M13 ′ is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the thirteenth transistor M13 ′ is electrically connected to the second pull-down node PD2.

[0472] The thirteenth transistor M13 ′ is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second pull-down node PD2 under the control of the input signal terminal IPT.

[0473] As a possible implementation, during the display phase of the display device 10000, the first denoising sub-circuit 127 and the second denoising sub-circuit 127' operate alternately. For example, when the first denoising sub-circuit 127 is in operation, the second denoising sub-circuit 127' is inoperative.

[0474] In some embodiments, as shown in FIG. 35 , the first shift register SR1 ( j ) further includes: a first reset sub-circuit 124 .

[0475] The first reset sub-circuit 124 is coupled to the first pull-down node PD1 , the first signal output terminal GOUT1 , and the second signal output terminal OUTC.

[0476] The first reset sub-circuit 124 is configured to reset the first signal output terminal GOUT1 and the second signal output terminal OUTC under the control of the voltage of the first pull-down node PD1 .

[0477] It should be noted that the above is merely an example of a possible operating mode of the first reset sub-circuit 124 when operating in the first shift register SR1(j), and does not limit the specific operating mode of the first reset sub-circuit 124 in the first shift register SR1(j). The above operating mode can be the operating mode of the first reset sub-circuit 124 in any operating stage of the display device, such as the display stage.

[0478] In some embodiments, as shown in FIG. 36 , the first reset sub-circuit 124 includes an eleventh transistor M11 and a twelfth transistor M12 .

[0479] A control electrode of the eleventh transistor M11 is electrically connected to the first pull-down node PD1 , a first electrode of the eleventh transistor M11 is electrically connected to the third voltage signal terminal VGL, and a second electrode of the eleventh transistor M11 is electrically connected to the first signal output terminal GOUT1 .

[0480] The eleventh transistor M11 is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the first signal output terminal GOUT1 under the control of the voltage of the first pull-down node PD1 .

[0481] A control electrode of the twelfth transistor M12 is electrically connected to the second pull-down node PD2 , a first electrode of the twelfth transistor M12 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the twelfth transistor M12 is electrically connected to the second signal output terminal OUTC.

[0482] The twelfth transistor M12 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second signal output terminal OUTC under the control of the voltage of the second pull-down node PD2.

[0483] In some other embodiments, as shown in FIG35 , the first shift register SR1(j) further includes a second reset sub-circuit 124 ′ coupled to the second pull-down node PD2 , the first signal output terminal GOUT1 , and the second signal output terminal OUTC.

[0484] The second reset sub-circuit 124 ′ is configured to reset the first signal output terminal GOUT1 and the second signal output terminal OUTC under the control of the voltage of the second pull-down node PD2 .

[0485] It should be noted that the above is merely an example of a possible operating mode of the second reset sub-circuit 124' when operating in the first shift register SR1(j), and does not limit the specific operating mode of the second reset sub-circuit 124' in the first shift register SR1(j). The above operating mode can be the operating mode of the second reset sub-circuit 124' in any operating stage of the display device, such as the display stage.

[0486] As a possible implementation, during the display phase of the display device 10000, the first reset subcircuit 124 and the second reset subcircuit 124' operate alternately. For example, when the first reset subcircuit 124 is in operation, the second reset subcircuit 124' is in non-operation.

[0487] In some embodiments, as shown in FIG. 36 , the second reset sub-circuit 124 ′ includes an eleventh transistor M11 ′ and a twelfth transistor M12 ′.

[0488] The control electrode of the eleventh transistor M11 ′ is electrically connected to the second pull-down node PD2 , the first electrode of the eleventh transistor M11 ′ is electrically connected to the third voltage signal terminal VGL, and the second electrode of the eleventh transistor M11 ′ is electrically connected to the first signal output terminal GOUT1 .

[0489] The eleventh transistor M11 ′ is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the first signal output terminal GOUT1 under the control of the voltage of the second pull-down node PD2 .

[0490] The control electrode of the twelfth transistor M12 ′ is electrically connected to the second pull-down node PD2 , the first electrode of the twelfth transistor M12 ′ is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the twelfth transistor M12 ′ is electrically connected to the second signal output terminal OUTC.

[0491] The twelfth transistor M12 ′ is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second signal output terminal OUTC under the control of the voltage of the second pull-down node PD2 .

[0492] In some embodiments, as shown in FIG35 , the first shift register SR1(j) further includes a third reset sub-circuit 125. The third reset sub-circuit 125 is coupled to the start signal terminal STV, the fourth voltage signal terminal LVGL, and the first pull-up node PU1. The third reset sub-circuit 125 is configured to, under the control of the start signal terminal STV, transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1.

[0493] It should be noted that the above is merely an example of a possible operating mode of the third reset sub-circuit 125 when operating in the first shift register SR1(j), and does not limit the specific operating mode of the third reset sub-circuit 125 in the first shift register SR1(j). The above operating mode can be the operating mode of the third reset sub-circuit 125 in any operating stage of the display device, such as the display stage.

[0494] 36 , the third reset sub-circuit 125 includes a seventh transistor M7 . A control electrode of the seventh transistor M7 is electrically connected to the start signal terminal STV , a first electrode of the seventh transistor M7 is electrically connected to the fourth voltage signal terminal LVGL , and a second electrode of the seventh transistor M7 is electrically connected to the first pull-up node PU1 .

[0495] The seventh transistor M7 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the start signal terminal STV.

[0496] In some embodiments, as shown in FIG35 , the first shift register SR1(j) further includes a fourth reset sub-circuit 126. The fourth reset sub-circuit 126 is coupled to the reset signal terminal RST, the fourth voltage signal terminal LVGL, and the first pull-up node PU1. The fourth reset sub-circuit 126 is configured to, under the control of the reset signal terminal RST, transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1.

[0497] It should be noted that the above is merely an example of a possible operating mode of the fourth reset sub-circuit 126 when operating in the first shift register SR1(j), and does not limit the specific operating mode of the fourth reset sub-circuit 126 in the first shift register SR1(j). The above operating mode can be the operating mode of the fourth reset sub-circuit 126 in any operating stage of the display device, such as the display stage.

[0498] 36 , the fourth reset sub-circuit 126 includes a fourteenth transistor M14. A control electrode of the fourteenth transistor M14 is electrically connected to the reset signal terminal RST, a first electrode of the fourteenth transistor M14 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the fourteenth transistor M14 is electrically connected to the first pull-up node PU1.

[0499] The fourteenth transistor M14 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the reset signal terminal RST.

[0500] In some embodiments, as shown in FIG28 and FIG37 , when the display panel 100 includes the second transistor T2, the display panel 100 further includes a second gate driving circuit 13. The second gate driving circuit 13 includes a second shift register unit SR2. The second shift register unit SR2 is disposed in the liquid crystal sealing area SA. A single second shift register unit SR2 is coupled to, for example, a row of second pixel circuits 3.

[0501] For example, the first shift register unit SR1(j) is configured to transmit an electrical signal to the first gate line GL1 to control the first transistor T1 coupled to the first gate line GL1 to be turned on. The second shift register unit SR2 is configured to transmit an electrical signal to the second gate line GL2 to control the second transistor T2 coupled to the second gate line GL2 to be turned on.

[0502] The display area AA and the light-transmitting area BB operate independently, and the second shift register unit SR2 has no cascade relationship with the first shift register unit SR1(j). A single shift register SR2 is coupled to at least one second gate line GL2.

[0503] Based on this, the second gate line GL2 is coupled to a second pixel circuit 3 via a second transistor T2 , and each second gate line GL2 is coupled to at least one row of second pixel circuits 3 .

[0504] In some examples, as shown in FIG28 and FIG37 , each second gate line GL2 is coupled to a row of second pixel circuits 3, and each second gate line GL2 can be electrically connected to the control electrodes of a plurality of second transistors T2 arranged in a row. In this way, a second gate line GL2 can control the conduction of a row of second transistors T2 electrically connected thereto.

[0505] In other examples, the plurality of second pixel circuits 3 are coupled to the same second gate line GL2, and the control electrodes of the plurality of second transistors T2 included in the display panel 100 are electrically connected to the same second gate line GL2. In this way, the second transistors T2 can be controlled to be turned on through the second gate line GL2.

[0506] It should be noted that the connection mode between the second gate line GL2 and the second pixel circuit 3 and the second transistor T2 can be selected as needed. The above is only an exemplary description of possible implementations of the present disclosure and is not intended to limit the present disclosure.

[0507] Exemplarily, the data line DL (first data line DL1 or second data line DL2) is coupled to the second pixel electrode 31, and each data line DL is coupled to at least one column of second pixel circuits 3. The data line DL may be the first data line DL1 and / or the second data line DL2.

[0508] In some examples, as shown in Figures 28 and 37, each data line DL is coupled to a column of second pixel circuits 3, and each data line DL can be electrically connected to the first electrodes of a plurality of second transistors T2 arranged in a column. In this way, a single data line DL can transmit a second data signal to a column of second pixel electrodes 31 through the plurality of second transistors T2 electrically connected thereto.

[0509] In other examples, the second pixel circuits 3 included in the display panel 100 are all coupled to the same data line DL, and the control electrodes of the second transistors T2 included in the display panel 100 are all electrically connected to the same data line DL. In this way, the second data signal can be transmitted to each second pixel electrode 31 via a second gate line GL2.

[0510] It should be noted that the connection mode between the data line DL and the second pixel circuit 3 and the second transistor T2 can be selected as needed. The above is only an exemplary description of possible implementations of the present disclosure and is not intended to limit the present disclosure.

[0511] In some embodiments, as shown in FIG37 , the second shift register SR2 includes a second pull-up node PU2 and a second output sub-circuit 131. The second pull-up node PU2 is electrically connected to the enable signal terminal OE. The second output sub-circuit 131 is coupled to the second pull-up node PU2, the enable signal terminal OE, and a third signal output terminal GOUT2. The third signal output terminal GOUT2 is coupled to the control electrode of the second transistor T2 via a second gate line GL2.

[0512] The second output sub-circuit 131 is configured to transmit the enable signal from the enable signal terminal OE to the third signal output terminal GOUT2 under the control of the voltage of the second pull-up node PU2, so as to charge the third signal output terminal GOUT2.

[0513] 35 and 37 , compared to the first gate driving circuit 12 , the second gate driving circuit 13 does not need to be provided with an input sub-circuit (the first pixel circuit 2 needs to be provided with an input sub-circuit 121 ), and the circuit architecture is simpler.

[0514] It should be noted that the above is merely an example of a possible operating mode of the second output sub-circuit 131 when operating in the second shift register SR2, and does not limit the specific operating mode of the second output sub-circuit 131 in the second shift register SR2. The above operating mode can be the operating mode of the second output sub-circuit 131 in any operating phase of the light-transmitting region BB, such as the light-emitting phase.

[0515] Exemplarily, the display panel 100 further includes a reset signal terminal ADD disposed in the liquid crystal sealing area SA, the reset signal terminal ADD being electrically connected to the second pull-up node PU2 and configured to pull down the potential of the second pull-up node PU2 in response to a reset signal.

[0516] By setting the reset signal terminal ADD, when the potential of the second pull-up node PU2 needs to be reset to a non-working level, a reset signal can be sent to the reset signal terminal ADD through the circuit board 200. Under the control of the reset signal, the reset signal terminal ADD pulls down the potential of the second pull-up node PU2 to reset / reset the second pull-up node PU2.

[0517] In some embodiments, as shown in FIG. 38 , the second output sub-circuit 131 includes: a third transistor N3 and a second capacitor C2 .

[0518] A control electrode of the third transistor N3 is electrically connected to the second pull-up node PU2 , a first electrode of the third transistor N3 is electrically connected to the enable signal terminal OE, and a second electrode of the third transistor N3 is electrically connected to the third signal output terminal GOUT2 .

[0519] The second capacitor C2 is configured to transmit the enable signal transmitted from the enable signal terminal OE to the third signal output terminal GOUT2 under the control of the voltage of the second pull-up node PU2.

[0520] A first plate of the second capacitor C2 is electrically connected to the second pull-up node PU2 , and a second plate of the second capacitor C2 is electrically connected to the second electrode of the third transistor N3 .

[0521] 37 , the second shift register SR2 further includes a third control subcircuit 132. The third control subcircuit 132 is coupled to the first voltage signal terminal VDD1, the third pull-down node PD3, and the second pull-up node PU2.

[0522] The third control sub-circuit 132 is configured to pull up the third pull-down node PD3 under the control of the voltage of the first voltage signal terminal VDD1 , and pull down the second pull-up node PU2 in response to the high level of the third pull-down node PD3 .

[0523] The third control sub-circuit 132 is further configured to pull the third pull-down node PD3 low in response to the high level of the second pull-up node PU2 .

[0524] Exemplarily, as shown in FIG38 , the second shift register SR2 further includes: a third pull-down control node PD-CN3 , and the third control sub-circuit 132 is further coupled to the third pull-down control node PD-CN3 .

[0525] The third control subcircuit 132 is configured to, under the control of the voltage of the first voltage signal terminal VDD1, transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the third pull-down control node PD-CN3 to pull the third pull-down control node PD-CN3 high.

[0526] The third control sub-circuit 132 is further configured to transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the third pull-down node PD3 under the control of the voltage of the third pull-down control node PD-CN3.

[0527] 35 and 37 , compared with the first gate driving circuit 12 , the circuit architecture of the second gate driving circuit 13 is simpler.

[0528] It should be noted that the above is merely an example of a possible operating mode of the third control sub-circuit 132 when operating in the second shift register SR2, and does not limit the specific operating mode of the third control sub-circuit 132 in the second shift register SR2. The above operating mode can be the operating mode of the third control sub-circuit 132 in any operating phase of the light-transmitting area BB, such as the light-emitting phase.

[0529] In some embodiments, as shown in FIG. 38 , the third control subcircuit 132 includes a fourth transistor N4 , a fifth transistor N5 , a seventh transistor N7 , a sixth transistor N6 , and an eighth transistor N8 .

[0530] The control electrode of the sixth transistor N6 is electrically connected to the first voltage signal terminal VDD1 , the first electrode of the sixth transistor N6 is electrically connected to the first voltage signal terminal VDD1 , and the second electrode of the sixth transistor N6 is electrically connected to the third pull-down control node PD-CN3 .

[0531] The sixth transistor N6 is configured to pull up the third pull-down control node PD-CN3 under the control of the first voltage signal terminal VDD1.

[0532] A control electrode of the seventh transistor N7 is electrically connected to the second pull-up node PU2 , a first electrode of the seventh transistor N7 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the seventh transistor N7 is electrically connected to the third pull-down control node PD-CN3 .

[0533] The seventh transistor N7 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the third pull-down control node PD-CN3 under the control of the voltage of the second pull-up node PU2.

[0534] The control electrode of the fourth transistor N4 is electrically connected to the third pull-down control node PD-CN3 , the first electrode of the fourth transistor N4 is electrically connected to the first voltage signal terminal VDD1 , and the second electrode of the fourth transistor N4 is electrically connected to the third pull-down node PD3 .

[0535] The fourth transistor N4 is configured to, under the control of the voltage of the third pull-down control node PD-CN3, transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the third pull-down node PD3 to pull the third pull-down node PD3 high.

[0536] A control electrode of the fifth transistor N5 is electrically connected to the second pull-up node PU2 , a first electrode of the fifth transistor N5 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the fifth transistor N5 is electrically connected to the third pull-down node PD3 .

[0537] The fifth transistor N5 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the third pull-down node PD3 under the control of the voltage of the second pull-up node PU2.

[0538] A control electrode of the eighth transistor N8 is electrically connected to the third pull-down node PD3 , a first electrode of the eighth transistor N8 is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the eighth transistor N8 is electrically connected to the second pull-up node PU2 .

[0539] The eighth transistor N8 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull-up node PU2 under the control of the voltage of the third pull-down node PD3.

[0540] 37 , the second shift register SR2 further includes a fourth control subcircuit 133. The fourth control subcircuit 133 is coupled to the second voltage signal terminal VDD2, the fourth pull-down node PD4, and the second pull-up node PU2.

[0541] The fourth control subcircuit 133 is configured to pull up the fourth pull-down node PD4 under the control of the voltage of the second voltage signal terminal VDD2 , and pull down the second pull-up node PU2 in response to the high level of the fourth pull-down node PD4 .

[0542] The fourth control sub-circuit 133 is further configured to pull the fourth pull-down node PD4 low in response to the high level of the second pull-up node PU2 .

[0543] Exemplarily, as shown in FIG38 , the second shift register SR2 further includes: a fourth pull-down control node PD-CN4 , and the fourth control sub-circuit 133 is further coupled to the fourth pull-down control node PD-CN4 .

[0544] The fourth control subcircuit 133 is configured to, under the control of the voltage of the second voltage signal terminal VDD2, transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the fourth pull-down control node PD-CN4 to pull the fourth pull-down control node PD-CN4 high.

[0545] The fourth control sub-circuit 133 is further configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the fourth pull-down node PD4 under the control of the voltage of the fourth pull-down control node PD-CN4.

[0546] 35 and 37 , compared with the first gate driving circuit 12 , the circuit architecture of the second gate driving circuit 13 is simpler.

[0547] It should be noted that the above is merely an example of a possible operating mode of the fourth control sub-circuit 133 when operating in the second shift register SR2, and does not limit the specific operating mode of the fourth control sub-circuit 133 in the second shift register SR2. The above operating mode can be the operating mode of the fourth control sub-circuit 133 in any operating phase of the light-transmitting area BB, such as the light-emitting phase.

[0548] As a possible implementation, during the light-emitting phase of the light-transmitting area BB, the third control subcircuit 132 and the fourth control subcircuit 133 operate alternately. For example, when the third control subcircuit 132 is in operation, the fourth control subcircuit 133 is in non-operation.

[0549] In some embodiments, as shown in FIG. 38 , the fourth control subcircuit 133 includes a fourth transistor N4 ′, a fifth transistor N5 ′, a sixth transistor N6 ′, a seventh transistor N7 ′, and an eighth transistor N8 ′.

[0550] The control electrode of the sixth transistor N6 ′ is electrically connected to the second voltage signal terminal VDD2 , the first electrode of the sixth transistor N6 ′ is electrically connected to the second voltage signal terminal VDD2 , and the second electrode of the sixth transistor N6 ′ is electrically connected to the fourth pull-down control node PD-CN4 .

[0551] The sixth transistor N6 ′ is configured to pull up the fourth pull-down control node PD-CN4 under the control of the second voltage signal terminal VDD2 .

[0552] A control electrode of the seventh transistor N7' is electrically connected to the second pull-up node PU2, a first electrode of the seventh transistor N7' is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the seventh transistor N7' is electrically connected to the fourth pull-down control node PD-CN4.

[0553] The seventh transistor N7 ′ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the fourth pull-down control node PD-CN4 under the control of the voltage of the second pull-up node PU2 .

[0554] The control electrode of the fourth transistor N4' is electrically connected to the fourth pull-down control node PD-CN4, the first electrode of the fourth transistor N4' is electrically connected to the second voltage signal terminal VDD2, and the second electrode of the fourth transistor N4' is electrically connected to the fourth pull-down node PD4.

[0555] The fourth transistor N4 ′ is configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the fourth pull-down node PD4 under the control of the voltage of the fourth pull-down control node PD-CN4 , and pull the fourth pull-down node PD4 high.

[0556] A control electrode of the fifth transistor N5 ′ is electrically connected to the second pull-up node PU2 , a first electrode of the fifth transistor N5 ′ is electrically connected to the fourth voltage signal terminal LVGL, and a second electrode of the fifth transistor N5 ′ is electrically connected to the fourth pull-down node PD4 .

[0557] The fifth transistor N5 ′ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the fourth pull-down node PD4 under the control of the voltage of the second pull-up node PU2 .

[0558] The control electrode of the eighth transistor N8 ′ is electrically connected to the fourth pull-down node PD4 , the first electrode of the eighth transistor N8 ′ is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the eighth transistor N8 ′ is electrically connected to the second pull-up node PU2 .

[0559] The eighth transistor N8 ′ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull-up node PU2 under the control of the voltage of the fourth pull-down node PD4 .

[0560] In some embodiments, as shown in FIG37 , the second shift register SR2 further includes a fifth reset sub-circuit 134. The fifth reset sub-circuit 134 is coupled to the third pull-down node PD3 and the third signal output terminal GOUT2.

[0561] The fifth reset sub-circuit 134 is configured to reset the third signal output terminal GOUT2 under the control of the voltage of the third pull-down node PD3 .

[0562] 35 and 37 , compared with the first gate driving circuit 12 , the circuit architecture of the second gate driving circuit 13 is simpler.

[0563] It should be noted that the above is merely an example of a possible operating mode of the fifth reset sub-circuit 134 when operating in the second shift register SR2, and does not limit the specific operating mode of the fifth reset sub-circuit 134 in the second shift register SR2. The above operating mode can be the operating mode of the fifth reset sub-circuit 134 in any operating phase of the light-transmitting region BB, such as the light-emitting phase.

[0564] In some embodiments, as shown in FIG38 , the fifth reset sub-circuit 134 includes a ninth transistor N9. A control electrode of the ninth transistor N9 is electrically connected to the third pull-down node PD3, a first electrode of the ninth transistor N9 is electrically connected to the third voltage signal terminal VGL, and a second electrode of the ninth transistor N9 is electrically connected to the third signal output terminal GOUT2. The ninth transistor N9 is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the third signal output terminal GOUT2 under the control of the voltage of the third pull-down node PD3.

[0565] In some embodiments, as shown in FIG37 , the second shift register SR2 further includes a sixth reset sub-circuit 135. The sixth reset sub-circuit 135 is coupled to the fourth pull-down node PD4 and the third signal output terminal GOUT2.

[0566] The sixth reset sub-circuit 135 is configured to reset the third signal output terminal GOUT2 under the control of the voltage of the fourth pull-down node PD4.

[0567] 35 and 37 , compared with the first gate driving circuit 12 , the circuit architecture of the second gate driving circuit 13 is simpler.

[0568] It should be noted that the above is merely an example of a possible operating mode of the sixth reset sub-circuit 135 when operating in the second shift register SR2, and does not limit the specific operating mode of the sixth reset sub-circuit 135 in the second shift register SR2. The above operating mode can be the operating mode of the sixth reset sub-circuit 135 in any operating phase of the light-transmitting region BB, such as the light-emitting phase.

[0569] As a possible implementation, during the light-emitting phase of the light-transmitting area BB, the fifth reset subcircuit 134 and the sixth reset subcircuit 135 operate alternately. For example, when the fifth reset subcircuit 134 is in operation, the sixth reset subcircuit 135 is in non-operation.

[0570] In some embodiments, as shown in FIG38 , the sixth reset sub-circuit 135 includes a ninth transistor N9′. A control electrode of the ninth transistor N9′ is electrically connected to the fourth pull-down node PD4, a first electrode of the ninth transistor N9′ is electrically connected to the third voltage signal terminal VGL, and a second electrode of the ninth transistor N9′ is electrically connected to the third signal output terminal GOUT2. The ninth transistor N9′ is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the third signal output terminal GOUT2 under the control of the voltage of the fourth pull-down node PD4.

[0571] In some embodiments, as shown in FIG. 39 and FIG. 40 , the display panel 100 further includes at least one light emitting data input terminal VL outside the display area AA, and the light emitting data input terminal VL is insulated from the data line DL.

[0572] Exemplarily, the light emitting data input terminal VL may be located in the bonding area BA.

[0573] Exemplarily, the single light emitting data input terminal VL is coupled to at least one second pixel electrode 31 . The single light emitting data input terminal VL may be coupled to one second pixel electrode 31 ; or the single light emitting data input terminal VL may be coupled to multiple second pixel electrodes 31 .

[0574] The following description will be made by taking the display panel 100 including a plurality of second pixel circuits 3 as an example.

[0575] In some examples, the display panel 100 emits the same light color in areas defined by different second pixel circuits 3. The area defined by the second pixel circuit 3 is, for example, the aforementioned second sub-pixel region P2.

[0576] The second pixel electrodes 31 of different second pixel circuits 3 can be coupled to the same light-emitting data input terminal VL; or, the light-emitting data input terminal VL and the second pixel electrodes 31 are set in a one-to-one correspondence, and different second pixel electrodes 31 are respectively coupled to different light-emitting data input terminals VL; or, a part of the multiple second pixel electrodes 31 are coupled to one light-emitting data input terminal VL, and the other part is coupled to another light-emitting data input terminal VL.

[0577] Depending on the connection method between the light emitting data input terminal VL and the second pixel circuit 3, the multiple second pixel circuits 3 included in the display panel 100 can work simultaneously or in time-sharing mode. The specific selection and setting can be made as needed, and this disclosure does not limit this.

[0578] In other examples, the plurality of second pixel circuits 3 include at least a first color pixel circuit 3a and a second color pixel circuit 3b, and the colors of the emitted light from the area defined by the first color pixel circuit 3a and the area defined by the second color pixel circuit 3b of the display panel 100 are different. The area defined by the first color pixel circuit 3a is, for example, a second sub-pixel region P2(1) of a first luminous color, and the area defined by the second color pixel circuit 3b is, for example, a second sub-pixel region P2(2) of a second luminous color.

[0579] The second pixel electrodes 31 of different first color pixel circuits 3a can be coupled to the same light-emitting data input terminal VL; or, the light-emitting data input terminal VL and the second pixel electrodes 31 are set in a one-to-one correspondence, the second pixel electrodes 31 of the first color pixel circuit 3a are coupled to one light-emitting data input terminal VL, and the second pixel electrodes 31 of the second color pixel circuit 3b are coupled to another light-emitting data input terminal VL; or, the light-emitting data input terminal VL and the second pixel electrodes 31 are set in a one-to-one correspondence, the second pixel electrodes 31 of different first color pixel circuits 3a are respectively coupled to different light-emitting data input terminals VL, and the second pixel electrodes 31 of different second color pixel circuits 3b are respectively coupled to different light-emitting data input terminals VL.

[0580] The first luminous color and the second luminous color can be any two of the three primary colors. The first luminous color second sub-pixel area P2(1) is, for example, the red light second sub-pixel area P2(R), and the second luminous color second sub-pixel area P2(2) is, for example, the green light second sub-pixel area P2(G).

[0581] The red second sub-pixel region P2 (R) and the green second sub-pixel region P2 (G) may be lit simultaneously or in a time-sharing manner.

[0582] When the red second sub-pixel area P2(R) and the green second sub-pixel area P2(G) are lit at the same time, the display panel 100 can be luminous / non-luminous through the transparent area BB (the red second sub-pixel area P2(R) and the green second sub-pixel area P2(G)), corresponding to the working state / non-working state of the sensor 300.

[0583] In the case where the red second sub-pixel region P2(R) and the green second sub-pixel region P2(G) can be lit in a time-sharing manner, the display panel 100 can also be lit by lighting the red second sub-pixel region P2(R) or the green second sub-pixel region P2(G) to distinguish between the working state and the non-working state of the sensor 300.

[0584] Exemplarily, the light emitting data input terminal VL may be located in the bonding area BA.

[0585] Exemplarily, at least one light-emitting data input terminal VL is insulated from the data line DL, which means that the light-emitting data input terminal VL is electrically insulated from the first data line DL1 and / or the second data line DL2 .

[0586] The light emitting data input terminal VL is configured to provide a second data signal to the second pixel electrode 31 .

[0587] The second data signal may be a grayscale signal, and the second sub-pixel region P2 achieves different luminous brightnesses according to the different grayscale signals received by the second pixel electrode 31. The luminous brightness of the light-transmitting region BB adopts 256 grayscales, for example. Accordingly, the luminous brightness of the second sub-pixel region P2 adopts 256 grayscales. The grayscale signals received by the second pixel electrode 31 are different when the second sub-pixel region P2 is emitting and when it is not emitting.

[0588] Based on this, when the second sub-pixel area P2 does not emit light, the grayscale signal received by the second pixel electrode 31 can be L0. Correspondingly, when the second sub-pixel area P2 emits light, the grayscale signal received by the second pixel electrode 31 can be any value from L1 to L255.

[0589] Furthermore, when the light-transmitting area BB changes the luminous brightness according to the working state of the sensor 300, when the sensor 300 is in the working state, the second sub-pixel area P2 emits light of the first brightness, and when the sensor 300 is in the non-working state, the second sub-pixel area P2 does not emit light or emits light of the second brightness.

[0590] Based on this, when the second sub-pixel area P2 emits the first brightness light and the second brightness light, the grayscale signal received by the second pixel electrode 31 can be any two different values ​​from L1 to L255. The specific values ​​can be selected as needed as long as the brightness difference between the first brightness light and the second brightness light can be clearly distinguished.

[0591] The above is merely an illustrative description of some possible implementations of the present disclosure and is not intended to limit the present disclosure.

[0592] 41 and 42 , the display panel 100 includes M light emitting data input terminals VL(f) (1≤f≤M), where M is greater than or equal to 2. Each light emitting data input terminal VL(f) is coupled to at least one second pixel electrode 31 .

[0593] The display panel 100 further includes a light emitting data driving circuit 14 and M control signal terminals IN(f), wherein the M control signal terminals IN(f) correspond one-to-one to the M light emitting data input terminals VL(f).

[0594] The light emitting data driving circuit 14 is configured to output the signal of the corresponding light emitting data input terminal VL from the output terminal of the light emitting data driving circuit 14 in response to the operating level of each of the M control signal terminals IN(f). When one of the M control signal terminals IN(h) outputs the operating level, the other control signal terminals IN(f) output the non-operating level.

[0595] The second pixel electrodes 31 of the second sub-pixel areas P2 of the same luminous color can be coupled to the same luminous data input terminal VL(f). With such a design, when the display panel 100 includes multiple second sub-pixel areas P2 of different luminous colors, when the second sub-pixel areas P2 of one luminous color receives the second data signal provided by the corresponding luminous data input terminal VL(f) to emit light, the second sub-pixel areas P2 of the other luminous colors will not receive the second data signal provided by the corresponding luminous data input terminal VL(f), so that the second sub-pixel areas P2 of the same luminous color can be lit at the same time, while the second sub-pixel areas P2 of different luminous colors will not be lit at the same time.

[0596] In some embodiments, as shown in FIG. 39 , the output end of the light emitting data driving circuit 14 is electrically connected to the second pixel electrode 31 .

[0597] In the case where the second data signal is provided to the second pixel electrode 31 by the light emitting data driving circuit 14 , the second pixel circuit 3 may be driven by an active drive method or a passive drive method.

[0598] In the case where the second pixel circuit 3 adopts a passive driving mode, in some examples, as shown in FIG40 , the light emitting data input terminal VL is coupled to the second pixel electrode 31 through the light emitting data driving circuit 14 .

[0599] In some examples, as shown in Figure 40, the second pixel circuit 3 adopts an active drive mode, the display panel 100 also includes a second transistor T2, the light-emitting data input terminal VL and the second pixel electrode 31 are coupled to the first electrode of the second transistor T2 through the light-emitting data driving circuit 14, and the second electrode of the second transistor T2 is electrically connected to the second pixel electrode 31.

[0600] In this case, as shown in FIG. 40 , the display panel 100 further includes a second transistor T2 , and the output end of the light emitting data driving circuit 14 is coupled to the second pixel electrode 31 through the second transistor T2 .

[0601] The passive driving mode adopted by the second pixel circuit 3 can be selected as needed, which is only used as an example to illustrate some possible implementation methods of the present disclosure and is not intended to limit the present disclosure.

[0602] In some embodiments, as shown in FIG41 and FIG42 , the display panel 100 includes: a first light-emitting data driving circuit 141 and a second light-emitting data driving circuit 142, wherein the first light-emitting data driving circuit 141 and the second light-emitting data driving circuit 142 are both light-emitting data driving circuits 14. The M control signal terminals IN(f) include a first control signal terminal IN(1) and a second control signal terminal IN(2), and the M light-emitting data input terminals VL(f) include: a first light-emitting data input terminal VL(1) and a second light-emitting data input terminal VL(2).

[0603] The display panel 100 includes a plurality of second pixel circuits 3, each comprising a first color pixel circuit 3a and a second color pixel circuit 3b. The display panel 100 emits light of different colors from the areas defined by the first color pixel circuit 3a and the areas defined by the second color pixel circuit 3b. A second pixel electrode 31a of the first color pixel circuit 3a is coupled to the output terminal of the first light-emitting data driving circuit 141, while a second pixel electrode 31b of the second color pixel circuit 3b is coupled to the output terminal of the second light-emitting data driving circuit 142.

[0604] In the first light-emitting data driving circuit 141 , the first control signal terminal IN( 1 ) corresponds to the first light-emitting data input terminal VL( 1 ), and the second control signal terminal IN( 2 ) corresponds to the second light-emitting data input terminal VL( 2 ).

[0605] The first light emitting data driving circuit 141 is configured to transmit the first light emitting data signal provided by the first light emitting data input terminal VL( 1 ) to the second pixel electrode 31 a under the control of the first control signal terminal IN( 1 ).

[0606] In the second light-emitting data driving circuit 142 , the first control signal terminal IN( 1 ) corresponds to the second light-emitting data input terminal VL( 2 ), and the second control signal terminal IN( 2 ) corresponds to the first light-emitting data input terminal VL( 1 ).

[0607] The second light emitting data driving circuit 142 is configured to transmit the second light emitting data signal provided by the second light emitting data input terminal VL( 2 ) to the second pixel electrode 31 b under the control of the second control signal terminal IN( 2 ).

[0608] For example, during the light-emitting phase of the light-transmitting region BB, the red second sub-pixel region P2(R) and the green second sub-pixel region P2(G) emit light in a time-sharing manner. When the red second sub-pixel region P2(R) emits light, the green second sub-pixel region P2(G) does not emit light; and when the green second sub-pixel region P2(G) emits light, the red second sub-pixel region P2(R) does not emit light.

[0609] As shown in Figures 41, 42, and 43, the light-emitting phases of the light-transmitting area BB include a first light-emitting phase Tf1 and a second light-emitting phase Tf2. During the first light-emitting phase Tf1, the red second sub-pixel region P2(R) emits light, while the green second sub-pixel region P2(G) does not. During the second light-emitting phase Tf2, the green second sub-pixel region P2(G) emits light, while the red second sub-pixel region P2(R) does not emit light.

[0610] When the voltage of the light-emitting data signal received by the second pixel electrode 31 is higher than or equal to the set operating voltage, the second sub-pixel area P2 emits light; when the voltage of the light-emitting data signal received by the second pixel electrode 31 is lower than the set operating voltage, the second sub-pixel area P2 does not emit light.

[0611] As shown in FIG42 , the voltage of the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) is higher than or equal to the set operating voltage, and the voltage of the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) is lower than the set operating voltage.

[0612] In the first light-emitting stage Tf1, as shown in FIG42, the second control signal provided by the second control signal terminal IN(2) is at a non-operating level, and the first control signal provided by the first control signal terminal IN(1) is at an operating level at least part of the time.

[0613] As shown in FIG41 and FIG42, when the first control signal is at the working level, the first light-emitting data driving circuit 141 transmits the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) to the second pixel electrode 31a, and the red second sub-pixel area P2(R) emits light.

[0614] As shown in Figures 41 and 42, when the first control signal is at the working level, the second light-emitting data driving circuit 142 transmits the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) to the second pixel electrode 31b, and the green light second sub-pixel area P2(G) does not emit light.

[0615] In the second light-emitting stage Tf2, as shown in FIG42, the first control signal provided by the first control signal terminal IN(1) is at a non-operating level, and the second control signal provided by the second control signal terminal IN(2) is at an operating level at least part of the time.

[0616] As shown in Figures 41 and 42, when the second control signal is at the working level, the first light-emitting data driving circuit 141 transmits the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) to the second pixel electrode 31a, and the red light second sub-pixel area P2(R) does not emit light.

[0617] As shown in Figures 41 and 42, when the first control signal is at the working level, the second light-emitting data driving circuit 142 transmits the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) to the second pixel electrode 31b, and the green light second sub-pixel area P2(G) emits light.

[0618] Without the light-emitting data driving circuit 14, when the second sub-pixel region P2 corresponding to the second data line DL2 emits light, the voltage of the second data signal transmitted by the second data line DL2 is higher than or equal to the set operating voltage; when the second sub-pixel region P2 corresponding to the second data line DL2 does not emit light, the voltage of the second data signal transmitted by the second data line DL2 is lower than the set operating voltage. In this case, the same second data line DL2 needs to transmit at least two different second data signals.

[0619] In this embodiment, by providing a data driving circuit 14, a control signal terminal IN(f), and a light-emitting data input terminal VL(f), the same second data line DL2 only needs to transmit a single light-emitting data signal. The light-emitting data signal transmitted by the signal line connecting the light-emitting data input terminal VL(f) to the data driving circuit 14 remains unchanged. Compared to using data lines DL to transmit light-emitting data signals, this simplifies the driving circuit of the display panel 100.

[0620] Moreover, during the light-emitting stage of the light-transmitting area BB, the second pixel electrodes 31 corresponding to the second sub-pixel areas P2 of different light-emitting colors are all coupled to the same light-emitting data input terminal VL(f). Through different connection methods of the data driving circuit 14, the control signal terminal IN(f) and the light-emitting data input terminal VL(f), the time-sharing lighting of the second sub-pixel areas P2 of different light-emitting colors is achieved.

[0621] Compared with setting different luminous data input terminals VL(f) for the second sub-pixel areas P2 of different luminous colors, some embodiments of the present disclosure can reduce the number of luminous data input terminals VL(f), thereby helping to reduce the width of the border AN of the display panel 100.

[0622] In some embodiments, as shown in FIG. 41 and FIG. 42 , the light-emitting data driving circuit 14 includes M transistors, and the control electrodes of the M transistors V are respectively coupled to M control signal terminals IN.

[0623] Exemplarily, as shown in FIG. 41 , the first light emitting data driving circuit 141 includes a first data driving transistor V1 and a first data driving transistor V1 ′.

[0624] The control electrode of the first data driving transistor V1 is electrically connected to the first control signal terminal IN(1), the first electrode of the first data driving transistor V1 is electrically connected to the first light-emitting data input terminal VL(1), and the second electrode of the first data driving transistor V1 is coupled to the second pixel electrode 31a of the first color pixel circuit 3a.

[0625] The first data driving transistor V1 is configured to be turned on under the control of the first control signal terminal IN(1) and transmit the first light emitting data signal provided by the first light emitting data input terminal VL(1) to the second pixel electrode 31a.

[0626] The control electrode of the first data driving transistor V1' is electrically connected to the second control signal terminal IN(2), the first electrode of the first data driving transistor V1' is electrically connected to the second light-emitting data input terminal VL(2), and the second electrode of the first data driving transistor V1' is coupled to the second pixel electrode 31a of the first color pixel circuit 3a.

[0627] The first data driving transistor V1 ′ is configured to be turned on under the control of the second control signal terminal IN( 2 ) and transmit the second light emitting data signal provided by the second light emitting data input terminal VL( 2 ) to the second pixel electrode 31 a .

[0628] As shown in FIG. 42 , the second light emitting data driving circuit 142 includes a second data driving transistor V2 and a second data driving transistor V2 ′.

[0629] The control electrode of the second data driving transistor V2 is electrically connected to the first control signal terminal IN2(1), the first electrode of the second data driving transistor V2 is electrically connected to the second light-emitting data input terminal VL(2), and the second electrode of the second data driving transistor V2 is coupled to the second pixel electrode 31b of the second color pixel circuit 3b.

[0630] The second data driving transistor V2 is configured to be turned on under the control of the first control signal terminal IN(1) and transmit the second light emitting data signal provided by the second light emitting data input terminal VL(2) to the second pixel electrode 31b.

[0631] The control electrode of the second data driving transistor V2 is electrically connected to the first control signal terminal IN(1), the first electrode of the second data driving transistor V2' is electrically connected to the first light-emitting data input terminal VL(1), and the second electrode of the second data driving transistor V2' is coupled to the second pixel electrode 31b of the second color pixel circuit 3b.

[0632] The second data driving transistor V2 ′ is configured to be turned on under the control of the second control signal terminal IN( 2 ) and transmit the first light emitting data signal provided by the first light emitting data input terminal VL( 1 ) to the second pixel electrode 31 b .

[0633] Different second sub-image areas P2 of different luminescent colors transmit luminescent data signals to corresponding second pixel electrodes 31 via different luminescent data driving circuits 14 (e.g., first luminescent data driving circuit 141 and second luminescent data driving circuit 142). The second pixel electrodes 31 corresponding to the second sub-image areas P2 of different luminescent colors are coupled to the same luminescent data input terminal VL(f). By using different connection methods between the data driving circuit 14, the control signal terminal IN(f), and the luminescent data input terminal VL(f), time-sharing lighting of the second sub-pixel areas P2 of different luminescent colors is achieved. This can reduce the number of luminescent data input terminals VL(f), thereby facilitating a reduction in the width of the bezel AN of the display panel 100.

[0634] Furthermore, the structure of the light emitting data driving circuit 14 is simple, so that the structure of the display panel 100 can be simplified.

[0635] The film structure of the display panel 100 is introduced below.

[0636] FIG44 is a partial cross-sectional view of the display area AA of the display panel 100 in some embodiments, in which only the first transistor T1 , the first pixel electrode 21 and the first common electrode 22 are shown.

[0637] In some embodiments, as shown in Figure 44, the display panel 100 includes: a gate conductive layer G, a first insulating layer J1, a source and drain conductive layer SD, a second insulating layer J2, a pixel electrode layer D1, a third insulating layer J3 and a common electrode layer D2 arranged in sequence along a direction away from the first substrate 1.

[0638] The display panel 100 further includes a first transistor T1. A control electrode T1 of the first transistor T1 G Located in the gate conductive layer G, the first electrode T1 of the first transistor T1 Sand the second electrode T1 of the first transistor T1 D Located in the source-drain conductive layer SD, the first pixel electrode 21 is located in the pixel electrode layer D1, and the first common electrode 22 is located in the common electrode layer D2.

[0639] The display panel 100 further includes: a second electrode T1 extending from the first pixel electrode 21 to the first transistor T1 D The first pixel electrode 21 is connected to the second electrode T1 of the first transistor T1 through the connection hole L. D Electrical connection.

[0640] 45 is a partially enlarged structural diagram of the display area AA of the display panel 100 , FIG46 is an enlarged structural diagram of the area V4 in FIG45 , and FIG47 is a cross-sectional structural diagram obtained according to the cross-sectional line G4 - G4 in FIG46 .

[0641] In other embodiments, as shown in FIG42, FIG45 and FIG46, the display panel 100 further includes: a first gate line GL1, a data line DL, a first transistor T1 and a switching electrode 14. The control electrode T1 of the first transistor T1 G The first gate line GL1 is electrically connected to the first electrode T1 of the first transistor T1. S The second electrode T1 of the first transistor T1 is electrically connected to the data line DL. D coupled to the first pixel electrode 21 .

[0642] As shown in Figure 47, the display panel 100 includes a gate conductive layer G, a first insulating layer J1, a source and drain conductive layer SD, a second insulating layer J2, a pixel electrode layer D1, a third insulating layer J3 and a common electrode layer D2, which are arranged in sequence along a direction away from the first substrate 1.

[0643] The first gate line GL1 and the control electrode T1 of the first transistor T1 G Located in the gate conductive layer G, the data line DL, the first electrode T1 of the first transistor T1 S and the second electrode T1 of the first transistor T1 D The first pixel electrode 21 is located in the pixel electrode layer D1 , and the switching electrode 14 and the first common electrode 22 are located in the common electrode layer D2 .

[0644] In the orthographic projection onto the first substrate 1 , the switching electrode 14 at least partially overlaps with the first pixel electrode 21 , and the switching electrode 14 overlaps with the second electrode T1 of the first transistor T1 D At least partially overlapping.

[0645] The display panel 100 further includes: a second electrode T1 extending from the switching electrode 14 to the first transistor T1 DThe first transfer via hole R1 and the second transfer via hole R2 extending from the transfer electrode 14 to the first pixel electrode 21 are formed.

[0646] The transfer electrode 14 is connected to the second electrode T1 of the first transistor T1 through the first transfer via R1. D Electrical connection: the transfer electrode 14 is electrically connected to the first pixel electrode 21 through the second transfer via R2.

[0647] In some embodiments of the present disclosure, as shown in FIG. 46 , by providing a switching electrode 14 , the first pixel electrode 21 is electrically connected to the switching electrode 14 , thereby reducing the resistance of the first pixel electrode 21 and further reducing the power consumption of the display panel 100 .

[0648] In some embodiments of the present disclosure, the transfer electrode 14 is provided and can be provided in the same layer as the first common electrode 22 . In this way, the transfer electrode 14 and the first common electrode 22 can be formed simultaneously in the same preparation step without adding additional preparation steps.

[0649] 44 , the first pixel electrode 21 passes through the second electrode T1 of the first transistor T1. D The connection hole L is connected to the second electrode T1 of the first transistor T1 D Thus, in the manufacturing process of the display panel 100, before forming the first pixel electrode 21, it is necessary to first form the second electrode T1 that penetrates the first transistor T1. D The connection hole L.

[0650] Based on this, in the display panel 100 provided by some embodiments of the present disclosure, as shown in FIG47 , the first pixel electrode 21 is connected to the second electrode T1 of the first transistor T1 via the switching electrode 14. D connected.

[0651] In this way, before forming the first pixel electrode 21, there is no need to set the connection hole L. After forming the first pixel electrode 21 and before forming the first common electrode 22, the first transfer via hole R1 and the second transfer via hole R2 are formed simultaneously through a punching step, so that the transfer electrode 14 formed in the subsequent process steps can connect the first pixel electrode 21 to the second electrode T1 of the first transistor T1 through the first transfer via hole R1 and the second transfer via hole R2. D While reducing the power consumption of the display panel 100, no additional process steps are added.

[0652] As shown in FIG44 , the first pixel electrode 21 passes through the second electrode T1 of the first transistor T1. D The connection hole is connected to the second electrode T1 of the first transistor T1 DThus, in the manufacturing process of the display panel 100, before forming the first common electrode 22, it is necessary to first form the second electrode T1 that penetrates the first transistor T1. D connection hole.

[0653] Exemplarily, the data line DL may be the aforementioned first data line DL1 .

[0654] Exemplarily, the third insulating layer J3 and the second spacer layer 33 described above may be the same film layer structure.

[0655] For example, as shown in FIG47 , the display panel 100 further includes an active layer B, which is located between the first substrate 1 and the gate conductive layer G. The active layer B includes an active pattern, and the gate conductive layer G includes a gate conductive pattern. The overlapping portion of the active pattern and the gate conductive pattern serves as a control electrode of a transistor (e.g., the first transistor T1 and the second transistor T2).

[0656] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel comprising a display area and a light-transmitting area located at least on one side of the display area; The light-transmitting area emits light of one color in one light-emitting period of the light-transmitting area; The display panel comprises: A first substrate and a second substrate arranged opposite to each other; A liquid crystal layer, disposed between the first substrate and the second substrate; a first pixel circuit, disposed between the first substrate and the second substrate and located in the display area; the first pixel circuit comprises a first pixel electrode and a first common electrode; the first pixel electrode and the first common electrode are configured to drive the movement of liquid crystal molecules in the liquid crystal layer; a second pixel circuit, disposed between the first substrate and the second substrate and located in the light-transmitting area; the second pixel circuit comprises a second pixel electrode and a second common electrode; the second pixel electrode and the second common electrode are configured to drive the movement of liquid crystal molecules in the liquid crystal layer; The sealing frame portion is arranged between the first substrate and the second substrate and is arranged around the liquid crystal layer; the inner side wall of the sealing frame portion is used to define a liquid crystal sealing area, and the display area and the light-transmitting area are both located in the liquid crystal sealing area.

2. The display panel according to claim 1, wherein: The display panel further comprises: a circuit structure located outside the display area; The circuit structure and the light-transmitting area are arranged side by side along an extension direction of at least one side boundary of the display area.

3. The display panel according to claim 2, wherein: The circuit structure includes a portion of the first common electrode line; the first common electrode line is electrically connected to the first common electrode.

4. The display panel according to claim 3, wherein: The first common electrode line is electrically connected to the second common electrode.

5. The display panel according to claim 4, wherein: The first common electrode line and the second common electrode are arranged in the same layer with a gap between them; The display panel further includes: a connection line, which is located on a side of the second common electrode close to or far from the first substrate and crosses the gap; the first common electrode line is electrically connected to the second common electrode through the connection line.

6. The display panel according to claim 5, wherein: The connecting line extends to the area where the first common electrode line is located, and is electrically connected to the first common electrode line through a plurality of connecting points in the area where the first common electrode line is located; and / or, The display panel includes a plurality of the second common electrodes, the plurality of the second common electrodes are connected to form an integral structure, the connection line extends to the light-transmitting area, and is electrically connected to the integral structure through a plurality of connection points in the light-transmitting area.

7. The display panel according to any one of claims 3 to 6, wherein: The display panel further includes: The second common electrode line is electrically connected to the first common electrode; the width of the first common electrode line is greater than the width of the second common electrode line.

8. The display panel according to any one of claims 2 to 7, wherein: The display panel further includes: an electrostatic protection circuit; The circuit structure includes a portion of a ground line; the ground line is electrically connected to the electrostatic protection circuit, the ground line is electrically insulated from the first common electrode, and the ground line is electrically insulated from the second common electrode.

9. The display panel according to claim 8, wherein: The ground line and the second common electrode are arranged in the same layer with a gap therebetween.

10. The display panel according to any one of claims 2 to 9, wherein: The circuit structure includes: a third pixel circuit located outside the display area and the light-transmitting area; The third pixel circuit includes a third pixel electrode and a third common electrode. The third pixel electrode is arranged in the same layer as the first pixel electrode, and the third common electrode and the first common electrode are an integrated structure.

11. The display panel according to any one of claims 2 to 10, wherein: The first common electrode and the second common electrode are arranged in the same layer.

12. The display panel according to claim 1, wherein: The first pixel electrode and the second pixel electrode are arranged in the same layer and made of the same material.

13. The display panel according to claim 1, wherein: The area defined by the first pixel circuit is a first sub-pixel area, the display area includes a plurality of first sub-pixel areas, the first sub-pixel areas are configured to emit light of one color, and at least two of the plurality of first sub-pixel areas emit light of different colors; The area defined by the second pixel circuit is a second sub-pixel area, and the light-transmitting area includes one or more second sub-pixel areas, and the second sub-pixel area is configured to emit light of one color; at least two of the multiple second sub-pixel areas emit light of different colors, or the light-emitting colors of the multiple second sub-pixel areas are all the same.

14. The display panel according to claim 13, wherein: The display panel further includes: A color filter layer, comprising a plurality of first filter portions located in the display area, the plurality of first filter portions being arranged corresponding to the plurality of first sub-pixel areas, and the plurality of first filter portions including filter portions of at least two filter colors; The thickness of the color filter layer in the area corresponding to the second sub-pixel area is 0; or, the color filter layer also includes: one or more second filter parts located in the light-transmitting area, each second filter part is arranged corresponding to a second sub-pixel area; the multiple second filter parts include filter parts of at least one filtering color.

15. The display panel according to claim 14, wherein: The filter parts with the same filter color are arranged in the same layer.

16. The display panel according to claim 1, wherein: The display panel further includes: a black matrix layer, wherein the black matrix layer has a plurality of first openings located in the display area, the first openings are arranged corresponding to the first pixel electrodes; along the arrangement direction of the light-transmitting area and the display area, a distance between two adjacent first openings is q; The black matrix layer also has a second opening that is as large as the light-transmitting area, and the distance between the first opening and the second opening that are closest to each other is w, 0.5q≤w≤1.5q, or w>1.5q; or, the black matrix layer also has a plurality of third openings located in the light-transmitting area, and the third openings are arranged corresponding to the second pixel electrode, and the distance between the first opening and the third opening that are closest to each other is r, 0.5q≤r≤1.5q, or r>1.5q.

17. The display panel according to claim 16, wherein: The display panel also has a sensor area located on one side of the display area, and the sensor area is located in the liquid crystal sealing area; The thickness of the black matrix layer in the area corresponding to the sensor area is 0.

18. The display panel according to claim 17, wherein: In an orthographic projection onto the first substrate, a boundary line of the black matrix layer surrounds the sensor area, and the black matrix layer has a fourth opening corresponding to the sensor area; or, In an orthographic projection onto the first substrate, the sensor region is outside a boundary line of the black matrix layer.

19. A display module, comprising: The display panel according to any one of claims 1 to 18; A circuit board, electrically connected to the display panel; The circuit board is configured to send a driving signal to the display panel.

20. The display module according to claim 19, wherein: The display module also includes: The sensor is arranged in the sensor area, and the light-transmitting area is configured to change the color of the emitted light according to the change of the working state of the sensor.

21. A display device, comprising: Backlight module; The display module according to claim 19 or 20, wherein the display module is arranged on the light emitting side of the backlight module; The backlight module has a first backlight area and a second backlight area; The display area of ​​the display module is projected on the backlight module within the range of the first backlight area; the light-transmitting area of ​​the display module is projected on the backlight module within the range of the second backlight area.

22. The display device according to claim 21, wherein: The first backlight area and the second backlight area can be independently controlled to be turned on and off.

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