Die lamination module and method for manufacturing die lamination module

Abstract

Provided is a die lamination module which inhibits degradation in reliability. A die lamination module 1 comprises: a first die laminate 101 and a second die laminate 102 which are each obtained by laminating an N number (N is an integer of 3-9) of dies 11, 12, 13, 14 with non-conductive films 30 therebetween, and which are arranged such that the second die laminate is laminated on the first die laminate; an underfill 50 which is interposed between the first die laminate 101 and the second die laminate 102; and a mold 40 which covers the first die laminate 101 and the second die laminate 102. At the boundary between the first die laminate 101 and the second die laminate 102, the underfill 50 is exposed to the side surface of the die lamination module 1. A die 11 in the lowest layer of the first die laminate 101 and a die 11 in the lowest layer of the second die laminate 102 are exposed to the side surface of the die lamination module 1.

Description

Die stacked module and method of manufacturing the die stacked module

[0001] The present invention relates to a die stack module and a method for manufacturing a die stack module.

[0002] In semiconductor modules such as memory modules or logic modules, a three-dimensional or two-and-a-half-dimensional packaging technology is known in which multiple semiconductor dies, such as multiple memory dies or multiple logic dies, are stacked using TSV (Through Silicon Via) technology. Such packaging technology allows high-density wiring to be formed on multiple semiconductor dies, such as multiple memory dies or multiple logic dies, thereby achieving miniaturization, thinning, and broadband.

[0003] Patent Documents 1 and 2 disclose such a die-stacked module. In this die-stacked module, multiple dies are stacked and arranged, and the multiple dies are electrically connected using TSV (Through Silicon Via) technology. In addition, a non-conductive film (NCF) is interposed between adjacent dies in the stacking direction, and the entire die-stacked module is molded.

[0004] U.S. Pat. No. 1,158,594 U.S. Pat. No. 1,289,454

[0005] Methods for manufacturing such die-stacked modules include, for example, a CoW process in which, using chip-on-wafer technology, multiple second-tier dies are two-dimensionally arranged at dicing intervals on a base wafer serving as a first-tier die via a non-conductive film; a CoC process in which, using chip-on-chip technology, multiple nth-tier dies are stacked on the multiple second-tier dies via a non-conductive film in (n-2) tiers to obtain an N-tier die-stacked wafer (N is an integer equal to or greater than 3, and n is an integer equal to or greater than 3 and N, inclusive); a molding process in which the entire die-stacked wafer is molded; and a dicing process in which the molded die-stacked wafer is divided into individual pieces along the dicing intervals to obtain a die-stacked module.

[0006] In such a manufacturing method for a die-stacked module, the heat and pressure applied in the CoW and CoC processes, in which multiple dies are stacked via a non-conductive film, can cause the non-conductive film to protrude from the side of the die into the space between the dicing holes.

[0007] This can cause voids during the molding process, as the protruding non-conductive film interferes with the mold's ability to fit into the dicing gap, reducing the reliability of the die-stacked module.

[0008] Furthermore, during the dicing process, protruding non-conductive film may be exposed on the side of the module mold, which can absorb moisture or allow moisture to penetrate through the interfaces between the non-conductive films or between the non-conductive film and the mold, reducing the reliability of the die-stacked module.

[0009] For example, the protrusion of the non-conductive film between the base wafer and the second die bulges upward on the base wafer, and the protrusion of the non-conductive film below the nth die bulges upward and further expands laterally due to the influence of the bulge below it. As a result, the more tiers the nth die has (e.g., 12 layers, 16 layers, etc.), the larger the lateral protrusion of the non-conductive film is expected to become, and the more pronounced the above-mentioned problem is expected to become.

[0010] Although this can be addressed by increasing the dicing interval, the more layers there are, the larger the dicing interval must be, which reduces the number of die stack modules that can be obtained from one wafer and increases costs.

[0011] An object of the present invention is to provide a die stacked module that suppresses a decrease in reliability and a method for manufacturing the die stacked module.

[0012] The die stack module of the present invention is a die stack module in which multiple dies are stacked and electrically connected using TSV technology, the die stack module comprising: a first die stack and a second die stack, each of which has N dies stacked thereon via a non-conductive film, the second die stack being stacked on the first die stack, where N is an integer between 3 and 9; an underfill interposed between the first die stack and the second die stack; and a mold covering the first die stack and the second die stack. At the boundary between the first die stack and the second die stack, the underfill is exposed at a side surface of the die stack module, and the bottom die in the first die stack and the bottom die in the second die stack are exposed at the side surface of the die stack module.

[0013] Another die stack module according to the present invention is a die stack module in which multiple dies are stacked and electrically connected using TSV technology, the die stack module comprising: a first die stack and a second die stack, each of which has N dies stacked thereon via a non-conductive film, the second die stack being stacked on the first die stack, where N is an integer between 3 and 9; an underfill or non-conductive film interposed between the first die stack and the second die stack; and a mold covering the first die stack and the second die stack. In each of the first die stack and the second die stack, the sizes of the N dies gradually decrease from the bottom layer to the top layer.

[0014] Another die stack module according to the present invention is a die stack module in which multiple dies are stacked and electrically connected using TSV technology, the multiple dies being stacked via a non-conductive film, and a mold covering the multiple dies, the sizes of the multiple dies gradually decreasing from the lower layer to the upper layer.

[0015] A method for manufacturing a die-stacked module according to the present invention is a method for manufacturing the die-stacked module, and includes: a die singulation process in which conductive bumps are formed on a die wafer on which a plurality of dies are formed two-dimensionally, and a non-conductive film is attached, and the plurality of dies with the non-conductive film attached are singulated to obtain a plurality of second-tier dies and a plurality of n-th tier dies; a CoW process in which, using chip-on-wafer technology, the plurality of second-tier dies are two-dimensionally arranged on a base wafer serving as first-tier dies via the non-conductive film at dicing intervals; a CoC process in which, using chip-on-chip technology, the plurality of n-th tier dies are stacked on the plurality of second-tier dies via the non-conductive film in (n-2) layers, respectively, to obtain an N-layer die-stacked wafer; a molding process in which N is an integer between 3 and 9, and n is an integer between 3 and N, inclusive; and a grinding process in which the top surface of the molded die-stacked wafer is ground to expose the back surface of the uppermost N-th tier die. This method for manufacturing a die stacked module further includes the steps of: grinding the top surface of the molded die stacked wafer obtained through the grinding step to expose TSVs, thereby obtaining a first die stacked wafer; obtaining the die stacked wafer obtained through the CoC step, the molded die stacked wafer obtained through the molding step, or the molded die stacked wafer obtained through the grinding step as a second die stacked wafer; stacking the second die stacked wafer on the first die stacked wafer via an underfill and molding the entire assembly to obtain a wafer stack; and dicing the wafer stack along the dicing intervals to obtain the die stacked module.

[0016] Another method for manufacturing a die stacked module according to the present invention is a method for manufacturing the above-mentioned other die stacked module, and includes a die singulation step of forming conductive bumps and attaching a non-conductive film on a die wafer on which a plurality of dies are formed two-dimensionally, and singulating the plurality of dies with the non-conductive film attached to obtain a plurality of second-stage dies and a plurality of n-stage dies, wherein the second-stage dies and the n-stage dies have different sizes, and using chip-on-wafer technology, a largest-sized die is mounted on a base wafer as a first-stage die via the non-conductive film. the CoW process of two-dimensionally arranging the plurality of second-tier dies, each having a dicing interval, and the CoC process of stacking a plurality of n-th tier dies in order of size on the plurality of second-tier dies via the non-conductive film using chip-on-chip technology to obtain an N-tier die-stacked wafer; the CoC process of molding the entire die-stacked wafer, where N is an integer of 3 to 9, and n is an integer of 3 to N, and the entire die-stacked wafer is molded; and the grinding process of grinding the top surface of the molded die-stacked wafer to expose the back surface of the uppermost N-th tier die. This other method for manufacturing a die stacked module further includes the steps of: grinding the top surface of the molded die stacked wafer obtained through the grinding step to expose TSVs, thereby obtaining a first die stacked wafer; obtaining the die stacked wafer obtained through the CoC step, the molded die stacked wafer obtained through the molding step, or the molded die stacked wafer obtained through the grinding step as a second die stacked wafer; stacking the second die stacked wafer on the first die stacked wafer via an underfill, and molding the entire assembly to obtain a wafer stack; and dicing the wafer stack along the dicing intervals to obtain the die stacked module.

[0017] Another method for manufacturing a die stacked module according to the present invention is a method for manufacturing the above-mentioned other die stacked module, and includes a die singulation step of forming conductive bumps and attaching a non-conductive film on a die wafer on which a plurality of dies are formed two-dimensionally, and singulating the plurality of dies with the non-conductive film attached to obtain a plurality of second-stage dies and a plurality of n-stage dies, wherein the second-stage dies and the n-stage dies have different sizes, and using chip-on-wafer technology, a largest-sized die is mounted on a base wafer as a first-stage die via the non-conductive film. the CoW process of two-dimensionally arranging the plurality of second-tier dies, each having a dicing interval, and the CoC process of stacking a plurality of n-th tier dies in order of size on the plurality of second-tier dies via the non-conductive film using chip-on-chip technology to obtain an N-tier die-stacked wafer; the CoC process of molding the entire die-stacked wafer, where N is an integer of 3 to 9, and n is an integer of 3 to N, and the entire die-stacked wafer is molded; and the grinding process of grinding the top surface of the molded die-stacked wafer to expose the back surface of the uppermost N-th tier die. This other method for manufacturing a die stacked module further includes the steps of: grinding the top surface of the molded die stacked wafer obtained by performing the grinding step to expose TSVs, thereby obtaining a die stacked wafer; attaching a non-conductive film to the die stacked wafer obtained by performing the CoC step, the molded die stacked wafer obtained by performing the molding step, or the molded die stacked wafer obtained by performing the grinding step, and singulating the plurality of die stacks with the non-conductive film attached, thereby obtaining a plurality of die stacks; two-dimensionally stacking the plurality of die stacks on the die stacked wafer via the non-conductive film using chip-on-wafer technology, with dicing gaps between them, and molding the whole to obtain a wafer stack; and singulating the wafer stack along the dicing gaps, thereby obtaining the die stacked module.

[0018] A further method for manufacturing a die stack module according to the present invention is a method for manufacturing the above-mentioned further other die stack module, comprising: a die singulation step of forming conductive bumps and attaching a non-conductive film on a die wafer on which a plurality of dies are formed two-dimensionally, and singulating the plurality of dies with the non-conductive film attached to obtain a plurality of second-tier dies and a plurality of n-th tier dies; wherein the second-tier dies and the n-th tier dies have different sizes, and the plurality of second-tier dies, which are the largest in size, are two-dimensionally diced at dicing intervals via the non-conductive film on a base wafer as a first-tier die using chip-on-wafer technology; a CoW process in which multiple n-th dies are stacked in (n-2) stages in order of size on the multiple second-stage dies via the non-conductive film using chip-on-chip technology to obtain an N-stage die-stacked wafer; a molding process in which the entire die-stacked wafer is molded; a grinding process in which the top surface of the molded die-stacked wafer is ground to expose the back surface of the N-th dies in the uppermost layer; and a process in which the molded die-stacked wafer after the grinding process is singulated along the dicing intervals to obtain the die-stacked modules.

[0019] According to the present invention, it is possible to suppress a decrease in reliability in a die stacked module.

[0020] FIG. 1 is a schematic cross-sectional view showing a die stack module according to a first embodiment. FIG. 2 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 3 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 4 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 5 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 6 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 7 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 8 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 9 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 10 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 11 is a view showing a method for manufacturing the die stack module according to the first embodiment. FIG. 12 is a view showing a method for manufacturing the die stack module according to a modification of the first embodiment. FIG. 13 is an enlarged view of the vicinity of a dicing gap of a conventional wafer stack. FIG. 14 is a schematic cross-sectional view showing a die stack module according to a second embodiment. FIG. 15 is a view showing a method for manufacturing the die stack module according to the second embodiment. FIG. 16 is a view showing a method for manufacturing the die stack module according to the second embodiment. FIG. 17 is a view showing a method for manufacturing the die stack module according to the second embodiment. FIG. 18 is a view showing a method for manufacturing the die stack module according to the second embodiment. FIG. 19 is a view showing a method for manufacturing the die stack module according to the second embodiment. 10A to 10C are diagrams illustrating a method for manufacturing a die stacked module according to a third embodiment, a method for manufacturing a die stacked module according to a modification of the third embodiment, and a method for manufacturing a die stacked module according to a modification of the third embodiment.

[0021] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0022] 1 is a schematic cross-sectional view showing a die-stacked module according to the first embodiment. The die-stacked module 1 shown in Fig. 1 is a stacked module in which multiple dies 11, 12, 13, and 14 are stacked via non-conductive films (NCFs) 30 and electrically connected using TSV (Through Silicon Via) technology (21).

[0023] Although this embodiment illustrates a memory die stacked module including a memory die on which a memory element is formed, the present invention is not limited to this and can also be applied to various die stacked modules in which various semiconductor dies, such as multiple logic dies, are stacked.

[0024] The die stack module 1 includes a plurality of die stacks 101 and 102, a mold 40, and an underfill 50. The plurality of die stacks includes a first die stack 101 and a second die stack 102.

[0025] In this embodiment, the multiple die stack is exemplified as including two die stacks, i.e., a first die stack 101 and a second die stack 102. However, the present invention is not limited to this, and may be configured as including three or more die stacks, i.e., a first die stack 101 and multiple second die stacks 102.

[0026] In each of the first die stack 101 and the second die stack 102, N dies 11, 12, 13, and 14 (N is an integer between 3 and 9) are stacked via an NCF 30. Each of the dies 11, 12, 13, and 14 is, for example, a silicon die in which a TSV 21 is formed, penetrating from a front surface 10F, which is a circuit layer in which memory elements are formed, to a back surface 10R. In each of the dies 11, 12, 13, and 14, pads 22 are formed on the front surface 10F and the back surface 10R.

[0027] In this embodiment, the N dies include four memory dies on which memory elements are formed. However, the present invention is not limited to this, and may include three to eight memory dies, or may include a base die on which input / output circuits for the memory elements are formed in addition to the memory dies.

[0028] The pads 22 on the back surface 10R of the die 11 and the pads 22 on the front surface 10F of the die 12 are electrically connected by microbumps 23. The pads 22 on the back surface 10R of the die 12 and the pads 22 on the front surface 10F of the die 13 are electrically connected by microbumps 23. The pads 22 on the back surface 10R of the die 13 and the pads 22 on the front surface 10F of the die 14 are electrically connected by microbumps 23.

[0029] In this manner, in each of the first die stack 101 and the second die stack 102, the dies 11, 12, 13, and 14 are electrically connected by the TSVs 21, the pads 22, and the microbumps 23.

[0030] The second die stack 102 is stacked on the first die stack 101 via an underfill 50. TSVs 21 are exposed on the back surface 10R of the top die 14 of the first die stack 101, and pads 22 are formed on the back surface 10R. The pads 22 on the back surface 10R of the top die 14 of the first die stack 101 and the pads 22 on the front surface 10F of the bottom die 11 of the second die stack 102 are electrically connected by microbumps 23.

[0031] In this manner, the first die stack 101 and the second die stack 102 are electrically connected by the pads 22 and the microbumps 23 .

[0032] Microbumps 23 are arranged on pads 22 on the front surface 10F of the bottom die 11 of the first die stack 101. Furthermore, the TSVs 21 are not exposed on the back surface 10R of the top die 14 of the second die stack 102.

[0033] In addition, when there are multiple second die stacks 102, the second die stacks 102 may be stacked with the underfill 50 interposed therebetween and connected by the microbumps 23.

[0034] The NCF 30 is disposed between the dies 11, 12, 13, and 14 in each of the first die stack 101 and the second die stack 102. The NCF 30 is in a film form, and examples of the material for the NCF 30 include thermosetting resin.

[0035] The underfill 50 is interposed between the first die stack 101 and the second die stack 102. When there are multiple second die stacks 102, the underfill 50 may also be interposed between the second die stacks 102. Examples of materials for the underfill 50 include epoxy resin.

[0036] The mold 40 covers the first die stack 101 and the second die stack 102. The mold 40 may be made of a material such as resin.

[0037] At the boundary between the first die stack 101 and the second die stack 102, the underfill 50 is exposed on the side of the die stack module 1. In addition, the bottom die 11 in the first die stack 101 and the bottom die 11 in the second die stack 102 are exposed on the side of the die stack module 1.

[0038] (Manufacturing Method) Next, a method for manufacturing the above-described die stacked module 1 will be described with reference to Figures 2A to 2I. Figures 2A to 2I are diagrams illustrating a method for manufacturing the die stacked module according to the first embodiment.

[0039] 2A, a base wafer 11W as a first-stage die 11 is temporarily bonded onto a glass carrier (support substrate) 5. The base wafer 11W is a silicon wafer on which a plurality of TSVs 21 are formed, and pads 22 are formed on a surface 10F, which is a circuit layer of the base wafer 11W.

[0040] Specifically, microbumps 23 are placed on pads 22 on the front surface 10F of the base wafer 11W, and adhesive 24 is applied to the front surface 10F of the base wafer 11W. Next, the base wafer 11W is bonded to the glass carrier 5 via the adhesive 24 so that the front surface 10F of the base wafer 11W faces the glass carrier 5. Next, the back surface 10R of the base wafer 11W is ground to expose the TSVs 21, and pads 22 are formed on the TSVs 21 exposed on the back surface 10R of the base wafer 11W.

[0041] Next, as shown in FIG. 2B , a plurality of second-stage dies 12 and a plurality of n-stage dies 13 and 14 are obtained from the wafers 12W, 13W, and 14W, respectively (die singulation process). Each of the wafers 12W, 13W, and 14W is a silicon wafer having a plurality of TSVs 21 formed therein, and a pad 22 is formed on the surface 10F. The dies 12, 13, and 14 are formed two-dimensionally on the surface 10F of the wafers 12W, 13W, and 14W, respectively.

[0042] Specifically, microbumps (conductive bumps) 23 are arranged on pads 22 on the front surface 10F of each of the wafers 12W, 13W, and 14W. The back surface 10R of each of the wafers 12W, 13W, and 14W is ground to expose the TSVs 21, and pads 22 are formed on the TSVs 21 exposed on the back surface 10R of each of the wafers 12W, 13W, and 14W. Next, the wafers 12W, 13W, and 14W are attached to the dicing tape 6 so that the back surface 10R of each of the wafers 12W, 13W, and 14W faces the dicing tape 6.

[0043] Next, an NCF 30F is attached to the front surface 10F of each of the wafers 12W, 13W, and 14W. Next, the dies 12, 13, and 14 to which the NCF 30F is attached are separated into individual pieces along dicing lines D. In this manner, a plurality of second-stage dies 12 to which the NCF 30 is attached and a plurality of n-th stage dies 13 and 14 to which the NCF 30 is attached are obtained.

[0044] Next, as shown in Fig. 2C, using chip-on-wafer (CoW) technology, multiple second-tier dies 12 are two-dimensionally arranged on a base wafer 11W serving as a first-tier die, with NCFs 30 interposed between them at a dicing interval W (CoW process). Specifically, the dies 12 are stacked in order on the base wafer 11W via the NCFs 30 so that the front surfaces 10F of the dies 12 face the back surface 10R of the base wafer 11W. The dicing interval is, for example, 300 μm to 600 μm.

[0045] 2D and 2E , using chip-on-chip (CoC) technology, multiple n-th dies 13 and 14 are stacked on multiple second-stage dies 12 via NCFs 30 in (n−2) stages to obtain an N-stage die-stacked wafer 100A (CoC process). Here, N is an integer between 3 and 9, and n is an integer between 3 and N. Specifically, the dies 13 are stacked on the dies 12 in order via the NCFs 30 so that the front surfaces 10F of the dies 13 face the back surfaces 10R of the dies 12. Next, the dies 14 are stacked on the dies 13 in order via the NCFs 30 so that the front surfaces 10F of the dies 14 face the back surfaces 10R of the dies 13.

[0046] Next, as shown in FIG. 2F, the entire die-stacked wafer 100A is molded to obtain a die-stacked wafer 100B (molding step).

[0047] Next, as shown in FIG. 2G, the upper surface of the molded die-stacked wafer 100B is ground to expose the back surface 10R of the uppermost Nth die 14, thereby obtaining a die-stacked wafer 100C (grinding step).

[0048] 2H , the top surface of the molded die-stacked wafer 100C obtained through the grinding process is further ground to expose the TSVs 21 on the back surface 10R of the Nth die 14 in the top layer, and pads 22 are formed on the exposed TSVs 21. This results in a first die-stacked wafer 101W.

[0049] Next, the glass carrier 5 and adhesive 24 are peeled off from the die-stacked wafer 100A obtained through the CoC process to expose the microbumps 23. In this way, a second die-stacked wafer 102W is obtained.

[0050] As shown in FIG. 3, the glass carrier 5 and adhesive 24 of the molded die-stacked wafer 100B obtained through the molding process may be peeled off to expose the microbumps 23, thereby obtaining a second die-stacked wafer 102W.

[0051] Alternatively, the glass carrier 5 and adhesive 24 may be peeled off from the molded die-stacked wafer 100C obtained through the grinding process, exposing the microbumps 23 to obtain the second die-stacked wafer 102W.

[0052] 2I , the second die-stacked wafer 102W is stacked on the first die-stacked wafer 101W via the underfill 50 to obtain a wafer stack 1W. Specifically, the second die-stacked wafer 102W is stacked on the first die-stacked wafer 101W, and the underfill 50 is injected between the first die-stacked wafer 101W and the second die-stacked wafer 102W.

[0053] Next, the entire wafer stack 1W is molded again, and the upper surface of the molded wafer stack 1W is ground.

[0054] Note that multiple second die-stacked wafers 102W may be stacked. Specifically, the top surface of the wafer stack 1W, i.e., the top surface of the second die-stacked wafer 102W, is further ground to expose the TSVs 21 on the back surface 10R of the Nth die 14 in the topmost layer of the second die-stacked wafer 102W, and pads 22 are formed on the exposed TSVs 21. Another second die-stacked wafer 102W is stacked on the second die-stacked wafer 102W with an underfill 50 interposed therebetween, the entire wafer stack 1W is molded again, and the top surface of the molded wafer stack 1W is ground.

[0055] Next, the glass carrier 5 and adhesive 24 are peeled off from the wafer stack 1W to expose the microbumps 23. Next, the wafer stack 1W is divided into individual pieces along the dicing interval W. This results in the die stack module 1 shown in FIG.

[0056] Here, Figure 4 is an enlarged view of the vicinity of the dicing gap W of the wafer stack in a conventional die stack module manufacturing method. The conventional die stack module manufacturing method shown in Figure 4 does not include the steps of Figures 2H and 2I. The dicing step is performed after the die singulation step, CoW step, CoC step, molding step, and grinding step shown in Figures 2A to 2G. In this conventional die stack module manufacturing method, if the number of layers is to be increased, the number of layers is increased in the CoC step shown in Figure 2E.

[0057] As shown in FIG. 4, the NCF may protrude from the side of the die into a dicing space W1 of the dicing interval W due to the heat and pressure applied in the CoW and CoC processes in which multiple dies are stacked via the NCF.

[0058] As a result, the protruding NCF interferes with the molding process, preventing the mold from fully fitting into the dicing gap W, which can result in voids, reducing the reliability of the die stacked module.

[0059] Furthermore, during the dicing process, the NCF may protrude and become exposed on the mold side of the module. This can cause the exposed NCF to absorb moisture or allow moisture to penetrate through the interfaces between the NCFs or between the NCF and the mold, reducing the reliability of the die-stacked module.

[0060] For example, the NCF protrusion between the base wafer and the second die bulges upward on the base wafer, and the non-conductive film protrusion below the nth die not only bulges upward but also spreads further laterally due to the influence of the bulge below it. As a result, the greater the number of tiers in the nth die (e.g., 12 layers, 16 layers, etc.), the greater the lateral protrusion of the non-conductive film is expected to become, and the above-mentioned problem is expected to become more pronounced.

[0061] Although this can be addressed by increasing the dicing spacing W, the more layers there are, the larger the dicing spacing W must be, which reduces the number of die stack modules that can be obtained from one wafer and increases costs.

[0062] In these respects, according to the first embodiment of the die stack module manufacturing method and die stack module 1, the second die stack 102 is stacked on the first die stack 101, and in each of the first die stack 101 and the second die stack 102, the number of dies stacked directly via the NCF 30 can be reduced to 9 layers or less.

[0063] This reduces the possibility that the mold 40 will not fully fit into the dicing gap W due to the overflow of the NCF 30 during the molding process, thereby reducing the occurrence of voids, thereby preventing a decrease in the reliability of the die stacked module 1.

[0064] Furthermore, in the dicing process, it is possible to reduce the exposure of the protruding NCF 30 to the mold 40 on the side surface of the module, thereby reducing the absorption of moisture by the exposed NCF 30 and the intrusion of moisture from the interface between the NCFs or the interface between the NCF and the mold, thereby suppressing a decrease in the reliability of the die stacked module 1.

[0065] Second Embodiment (Configuration) In the first embodiment, the sizes of the dies 12, 13, and 14 in the second and subsequent tiers, excluding the first-tier die 11, are the same in each of the first die stack 101 and the second die stack 102. In the second embodiment, the sizes of the dies 12, 13, and 14 in the second and subsequent tiers are also different in each of the first die stack 101 and the second die stack 102.

[0066] Fig. 5 is a schematic cross-sectional view showing a die stack module according to a second embodiment. The die stack module 1 shown in Fig. 5 differs from the die stack module 1 shown in Fig. 1 in that the sizes of not only the first die 11 but also the second and subsequent die dies 12, 13, and 14 in each of the first die stack 101 and the second die stack 102 are different.

[0067] Specifically, in each of the first die stack 101 and the second die stack, the sizes of the N dies 11, 12, 13, and 14 gradually decrease from the bottom layer to the top layer, while the sizes of the circuit regions of the (N-1) dies 12, 13, and 14, excluding the bottommost die 11, are the same.

[0068] In this embodiment, the multiple die stack includes two die stacks, i.e., the first die stack 101 and the second die stack 102, but the multiple die stack may include three or more die stacks, i.e., the first die stack 101 and multiple second die stacks 102. In this case, the second die stack 102 may be stacked via the underfill 50 and connected by the microbumps 23.

[0069] In addition, in this embodiment, the N dies are exemplified as including four memory dies on which memory elements are formed, but the present invention is not limited to this and may be a form including three to eight memory dies, or a form including, in addition to the memory dies, a base die on which input / output circuits for the memory elements are formed.

[0070] (Manufacturing Method) Next, a method for manufacturing the above-described die stacked module 1 will be described with reference to Figures 6A to 6I. Figures 6A to 6I are diagrams showing a method for manufacturing the die stacked module according to the second embodiment.

[0071] 6A , a base wafer 11W serving as a first-stage die 11 is temporarily bonded onto a glass carrier (support substrate) 5. The base wafer 11W is a silicon wafer on which a plurality of TSVs 21 are formed, and pads 22 are formed on a surface 10F, which is a circuit layer of the base wafer 11W.

[0072] Specifically, microbumps 23 are placed on pads 22 on the front surface 10F of the base wafer 11W, and adhesive 24 is applied to the front surface 10F of the base wafer 11W. Next, the base wafer 11W is bonded to the glass carrier 5 via the adhesive 24 so that the front surface 10F of the base wafer 11W faces the glass carrier 5. Next, the back surface 10R of the base wafer 11W is ground to expose the TSVs 21, and pads 22 are formed on the TSVs 21 exposed on the back surface 10R of the base wafer 11W.

[0073] Next, as shown in FIG. 6B , a plurality of second-stage dies 12 and a plurality of n-stage dies 13 and 14 are obtained from the wafers 12W, 13W, and 14W, respectively (die singulation process). Each of the wafers 12W, 13W, and 14W is a silicon wafer having a plurality of TSVs 21 formed therein, and a pad 22 is formed on the surface 10F. Furthermore, the dies 12, 13, and 14 are formed two-dimensionally on the surface 10F of the wafers 12W, 13W, and 14W, respectively.

[0074] Specifically, microbumps (conductive bumps) 23 are arranged on pads 22 on the front surface 10F of each of the wafers 12W, 13W, and 14W. The back surface 10R of each of the wafers 12W, 13W, and 14W is ground to expose the TSVs 21, and pads 22 are formed on the TSVs 21 exposed on the back surface 10R of each of the wafers 12W, 13W, and 14W. Next, the wafers 12W, 13W, and 14W are attached to the dicing tape 6 so that the back surface 10R of each of the wafers 12W, 13W, and 14W faces the dicing tape 6.

[0075] Next, an NCF 30F is attached to the front surface 10F of each of the wafers 12W, 13W, and 14W. Next, the dies 12, 13, and 14 to which the NCF 30F is attached are separated into individual pieces along dicing lines D. In this manner, a plurality of second-stage dies 12 to which the NCF 30 is attached and a plurality of n-th stage dies 13 and 14 to which the NCF 30 is attached are obtained.

[0076] The second die 12 and the nth die 13, 14 have different sizes that gradually decrease from the lower die 12 to the upper die 13. On the other hand, the circuit area sizes of the second die 12 and the nth die 13, 14 are the same.

[0077] 6C , using chip-on-wafer (CoW) technology, a plurality of second-tier dies 12, which are the largest in size, are two-dimensionally arranged on a base wafer 11W as a first-tier die, with a dicing interval W therebetween, via NCFs 30 (CoW process). Specifically, the dies 12 are stacked in order on the base wafer 11W via the NCFs 30 so that the front surfaces 10F of the dies 12 face the back surface 10R of the base wafer 11W.

[0078] Next, as shown in Figures 6D and 6E, using chip-on-chip (CoC) technology, multiple n-th dies 13 and 14 are stacked on multiple second-stage dies 12 via NCFs 30 in (n-2) stages in descending order of size, thereby obtaining an N-stage die-stacked wafer 100A (CoC process). Here, N is an integer between 3 and 9, and n is an integer between 3 and N. Specifically, the dies 13 are stacked on the dies 12 in order via the NCFs 30 so that the front surfaces 10F of the dies 13 face the back surfaces 10R of the dies 12. Next, the dies 14 are stacked on the dies 13 in order via the NCFs 30 so that the front surfaces 10F of the dies 14 face the back surfaces 10R of the dies 13.

[0079] Next, as shown in FIG. 6F, the entire die-stacked wafer 100A is molded to obtain a die-stacked wafer 100B (molding step).

[0080] Next, as shown in FIG. 6G, the upper surface of the molded die-stacked wafer 100B is ground to expose the back surface 10R of the uppermost Nth die 14, thereby obtaining a die-stacked wafer 100C (grinding step).

[0081] 6H , the top surface of the molded die-stacked wafer 100C obtained through the grinding process is further ground to expose the TSVs 21 on the back surface 10R of the Nth die 14 in the top layer, and pads 22 are formed on the exposed TSVs 21. This results in a first die-stacked wafer 101W.

[0082] Next, the glass carrier 5 and adhesive 24 are peeled off from the die-stacked wafer 100A obtained through the CoC process to expose the microbumps 23. In this way, a second die-stacked wafer 102W is obtained.

[0083] As shown in FIG. 7, the glass carrier 5 and adhesive 24 of the molded die-stacked wafer 100B obtained through the molding process may be peeled off to expose the microbumps 23, thereby obtaining a second die-stacked wafer 102W.

[0084] Alternatively, the glass carrier 5 and adhesive 24 may be peeled off from the molded die-stacked wafer 100C obtained through the grinding process, exposing the microbumps 23 to obtain the second die-stacked wafer 102W.

[0085] 6I, the second die-stacked wafer 102W is stacked on the first die-stacked wafer 101W via the underfill 50 to obtain a wafer stack 1W. Specifically, the second die-stacked wafer 102W is stacked on the first die-stacked wafer 101W, and the underfill 50 is injected between the first die-stacked wafer 101W and the second die-stacked wafer 102W.

[0086] Next, the entire wafer stack 1W is molded again, and the upper surface of the molded wafer stack 1W is ground.

[0087] Note that multiple second die-stacked wafers 102W may be stacked. Specifically, the top surface of the wafer stack 1W, i.e., the top surface of the second die-stacked wafer 102W, is further ground to expose the TSVs 21 on the back surface 10R of the Nth die 14 in the topmost layer of the second die-stacked wafer 102W, and pads 22 are formed on the exposed TSVs 21. Another second die-stacked wafer 102W is stacked on the second die-stacked wafer 102W with an underfill 50 interposed therebetween, the entire wafer stack 1W is molded again, and the top surface of the molded wafer stack 1W is ground.

[0088] Next, the glass carrier 5 and adhesive 24 are peeled off from the wafer stack 1W to expose the microbumps 23. Next, the wafer stack 1W is divided into individual pieces along the dicing interval W. This results in the die stack module 1 shown in FIG.

[0089] According to the die stack module manufacturing method and die stack module 1 of the second embodiment, the second die stack 102 is stacked on the first die stack 101, and in each of the first die stack 101 and the second die stack 102, the sizes of the multiple dies 11, 12, 13, and 14 gradually decrease from the bottom to the top. As a result, as shown in FIG. 8 , the protruding NCF 30 below the nth die 13 or 14 is not affected by the protruding NCF 30 below it, and further lateral expansion is reduced. Note that the NCF protruding from under a die adheres to the side of that die.

[0090] This reduces the possibility that the mold 40 will not fully fit into the dicing gap W due to the protruding NFC 30 during the molding process, thereby reducing the occurrence of voids. As a result, it is possible to suppress a decrease in the reliability of the die stacked module 1.

[0091] Furthermore, in the dicing process, it is possible to reduce the exposure of the protruding NCF 30 to the mold 40 on the side surface of the module, thereby reducing the absorption of moisture by the exposed NCF 30 and the intrusion of moisture from the interface between the NCFs or the interface between the NCF and the mold, thereby suppressing a decrease in the reliability of the die stacked module 1.

[0092] (Third Embodiment) (Configuration) In the second embodiment, the die 11 in each of the first die stack 101 and the second die stack 102 is exposed on the side surface of the die stack module 1. In the third embodiment, the die 11 of the second die stack 102 is not exposed on the side surface of the die stack module 1.

[0093] 9 is a schematic cross-sectional view showing a die stack module according to a third embodiment. In the die stack module 1 shown in FIG. 6 , the first die 11 of the second die stack 102 is not exposed at the side surface of the die stack module 1.

[0094] An NCF 30 is interposed between the first die stack 101 and the second die stack 102 instead of an underfill.

[0095] In this embodiment, the multiple die stack includes two die stacks, i.e., the first die stack 101 and the second die stack 102, but the multiple die stack may include three or more die stacks, i.e., the first die stack 101 and multiple second die stacks 102. In this case, the second die stack 102 may be stacked via the NCF 30 and connected by the microbumps 23.

[0096] In addition, in this embodiment, the N dies are exemplified as including four memory dies on which memory elements are formed, but the present invention is not limited to this and may be a form including three to eight memory dies, or a form including, in addition to the memory dies, a base die on which input / output circuits for the memory elements are formed.

[0097] (Manufacturing Method) Next, a method for manufacturing the above-described die stacked module 1 will be described with reference to Figures 10A and 10B. Figures 10A and 10B are diagrams illustrating a method for manufacturing the die stacked module according to the second embodiment.

[0098] First, as described above, the die singulation step, CoW step, CoC step, molding step, and grinding step shown in FIGS. 6A to 6G are performed.

[0099] 10A , the top surface of the molded die-stacked wafer 100C obtained through the grinding process is further ground to expose the TSVs 21 on the back surface 10R of the Nth die 14 in the top layer, and pads 22 are formed on the exposed TSVs 21. In this way, a die-stacked wafer 101W is obtained.

[0100] Next, the glass carrier 5 and adhesive 24 are peeled off from the die-stacked wafer 100A obtained by performing the CoC process, an NFC 30 is attached to the die-stacked wafer 100A, and the multiple die stacks 102 with the NFC 30 attached are diced into individual pieces to obtain multiple die stacks 102.

[0101] As shown in FIG. 11 , the glass carrier 5 and adhesive 24 may be peeled off from the molded die-stacked wafer 100B obtained through the molding process, an NFC 30 may be attached to the die-stacked wafer 100B, and the multiple die stacks 102 with the NFC 30 attached may be separated into individual pieces to obtain multiple die stacks 102.

[0102] Alternatively, the glass carrier 5 and adhesive 24 may be peeled off from the molded die-stacked wafer 100C obtained through the grinding process, an NFC 30 may be attached to the die-stacked wafer 100C, and the multiple die stacks 102 with the NFC 30 attached may be separated into individual pieces to obtain multiple die stacks 102.

[0103] Next, as shown in FIG. 10B, using chip-on-wafer (CoW) technology, a plurality of die stacks 102 are two-dimensionally arranged on a die-stacked wafer 101W via NCFs 30 at dicing intervals W.

[0104] Next, the entire wafer stack 1W is molded again, and the upper surface of the molded wafer stack 1W is ground.

[0105] Note that multiple die stacks 102 may be stacked. Specifically, the top surface of the wafer stack 1W, i.e., the top surface of the die stack 102, is further ground to expose the TSVs 21 on the back surface 10R of the Nth die 14 in the top layer of the die stack 102, and pads 22 are formed on the exposed TSVs 21. Multiple more die stacks 102 are further stacked on the multiple die stacks 102 via the NCF 30, the entire wafer stack 1W is molded again, and the top surface of the molded wafer stack 1W is ground.

[0106] Next, the glass carrier 5 and adhesive 24 are peeled off from the wafer stack 1W to expose the microbumps 23. Next, the wafer stack 1W is divided into individual pieces along the dicing interval W. This results in the die stack module 1 shown in FIG.

[0107] The die stack module 1 of the third embodiment also provides the same advantages as the die stack module 1 of the second embodiment.

[0108] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the features of the above-described embodiments may be combined and applied.

[0109] In the second embodiment described above, for example, the die stacked module 1 is illustrated in which the second die stack 102 is stacked on the first die stack 101. However, the features of the present invention are not limited to this, and may also be applied to a die stacked module configured with a single die stack.

[0110] Specifically, the die stack module may be configured with only one die stack as shown in Fig. 5. That is, the die stack module may include a plurality of dies stacked with a non-conductive film interposed therebetween and a mold covering the plurality of dies, and the sizes of the plurality of dies gradually decrease from the lower layer to the upper layer.

[0111] As a manufacturing method for this die-stacked module, as described above, the die-single process, CoW process, CoC process, molding process, and grinding process shown in Figures 6A to 6G are performed, and then the die-stacked wafer 100C shown in Figure 6G is diced along the dicing intervals.

[0112] REFERENCE SIGNS LIST 1 Die stack module 5 Glass carrier (support substrate) 6 Dicing tape 11, 12, 13, 14 Die 11W, 12W, 13W, 14W Wafer 21 TSV 22 Pad 23 Microbump (conductive bump) 24 Adhesive 30, 30F NCF (non-conductive film) 40 Mold 50 Underfill 100A, 100B, 100C Die stack wafer 101 First die stack 102 Second die stack 101W First die stack wafer 102W Second die stack wafer

Claims

1. A die stack module in which a plurality of dies are stacked and electrically connected using TSV technology, A first die stack body and a second die stack body in which N dies are respectively stacked via a non-conductive film, and the second die stack body is stacked on the first die stack body, The first die stack body and the second die stack body, where N is an integer of 3 or more and 9 or less, Underfill intervening between the first die stack body and the second die stack body, A mold covering the first die stack body and the second die stack body, The underfill is exposed on the side surface of the die stack module at the boundary between the first die stack body and the second die stack body, The lowermost die in the first die stack body and the lowermost die in the second die stack body are exposed on the side surface of the die stack module. Die stack module.

2. A plurality of the second die stack bodies are stacked on the first die stack body, Underfill intervenes between the second die stack bodies, The plurality of second die stack bodies are covered with the mold, The underfill is exposed on the side surface of the die stack module at the boundary between the plurality of second die stack bodies, The lowermost die in the plurality of second die stack bodies is exposed on the side surface of the die stack module. The die stack module according to claim 1.

3. A die stack module in which a plurality of dies are stacked and electrically connected using TSV technology, A first die stack body and a second die stack body in which N dies are respectively stacked via a non-conductive film, and the second die stack body is stacked on the first die stack body, The first die stack body and the second die stack body, where N is an integer of 3 or more and 9 or less, Underfill or a non-conductive film intervening between the first die stack body and the second die stack body, A mold covering the first die stack body and the second die stack body, In each of the first die stack body and the second die stack body, the sizes of the N dies gradually decrease from the lower layer to the upper layer. Die stack module.

4. A plurality of the second die stacks are laminated on the first die stack, the underfill or the non-conductive film is interposed between the second die stacks, the plurality of second die stacks are covered by the mold, and in each of the plurality of second die stacks, the sizes of the N dies gradually decrease from the lower layer to the upper layer. The die stack module according to claim 3.

5. The sizes of the circuit regions of the (N - 1) dies excluding the lowermost die among the N dies are the same. The die stack module according to claim 3.

6. A die stack module in which a plurality of dies are laminated and electrically connected using TSV technology, comprising: a plurality of dies laminated via a non-conductive film; and a mold covering the plurality of dies, wherein the sizes of the plurality of dies gradually decrease from the lower layer to the upper layer. The die stack module.

7. The sizes of the circuit regions of the dies excluding the lowermost die among the plurality of dies are the same. The die stack module according to claim 6.

8. A method for manufacturing the die stack module according to claim 1, comprising: forming conductive bumps and attaching a non-conductive film on a die wafer on which a plurality of dies are two-dimensionally formed; singulating the plurality of dies to which the non-conductive film is attached to obtain a plurality of second-stage dies and a plurality of n-stage dies; a die singulation step; a CoW step of two-dimensionally arranging the plurality of second-stage dies on a base wafer as a first-stage die with a dicing interval via the non-conductive film using chip-on-wafer technology; a CoC step of stacking the plurality of n-stage dies on the plurality of second-stage dies via the non-conductive film using chip-on-chip technology, with each of (n - 2) stages stacked to obtain an N-stage die stack wafer, where N is an integer from 3 to 9 and n is an integer from 3 to N; a molding step of molding the entire die stack wafer; a grinding step of grinding the upper surface of the molded die stack wafer to expose the back surface of the uppermost N-stage die; a step of grinding the upper surface of the molded die stack wafer obtained up to the grinding step to expose the TSV to obtain a first die stack wafer; a step of obtaining the die stack wafer obtained up to the CoC step, the molded die stack wafer obtained up to the molding step, or the molded die stack wafer obtained up to the grinding step as a second die stack wafer; a step of stacking the second die stack wafer on the first die stack wafer via underfill and molding the whole to obtain a wafer stack; and a step of singulating the wafer stack along the dicing interval to obtain the die stack module.

9. In the step of obtaining the wafer stack, the upper surface of the second die stack wafer on the first die stack wafer is ground to expose the TSV, and the second die stack wafer is stacked on the second die stack wafer on the first die stack wafer via underfill and molded to obtain the wafer stack in which a plurality of the second die stacks are stacked on the first die stack body. The method for manufacturing a die stack module according to claim 8.

10. A method for manufacturing the die stack module according to claim 3, comprising: forming conductive bumps and attaching a non-conductive film on a die wafer on which a plurality of dies are formed two-dimensionally; singulating the plurality of dies to which the non-conductive film is attached to obtain a plurality of second-stage dies and a plurality of n-stage dies, wherein the second-stage dies and the n-stage dies have different sizes; using chip-on-wafer technology, arranging the plurality of second-stage dies having the largest size two-dimensionally with a dicing interval on a base wafer as a first-stage die through the non-conductive film, which is a CoW process; using chip-on-chip technology, stacking a plurality of n-stage dies on the plurality of second-stage dies through the non-conductive film in (n - 2) stages in descending order of size to obtain an N-stage die stack wafer, where N is an integer of 3 or more and 9 or less, and n is an integer of 3 or more and N or less, which is a CoC process; molding the entire die stack wafer, which is a molding process; grinding the upper surface of the molded die stack wafer to expose the back surface of the uppermost N-stage die, which is a grinding process; including a step of grinding the upper surface of the molded die stack wafer obtained up to the grinding process to expose the TSV to obtain a first die stack wafer; a step of obtaining the die stack wafer obtained up to the CoC process, the molded die stack wafer obtained up to the molding process, or the molded die stack wafer obtained up to the grinding process as a second die stack wafer; a step of stacking the second die stack wafer on the first die stack wafer through underfill and molding the whole to obtain a wafer stack; and a step of singulating the wafer stack along the dicing interval to obtain the die stack module.

11. In the step of obtaining the wafer laminate, the upper surface of the second die laminate wafer on the first die laminate wafer is ground to expose the TSV, and the second die laminate wafer is laminated on the second die laminate wafer on the first die laminate wafer via underfill, and the whole is molded to obtain the wafer laminate in which a plurality of the second die laminates are laminated on the first die laminate, the method for manufacturing a die laminate module according to claim 10.

12. A method for manufacturing the die stack module according to claim 3, comprising: forming conductive bumps and attaching a non-conductive film on a die wafer on which a plurality of dies are formed two-dimensionally; singulating the plurality of dies to which the non-conductive film is attached to obtain a plurality of second-stage dies and a plurality of n-stage dies, where the second-stage dies and the n-stage dies have different sizes; using chip-on-wafer technology, arranging the plurality of second-stage dies having the largest size two-dimensionally with a dicing interval on a base wafer as a first-stage die through the non-conductive film, which is a CoW process; using chip-on-chip technology, laminating a plurality of n-stage dies through the non-conductive film on the plurality of second-stage dies in (n - 2) stages in descending order of size to obtain an N-stage die stack wafer, where N is an integer from 3 to 9 and n is an integer from 3 to N, which is a CoC process; a molding process of molding the entire die stack wafer; a grinding process of grinding the upper surface of the molded die stack wafer to expose the back surface of the uppermost N-stage die; a process of grinding the upper surface of the molded die stack wafer obtained up to the grinding process to expose the TSVs to obtain a die stack wafer; a process of attaching a non-conductive film on the die stack wafer obtained up to the CoC process, the molded die stack wafer obtained up to the molding process, or the molded die stack wafer obtained up to the grinding process, and singulating the plurality of die stacks to which the non-conductive film is attached to obtain a plurality of die stacks; a process of using chip-on-wafer technology to laminate the plurality of die stacks two-dimensionally with a dicing interval on the die stack wafer through the non-conductive film, and molding the whole to obtain a wafer stack; and a process of singulating the wafer stack along the dicing interval to obtain the die stack module.

13. In the step of obtaining the wafer laminate, the upper surfaces of the plurality of die laminates on the die laminate wafer are ground to expose the TSVs, and using the chip-on-chip technology, the plurality of die laminates on the die laminate wafer are laminated via the non-conductive film, and the whole is molded to obtain the wafer laminate in which the plurality of the plurality of die laminates are laminated on the die laminate wafer, the method for manufacturing a die laminate module according to claim 12.

14. A method for manufacturing a die laminate module according to claim 6, comprising: a die singulation step of forming conductive bumps and attaching a non-conductive film on a die wafer on which a plurality of dies are two-dimensionally formed, and singulating the plurality of dies to which the non-conductive film is attached to obtain a plurality of second-stage dies and a plurality of n-stage dies, where the second-stage dies and the n-stage dies are of different sizes; a CoW step of two-dimensionally arranging the plurality of second-stage dies having the largest size among them at a dicing interval via the non-conductive film on a base wafer as a first-stage die using the chip-on-wafer technology; a CoC step of laminating the plurality of n-stage dies via the non-conductive film on the plurality of second-stage dies in (n - 2) stages in descending order of size to obtain an N-stage die laminate wafer, where N is an integer of 3 or more and n is an integer of 3 or more and N or less; a molding step of molding the whole of the die laminate wafer; a grinding step of grinding the upper surface of the molded die laminate wafer to expose the back surface of the topmost N-stage die; and a step of singulating the molded die laminate wafer along the dicing interval to obtain the die laminate module.

Images