Memristor, memristor array, and neuromorphic device

Abstract

This memristor includes a first reference layer, a second reference layer, a domain wall movement layer, a first nonmagnetic layer, and a second nonmagnetic layer. The first reference layer and the second reference layer each include a ferromagnetic body in which magnetization is oriented in one direction. The domain wall movement layer has: a first region in which magnetization is oriented in a first magnetization direction; a second region in which magnetization is oriented in a second magnetization direction different from the first magnetization direction; and a third region in which a domain wall can move between the first region and the second region. The first nonmagnetic layer is sandwiched between the domain wall movement layer and the first reference layer. The second nonmagnetic layer is sandwiched between the domain wall movement layer and the second reference layer. The length of the first reference layer in a first direction from the first region toward the second region is longer than that of the third region.

Description

Memristors, memristor arrays and neuromorphic devices

[0001] The present disclosure relates to memristors, memristor arrays, and neuromorphic devices.

[0002] A neuromorphic device is a device that performs neural network calculations and artificially mimics the relationship between neurons and synapses in the human brain.

[0003] Neuromorphic devices have been proposed that integrate memristors such as phase-change memory (PCM), resistive random access memory (ReRAM), and domain wall motion magnetoresistive effect elements (domain wall motion elements). Memristors output a current that is the product of an input voltage and the memristor's own conductance. The memristor functions as a product operation element in the product-sum operation of the neuromorphic device. For example, Patent Document 1 describes a neuromorphic device that uses domain wall motion elements.

[0004] The conductance of a memristor corresponds to the weight used in learning a neuromorphic device. Learning a neuromorphic device requires both positive and negative weights. It is difficult to achieve negative conductance in real devices. Therefore, a method has been proposed in which two devices are treated as a pair, a positive weight and a negative weight are assigned to each device, and the difference between the output currents from the two devices is calculated. For example, Patent Document 2 discloses a method in which element strings are separated into positive and negative values, the absolute value of a weight is assigned to each element string, and the difference is calculated after a product operation.

[0005] Patent No. 6617829 International Publication No. 2018 / 034163

[0006] In order to process a large amount of information in a small area, it is necessary to integrate devices at high density within a limited area. For example, as described in Patent Document 2, if two elements are used to represent positive and negative weights, it is difficult to sufficiently increase the integration density of the device.

[0007] The embodiments of the present disclosure have been made in consideration of the above-mentioned problems, and aim to provide a memristor that can increase integration, a memristor array with high integration, and a neuromorphic device.

[0008] A memristor according to a first aspect includes a first reference layer, a second reference layer, a domain wall displacement layer, a first non-magnetic layer, and a second non-magnetic layer. The first reference layer and the second reference layer each include a ferromagnetic material with magnetization oriented in one direction. The domain wall displacement layer has a first region with magnetization oriented in a first magnetization direction, a second region with magnetization oriented in a second magnetization direction different from the first magnetization direction, and a third region in which a domain wall can move between the first region and the second region. The first non-magnetic layer is sandwiched between the domain wall displacement layer and the first reference layer. The second non-magnetic layer is sandwiched between the domain wall displacement layer and the second reference layer. The length of the first reference layer in a first direction from the first region toward the second region is longer than that of the third region.

[0009] 1 is a block diagram of a memristor device according to the first embodiment. FIG. 2 is a circuit diagram of a memristor array according to the first embodiment. FIG. 3 is a cross-sectional view of a memristor array according to the first embodiment. FIG. 4 is a cross-sectional view of a memristor according to the first embodiment. FIG. 5 is a plan view of a memristor according to the first embodiment. FIG. 6 is a diagram for explaining a manufacturing method of a memristor according to the first embodiment. FIG. 7 is a diagram for explaining a manufacturing method of a memristor according to the first embodiment. FIG. 8 is a diagram for explaining a manufacturing method of a memristor according to the first embodiment. FIG. 9 is a diagram for explaining a manufacturing method of a memristor according to the first embodiment. FIG. 10 is a diagram for explaining a manufacturing method of a memristor according to the first embodiment. FIG. 11 is a diagram for explaining a write operation to a memristor according to the first embodiment. FIG. 12 is a diagram for explaining a first example of a read operation from a memristor according to the first embodiment. FIG. 13 is a diagram for explaining a second example of a read operation from a memristor according to the first embodiment. FIG. 14 is a diagram for explaining a conductance change of a memristor according to the first embodiment. FIG. 15 is a conceptual diagram of a neural network. FIG. 16 is a block diagram of a system including a neuromorphic device according to the first embodiment. FIG. 17 is a cross-sectional view of a memristor according to the second embodiment. FIG. 18 is a plan view of a memristor according to the third embodiment. FIG. 19 is a plan view of a memristor according to the fourth embodiment. FIG. 20 is a plan view of a memristor according to the fifth embodiment. FIG. 21 is a cross-sectional view of a memristor according to the sixth embodiment. FIG. 22 is a cross-sectional view of a memristor according to the seventh embodiment. FIG. 23 Fig. 16 is a cross-sectional view of a memristor according to a ninth embodiment; Fig. 17 is a cross-sectional view of a memristor according to a tenth embodiment; Fig. 18 is a cross-sectional view of a memristor according to an eleventh embodiment; Fig. 19 is a perspective view of a memristor according to a twelfth embodiment;

[0010] The present embodiment will be described in detail below with reference to the accompanying drawings. The drawings used in the following description may show characteristic portions enlarged for the sake of clarity, and the dimensional ratios of the components may differ from the actual values. The materials, dimensions, and the like exemplified in the following description are merely examples, and the present embodiment is not limited thereto. Appropriate modifications can be made within the scope of the effects of the present embodiment.

[0011] First, the directions will be defined. The x direction and y direction are directions approximately parallel to one surface of the substrate Sub (see FIG. 3 ), which will be described later. The x direction is the longitudinal direction of the domain wall displacement layer 30, which will be described later, and is the direction from the first region A1 to the second region A2. The x direction is sometimes referred to as the first direction. The y direction is a direction perpendicular to the x direction. The y direction is sometimes referred to as the second direction. The z direction is the direction from the substrate Sub, which will be described later, to the memristor 100. The z direction is sometimes referred to as the stacking direction. In this specification, the +z direction may be expressed as "up" and the -z direction as "down", but these expressions are used for convenience and do not define the direction of gravity.

[0012] 1 is a block diagram of a memristor device 1 according to a first embodiment. The memristor device 1 includes a memristor array 2 and a control device 3.

[0013] The memristor array 2 has multiple memristors 100 (see FIG. 2 ). The control device 3 controls the operation of each of the memristors 100 in the memristor array 2. The control device 3 may be located, for example, on the periphery of the memristor array 2 as shown in FIG. 1 . The control device 3 may also be located at a position overlapping the memristor array 2 in the z direction.

[0014] The control device 3 includes, for example, a signal input unit 4 , a calculation unit 5 , and an output unit 6 .

[0015] The signal input unit 4 has a control unit 7 and a power supply 8. The control unit 7 has, for example, a processor and a memory. The processor is, for example, a CPU (Central Processing Unit). The processor controls, for example, the address of the element to which a pulse is applied, the potential of the element to which the pulse is applied, the magnitude of the pulse (voltage, pulse length) to be applied to the element, etc. The memory stores the address of the element, a program to operate the processor, etc.

[0016] The calculation unit 5 performs calculations based on the conductance of each element in the memristor array 2 or the output current from each element. The calculation unit 5 includes, for example, a processor. The calculation unit 5, for example, adds up the output currents from multiple elements in the memristor array 2. The calculation unit 5 may, for example, perform processing to determine the difference between a first read current and a second read current output from each memristor. When the memristor device 1 is applied to a neural network, the calculation unit 5 may add up the output currents from multiple elements and assign the result to an activation function.

[0017] The output unit 6 is connected to the calculation unit 5. The output unit 6 outputs the calculation result of the calculation unit 5 to the outside. The output unit 6 includes, for example, an output capacitor, an amplifier, a converter, etc. The output unit 6 may also feed back the calculation result to the signal input unit 4. The calculation result is stored in, for example, a memory of the signal input unit 4.

[0018] 2 is a circuit diagram of a memristor array 2 according to the first embodiment. The memristor array 2 includes multiple memristors 100, multiple first interconnects L1, multiple second interconnects L2, multiple third interconnects L3, and multiple fourth interconnects L4. Each memristor 100 is connected to switch elements SW1, SW2, SW3, and SW4 that control the operation of the memristor 100. Any of the switch elements SW1, SW2, SW3, and SW4 may be shared by multiple memristors 100. For example, the switch element SW1 may be connected to one end of the first interconnect L1. Similarly, the other switch elements SW2, SW3, and SW4 may be connected to one end of interconnects connecting multiple memristors 100.

[0019] Each of the first wirings L1 is a common wiring that can be used both when writing and reading a signal. Each of the first wirings L1 is connected to, for example, the signal input unit 4 or the calculation unit 5. Each of the second wirings L2 is a write wiring. Each of the second wirings L2 is connected to the signal input unit 4. Each of the third wirings L3 and the fourth wirings L4 is a read wiring. Each of the third wirings L3 and the fourth wirings L4 is connected to the signal input unit 4 or the calculation unit 5.

[0020] Each of the switch elements SW1, SW2, SW3, and SW4 is an element that controls the flow of current. For example, each of the switch elements SW1, SW2, SW3, and SW4 is an element that uses a phase change of a crystal layer such as a transistor or an Ovonic Threshold Switch (OTS), an element that uses a change in band structure such as a metal-insulator transition (MIT) switch, an element that uses a breakdown voltage such as a Zener diode or an avalanche diode, or an element whose conductivity changes with a change in atomic position.

[0021] The switch element SW1 is, for example, located between the first wiring L1 and the memristor 100. The switch element SW2 is, for example, located between the second wiring L2 and the memristor 100. The switch element SW3 is, for example, located between the third wiring L3 and the memristor 100. The switch element SW4 is, for example, located between the fourth wiring L4 and the memristor 100. The arrangement of the switch elements SW1, SW2, SW3, and SW4 is not important as long as they can control the write current or read current to the memristor 100. In order to increase the integration density within the memristor array 2, it is preferable to reduce the number of switch elements arranged within the memristor array 2.

[0022] The switch elements SW1 and SW2 are responsible for controlling the write current to the memristor 100. The switch elements SW3 and SW4 are responsible for controlling the read current to the memristor 100. The write current used to write data to the memristor 100 is larger than the read current used to read data from the memristor 100. Therefore, the element sizes of the switch elements SW3 and SW4 may be smaller than the element sizes of the switch elements SW1 and SW2. The element size is, for example, the area occupied by the switch on the surface of the substrate Sub. By designing the element sizes of the switch elements SW1, SW2, SW3, and SW4 according to the maximum rated current, the overall size of the memristor array 2 can be reduced.

[0023] 3 is a cross-sectional view of the memristor array 2 according to the first embodiment. The memristor array 2 includes, for example, a substrate Sub, a plurality of transistors Tr formed on the substrate Sub, a plurality of memristors 100, a plurality of wirings C1 and C2, and an insulating layer 90.

[0024] The substrate Sub is, for example, a semiconductor substrate. Details of the memristor 100 will be described later.

[0025] The transistor Tr is an example of the above-mentioned switch elements SW3 and SW4. The switch elements SW1 and SW2 are located at different positions in the y direction from the plane shown in FIG. 3. The transistor Tr includes a gate electrode G, an insulating film GI, an active region AA1, and an active region AA2. The active region AA1 and the active region AA2 are formed in the substrate Sub, and serve as a source or a drain depending on the direction of current flow.

[0026] The transistor Tr and the memristor 100 are connected via at least one of wiring C1 and wiring C2. Wiring C1 extends in the z direction. Wiring C2 extends in any direction within the xy plane. Wiring C1 and wiring C2 are conductors. Wirings C1 and C2 shown in FIG. 3 electrically connect the third wiring L3 or the fourth wiring L4 to the transistor Tr, and electrically connect the transistor Tr to the memristor 100.

[0027] The insulating layer 90 provides insulation between the transistor Tr and the memristor 100. The insulating layer 90 is an insulating layer that provides insulation between the wirings of the multilayer wiring and between the elements. The memristor 100 and the transistor Tr are electrically isolated by the insulating layer 90 except for the wirings C1 and C2. The insulating layer 90 is made of, for example, silicon oxide (SiO ｘ ), silicon nitride (SiN ｘ ), silicon carbide (SiC), chromium nitride (CrN), silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al ２ O ３ ), zirconium oxide (ZrO ｘ ), magnesium oxide (MgO), etc.

[0028] Fig. 4 is a cross-sectional view of the memristor 100. Fig. 4 is a diagram of the memristor 100 cut at the center in the y direction of the domain wall displacement layer 30. Fig. 5 is a plan view of one surface of the domain wall displacement layer 30 of the memristor 100 as viewed from the z direction.

[0029] Memristor 100 includes, for example, first reference layer 10, second reference layer 20, domain wall displacement layer 30, first non-magnetic layer 40, second non-magnetic layer 50, first electrode E1, second electrode E2, third electrode E3, and fourth electrode E4. The periphery of memristor 100 is covered with insulating layer 90, except for wiring C1.

[0030] The memristor 100 includes a first magnetoresistive effect unit MTJ1 and a second magnetoresistive effect unit MTJ2. The first magnetoresistive effect unit MTJ1 is composed of a first reference layer 10, a first non-magnetic layer 40, and a domain wall displacement layer 30. The second magnetoresistive effect unit MTJ2 is composed of a second reference layer 20, a second non-magnetic layer 50, and the domain wall displacement layer 30.

[0031] The magnetoresistive effect is a phenomenon in which the resistance value in the z direction changes depending on the relative angle between the magnetizations of two ferromagnetic layers sandwiching a nonmagnetic layer. The resistance value in the z direction of the first magnetoresistive effect unit MTJ1 changes when the relative angle between the magnetization of the first reference layer 10 and the magnetization of the domain wall displacement layer 30 changes. The resistance value in the z direction of the second magnetoresistive effect unit MTJ2 changes when the relative angle between the magnetization of the second reference layer 20 and the magnetization of a portion of the domain wall displacement layer 30 that faces the second reference layer 20 changes. Because conductance is expressed as the reciprocal of the resistance value, the conductance of each of the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2 changes depending on the position of the domain wall DW in the domain wall displacement layer 30.

[0032] The conductance of the first magnetoresistive unit MTJ1 changes when the domain wall DW moves in the region where the first reference layer 10 and the third region A3 overlap as viewed from the z direction. The conductance of the second magnetoresistive unit MTJ2 changes when the domain wall DW moves in the region where the second reference layer 20 and the third region A3 overlap as viewed from the z direction. The first overlapping area where the second reference layer 20 and the third region A3 overlap is, for example, smaller than the second overlapping area where the first reference layer 10 and the third region A3 overlap.

[0033] The first reference layer 10 includes a ferromagnetic material. The first reference layer 10 is a ferromagnetic layer whose length in the x direction is longer than its width in the y direction. The magnetization M of the first reference layer 10 １０ is oriented in one direction and fixed in the normal environment in which the memristor 100 is used. Here, "the magnetization is fixed" means that the magnetization direction does not reverse during normal operation of the memristor 100 (when no external force exceeding the expected value is applied).

[0034] The first reference layer 10 includes, for example, a material that easily provides a coherent tunneling effect between the first reference layer 10 and the domain wall displacement layer 30. The first reference layer 10 includes, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, or an alloy containing these metals and at least one or more of B, C, and N. The first reference layer 10 is, for example, Co—Fe, Co—Fe—B, or Ni—Fe.

[0035] The first reference layer 10 may be, for example, a Heusler alloy. Heusler alloys are half-metallic and have high spin polarization. Heusler alloys are either XYZ or X ２ It is an intermetallic compound having a chemical composition of YZ, where X is a transition metal element or a noble metal element of the Co, Fe, Ni, or Cu group on the periodic table, Y is a transition metal element or an element species of X of the Mn, V, Cr, or Ti group, and Z is a typical element of groups III to V. ２ FeSi, Co ２ FeGe, Co ２ FeGa, Co ２ MnSi, Co ２ Mn １－ａ Fe ａ Al ｂ Si １－ｂ , Co ２ FeGe １－ｃ Ga ｃ etc.

[0036] The first reference layer 10 may have a synthetic antiferromagnetic structure (SAF structure). The synthetic antiferromagnetic structure is composed of two magnetic layers sandwiching a nonmagnetic layer. For example, the first reference layer 10 may be a stack of a ferromagnetic layer, a spacer layer, and another ferromagnetic layer. The antiferromagnetic coupling between the two ferromagnetic layers constituting the SAF structure increases the coercive force of the first reference layer 10 compared to a non-SAF structure. The magnetic layer constituting the SAF structure includes, for example, a ferromagnetic material and may also include an antiferromagnetic material such as IrMn or PtMn. The spacer layer includes, for example, at least one selected from the group consisting of Ru, Ir, and Rh.

[0037] The length of the first reference layer 10 in the x direction is, for example, longer than the length of a third region A3 of the domain wall displacement layer 30 (described later). By having the first reference layer 10 face the entire surface of the third region A3, which is the range in which the domain wall DW can move, it is possible to eliminate a dead region in the conductance of the first magnetoresistive effect unit MTJ1. The dead region refers to a region in which the conductance of the magnetoresistive effect unit does not change even when the position of the domain wall DW changes. Furthermore, the length of the first reference layer 10 in the x direction is, for example, longer than the length of the domain wall displacement layer 30 in the x direction. If the area of ​​the first reference layer 10 is larger than the area of ​​the domain wall displacement layer 30, the heat capacity of the first reference layer 10 increases, improving the efficiency of heat removal from the domain wall displacement layer 30. Furthermore, if the area of ​​the first reference layer 10 is larger than the area of ​​the domain wall displacement layer 30, the flatness of the domain wall displacement layer 30 improves, allowing the domain wall DW to move more smoothly.

[0038] The second reference layer 20 includes a ferromagnetic material. The second reference layer 20 is a ferromagnetic layer whose length in the x direction is longer than its length in the y direction. The second reference layer 20 is located, for example, farther from the substrate Sub than the first reference layer 10.

[0039] The magnetization M of the second reference layer 20 ２０ are oriented in one direction and fixed in a normal environment in which memristor 100 is used. Second reference layer 20 includes, for example, a material that easily achieves a coherent tunneling effect between second reference layer 20 and domain wall displacement layer 30. For second reference layer 20, for example, the same material as first reference layer 10 can be used.

[0040] The length in the x direction of the second reference layer 20 is, for example, shorter than the length in the x direction of the domain wall displacement layer 30, which will be described later. The length in the x direction of the second reference layer 20 may be shorter than the length in the x direction of a third region A3 of the domain wall displacement layer 30, which will be described later. If there is a region where the second reference layer 20 and the domain wall displacement layer 30 do not overlap when viewed from the z direction, it becomes easier to fabricate the first electrode E1 and the second electrode E2.

[0041] 5 , the width W20 of the second reference layer 20 in the y direction is narrower than the width W10 of the first reference layer 10. The width W20 of the second reference layer 20 in the y direction is also narrower than the width W3 of the third region A3 of the domain wall displacement layer 30. By making the width W20 of the second reference layer 20 narrower than the width W10 of the first reference layer 10, it is possible to prevent a short circuit from occurring between the domain wall displacement layer 30 and the second reference layer 20.

[0042] The first non-magnetic layer 40 is sandwiched between the first reference layer 10 and the domain wall displacement layer 30. The first non-magnetic layer 40 is, for example, on the first reference layer 10. The first non-magnetic layer 40 is a non-magnetic layer whose length in the x direction is longer than its length in the y direction.

[0043] The first nonmagnetic layer 40 is made of, for example, a nonmagnetic insulator, a semiconductor, or a metal. ２ O ３ , SiO ２ , MgO, MgAl ２ O ４ , and materials in which a portion of these Al, Si, and Mg is replaced with Zn, Be, or the like. These materials have a large band gap and excellent insulating properties. When the first nonmagnetic layer 40 is made of a nonmagnetic insulator, the first nonmagnetic layer 40 is a tunnel barrier layer. Examples of nonmagnetic metals include Cu, Au, and Ag. Examples of nonmagnetic semiconductors include Si, Ge, and CuInSe. ２ , CuGaSe ２ , Cu(In,Ga)Se ２ etc.

[0044] The thickness of the first non-magnetic layer 40 is, for example, 20 Å or more, and may be 25 Å or more. The area resistance (RA) of the first magnetoresistive effect unit MTJ1 can be changed by changing the thickness and material of the first non-magnetic layer 40. The area resistance (RA) is expressed as the product of the element resistance and the element cross-sectional area. The element cross section of the first magnetoresistive effect unit MTJ1 is a cross section of the first magnetoresistive effect unit MTJ1 cut along the xy plane.

[0045] The second non-magnetic layer 50 is sandwiched between the second reference layer 20 and the domain wall displacement layer 30. The second non-magnetic layer 50 is, for example, on the domain wall displacement layer 30. The second non-magnetic layer 50 is, for example, located farther from the substrate Sub than the first non-magnetic layer 40. The second non-magnetic layer 50 is a non-magnetic layer whose length in the x direction is longer than its length in the y direction.

[0046] The second nonmagnetic layer 50 is made of, for example, a nonmagnetic insulator, semiconductor, or metal. The second nonmagnetic layer 50 can be made of the same material as the first nonmagnetic layer 40.

[0047] The thickness of each second nonmagnetic layer 50 is, for example, 20 Å or more, and may be 25 Å or more. The area resistance (RA) of the second magnetoresistive unit MTJ2 can be changed by changing the thickness of the second nonmagnetic layer 50. For example, the area resistance (RA) of the second magnetoresistive unit MTJ2 may be smaller than the area resistance of the first magnetoresistive unit MTJ1.

[0048] The domain wall displacement layer 30 is sandwiched between, for example, a first non-magnetic layer 40 and a second non-magnetic layer 50. The domain wall displacement layer 30 is, for example, a ferromagnetic layer whose length in the x direction is longer than its width in the y direction. The domain wall displacement layer 30 has a domain wall DW therein. The domain wall DW is the boundary between different magnetic domains. The domain wall DW moves in the x direction inside the domain wall displacement layer 30. The domain wall displacement layer 30 is also called an analog layer or a magnetic recording layer.

[0049] The domain wall displacement layer 30 has a first region A1, a second region A2, and a third region A3. The first region A1 is a region that overlaps with the first electrode E1 when viewed from the z direction. The second region A2 is a region that at least partially overlaps with the second electrode E2 when viewed from the z direction. The third region A3 is a region other than the first region A1 and the second region A2 of the domain wall displacement layer 30. The third region A3 is sandwiched between the first region A1 and the second region A2 in the x direction, for example.

[0050] In the first region A1, the magnetization M Ａ１ is oriented in the first magnetization direction (for example, the +z direction). Ａ２ is oriented in the second magnetization direction (for example, the −z direction). Ａ１ and the magnetization M of the second region A2 Ａ２ The magnetization M of the first region A1 is oriented in the opposite direction. Ａ１ and the magnetization M of the second region A2 Ａ２ Since the magnetic domain wall DW is fixed, the magnetic domain wall DW does not invade the first region A1 and the second region A2. The first magnetization direction and the second magnetization direction are not limited to the z direction, but may be any direction within the xy plane.

[0051] The third region A3 is a region where the magnetization direction changes and the domain wall DW can move. The third region A3 is called a domain wall movable region. The third region A3 has a first magnetic domain A31 and a second magnetic domain A32. The first magnetic domain A31 and the second magnetic domain A32 have magnetization orientation directions opposite to each other. The boundary between the first magnetic domain A31 and the second magnetic domain A32 is the domain wall DW. The magnetization M of the first magnetic domain A31 Ａ３１ is, for example, the magnetization M of the first region A1 Ａ１ The magnetization M of the second magnetic domain A32 is oriented in the same direction as Ａ３２ is, for example, the magnetization M of the second region A2 Ａ２ In principle, the domain wall DW moves within the third region A3.

[0052] When the volume ratio between the first magnetic domain A31 and the second magnetic domain A32 changes, the domain wall DW moves. The domain wall DW moves, for example, by applying a write current (e.g., a current pulse) in the x direction of the domain wall displacement layer 30 or by applying an external magnetic field to the domain wall displacement layer 30. For example, when a write current is applied between the first electrode E1 and the second electrode E2, the domain wall DW moves.

[0053] 5, when viewed in the z direction, the width W1 of the first region A1 may be wider than the width W3 of the third region A3, and the width W2 of the second region A2 may be wider than the width W3 of the third region A3. In this case, the current density of the current flowing through the domain wall displacement layer 30 drops sharply at the position from the third region A3 to the first region A1 or the second region A2. When the current density of the current flowing through the domain wall displacement layer 30 drops sharply, the force moving the domain wall DW weakens, and it is possible to prevent the domain wall DW from entering the first region A1 and the second region A2.

[0054] The area of ​​the second region A2 may be larger than the area of ​​the first region A1. The width W2 of the second region A2 may be larger than the width W1 of the first region A1. If the area of ​​the second region A2 is larger than the first region A1, the domain wall DW is less likely to invade the second region A2 even if the second electrode E2 is not made of a ferromagnetic material.

[0055] The thickness of the domain wall displacement layer 30 is, for example, 5 nm or more. The spin diffusion length in a ferromagnetic layer is at most about 4 nm. Therefore, if the thickness of the domain wall displacement layer 30 is 5 nm or more, even when a read current flows in the z direction, the influence of spin transfer torque due to spins injected from an adjacent ferromagnetic layer can be suppressed, and unexpected magnetization reversal can be suppressed.

[0056] The domain wall displacement layer 30 includes a magnetic material. For example, the same material as that of the first reference layer 10 can be used for the domain wall displacement layer 30. The domain wall displacement layer 30 may be a ferromagnetic material, a ferrimagnetic material, or a combination of these with an antiferromagnetic material whose magnetic state can be changed by a current. Each domain wall displacement layer 30 preferably contains at least one element selected from the group consisting of Co, Ni, Fe, Pt, Pd, Gd, Tb, Mn, Ge, and Ga.

[0057] The domain wall displacement layer 30 may be, for example, a laminated film of Co and Ni, a laminated film of Co and Pt, a laminated film of Co and Pd, an MnGa-based material, a GdCo-based material, a TbCo-based material, or the like. Ferrimagnetic materials such as MnGa-based materials, GdCo-based materials, and TbCo-based materials have small saturation magnetization, and the threshold current required to move the domain wall DW is small. Furthermore, a laminated film of Co and Ni, a laminated film of Co and Pt, and a laminated film of Co and Pd have large coercive force, and the displacement speed of the domain wall DW is slow. The antiferromagnetic material may be, for example, Mn ３ X (X is Sn, Ge, Ga, Pt, Ir, etc.), CuMnAs, Mn ２ Au et al.

[0058] The first electrode E1 is in contact with the first region A1 of the domain wall displacement layer 30. The first electrode E1 is electrically connected to, for example, the switch element SW1. The first electrode E1 may include an intermediate layer at the interface with the domain wall displacement layer 30. When viewed from the z direction, the area of ​​the first electrode E1 may be larger than the area of ​​the first region A1. When viewed from the z direction, the first region A1 may be included within the first electrode E1.

[0059] The first electrode E1 is a conductor. The first electrode E1 may be, for example, a ferromagnetic material. For example, the same material as that of the first reference layer 10 may be used for the first electrode E1. The first electrode E1 may have an SAF structure. The magnetization M of the first electrode E1 Ｅ１ is oriented in the first magnetization direction. Ｅ１ is, for example, the magnetization M of the first region A1 Ａ１ The orientation of the magnetization M Ｅ１ and magnetization M Ａ１ and are oriented in the same direction.

[0060] The first interface S1 between the first electrode E1 and the domain wall displacement layer 30 may be closer to the first non-magnetic layer 40 than the second interface S2 between the second non-magnetic layer 50 and the domain wall displacement layer 30. The distance in the z direction between the first interface S1 and the first non-magnetic layer 40 is shorter than the distance in the z direction between the second interface S2 and the first non-magnetic layer 40. When a part of the first electrode E1 is embedded in the domain wall displacement layer 30, the magnetization M of the first region A1 Ａ１Furthermore, if the first reference layer 10, the first non-magnetic layer 40, the domain wall displacement layer 30, the second non-magnetic layer 50, and the second reference layer 20 are stacked in this order, and then portions of the second non-magnetic layer 50 and the second reference layer 20 are removed before the first electrode E1 is formed, the first interface S1 may be closer to the first non-magnetic layer 40 than the second interface S2. By successively depositing the first reference layer 10, the first non-magnetic layer 40, the domain wall displacement layer 30, the second non-magnetic layer 50, and the second reference layer 20, the flatness of the interfaces of the layers of the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2 is improved, and the magnetic properties of the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2 are improved.

[0061] The second electrode E2 is in contact with the second region A2 of the domain wall displacement layer 30. The second electrode E2 is electrically connected to, for example, the switch element SW2. The second electrode E2 may include an intermediate layer at the interface with the domain wall displacement layer 30. When viewed from the z direction, the area of ​​the second electrode E2 may be larger than the area of ​​the second region A2. When viewed from the z direction, the second region A2 may be included in the second electrode E2. When viewed from the z direction, the second electrode E2 may overlap with the entire second region A2 or only a portion of the second region A2.

[0062] The second electrode E2 is a conductor and may be made of the same material as the first electrode E1 or any other conductor.

[0063] The second electrode E2 may be made of, for example, a ferromagnetic material. When the second electrode E2 is made of a ferromagnetic material, the film thickness of the second electrode E2 may be different from the film thickness of the first electrode E1. When the film thickness of the second electrode E2 is different from the film thickness of the first electrode E1, a difference occurs between the coercive force of the second electrode E2 and the coercive force of the first electrode E1, making it easier to fix the orientation direction of the magnetization in the opposite direction.

[0064] From the viewpoint of ease of manufacture, the second electrode E2 is preferably made of a non-magnetic material. Even when the second electrode E2 is made of a non-magnetic material, the current density of the current flowing through the domain wall displacement layer 30 drops sharply when it moves from the third region A3 to the second region A2, thereby limiting the range of movement of the domain wall DW.

[0065] The interface between the second electrode E2 and the domain wall displacement layer 30 may be closer to the first non-magnetic layer 40 than the second interface S2 between the second non-magnetic layer 50 and the domain wall displacement layer 30 .

[0066] The third electrode E3 is connected to the second reference layer 20. The third electrode E3 is a conductor. The third electrode E3 is electrically connected to the switch element SW3.

[0067] The fourth electrode E4 is connected to the first reference layer 10. The fourth electrode E4 is a conductor. The fourth electrode E4 is electrically connected to the switch element SW4.

[0068] The magnetization direction of each layer of the memristor 100 can be confirmed, for example, by measuring a magnetization curve. The magnetization curve can be measured, for example, using MOKE (Magneto-Optical Kerr Effect). MOKE measurement is a measurement method that uses the magneto-optical effect (magnetic Kerr effect) in which linearly polarized light is incident on a measurement object and the polarization direction rotates.

[0069] The memristor 100 can be fabricated by a known method. The switch elements SW1, SW2, SW3, and SW4 can be fabricated using, for example, photolithography. A commercially available semiconductor substrate on which multiple transistors are formed may also be used.

[0070] The memristor 100 is formed by a process of stacking each layer and a process of processing a part of each layer into a predetermined shape.

[0071] 6 to 10 are diagrams for explaining a method for manufacturing the memristor 100 according to the first embodiment.

[0072] 6, an electrode layer 91, a ferromagnetic layer 92, a non-magnetic layer 93, a ferromagnetic layer 94, a non-magnetic layer 95, and a ferromagnetic layer 96 are sequentially stacked on an insulating layer 90 on which a wiring C1 has been formed. The layers can be stacked by sputtering, chemical vapor deposition (CVD), electron beam evaporation (EB evaporation), atomic laser deposition, or the like.

[0073] 7, the stacked laminate is processed into a predetermined shape. Each layer can be processed using photolithography, etching (e.g., Ar etching, ion beam etching (IBE)), or the like. Through this processing, the electrode layer 91 becomes the fourth electrode E4, the ferromagnetic layer 92 becomes the first reference layer 10, the nonmagnetic layer 93 becomes the first nonmagnetic layer 40, and the ferromagnetic layer 94 becomes the domain wall displacement layer 30.

[0074] Next, as shown in FIG. 8 , the nonmagnetic layer 95 and the ferromagnetic layer 96 are further processed. Through this processing, the nonmagnetic layer 95 becomes the second nonmagnetic layer 50, and the ferromagnetic layer 96 becomes the second reference layer 20. During the first processing, a portion of the sample etched by the ion beam may re-adhere to the side surface of the nonmagnetic layer 95. By removing this re-adhesion in the second processing, it is possible to prevent a short circuit between the domain wall displacement layer 30 and the second reference layer 20. Next, the peripheries of the second nonmagnetic layer 50 and the second reference layer 20 are covered with an insulator.

[0075] Next, as shown in FIG. 9, openings H1 and H2 are formed at positions that overlap with parts of the domain wall displacement layer 30 when viewed from the z direction.

[0076] 10 , the openings H1 and H2 are filled with a conductor to form the first electrode E1 and the second electrode E2. Next, a third electrode E3 is formed at a position overlapping the second reference layer 20, and the first electrode E1, the second electrode E2, and the third electrode E3 are covered with an insulator. Openings H3, H4, and H5 are formed in the insulating layer and filled with a conductor to fabricate the memristor 100.

[0077] Next, the operation of the memristor 100 according to the first embodiment will be described. The operation of the memristor 100 includes a write operation and a read operation. In a write operation, the position of the domain wall DW of the domain wall displacement layer 30 is changed. In a read operation, the conductance of the memristor 100 or the output current from the memristor 100 is detected.

[0078] 11 is a diagram for explaining the write operation of the memristor 100. When writing a signal to a memristor 100, first, a selection is made to which memristor 100 in the memristor array 2 the signal is to be written. This selection is made, for example, by the control unit 7. Next, the switch elements SW1 and SW2 connected to the memristor 100 to be written are turned ON, and the switch elements SW3 and SW4 are turned OFF (see FIG. 2). By turning ON the switch elements SW1 and SW2, a write current I flows along the domain wall displacement layer 30. Ｗ (write pulse) is applied.

[0079] A write current I Ｗ When this voltage is applied, the position of the domain wall DW changes in the domain wall displacement layer 30. The position and direction of the domain wall DW in the domain wall displacement layer 30 can be controlled by controlling the potential difference between the first electrode E1 and the second electrode E2.

[0080] Write current I Ｗ The magnitude of the write pulse may be constant or may vary depending on the position of the domain wall DW. For example, the magnitude of the first write pulse may be smaller than the magnitude of the second write pulse. These write pulses are controlled by the control unit 7. The first write pulse is a write pulse applied to the domain wall displacement layer 30 when the domain wall DW is located in a region where the second reference layer 20 and the domain wall displacement layer 30 overlap as viewed from the z direction. The second write pulse is a write pulse applied to the domain wall displacement layer 30 when the domain wall DW is located in a region where the second reference layer 20 and the domain wall displacement layer 30 do not overlap as viewed from the z direction. When the domain wall DW is located in a region where the second reference layer 20 and the domain wall displacement layer 30 do not overlap as viewed from the z direction, the conductance of the second magnetoresistive part MTJ2 does not change. By increasing the magnitude of the write pulse in a region where the conductance change is small, the linearity of the conductance change per pulse can be improved.

[0081] The magnitude of the write pulse can be adjusted by the pulse amplitude, pulse length, etc. The smaller the pulse amplitude and the shorter the pulse length, the smaller the write pulse magnitude.

[0082] When the position of the domain wall DW in the domain wall displacement layer 30 changes, the resistance values ​​in the z direction of the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2 in the memristor 100 change. Conductance is the reciprocal of the resistance value, and the conductance in the z direction of the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2 also changes. Here, the conductance in the z direction of the first magnetoresistive effect unit MTJ1 is the conductance between the first electrode E1 and the fourth electrode E4, and the conductance in the z direction of the second magnetoresistive effect unit MTJ2 is the conductance between the first electrode E1 and the third electrode E3. These conductances correspond to the written signals.

[0083] FIG. 12 is a diagram for explaining a first example of a read operation of the memristor 100. In FIG.

[0084] When reading a signal from a memristor 100, first, a selection is made from which memristor 100 in the memristor array 2 the signal is to be read from. This selection is made, for example, by the control unit 7. Next, the switch elements SW1, SW3, and SW4 connected to the memristor 100 to be read are turned ON, and the switch element SW2 is turned OFF. When a read voltage is applied to the memristor 100 to be read, a read current flows through the memristor 100 to be read. Here, a case where a read current flows through the first electrode E1 is described; however, it is also possible to pass a read current through the second electrode E2 by turning ON the switch elements SW2, SW3, and SW4 connected to the memristor 100 to be read, and turning OFF the switch element SW1.

[0085] 12 , the potential of the first reference layer 10 is set to be higher than the potential of the domain wall displacement layer 30, and the potential of the second reference layer 20 is set to be lower than the potential of the domain wall displacement layer 30. These potentials are controlled by the control unit 7. In the example shown in FIG. 12 , a positive potential is applied to the first reference layer 10 and a negative potential is applied to the second reference layer 20, with the potential of the domain wall displacement layer 30 as the reference. Therefore, during reading, the first read voltage applied to the first reference layer 10 and the second read voltage applied to the second reference layer have opposite polarities with the potential of the domain wall displacement layer 30 as the reference. The example shown in FIG. 12 is just one example, and a negative potential may be applied to the first reference layer 10 and a positive potential may be applied to the second reference layer 20, with the potential of the domain wall displacement layer 30 as the reference.

[0086] The absolute values ​​of the first read voltage and the second read voltage may be the same or different. The first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2 have different element areas, and therefore different possible conductance values. By changing the absolute values ​​of the first read voltage and the second read voltage, the first read current I Ｒ１ and the second read current I Ｒ２ The size of these differences (I Ｒ１ -I Ｒ２ ) can be designed within an appropriate range.

[0087] First read current I Ｒ１ flows between the fourth electrode E4 and the first electrode E1. In the example shown in FIG. 12, the first read current I Ｒ１ flows from the fourth electrode E4 to the first electrode E1. Ｒ１ flows in the z-direction inside the first magnetoresistive unit MTJ1, so that the conductance G1 of the first magnetoresistive unit MTJ1 is obtained. The conductance G1 of the first magnetoresistive unit MTJ1 changes depending on the position of the domain wall DW in the x-direction.

[0088] Second read current I Ｒ２ flows between the third electrode E3 and the first electrode E1. In the example shown in FIG. 12, the second read current I Ｒ２ flows from the first electrode E1 to the third electrode E3. Ｒ２flows in the z-direction inside the second magnetoresistive unit MTJ2, so that the conductance G2 of the second magnetoresistive unit MTJ2 is obtained. The conductance G2 of the second magnetoresistive unit MTJ2 changes depending on the position of the domain wall DW in the x-direction.

[0089] The current flowing between the first electrode E1 and the switch element SW1 is a first read current I Ｒ１ and the second read current I Ｒ２ The difference between (I Ｒ１ -I Ｒ２ ) This difference (I Ｒ１ -I Ｒ２ ), it is possible to detect the difference (G1-G2) between the conductance G1 of the first magnetoresistive unit MTJ1 and the conductance G2 of the second magnetoresistive unit MTJ2. Ｒ１ and the second read current I Ｒ２ and are read out separately, and the difference (I Ｒ１ -I Ｒ２ ), and the difference (G1-G2) between the conductances of the first magnetoresistive unit MTJ1 and the second magnetoresistive unit MTJ2 may be calculated.

[0090] 13 is a diagram for explaining a second example of a read operation of memristor 100. The second example of the read operation is similar to the first example of the read operation except that the values ​​of the read voltages applied to first reference layer 10 and second reference layer 20 are different.

[0091] 13 , the potential of the first reference layer 10 is set to be higher than the potential of the domain wall displacement layer 30, and the potential of the second reference layer 20 is set to be higher than the potential of the domain wall displacement layer 30. These potentials are also controlled by the control unit 7. In the example shown in FIG. 13 , a positive potential is applied to the first reference layer 10 and the second reference layer 20 with the potential of the domain wall displacement layer 30 as the reference. Therefore, during reading, the first read voltage applied to the first reference layer 10 and the second read voltage applied to the second reference layer 20 have the same polarity with the potential of the domain wall displacement layer 30 as the reference.

[0092] The behavior of the magnetoresistance change of the magnetoresistive element may differ depending on whether a positive voltage or a negative voltage is applied to the magnetoresistive element. That is, the behavior of the magnetoresistance change when a positive voltage is applied to the magnetoresistive element may be asymmetric with the behavior of the magnetoresistance change when a negative voltage is applied to the magnetoresistive element. When potentials of the same polarity are applied to the first reference layer 10 and the second reference layer 20 with respect to the potential of the domain wall displacement layer 30, this asymmetry in the behavior of the magnetoresistance change does not need to be taken into consideration. The example shown in FIG. 13 is just one example, and a negative potential may be applied to the first reference layer 10 and the second reference layer 20 with respect to the potential of the domain wall displacement layer 30.

[0093] First read current I Ｒ１ In the example shown in FIG. 13, the first read current I′ flows between the fourth electrode E4 and the first electrode E1. Ｒ１ The first read current I′ flows from the fourth electrode E4 to the first electrode E1. Ｒ１ ' flows in the z direction inside the first magnetoresistive unit MTJ1, and thus the conductance G1 of the first magnetoresistive unit MTJ1 is obtained.

[0094] Second read current I Ｒ２ In the example shown in FIG. 13, the second read current I′ flows between the third electrode E3 and the first electrode E1. Ｒ２ The second read current I′ flows from the third electrode E3 to the first electrode E1. Ｒ２ The conductance G2 of the second magnetoresistive unit MTJ2 is obtained by the flow of the current ' in the z direction inside the second magnetoresistive unit MTJ2.

[0095] During reading, a first read current I Ｒ１ ' and the second read current I Ｒ２ Then, the calculation unit 5 calculates the difference (I Ｒ１ '-I Ｒ２ '), and the difference (G1-G2) in conductance between the first magnetoresistive unit MTJ1 and the second magnetoresistive unit MTJ2 are obtained. Ｒ１ ' and the second read current I Ｒ２ 'Difference (I Ｒ１ '-I Ｒ２The comparator may calculate the first read current I Ｒ１ a third wiring L3 through which a second read current I′ flows; Ｒ２ The fourth wiring L4 through which currents ' flow is connected to the fourth wiring L5.

[0096] In both the first and second examples, the difference (G1-G2) in conductance between the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2 is read out as a signal from the memristor 100.

[0097] 14 is a diagram illustrating the conductance change of the memristor 100 according to the first embodiment. The horizontal axis of FIG. 14 represents the position of the domain wall DW in the x-direction, and the vertical axis represents the conductance. The horizontal axis of FIG. 14 corresponds to the position in the x-direction from the first end to the second end of the third region A3 in which the domain wall DW can move. FIG. 14 shows the conductance G1 of the first magnetoresistive effect unit MTJ1, the conductance G2 of the second magnetoresistive effect unit MTJ2, and the conductance (G1-G2) of the memristor 100.

[0098] As the domain wall DW moves in the +x direction, the volume ratio of the first magnetic domain A31 in the third region A3 increases. In the first magnetoresistive unit MTJ1, as the domain wall DW moves in the +x direction, the magnetization M of the first reference layer 10 １０ Therefore, the resistance of the first magnetoresistive unit MTJ1 decreases as the domain wall DW moves in the +x direction, and the conductance G1 of the first magnetoresistive unit MTJ1 increases as the domain wall DW moves in the +x direction.

[0099] In the second magnetoresistive effect unit MTJ2, the magnetization relationship between the domain wall displacement layer 30 and the second reference layer 20 sandwiching the second non-magnetic layer 50 does not change until the domain wall DW reaches a position where it overlaps with the second reference layer 20 as viewed from the z direction. Therefore, this region becomes an insensitive region where the conductance does not change even if the domain wall DW moves in the x direction. When the domain wall DW reaches a position where it overlaps with the second reference layer 20 as viewed from the z direction, the resistance of the second magnetoresistive effect unit MTJ2 increases as the domain wall DW moves in the +x direction, and the conductance G2 of the second magnetoresistive effect unit MTJ2 decreases as the domain wall DW moves in the +x direction. The magnetization M of the second reference layer 20 decreases as the domain wall DW moves in the +x direction. ２０ This is because the volume ratio of the portion (first magnetic domain A31) in which the magnetization is oriented in a direction antiparallel to the first magnetic domain A31 increases.

[0100] The conductance of the memristor 100 is calculated as the difference (G1-G2) between the conductance G1 of the first magnetoresistive unit MTJ1 and the conductance G2 of the second magnetoresistive unit MTJ2. By calculating the difference between the conductance G1 of the first magnetoresistive unit MTJ1 and the conductance G2 of the second magnetoresistive unit MTJ2, a negative value can also be selected for the conductance of the memristor 100. In other words, the memristor 100 can express a range of conductance from negative to positive values ​​with a single element.

[0101] It is preferable that the range in which the conductance G1 of the first magnetoresistive effect unit MTJ1 can change and the range in which the conductance G2 of the second magnetoresistive effect unit MTJ2 can change overlap at least partially. When the conductance ranges of the two magnetoresistive effect units overlap, there is a point where the conductance G1 and the conductance G2 match. Therefore, the point where the conductance (G1-G2) of the memristor 100 is zero can be used as a reference, making it easy to convert negative conductance and positive conductance values. Note that even when the conductance ranges of the two magnetoresistive effect units do not overlap, the first read current I can be generated by a circuit external to the memristor 100, which makes the magnitudes of the first read voltage and the second read voltage different. Ｒ１ ' or the second read current I Ｒ２By using a method such as amplifying ', the memristor 100 can express negative and positive conductances.

[0102] The maximum value G1 of the conductance G1 of the first magnetoresistive effect portion MTJ1 ｍａｘ is the maximum value G2 of the conductance G2 of the second magnetoresistive effect unit MTJ2 ｍａｘ The maximum value G2 of the conductance G2 of the second magnetoresistive effect portion MTJ2 is ｍａｘ is the minimum value G1 of the conductance G1 of the first magnetoresistive effect portion MTJ1 ｍｉｎ The minimum value G1 of the conductance G1 of the first magnetoresistive element MTJ1 is ｍｉｎ is the minimum value G2 of the conductance G2 of the second magnetoresistive effect portion MTJ2 ｍｉｎ It is preferable that the G ｍａｘ >G2 ｍａｘ >G1 ｍｉｎ >G2 ｍｉｎ It is preferable that the following relationship be satisfied. When this relationship is satisfied, the range of values ​​(dynamic range) that the conductance (G1-G2) of the memristor 100 can take can be increased.

[0103] The maximum and minimum values ​​of the conductance can be freely designed by changing the materials of each layer constituting the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2, the length and width of the region where the domain wall displacement layer 30 overlaps with the first reference layer 10 or the second reference layer 20, and the thickness of the first non-magnetic layer 40 or the second non-magnetic layer 50.

[0104] As described above, the memristor 100 according to the first embodiment can exhibit both positive and negative conductance with a single element. Therefore, as shown in FIG. 2 , it can be controlled with a total of four switch elements: two switch elements SW1 and SW2 for writing data and two switch elements SW3 and SW4 for reading data. In contrast, if two elements are used to express both positive and negative conductance, a total of six switch elements are required: three switch elements for controlling the element exhibiting positive conductance (two switch elements for writing data and one switch element for reading data) and three switch elements for controlling the element exhibiting negative conductance (two switch elements for writing data and one switch element for reading data). In other words, the memristor 100 according to the first embodiment can eliminate two switch elements compared to the case where two elements are used to express both positive and negative conductance. In particular, the two eliminated switch elements are both large-sized switch elements for writing data. In this way, the memristor 100 according to the first embodiment can express the same conductance with fewer elements than when two elements are used to express positive and negative conductance, and therefore the memristor array 2 according to the first embodiment has excellent integration properties.

[0105] The memristor device 1 according to the first embodiment can be used in, for example, a neuromorphic device.

[0106] A neuromorphic device is a device that artificially mimics the relationship between neurons and synapses in the human brain. Neuromorphic devices are capable of performing neural network calculations.

[0107] 15 is a schematic diagram of the neural network NN. The neural network NN has an input layer L ｉｎ and the middle layer L ｍ and the output layer L ｏｕｔ In FIG. 15, the intermediate layer L ｍ presents an example of three layers, but the middle layer L ｍ The number of input layers L ｉｎand the middle layer L ｍ and the output layer L ｏｕｔ Each of the input layers L has a plurality of chips C, each of which corresponds to a neuron in the brain. ｉｎ and the middle layer L ｍ and the output layer L ｏｕｔ The chips C and the number of transmission means shown in FIG. 15 are merely examples.

[0108] Neural networks (NN) improve the rate of correct answers to questions by learning through their transmission means (synapses). Learning is the process of finding knowledge that may be useful in the future from information. Neural networks (NN) learn by operating while changing the weights of their transmission means. The transmission means performs a multiplication operation, which applies a weight to the input signal, and an addition operation, which adds the result of the multiplication operation. In other words, the transmission means performs a product-sum operation.

[0109] 16 is a block diagram showing a system including the neuromorphic device 200 according to the first embodiment. The system 300 includes a plurality of sensors 201, the neuromorphic device 200, and a communication unit 202.

[0110] Any sensor can be used for each of the multiple sensors 201 depending on the application. For example, a temperature sensor, a humidity sensor, a speed sensor, a pressure sensor, an acceleration sensor, etc. can be used as the multiple sensors 201. The signals from these sensors are input to, for example, the input layer L ｉｎ corresponds to the signal input to

[0111] The neuromorphic device 200 includes, for example, multiple memristor devices 1. Each memristor device 1 performs a product-sum operation. Each memristor device 1 performs operations from each layer of the neural network NN to the next layer. Each memristor device 1 may have a separate control device 3, or may share the control device 3.

[0112] The conductance of the memristor 100 changes depending on the position of the domain wall DW. The conductance of the memristor 100 corresponds to the weight of the transmission means in the neural network NN. The conductance of the memristor 100 can be expressed from negative to positive values ​​and changes linearly with respect to the input. In the learning of the neural network NN, both positive and negative weights are required. Because the conductance of the memristor 100 can be expressed from negative to positive values, it is suitable as a parameter representing the weight of the transmission means. For example, if information (e.g., temperature) from a specific sensor 201 among multiple sensors 201 is important, the conductance (weight) of the memristor 100 responsible for transmitting the signal from that sensor 201 is increased when the neuromorphic device 200 learns.

[0113] Each memristor 100 functions as a product calculation element, outputting a signal that is the product of the input voltage and the conductance of the memristor 100 itself. The memristor array 2 functions as a product-sum calculation unit, combining the outputs from multiple memristors 100. The product-sum calculation performed by the multiple memristors 100 is controlled by a control device 3.

[0114] The neuromorphic device 200 performs learning and inference. The conductance of the memristor 100 (corresponding to the weight of the transmission means) is adjusted during learning. Inference is performed using the set conductance of the memristor 100 (corresponding to the weight of the transmission means).

[0115] The neuromorphic device 200 used in the system 300 may be capable of both learning and inference, or may be capable of only inference. When only inference is performed, learning tailored to the task is performed in advance, and weights tailored to the task are installed in the memristors 100 of the neuromorphic device 200. For example, the conductance of each memristor 100 is adjusted to correspond to the weights of the transmission means determined in the advance learning. If the neuromorphic device 200 is capable of only inference, the computational load on the edge device can be reduced.

[0116] The communication unit 202 outputs the calculation results of the neuromorphic device 200 to the outside. For example, an inference result for a predetermined task obtained by the neuromorphic device 200 is input to the communication unit 202, and the communication unit 202 outputs the information to the outside. The communication unit 202 may be wired or wireless.

[0117] The memristor device 1 according to this embodiment has excellent integration capabilities, and therefore the size of the entire system 300 can be reduced.

[0118] 17 is a cross-sectional view of a memristor 101 according to a second embodiment. The memristor 101 according to the second embodiment differs from the memristor 100 according to the first embodiment in the shape of the first electrode E1′. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0119] The first electrode E1' contacts the first region A1 of the domain wall displacement layer 30. The first electrode E1' may include an intermediate layer at the interface with the domain wall displacement layer 30. A first interface S1 between the first electrode E1' and the domain wall displacement layer 30 may be closer to the first non-magnetic layer 40 than a second interface S2 between the second non-magnetic layer 50 and the domain wall displacement layer 30.

[0120] The first electrode E1' is a conductor. For example, the first electrode E1' can be made of the same material as the first electrode E1. The magnetization M of the first electrode E1' Ｅ１ ' is, for example, oriented in the first magnetization direction.

[0121] When viewed from the z direction, a portion of the first electrode E1' protrudes outward from the domain wall displacement layer 30. Of the x direction ends of the first electrode E1', a first end located away from the geometric center GC of the domain wall displacement layer 30 is located away from the geometric center GC than the first end 30A of the x direction of the domain wall displacement layer 30.

[0122] More specifically, among the x-direction ends of the lower surface S3 of the first electrode E1', a first end S3A located away from the geometric center GC of the domain wall displacement layer 30 is located farther from the geometric center GC than the first end 30A of the domain wall displacement layer 30 in the x-direction. The lower surface S3 is the surface of the first electrode E1' closer to the first non-magnetic layer 40 in the z-direction. The lower surface S3 is not limited to a flat surface and may be curved. The lower surface S3 protrudes outward from the domain wall displacement layer 30 when viewed in the z-direction.

[0123] By widening the lower surface S3, the flatness of the surface on which the first electrode E1′ is formed is increased. When the flatness of the first electrode E1′ is high, the magnetization M of the first electrode E1′ is increased. Ｅ１ ' becomes more stable.

[0124] The memristor 101 according to the second embodiment can express positive and negative conductance, similar to the memristor 100 according to the first embodiment. Ｅ１ The magnetization M of the first region A1 increases due to the increased stability of Ａ１ is strongly fixed, the range of movement of the domain wall DW can be limited, and the domain wall displacement layer 30 can be prevented from becoming a single magnetic domain.

[0125] 18 is a plan view of a memristor 102 according to a third embodiment. Fig. 18 is a plan view of the surface of the domain wall displacement layer 30. Like the memristor 100 according to the first embodiment, the memristor 102 includes, for example, a first reference layer 10, a second reference layer 20, a domain wall displacement layer 30, a first non-magnetic layer 40, a second non-magnetic layer 50, a first electrode E1, a second electrode E2, a third electrode E3, and a fourth electrode E4.

[0126] In the memristor 102 according to the third embodiment, the distance D1 in the x direction between the first electrode E1 and the second reference layer 20 is different from the distance D2 in the x direction between the second electrode E2 and the second reference layer 20. The distance D1 in the x direction between the first electrode E1 and the second reference layer 20 corresponds to the distance in the x direction between the first region A1 with which the first electrode E1 is in contact and the second reference layer 20. The distance D2 in the x direction between the second electrode E2 and the second reference layer 20 corresponds to the distance in the x direction between the second region A2 with which the second electrode E2 is in contact and the second reference layer 20. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference symbols, and descriptions thereof will be omitted.

[0127] 18, the distance D1 is shorter than the distance D2. From the viewpoint of ease of manufacturing, the first electrode E1 may be made of a magnetic material and the second electrode E2 may be made of a non-magnetic material. In this case, the magnetization M of the second region A2 Ａ２ is the magnetization M of the first region A1 Ａ１ The orientation direction is more likely to change. Ａ１ is the magnetization M of the first electrode E1 Ｅ１ If the distance D2 between the second region A2 and the second reference layer 20 is long, the domain wall DW can be prevented from penetrating into the second region A2, and the domain wall displacement layer 30 can be prevented from becoming a single magnetic domain.

[0128] 18, the distance D1 may be longer than the distance D2. When the first electrode E1 is made of a magnetic material, the leakage magnetic field generated at the first electrode E1 is applied to the magnetization M of the second reference layer 20. ２０ When the distance D1 between the first region A1 and the second reference layer 20 is long, the leakage magnetic field generated at the first electrode E1 affects the magnetization M of the second reference layer 20. ２０ The impact on

[0129] The memristor 102 according to the third embodiment can express positive and negative conductance, similar to the memristor 100 according to the first embodiment. Furthermore, by making the distance D1 and the distance D2 different from each other, the reliability of the operation of the memristor 102 can be improved.

[0130] 19 is a plan view of a memristor 103 according to a fourth embodiment. Fig. 19 is a plan view of the surface of the domain wall displacement layer 30. The memristor 103 according to the fourth embodiment differs from the memristor 100 according to the first embodiment in the shapes of the first region A1' and the second region A2'. In the fourth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0131] The first region A1' is the same as the first region A1 according to the first embodiment except for the shape. The second region A2' is the same as the second region A2 according to the first embodiment except for the shape.

[0132] The width W1' of the first region A1' is the same as the width W3 of the third region A3. The width W2' of the second region A2' is wider than the width W1' of the first region A1' and the width W3 of the third region A3. The second boundary surface BS2 between the second region A2' and the third region A3 is wider in area than the first boundary surface BS1 between the first region A1' and the third region A3.

[0133] When the first electrode E1 is magnetic and the second electrode E2 is non-magnetic, the magnetization of the first region A1' is more strongly oriented than the magnetization of the second region A2'. In other words, the magnetization of the second region A2' is more unstable than the magnetization of the first region A1'. If the second boundary surface BS2 is wide, the current density drops sharply from the third region A3 to the second region A2'. If the current density is low, the force that moves the domain wall DW becomes weak. Therefore, if the second boundary surface BS2 is wide, even if the magnetization stability of the second region A2' is low, it is possible to prevent the domain wall DW from penetrating the second region A2' and the domain wall displacement layer 30 from becoming a single magnetic domain.

[0134] Furthermore, the first region A1' and the second region A2' are portions into which the domain wall DW does not penetrate and therefore do not contribute to the magnetoresistance change. If the area of ​​the first region A1' and the second region A2' relative to the entire domain wall displacement layer 30 is small, the effective magnetoresistance effect ratio of the first magnetoresistance effect part MTJ1 becomes large. The area of ​​the first region A1' and the second region A2' relative to the entire domain wall displacement layer 30 can be reduced by, for example, matching the width W1' of the first region A1' with the width W3 of the third region A3 and narrowing the width W2' of the second region A2' as it moves away from the third region A3.

[0135] The memristor 103 according to the fourth embodiment can express positive and negative conductance, similar to the memristor 100 according to the first embodiment. Furthermore, the memristor 103 has a large area of ​​the second boundary surface BS2, which increases the reliability of its operation. Furthermore, the memristor 103 has a small area of ​​the first region A1' and the second region A2' relative to the entire domain wall displacement layer 30, which increases the effective magnetoresistance ratio of the first magnetoresistance effect part MTJ1.

[0136] Fifth Embodiment FIG. 20 is a plan view of a memristor 104 according to a fifth embodiment. FIG. 20 is a plan view of the surface of the domain wall displacement layer 30. The memristor 104 according to the fifth embodiment differs from the memristor 103 according to the fourth embodiment in the shape of the second region A2″. In the fifth embodiment, the same components as those in the fourth embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0137] The second region A2" is the same as the second region A2 according to the first embodiment, except for its shape. The second region A2" has a widening region A21. The widening region A21 is a region whose width in the y direction increases continuously from the second boundary surface BS2 between the second region A2" and the third region A3.

[0138] The widened region A21 suppresses local current concentration at the second boundary surface BS2 between the second region A2" and the third region A3. Current tends to concentrate at corners. When local current concentration occurs in the domain wall displacement layer 30, the domain wall displacement layer 30 generates heat locally. The local heat generation in the domain wall displacement layer 30 hinders stable operation of the domain wall DW and may also cause damage to the domain wall displacement layer 30.

[0139] The memristor 104 according to the fifth embodiment can express positive and negative conductance, similar to the memristor 100 according to the first embodiment. If the second region A2" has the widened region A21, local current concentration can be prevented and the reliability of the operation of the memristor 104 can be improved. Here, an example is shown in which the second region A2" has the widened region A21, but the first region A1 may have a widened region whose width in the y direction continuously increases from the first boundary surface BS1 between the first region A1 and the third region A3.

[0140] 21 is a cross-sectional view of a memristor 105 according to a sixth embodiment. The memristor 105 according to the sixth embodiment differs from the memristor 100 according to the first embodiment in the shape of the second nonmagnetic layer 51. In the sixth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0141] The second non-magnetic layer 51 covers the entire surface of the third region A3 of the domain wall displacement layer 30. The second non-magnetic layer 51 has an overlapping region 51A that overlaps with the second reference layer 20 when viewed from the z direction, and a non-overlapping region 51B that does not overlap with the second reference layer 20 when viewed from the z direction. The second non-magnetic layer 51 differs from the second non-magnetic layer 50 in having the non-overlapping region 51B. The overlapping region 51A and the non-overlapping region 51B may have different film thicknesses. For example, the film thickness of the non-overlapping region 51B may be thinner than the film thickness of the overlapping region 51A.

[0142] When the second non-magnetic layer 50 covers the entire surface of the third region A3, the degree of orientation of the magnetization in the third region A3 increases. This is because interfacial magnetic anisotropy occurs at the interface between the domain wall displacement layer 30 and the second non-magnetic layer 51. For example, the magnetization M of the third region A3 Ａ３１ , M Ａ３２ The magnetization M of the third region A3 is oriented in the z direction. Ａ３１ , M Ａ３２ When the orientation of the magnetic domain wall displacement layer 30 is high, the magnetoresistance change rate of the first magnetoresistance effect unit MTJ1 increases. As a result, the memristor 105 has a large change range in the conductance of the first magnetoresistance effect unit MTJ1. Furthermore, if there is no difference in the magnetization state between the portion of the magnetic domain wall displacement layer 30 that contacts the overlapping region 51A and the portion that contacts the non-overlapping region 51B, the variation in the magnetic domain wall DW displacement characteristics decreases.

[0143] The magnetic elements may also be scattered on the top surface of the non-overlapping region 51B. The magnetic elements may also be scattered inside the non-overlapping region 51B. Here, "scattered" refers to a state in which multiple magnetic elements are present at a distance from each other within a non-magnetic material. The magnetic elements function as trap sites that restrict the movement of the domain wall DW within the domain wall displacement layer 30. The trap sites restrict the movement of the domain wall DW and prevent the domain wall DW from penetrating into the first region A1 and the second region A2.

[0144] The memristor 105 according to the sixth embodiment can exhibit positive and negative conductance, similar to the memristor 100 according to the first embodiment. Furthermore, since the second nonmagnetic layer 51 has the non-overlapping region 51B, the range of change in the conductance of the memristor 105 can be widened, thereby improving the operational stability.

[0145] 22 is a cross-sectional view of a memristor 106 according to a seventh embodiment. The memristor 106 according to the seventh embodiment differs from the memristor 100 according to the first embodiment in the configuration of the domain wall displacement layer 31. In the seventh embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0146] The domain wall displacement layer 31 has a first layer 31A, a second layer 31B, and an intermediate layer 31C. The first layer 31A contacts the first non-magnetic layer 40. The second layer 31B contacts the second non-magnetic layer 50. The intermediate layer 31C is located between the first layer 31A and the second layer 31B. The first layer 31A and the second layer 31B are ferromagnetic layers. The first layer 31A and the second layer 31B can be made of the same material as the domain wall displacement layer 30. The first layer 31A and the second layer 31B are magnetically coupled. The intermediate layer 31C is, for example, a non-magnetic material.

[0147] The second layer 31B is, for example, thicker than the first layer 31A. The second layer 31B is located farther from the substrate Sub than the first layer 31A, and is milled for a longer period of time during processing. Furthermore, the first electrode E1 and the second electrode E2 are partially embedded in the second layer 31B. By increasing the thickness of the second layer 31B, damage during processing can be prevented.

[0148] The first layer 31A is responsible for the magnetoresistance change of the first magnetoresistance effect unit MTJ1, and the second layer 31B is responsible for the magnetoresistance change of the second magnetoresistance effect unit MTJ2. By increasing the thickness of the second layer 31B, which is susceptible to processing damage, it is possible to prevent a large difference in magnetic properties between the second layer 31B and the first layer 31A.

[0149] The memristor 106 according to the seventh embodiment can express positive and negative conductance, similar to the memristor 100 according to the first embodiment. Furthermore, since the domain wall displacement layer 30 is made up of multiple layers, the magnetic properties of the memristor 106 can be improved.

[0150] Although an example in which the domain wall displacement layer 30 has three layers has been shown here, it may have four or more layers, or may have two layers. When the domain wall displacement layer 30 has two layers, the materials of the first layer 31A and the second layer 31B are different.

[0151] 23 is a cross-sectional view of a memristor 107 according to an eighth embodiment. The memristor 107 according to the eighth embodiment has a magnetization M １０ and the magnetization M of the second reference layer 20 ２０ The eighth embodiment differs from the memristor 100 according to the first embodiment in that the and are oriented in the same direction. In the eighth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0152] 24 is a diagram illustrating the conductance change of the memristor 107 according to the eighth embodiment. The horizontal axis of FIG. 24 represents the position of the domain wall DW in the x-direction, and the vertical axis represents the conductance. The horizontal axis of FIG. 24 corresponds to the position in the x-direction from the first end to the second end of the third region A3 in which the domain wall DW can move. FIG. 24 shows the conductance G1 of the first magnetoresistive effect unit MTJ1, the conductance G2 of the second magnetoresistive effect unit MTJ2, and the conductance (G1-G2) of the memristor 107.

[0153] As the domain wall DW moves in the +x direction, the volume ratio of the first magnetic domain A31 in the third region A3 increases. In the first magnetoresistive unit MTJ1, as the domain wall DW moves in the +x direction, the magnetization M of the first reference layer 10 １０ Therefore, the resistance of the first magnetoresistive unit MTJ1 decreases as the domain wall DW moves in the +x direction, and the conductance G1 of the first magnetoresistive unit MTJ1 increases as the domain wall DW moves in the +x direction.

[0154] In the second magnetoresistive effect unit MTJ2, the magnetization relationship between the domain wall displacement layer 30 and the second reference layer 20 sandwiching the second non-magnetic layer 50 does not change until the domain wall DW reaches a position where it overlaps with the second reference layer 20 as viewed from the z direction. Therefore, this region becomes an insensitive region where the conductance does not change even if the domain wall DW moves in the x direction. When the domain wall DW reaches a position where it overlaps with the second reference layer 20 as viewed from the z direction, the resistance of the second magnetoresistive effect unit MTJ2 decreases as the domain wall DW moves in the +x direction, and the conductance G2 of the second magnetoresistive effect unit MTJ2 increases as the domain wall DW moves in the +x direction. The magnetization M of the second reference layer 20 decreases as the domain wall DW moves in the +x direction.２０ This is because the volume ratio of the portion (first magnetic domain A31) in which the magnetization is oriented in a direction parallel to the direction of the first magnetic domain A31 increases.

[0155] The conductance of the memristor 107 is calculated as the difference (G1-G2) between the conductance G1 of the first magnetoresistive effect unit MTJ1 and the conductance G2 of the second magnetoresistive effect unit MTJ2. Even if the behavior of the change in conductance with respect to the position of the domain wall DW tends to be similar between the first magnetoresistive effect unit MTJ1 and the second magnetoresistive effect unit MTJ2, a negative value can also be selected for the conductance of the memristor 107. In other words, the memristor 107 can express conductance values ​​ranging from negative to positive with a single element.

[0156] Here, an example has been shown in which the conductance G1 and the conductance G2 increase as the position of the domain wall DW moves in the x direction, but a configuration in which the conductance G1 and the conductance G2 decrease may also be used.

[0157] The memristor 107 according to the eighth embodiment can exhibit positive and negative conductance, similar to the memristor 100 according to the first embodiment.

[0158] 25 is a cross-sectional view of a memristor 108 according to a ninth embodiment. The memristor 108 according to the ninth embodiment differs from the memristor 100 according to the first embodiment in the stacking order of the layers. In the ninth embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0159] In the memristor 108 according to the ninth embodiment, the second reference layer 20, the second non-magnetic layer 50, the domain wall displacement layer 30, the first non-magnetic layer 40, and the first reference layer 10 are arranged near the substrate Sub in this order.

[0160] The memristor 108 according to the ninth embodiment has the same effects as the memristor 100 according to the first embodiment, except that the stacking order of the layers is different from that of the memristor 100 according to the first embodiment.

[0161] 26 is a cross-sectional view of a memristor 109 according to a tenth embodiment. The memristor 109 according to the tenth embodiment differs from the memristor 101 according to the second embodiment in that the second electrode E2′ includes a ferromagnetic material. In the tenth embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0162] The second electrode E2' is in contact with the second region A2 of the domain wall displacement layer 30. The second electrode E2' may include an intermediate layer at the interface with the domain wall displacement layer 30. The second electrode E2' is a ferromagnetic conductor. For example, the second electrode E2' may be made of the same material as the first electrode E1'. The magnetization M of the second electrode E2' Ｅ２ ' is, for example, oriented in the second magnetization direction.

[0163] The second electrode E2' is different in size from the first electrode E1'. In an xz cross section passing through the center of the memristor 109 in the y direction, the area of ​​the second electrode E2' is different from that of the first electrode E1'. For example, as shown in FIG. 26, the area of ​​the second electrode E2' may be smaller than that of the first electrode E1'. Conversely, the area of ​​the second electrode E2' may be larger than that of the first electrode E1'. Also, as shown in FIG. 26, the position of the lower surface of the first electrode E1' in the z direction may be different from the position of the lower surface of the second electrode E2' in the z direction.

[0164] When the second electrode E2' and the first electrode E1' are different in size, the difference in coercive force between them can be utilized to easily orient the magnetization of the second electrode E2' and the magnetization of the first electrode E1' in different directions. Furthermore, when the z-direction position of the lower surface of the first electrode E1' is different from the z-direction position of the lower surface of the second electrode E2', a further difference in coercive force can be created between the first region A1 and the second region A2.

[0165] The memristor 109 according to the tenth embodiment can express positive and negative conductance, similar to the memristor 100 according to the first embodiment.

[0166] 27 is a cross-sectional view of a memristor 110 according to an eleventh embodiment. The memristor 110 according to the eleventh embodiment differs from the memristor 100 according to the first embodiment in that the domain wall displacement layer 30 extends in the z direction. In the eleventh embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted.

[0167] The memristor 110 according to the eleventh embodiment corresponds to the memristor 100 according to the first embodiment rotated by 90 degrees. In the memristor 110 according to the eleventh embodiment, the domain wall DW moves in the z direction.

[0168] The memristor 110 according to the eleventh embodiment can be fabricated by peeling a memristor fabricated on a release substrate using the same procedure as for the memristor 100, rotating it by 90 degrees after peeling it off from the release substrate, and then placing it on the substrate Sub shown in FIG.

[0169] The memristor 110 according to the eleventh embodiment has a different orientation from the memristor 100 according to the first embodiment, but has the same effects as the memristor 100 according to the first embodiment.

[0170] 28 is a perspective view of a memristor 111 according to a twelfth embodiment. The memristor 111 according to the twelfth embodiment includes, for example, a first reference layer 12, a second reference layer 22, a domain wall displacement layer 32, a first nonmagnetic layer 42, a first electrode E1", a second electrode E2", a third electrode E3", and a fourth electrode E4". The periphery of the memristor 111 is covered with an insulating layer 90, except for the wiring C1 and wiring C2.

[0171] The memristor 111 includes a first magnetoresistive effect unit MTJ1' and a second magnetoresistive effect unit MTJ2'. The first magnetoresistive effect unit MTJ1' is composed of a first reference layer 12, a first non-magnetic layer 42, and a domain wall displacement layer 32. The second magnetoresistive effect unit MTJ2' is composed of a second reference layer 22, a first non-magnetic layer 42, and a domain wall displacement layer 32. The conductance of the first magnetoresistive effect unit MTJ1' and the second magnetoresistive effect unit MTJ2' each changes depending on the position of the domain wall DW in the domain wall displacement layer 32.

[0172] The first reference layer 12 corresponds to the first reference layer 10 according to the first embodiment, and has the same configuration and material as the first reference layer 10. The first reference layer 12 is in contact with, for example, the first nonmagnetic layer 42. The first reference layer 12 faces the first portion P1 of the domain wall displacement layer 32.

[0173] The second reference layer 22 corresponds to the second reference layer 20 according to the first embodiment, and the same material as that of the second reference layer can be used. The second reference layer 22 contacts the first non-magnetic layer 42 at a position different from that of the first reference layer 12. The second reference layer 22 and the first reference layer 12 contact the same surface of the first non-magnetic layer 42. The second reference layer 22 faces the second portion P2 of the domain wall displacement layer 32. The second portion P2 is a portion different from the first portion P1, and is located, for example, at a position shifted from the first portion P1 in the y direction.

[0174] The second reference layer 22 differs from the second reference layer 20 in that the length in the x direction is approximately the same as the length in the x direction of the domain wall displacement layer 32. The length in the x direction of the second reference layer 22 is approximately the same as the length in the x direction of the first reference layer 12. For example, the second reference layer 22 may overlap the first region A1 and the second region A2 of the domain wall displacement layer 32 when viewed from the z direction.

[0175] The first non-magnetic layer 42 corresponds to the first non-magnetic layer 40 according to the first embodiment, and may have the same thickness and be made of the same material as the first non-magnetic layer 40. The first non-magnetic layer 42 extends, for example, over one surface of the domain wall displacement layer 32. The first non-magnetic layer 42 is sandwiched between the first reference layer 12 and the first portion P1 of the domain wall displacement layer 32. The first non-magnetic layer 42 is sandwiched between the second reference layer 22 and the second portion P2 of the domain wall displacement layer 32.

[0176] The domain wall displacement layer 32 corresponds to the domain wall displacement layer 30 according to the first embodiment, and can be of the same thickness and material as the domain wall displacement layer 30 .

[0177] The domain wall displacement layer 32 extends in the xy plane. The domain wall displacement layer 32 has a first portion P1, a second portion P2, and a third portion P3. The first portion P1 faces the first reference layer 12. The second portion P2 faces the second reference layer 22. The third portion P3 faces neither the first reference layer 12 nor the second reference layer 22.

[0178] The domain wall displacement layer 32 has a first region A1, a second region A2, and a third region A3, each of which is the same as that in the first embodiment.

[0179] The first electrode E1" corresponds to the first electrode E1 according to the first embodiment, and may have the same configuration and material as the first electrode E1. The second electrode E2" corresponds to the second electrode E2 according to the first embodiment, and may have the same configuration and material as the first electrode E1. The first electrode E1" and the second electrode E2" are write terminals for both the first magnetoresistive effect unit MTJ1' and the second magnetoresistive effect unit MTJ2'. The first electrode E1" is electrically connected to the switch element SW1. The second electrode E2" is electrically connected to the switch element SW2.

[0180] The third electrode E3" corresponds to the third electrode E3 according to the first embodiment, and the same configuration and material can be used. The fourth electrode E4" corresponds to the fourth electrode E4 according to the first embodiment, and the same configuration and material can be used. The third electrode E3" is a read terminal of the second magnetoresistive effect unit MTJ2', and is electrically connected to the switch element SW3. The fourth electrode E4" is a read terminal of the first magnetoresistive effect unit MTJ1', and is electrically connected to the switch element SW4.

[0181] The memristor 111 is formed by a process of stacking each layer and a process of processing a part of each layer into a predetermined shape.

[0182] The memristor 111 performs a write operation and a read operation. In a write operation, the position of the domain wall DW of the domain wall displacement layer 32 is changed. In a read operation, the conductance of the memristor 111 or the output current from the memristor 111 is detected.

[0183] When writing a signal to the memristor 111, a write current (write pulse) is applied between the first electrode E1″ and the second electrode E2″. Ｗ When the magnetic field is applied, the position of the domain wall DW in the domain wall displacement layer 32 changes.

[0184] When the position of the domain wall DW in the domain wall displacement layer 32 changes, the conductance in the z direction of the first magnetoresistive effect unit MTJ1' and the second magnetoresistive effect unit MTJ2' in the memristor 111 also changes.

[0185] When reading a signal from the memristor 111, a read current is passed between the first electrode E1" and the fourth electrode E4" to determine the conductance of the first magnetoresistive effect unit MTJ1', and a read current is passed between the first electrode E1" and the third electrode E3" to determine the conductance of the second magnetoresistive effect unit MTJ2'. For example, with respect to the potential of the domain wall displacement layer 32 as a reference, a positive potential may be applied to the first reference layer 12 and a negative potential may be applied to the second reference layer 22. Alternatively, with respect to the potential of the domain wall displacement layer 32 as a reference, a positive potential may be applied to the first reference layer 12 and the second reference layer 22. In other words, during reading, the first read voltage applied to the first reference layer 10 and the second read voltage applied to the second reference layer 22 may have the same or opposite polarities with respect to the potential of the domain wall displacement layer 30 as a reference.

[0186] The difference in conductance (G1-G2) between the first magnetoresistive unit MTJ1' and the second magnetoresistive unit MTJ2' can be calculated from their respective conductances. Alternatively, the difference in conductance (G1-G2) may be calculated from the difference between the read current flowing through the first magnetoresistive unit MTJ1' and the read current flowing through the second magnetoresistive unit MTJ2'.

[0187] As in the first embodiment, the conductance difference (G1-G2) is output as the overall conductance of the memristor 111. By using the conductance difference, the memristor 111 can express conductance ranging from negative to positive values ​​with a single element.

[0188] Furthermore, since the memristor 111 according to the twelfth embodiment can also be controlled by four switch elements, a memristor array using this memristor 111 has excellent integration properties, similar to the memristor array according to the first embodiment.

[0189] Any of the memristors according to the second to twelfth embodiments can be substituted for the memristor 100 shown in FIG.

[0190] Although the preferred embodiments have been described in detail above, the present invention is not limited to these embodiments. For example, the characteristic features of the respective embodiments may be combined, or some parts may be modified without departing from the spirit of the invention.

[0191] REFERENCE SIGNS LIST 1 memristor device 2 memristor array 3 control device 4 signal input unit 5 calculation unit 6 output unit 7 control unit 8 power supply 10 first reference layer 20 second reference layer 30, 31 domain wall displacement layer 30A first end 31A first layer 31B second layer 31C intermediate layer 40 first non-magnetic layer 50, 51 second non-magnetic layer 51A overlapping region 51B non-overlapping region 90 insulating layer 100, 101, 102, 103, 104, 105, 106, 107, 108 memristor 200 neuromorphic device 201 sensor 202 communication unit 300 system A1, A1' first region A2, A2', A2" second region A3 third region A21 widening region BS1 first boundary surface BS2 Second boundary surface DW Domain wall E1, E1' First electrode E2 Second electrode E3 Third electrode E4 Fourth electrode MTJ1 First magnetoresistive section MTJ2 Second magnetoresistive section S1 First interface S1A First end S2 Second interface

Claims

1. A memory device includes a first reference layer, a second reference layer, a magnetic wall movement layer, a first non-magnetic layer, and a second non-magnetic layer. The first reference layer and the second reference layer each include a ferromagnetic material with magnetization oriented in one direction. The magnetic wall movement layer has a first region with magnetization oriented in a first magnetization direction, a second region with magnetization oriented in a second magnetization direction different from the first magnetization direction, and a third region where a magnetic wall can move between the first region and the second region. The first non-magnetic layer is sandwiched between the magnetic wall movement layer and the first reference layer. The second non-magnetic layer is sandwiched between the magnetic wall movement layer and the second reference layer. The first reference layer has a length in a first direction from the first region to the second region that is longer than the third region.

2. The first reference layer, the first non-magnetic layer, and the magnetic wall movement layer constitute a first magnetoresistive effect unit. The second reference layer, the second non-magnetic layer, and the magnetic wall movement layer constitute a second magnetoresistive effect unit. The conductance of each of the first magnetoresistive effect unit and the second magnetoresistive effect unit changes as the position of the magnetic wall in the magnetic wall movement layer changes. At least a part of the range in which the conductance of the first magnetoresistive effect unit can change overlaps with the range in which the conductance of the second magnetoresistive effect unit can change. The memory device according to claim 1.

3. The maximum value of the conductance of the first magnetoresistive effect unit is larger than the maximum value of the conductance of the second magnetoresistive effect unit. The maximum value of the conductance of the second magnetoresistive effect unit is larger than the minimum value of the conductance of the first magnetoresistive effect unit. The minimum value of the conductance of the first magnetoresistive effect unit is larger than the minimum value of the conductance of the second magnetoresistive effect unit. The memory device according to claim 2.

4. The second reference layer has a shorter length in the first direction than the third region. The memory device according to claim 1.

5. In a second direction orthogonal to the first direction when viewed from the stacking direction, the second reference layer is narrower than the first reference layer. The memory device according to claim 1.

6. Further comprising a first electrode and a second electrode, the first electrode being in contact with the first region of the magnetic wall movement layer, the second electrode being in contact with the second region of the magnetic wall movement layer, the first electrode including a ferromagnetic material having magnetization oriented in the first magnetization direction, and a first interface between the first electrode and the magnetic wall movement layer being closer to the first non-magnetic layer than a second interface between the second non-magnetic layer and the magnetic wall movement layer. The memristor according to claim 1.

7. A first end portion of the first electrode at a position away from the geometric center of the magnetic wall movement layer among the end portions of the first electrode in the first direction is at a position farther from the geometric center than a first end portion of the magnetic wall movement layer in the first direction. The memristor according to claim 6.

8. A distance in the first direction between the first electrode and the second reference layer is different from a distance in the first direction between the second electrode and the second reference layer. The memristor according to claim 6.

9. Further comprising a first electrode and a second electrode, the first electrode being in contact with the first region of the magnetic wall movement layer, the second electrode being in contact with the second region of the magnetic wall movement layer, the first electrode including a ferromagnetic material having magnetization oriented in the first magnetization direction, the second electrode including a ferromagnetic material having magnetization oriented in the second magnetization direction, and the second electrode having a different size from the first electrode. The memristor according to claim 1.

10. When viewed from the stacking direction, an area of the second region is larger than an area of the first region, or a second boundary surface between the second region and the third region has a larger area than a first boundary surface between the first region and the third region. The memristor according to claim 1.

11. The second region has a widened region in which a width in a second direction orthogonal to the first direction continuously increases from a second boundary surface with the third region. The memristor according to claim 1.

12. When viewed from the stacking direction, the second non-magnetic layer covers the entire surface of the third region. The memristor according to claim 1.

13. The second non-magnetic layer has a non-overlapping region that does not overlap with the second reference layer when viewed from the stacking direction, and magnetic elements are scattered on one surface or inside the non-overlapping region. The memristor according to claim 1.

14. The first reference layer, the first non-magnetic layer, and the magnetic wall movement layer constitute a first magnetoresistive effect portion, the second reference layer, the second non-magnetic layer, and the magnetic wall movement layer constitute a second magnetoresistive effect portion, the sheet resistance of the second magnetoresistive effect portion is smaller than the sheet resistance of the first magnetoresistive effect portion, and a first overlapping area where the second reference layer and the third region overlap when viewed in the stacking direction is narrower than a second overlapping area where the first reference layer and the third region overlap when viewed in the stacking direction. The memory element according to claim 1.

15. The second reference layer is located farther from the substrate than the first reference layer, the magnetic wall movement layer has a first layer in contact with the first non-magnetic layer and a second layer in contact with the second non-magnetic layer, and the second layer is thicker than the first layer. The memory element according to claim 1.

16. A first read voltage applied to the first reference layer during reading and a second read voltage applied to the second reference layer during reading are configured to have opposite polarities with reference to the potential of the magnetic wall movement layer. The memory element according to claim 1.

17. A first read voltage applied to the first reference layer during reading and a second read voltage applied to the second reference layer during reading are configured to have the same polarity with reference to the potential of the magnetic wall movement layer. The memory element according to claim 1.

18. A first read voltage applied to the first reference layer during reading and a second read voltage applied to the second reference layer during reading are configured to have different absolute values. The memory element according to claim 1.

19. The first write pulse is configured to have a smaller amplitude or a shorter length than the second write pulse. The first write pulse is a pulse applied to the magnetic wall movement layer when the magnetic wall is in a region where the second reference layer and the magnetic wall movement layer overlap when viewed in the stacking direction. The second write pulse is a pulse applied to the magnetic wall movement layer when the magnetic wall is in a region where the second reference layer and the magnetic wall movement layer do not overlap when viewed in the stacking direction. The memory element according to claim 1.

20. The thickness of the magnetic wall movement layer is 5 nm or more. The memory element according to claim 1.

21. A first switch electrically connected to the first end of the magnetic wall movement layer, a second switch electrically connected to the second end of the magnetic wall movement layer, a third switch electrically connected to the first reference layer, and a fourth switch electrically connected to the second reference layer, wherein the element sizes of the third switch and the fourth switch are smaller than the element sizes of the first switch and the second switch. The memory cell according to claim 1.

22. A first reference layer, a second reference layer, a magnetic wall movement layer, and a first non-magnetic layer, wherein the first reference layer and the second reference layer each have a length in a first direction in which the magnetic wall movement layer extends longer than the lengths in other directions, the first reference layer and the second reference layer are spaced apart in a second direction orthogonal to the first direction, the first reference layer and the second reference layer each include a ferromagnetic material with magnetization oriented in one direction, the magnetic wall movement layer has a first region with magnetization oriented in a first magnetization direction, a second region with magnetization oriented in a second magnetization direction different from the first magnetization direction, and a third region where a magnetic wall can move between the first region and the second region, the first non-magnetic layer is sandwiched between the magnetic wall movement layer and the first reference layer and the second reference layer, the first reference layer faces a first portion of the magnetic wall movement layer, and the second reference layer faces a second portion of the magnetic wall movement layer different from the first portion. The memory cell.

23. A memory cell array including the memory cell according to claim 1.

24. A memory cell array including the memory cell according to claim 22.

25. A neuromorphic device including the memory cell array according to claim 23.

26. A neuromorphic device including the memory cell array according to claim 24.

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