Semiconductor apparatus and method for manufacturing semiconductor apparatus

Abstract

The present invention includes a first semiconductor element and a second semiconductor element. The second semiconductor element includes: a second laminate that is composed of second semiconductor layers and a second gate electrode covering the periphery of the second semiconductor layers in a cross section in the gate width direction of the second semiconductor element; second gate insulation films that are each interposed between the second semiconductor layer and the second gate electrode and thicker than a first gate insulation film; a second source drain region that is formed on side surfaces in the gate length direction of the second laminate; and a third semiconductor layer and a second insulation layer that are formed between the side surfaces of the second gate electrode and the second source drain region so as to be disposed between the second semiconductor layers.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] In a semiconductor device having a GAA-FET (Gate All Around Field Effect Transistor) using a nanosheet structure, an input / output (IO) device is formed near a logic device using a GAA-FET. The I / O device needs to operate at a voltage higher than that of the GAA-FET that constitutes the logic device. For this reason, when forming an I / O device using a GAA-FET, it is necessary to make the gate insulating film thicker than conventional devices.

[0003] However, when manufacturing an input / output device with a GAA-FET structure using a conventional nanosheet-based GAA-FET manufacturing method, it is difficult to form a gate insulating film thick enough to withstand high voltages. For example, if a thick gate insulating film is formed on a GAA-FET using nanosheets in the input / output section, the insulating film will fill the spaces between the stacked Si layers (Si nanosheet layers). In this case, it is difficult to form a gate electrode between the Si layers, significantly reducing the performance of the semiconductor device.

[0004] In response to these issues, a method has been proposed for input / output devices with a GAA-FET structure using a nanosheet structure, in which the thickness of the SiGe layer stacked between Si layers is made thicker than the SiGe layer in the logic device (see, for example, Patent Document 1). In this method, when forming the SiGe layer between the Si layers in the manufacturing process of the GAA-FET, a separate epitaxial growth process is added only on the input / output device side. This added epitaxial growth process increases the thickness of the SiGe layer stacked between the Si nanosheet layers only on the input / output device side. This creates a larger space between the Si layers, ensuring space for forming a gate electrode even in a configuration in which a thick gate insulating film is formed.

[0005] Furthermore, a method has been proposed for removing the intermediate Si layer only on the input / output device side in a GAA-FET having a structure in which three or more Si nanosheet layers are stacked (see, for example, Patent Document 2). In this method, for example, a stacked structure of [Si layer / SiGe layer / Si layer / SiGe layer / Si layer] is formed, and the SiGe layer in contact with the intermediate Si layer is selectively oxidized. This selective oxidation of the SiGe layer results in Si being replaced with SiGe in the Si layer in contact with this SiGe layer. Therefore, the Si layer is replaced with SiGe, and further, the nanosheet itself substituted with SiGe is selectively oxidized. As a result, the intermediate Si layer can be selectively removed along with the SiGe layer, leaving the other Si layers (first and third layers). Therefore, a large space is formed between the first and third Si layers, ensuring space for forming a gate electrode even in a structure in which a thick gate insulating film is formed.

[0006] U.S. Patent No. 10,243,054 U.S. Patent No. 10,141,403

[0007] However, in the semiconductor device described in Patent Document 1, the thick SiGe epitaxially grown layer of the input / output device must be formed in a separate process from the logic device. This makes it difficult to align the heights of the Si layer formed above the SiGe layer between the input / output device and the logic device. This height difference results in variations in the processing height in subsequent processes. Furthermore, because some SiGe layers are very thick, it is difficult to cover the thick SiGe layer with an insulating layer when forming an insulating layer on the wall surface of the SiGe layer. Therefore, structures in which SiGe layers with large thickness differences are stacked are prone to problems with film formation. Furthermore, in the semiconductor device described in Patent Document 2, the selective oxidation of the SiGe layer to replace Si with SiGe and the control of this process are extremely difficult. Furthermore, because the SiGe layer is oxidized after the source / drain formation, the source / drain are affected by the oxidation process and deteriorate. Furthermore, this method cannot be applied to structures using two types of SiGe with different compositions. As such, the manufacturing process for semiconductor devices with conventional configurations is complicated.

[0008] In order to solve the above-mentioned problems, the present invention provides a semiconductor device that can be manufactured through easier steps and that allows the formation of a thick gate insulating film, and a method for manufacturing the semiconductor device.

[0009] The semiconductor device of the present invention includes a first semiconductor element and a second semiconductor element on a substrate, the first semiconductor element having a first stacked structure including a first semiconductor layer and a first gate electrode covering the periphery of the first semiconductor layer in a cross section in the gate width direction of the first semiconductor element, a first gate insulating film interposed between the first semiconductor layer and the first gate electrode, first source / drain regions formed on side surfaces of the first stacked structure in the gate length direction, and a first insulating layer formed between the side surfaces of the first gate electrode and the first source / drain regions disposed between the first semiconductor layers. The second semiconductor element has a second stacked body composed of a second semiconductor layer and a second gate electrode covering the periphery of the second semiconductor layer in a cross section in the gate width direction of the second semiconductor element, a second gate insulating film interposed between the second semiconductor layer and the second gate electrode and thicker than the first gate insulating film, second source / drain regions formed on side surfaces in the gate length direction of the second stacked body, a third semiconductor layer formed between the side surfaces of the second gate electrode and the second source / drain regions arranged between the layers of the second semiconductor layer, and a second insulating layer.

[0010] A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, the method including the steps of: stacking a semiconductor layer and a SiGe layer in a first semiconductor element formation region and a second semiconductor element formation region to form a Si / SiGe stack; ion-implanting an impurity into the semiconductor layer in the second semiconductor element formation region; forming an insulating layer on a sidewall of the SiGe layer; removing the SiGe layer in the first semiconductor element formation region; forming a first gate electrode through the first gate insulating film in the first semiconductor element formation region; removing the SiGe layer in the second semiconductor element formation region; removing the impurity-implanted semiconductor layer so that it remains only between the insulating layers; forming a second gate insulating film thicker than the first gate insulating film in the second semiconductor element formation region; and forming the second gate electrode on the gate insulating film of the second semiconductor element.

[0011] According to the present invention, it is possible to provide a semiconductor device that can be manufactured through simple steps and that allows the formation of a thick gate insulating film, and a method for manufacturing the semiconductor device.

[0012] 1 is a diagram (plan view) showing a schematic configuration of a semiconductor device of a first embodiment. FIG. 1 is a cross-sectional view (cross-sectional view in the gate length direction) of a first semiconductor element shown in FIG. 1 . FIG. 2 is a cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element shown in FIG. 1 . FIG. 3 is a cross-sectional view (cross-sectional view in the gate length direction) of a second semiconductor element shown in FIG. 1 . FIG. 4 is a cross-sectional view (cross-sectional view in the gate width direction) of a second semiconductor element shown in FIG. 1 . FIG. 5 is a cross-sectional view (cross-sectional view in the gate length direction) of a second semiconductor element shown in FIG. 1 . FIG. 6 is a cross-sectional view (cross-sectional view in the gate width direction) of a second semiconductor element shown in FIG. 1 . FIG. 7 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 8 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 9 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 10 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 11 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 12 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. 1 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 2 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 3 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 4 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 5 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 6 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 7 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 8 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 9 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 10 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 11 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 12 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 13 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; 14 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment;1 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; FIG. 2 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment; FIG. 3 is a cross-sectional view (cross-sectional view in the gate length direction) of a first semiconductor element of the semiconductor device of the second embodiment taken along line X1; FIG. 4 is a cross-sectional view (cross-sectional view in the gate length direction) of a second semiconductor element of the semiconductor device of the second embodiment taken along line X2; FIG. 5 is a diagram for explaining a manufacturing process of the semiconductor device of the second embodiment; FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device of the second embodiment;

[0013] Hereinafter, examples of embodiments for carrying out the present invention will be described, but the present invention is not limited to the following examples. The description will be made in the following order: 1. First embodiment of semiconductor device 2. Manufacturing method of semiconductor device 3. Second embodiment of semiconductor device

[0014] 1. First Embodiment of Semiconductor Device Below, specific embodiments of the semiconductor device of the present invention will be described. FIGS. 1-5 show schematic configuration diagrams of a semiconductor device according to a first embodiment. [Configuration of Semiconductor Device] FIG. 1 is a plan view (top view) of the semiconductor device. FIG. 2 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X1. FIG. 3 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y1. FIG. 4 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X2. FIG. 5 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y2.

[0015] The semiconductor device 10 shown in FIG. 1 includes a first semiconductor element 100 and a second semiconductor element 200 on a substrate 11. As shown in FIGS. 2-5, the first semiconductor element 100 is a GAA (Gate All Around)-FET formed by a first stack of semiconductor layers (first semiconductor layers, hereinafter simply referred to as Si layers) 101, 102, and 103 and gate electrodes 112, 113, 114, and 115. The second semiconductor element 200 is a GAA-FET formed by a second stack of semiconductor layers (second semiconductor layers, hereinafter simply referred to as Si layers) 201 and 203 and gate electrodes 212, 213, and 214. The Si layers 101, 102, and 103 of the first semiconductor element 100 and the Si layers 201 and 203 of the second semiconductor element 200 are both formed by nanosheet layers. The semiconductor layer may be made of not only Si but also other semiconductor materials such as SiGe, if necessary.

[0016] 1, the first semiconductor element 100 includes a gate electrode 112 (first gate electrode), a source region 108, and a drain region 109 (first source-drain region) formed on a substrate 11. The second semiconductor element 200 includes a gate electrode 212 (second gate electrode) formed on the substrate 11, and a source region 208 and a drain region 209 (second source-drain region).

[0017] 1 , the second semiconductor element 200 has a larger gate length than the first semiconductor element 100. Because the second semiconductor element 200 is an input / output device, a higher voltage is applied to the gate electrode 112 than to the first semiconductor element 100. For this reason, it is preferable that the second semiconductor element 200 has a larger gate length than the first semiconductor element 100 in order to suppress a through current, or so-called punch-through, between the source region 108 and the drain region 109. On the other hand, it is preferable that the first semiconductor element 100, which serves as a logic device, has a shorter gate length in order to improve switching speed.

[0018] 2 and 4 , which are cross-sectional views of the first semiconductor element 100 and the second semiconductor element 200 in the gate length direction, the entire surfaces of the second semiconductor element 200 and the first semiconductor element 100 are sealed by an insulating layer 41 on the substrate 11. An STI (Shallow Trench Isolation) 42 is formed on the surface of the substrate 11 as an element isolation region. The STI 42 is composed of the insulating layer 41 embedded in the substrate 11. The STI 42 is formed between the first semiconductor element 100 and the second semiconductor element 200. The STI 42 is formed in a region other than the region where the first semiconductor element 100 and the second semiconductor element 200 are formed.

[0019] 2 , the first semiconductor element 100 has a gate electrode 113 as the bottom layer on a substrate 11. The first semiconductor element 100 also has a first stacked body having a stacked structure including the gate electrode 113, that is, [gate electrode 113 / Si layer 101 / gate electrode 114 / Si layer 102 / gate electrode 115 / Si layer 103].

[0020] 2 , the first semiconductor element 100 has a gate electrode 112 and sidewalls 106 above the uppermost Si layer 103. The gate electrode 112 is formed in the center of the Si layer 103, and the sidewalls 106 are formed around the gate electrode 112. The gate electrode 112 includes a metal layer 104. A high-dielectric-constant material layer (first high-dielectric-constant layer) 105 is provided on the bottom and side surfaces of the gate electrode 112, i.e., on the contact surfaces between the Si layer 103 and the sidewalls 106. The metal layer 104 is filled in the high-dielectric-constant material layer 105. In the first semiconductor element 100, the high-dielectric-constant material layer 105 may be formed in combination with a layer (not shown) made of a low-dielectric-constant material that is thinner than the high-dielectric-constant material layer 105 and has a lower dielectric constant than the high-dielectric-constant material layer 105. In the first semiconductor element 100, the stacked film of the high-dielectric-constant material layer 105 and the layer of the low-dielectric-constant material functions as a gate insulating film (first gate insulating film).

[0021] The first semiconductor element 100 includes a source region 108 and a drain region 109 on the side surfaces of a first stack made up of Si layers 101, 102, and 103 and gate electrodes 113, 114, and 115. The Si layers 101, 102, and 103 are connected to the source region 108 and the drain region 109. An inner spacer 107 (first inner spacer) made of an insulating layer (first insulating layer) is formed between the gate electrodes 113, 114, and 115 and the source region 108 and the drain region 109.

[0022] 2 , gate electrodes 113, 114, and 115 formed between Si layers 101, 102, and 103 are formed of metal layer 104. Contact surfaces of gate electrodes 113, 114, and 115 with Si layers 101, 102, and 103 and inner spacer 107 are covered with high-dielectric-constant material layer 105. Metal layer 104 is filled inside high-dielectric-constant material layer 105. Metal layer 104 is formed continuously with gate electrodes 113, 114, and 115 and gate electrode 112.

[0023] 3, the first semiconductor element 100 has a high-dielectric-constant material layer 105 formed on the substrate 11 and the STI 42. The first semiconductor element 100 also has Si layers 101, 102, and 103 stacked on the high-dielectric-constant material layer 105 with a metal layer 104 constituting a gate electrode 112 interposed therebetween. The high-dielectric-constant material layer 105 is also formed between the metal layer 104 and the Si layers 101, 102, and 103. Therefore, in the cross-sectional view in the gate width direction, the Si layers 101, 102, and 103 are each surrounded by the high-dielectric-constant material layer 105.

[0024] 3, the metal layer 104 is formed continuously with the gate electrodes 113, 114, and 115 shown in FIG. 2 and the gate electrode 112. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3, the peripheries of the Si layers 101, 102, and 103 are covered by the gate electrodes 113, 114, and 115 (FIG. 2) and the gate electrode 112 (FIG. 2). That is, in the first semiconductor element 100, the entire cross sections in the gate length direction of the Si layers 101, 102, and 103 that form channel portions are surrounded by the metal layer 104 that constitutes the gate electrodes 112, 113, 114, and 115 (FIG. 2), as shown in FIG.

[0025] 4 , the second semiconductor element 200 has a gate electrode 213 in the lowermost layer on the substrate 11. The second semiconductor element 200 also has a second stacked body having a stacked structure including the gate electrode 213, that is, [gate electrode 213 / Si layer 201 / gate electrode 214 / Si layer 203].

[0026] 4 , the second semiconductor element 200 has a gate insulating film 210 (second gate insulating film), a gate electrode 212, and sidewalls 206 above the uppermost Si layer 203. The gate insulating film 210 and the gate electrode 212 are formed in the center of the Si layer 203, and the sidewalls 206 are formed around the gate insulating film 210 and the gate electrode 212.

[0027] The gate electrode 212 includes a metal layer 204. A high-dielectric-constant material layer 205 (second high-dielectric-constant material layer) is also provided on the bottom and side surfaces of the gate electrode 212, i.e., on the contact surface with the gate insulating film 210. The metal layer 204 is filled in the high-dielectric-constant material layer 205.

[0028] The gate insulating film 210 is formed between the Si layer 203 and the sidewall 216 and the gate electrode 212. The gate insulating film 210 has a sufficient thickness to withstand the high voltage applied to the second semiconductor element 200 which serves as an input / output device. For this reason, the gate insulating film 210 is formed to be sufficiently thicker than the high-dielectric-constant material layer 205.

[0029] The second semiconductor element 200 includes a source region 208 and a drain region 209 on the side surfaces of a second stacked body made up of Si layers 201 and 203 and gate electrodes 213 and 214. The Si layers 201 and 203 are connected to the source region 208 and the drain region 209.

[0030] A gate insulating film 210 is also formed between the gate electrodes 213 and 214 and the Si layers 201 and 203. The gate insulating film 210 is formed so as to cover the entire periphery of the gate electrodes 213 and 214 in the cross-sectional view in the gate length direction shown in FIG. 4. The gate insulating film 210 covering the entire periphery of the gate electrodes 213 and 214 also has a sufficient thickness to be able to withstand the high voltage applied to the second semiconductor element 200.

[0031] Furthermore, an inner spacer 207 (second inner spacer) made of an insulating layer (second insulating layer) is formed between the gate insulating film 210 covering the gate electrodes 213 and 214 and the source region 208 and drain region 209. Furthermore, an Si layer 202 is formed between the gate electrode 214 and the source region 208 and drain region 209, with the gate insulating film 210 interposed therebetween. Therefore, the gate insulating film 210, the inner spacer 207, and the semiconductor layer (third semiconductor layer, hereinafter simply referred to as the Si layer) 202 are interposed between the gate electrodes 213 and 214 and the source region 208 and drain region 209. Furthermore, the gate insulating film 210 covering the gate electrodes 213 and 214 is interposed between the gate electrodes 213 and 214 and the source region 208 and drain region 209.

[0032] 4, gate electrodes 213 and 214 formed between Si layers 201 and 203 are formed of metal layer 204. The contact surfaces of gate electrodes 213 and 214 with gate insulating film 210 are covered with high-dielectric-constant material layer 205. Metal layer 204 is filled inside high-dielectric-constant material layer 205. Metal layer 204 is formed continuously with gate electrodes 213 and 214 and gate electrode 212 (see FIG. 5).

[0033] 5 , the second semiconductor element 200 has a high-dielectric-constant material layer 205 formed on the substrate 11 and the STI 42. The second semiconductor element 200 also has Si layers 201 and 203 stacked on the high-dielectric-constant material layer 205 with a metal layer 204 constituting a gate electrode 212 interposed therebetween. The Si layers 201 and 203 are each covered by a gate insulating film 210. The gate insulating film 210 is in turn covered by a high-dielectric-constant material layer 205. Therefore, in the cross-sectional view in the gate width direction, the Si layers 201 and 203 are each covered by the gate insulating film 210 and the high-dielectric-constant material layer 205. The high-dielectric-constant material layer 205 covers the entire contact surface between the gate insulating film 210 and the metal layer 204.

[0034] 4 and 5, the metal layer 204 is formed continuously with the gate electrodes 213 and 214 and the gate electrode 212 in the cross section in the gate width direction shown in Fig. 5. Therefore, in the cross section in the gate width direction shown in Fig. 5, the peripheries of the Si layers 201 and 203 are covered with the gate electrodes 213 and 214 (Fig. 4) and the gate electrode 212 (Fig. 4). That is, in the second semiconductor element 200, the entire cross section in the gate length direction of the Si layers 201 and 203, which form the channel portions, is surrounded by the metal layer 204 that constitutes the gate electrodes 212, 213, and 214 (Fig. 4), as shown in Fig. 5.

[0035] (Layer Structure of Second Semiconductor Element) The gate electrode 214 of the second semiconductor element 200 is formed at approximately the same height as the Si layer 102 of the first semiconductor element 100, with the upper surface of the substrate 11 as the reference. In particular, the center of the height direction of the metal layer 204 of the gate electrode 214 and the center of the height direction of the Si layer 102 are located at approximately the same height.

[0036] An Si layer 202 is formed between the gate electrode 214 and the source region 208 and drain region 209, with a gate insulating film 210 interposed therebetween. The Si layer 202 is also formed on both sides of the gate electrode 214. That is, the second semiconductor element 200 includes an Si layer 202 in contact with the source region 208 and an Si layer 202 in contact with the drain region 209. The Si layer 202 on the source region 208 side and the Si layer 202 on the drain region 209 side are separated from each other.

[0037] In the second semiconductor element 200, the inner spacer 207 is divided into two or more parts at least in the stacking direction by the Si layer 202. Therefore, in the region between the Si layer 201 and the Si layer 203 on which the gate electrode 214 is formed, the inner spacer 207 is formed so as to be divided into two or more parts in the stacking direction. The Si layer 202 is interposed between the stacked parts of the inner spacer 207.

[0038] The Si layer 202 is formed so that its thickness in the surface direction of the substrate 11 is smaller than that of the inner spacer 207. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3 , the Si layer 202 and the inner spacer 207 have a step on the wall surface toward the center of the second semiconductor element 200. This step forms a recess on the side surface of the Si layer 202. An insulating film 210 is buried in the recess on the side surface of the Si layer 202. As a result, the Si layer 202 and the insulating film 210 are disposed between the stacked inner spacers 207. The Si layer 202 contacts the insulating film 210, the inner spacer 207, and the source region 208 or the drain region 209.

[0039] The Si layer 202 may have the same thickness as the inner spacer 207, as long as it is equal to or less than the thickness of the inner spacer 207. If the Si layer 202 and the inner spacer 207 have the same thickness, the recessed portion is not formed. Therefore, the gate insulating film 210 embedded in the recessed portion is not present. Then, only the Si layer 202 is disposed between the stacked inner spacers 207.

[0040] Furthermore, the source region 208 and the drain region 209 are not exposed because the Si layer 202 remains between the stacked layers of the inner spacer 207. Therefore, in the manufacturing process of the semiconductor device described later, damage to the source region 208 and the drain region 209 can be suppressed in the process of removing the Si layer 202, the process of removing the SiGe layer, the process of forming a gate electrode, etc.

[0041] In the second semiconductor element 200, the Si layer 202 and the metal layer 204 of the gate electrode 214 are formed at approximately the same height with respect to the upper surface of the substrate 11. In particular, the center of the height direction of the metal layer 204 of the gate electrode 214 and the center of the height direction of the Si layer 202 are located at approximately the same height. Furthermore, the Si layer 202 and the metal layer 204 of the second semiconductor element 200 are formed at approximately the same height with respect to the Si layer 102 of the first semiconductor element 100 with respect to the upper surface of the substrate 11. Therefore, the Si layer 202 is formed at approximately the same height with respect to the upper surface of the substrate 11, as are the gate electrode 214 of the second semiconductor element 200 and the Si layer 102 of the first semiconductor element 100. In particular, the center of the height direction of the Si layer 202, the center of the height direction of the metal layer 204 of the gate electrode 214, and the center of the height direction of the Si layer 102 are located at approximately the same height.

[0042] The Si layer 201 of the second semiconductor element 200 is formed at approximately the same height as the Si layer 101 of the first semiconductor element 100, with the upper surface of the substrate 11 as the reference. The Si layer 203 of the second semiconductor element 200 is formed at approximately the same height as the Si layer 103 of the first semiconductor element 100, with the upper surface of the substrate 11 as the reference.

[0043] Furthermore, the distance between the Si layer 101 and the Si layer 102 in the first semiconductor element 100 is approximately the same as the distance between the Si layer 102 and the Si layer 103. Similarly, the distance between the Si layer 201 and the Si layer 202 and the metal layer 204 in the second semiconductor element 200 is approximately the same as the distance between the Si layer 202 and the metal layer 204 and the Si layer 203. In contrast, in the first semiconductor element 100, the distance from the top surface of the substrate 11 to the Si layer 101 is greater than the distance between the Si layer 101 and the Si layer 102 and the distance between the Si layer 102 and the Si layer 103. Similarly, in the second semiconductor element 200, the distance from the top surface of the substrate 11 to the Si layer 201 is greater than the distance between the Si layer 201 and the Si layer 202 and the metal layer 204 and the Si layer 203.

[0044] Therefore, in the second semiconductor element 200, the region in which the gate electrode 214 formed between the Si layer 201 and the Si layer 203 and the gate insulating film 210 are formed is the same as the region in which the Si layer 102 and the gate electrodes 114 and 115 are formed in the first semiconductor element 100. Therefore, the gate electrode 214 and the gate insulating film 210 of the second semiconductor element 200 are formed in a region that is sufficiently wider than the gate electrodes 114 and 115 of the first semiconductor element 100.

[0045] Furthermore, in the first semiconductor element 100 and the second semiconductor element 200, the distance from the upper surface of the substrate 11 to the Si layer 101 and the Si layer 201 is larger than the distance between the Si layer 101, the Si layer 102, and the Si layer 103. Therefore, the gate electrode 113 of the first semiconductor element 100 and the gate electrode 213 of the second semiconductor element 200 are formed in a sufficiently larger area than the gate electrodes 114 and 115 of the first semiconductor element 100.

[0046] According to the above-described configuration, the second semiconductor element 200 has an area secured for forming a gate insulating film of sufficient thickness to withstand the high voltage applied to the second semiconductor element 200, which serves as an input / output device. This structure allows the second semiconductor element 200 to operate at a voltage higher than that of the first semiconductor element 100, which constitutes the logic device, while having the shape of a GAA-FET. This makes it possible to suppress a decrease in the reliability of the second semiconductor element 200.

[0047] Furthermore, in the first semiconductor element 100 and the second semiconductor element 200, the Si layers 101, 102, 103 and the Si layers 201, 202, 203 are formed to the same height. Therefore, the first semiconductor element 100 and the second semiconductor element 200 can share the same process for forming the Si layers 101, 102, 103 and the Si layers 201, 202, 203. As a result, variations in height between the Si layers 101, 102, 103 and the Si layers 201, 202, 203 can be suppressed. Furthermore, by sharing the same process for forming the Si layers 101, 102, 103 and the Si layers 201, 202, 203, it is possible to suppress the complexity of the manufacturing process and the increase in manufacturing costs.

[0048] 2. Manufacturing Method of Semiconductor Device Next, a manufacturing method of the semiconductor device 10 shown in FIGS. 1-5 will be described. Figures 6 to 37 show manufacturing process diagrams of the semiconductor device 10. In the manufacturing process diagrams of the semiconductor device 10 shown in Figures 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, and 36, the left side of the drawing (a) shows a cross-sectional view of the first semiconductor element 100 taken along line X1 (cross-sectional view in the gate length direction), and the right side of the drawing (b) shows a cross-sectional view of the second semiconductor element 200 taken along line X2 (cross-sectional view in the gate length direction). In addition, in the manufacturing process diagrams of the semiconductor device 10 shown in Figures 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, and 37, the left side of the drawing (a) shows a cross-sectional view of the first semiconductor element 100 taken along line Y1 (cross-sectional view in the gate width direction), and the right side of the drawing (b) shows a cross-sectional view of the second semiconductor element 200 taken along line Y2 (cross-sectional view in the gate width direction).

[0049] First, as shown in FIGS. 6 and 7 , a SiGe layer 12, a Si layer 13, a SiGe layer 14, and a Si layer 15 are stacked on a substrate 11. The SiGe layers 12, 14, and the Si layers 13, 15 are formed by epitaxial growth of Si and SiGe. The SiGe layer 12 is formed to a thickness of, for example, about 20-30 nm. The SiGe layer 14 is formed to a thickness of, for example, about 10-15 nm. The Si layers 13, 15 are formed to a thickness of, for example, about 5 nm. In this manner, the bottommost SiGe layer 12 is formed thicker than the upper SiGe layer 14. The SiGe layer 12 is preferably formed to a thickness that allows for the formation of a gate insulating film 210 and a metal layer 204 of sufficient thickness in the second semiconductor element 200 shown in FIG. 4 .

[0050] Next, as shown in FIGS. 8 and 9 , a resist layer 16 is patterned on the Si layer 15, excluding the region where the second semiconductor element 200 will be formed. The resist layer 16 is patterned, for example, by forming the resist layer 16 on the front surface, followed by exposure and development using a photomask with a predetermined pattern. Then, using the resist layer 16 as a mask, high-concentration ion implantation is performed on the Si layer 15 in the region where the second semiconductor element 200 will be formed. There is no particular restriction on the impurities used for ion implantation, and impurities such as B, P, As, and Ge can be used regardless of the conductivity type of the second semiconductor element 200. The Si layer 15 after ion implantation is then annealed and surface-treated to restore the crystallinity of the Si layer 15. This forms an impurity-implanted Si layer 15A in the region where the second semiconductor element 200 will be formed.

[0051] 10 and 11, a SiGe layer 17 and a Si layer 18 are stacked on the Si layers 15 and 15A. The SiGe layer 17 and the Si layer 18 are formed by epitaxial growth of Si and SiGe. The SiGe layer 17 is formed to a thickness of, for example, about 10-15 nm. The Si layer 18 is formed to a thickness of, for example, about 5 nm. This forms a stacked body consisting of the SiGe layer 12, the Si layer 13, the SiGe layer 14, the Si layers 15 and 15A, the SiGe layer 17, and the Si layer 18.

[0052] Next, an STI is formed in the substrate 11, and a dummy gate insulating film 19, a dummy gate 20, a hard mask 21, and sidewalls 106 and 206 are formed. Then, the stack of the SiGe layer 12, the Si layer 13, the SiGe layer 14, the Si layers 15 and 15A, the SiGe layer 17, and the Si layer 18 is etched using reactive ion etching (RIE) or the like. As a result, as shown in FIGS. 12 and 13 , independent Si / SiGe stacks (pillars) are formed in the first semiconductor element 100 and the second semiconductor element 200. Here, a stack of the SiGe layer 12, the Si layer 101, the SiGe layer 14, the Si layer 102, the SiGe layer 17, and the Si layer 103 is formed in the first semiconductor element 100. Furthermore, a stack of SiGe layer 12, Si layer 201, SiGe layer 14, Si layer 15A, SiGe layer 17, and Si layer 203 is formed on the second semiconductor element 200. Furthermore, inner spacers 107 and 207 are formed on the Si / SiGe stack. Then, an STI 42 embedded in the substrate 11 is formed between the region where the first semiconductor element 100 is formed and the region where the second semiconductor element 200 is formed. Then, an insulating layer 41 covering the entire substrate 11 is formed, and the insulating layer 41 is polished and planarized by CMP or the like to expose and planarize the upper surface of the hard mask 21. Furthermore, source regions 108 and 208 and drain regions 109 and 209 are formed on the side surfaces of the Si / SiGe stack. Each of these steps is performed by a conventionally known method. Through these processes, a Si / SiGe stack, a dummy gate insulating film 19, a dummy gate 20, a hard mask 21, sidewalls 106, 206, inner spacers 107, 207, source regions 108, 208, and drain regions 109, 209 are formed on the substrate 11 having the structure shown in FIGS. 12 and 13.

[0053] 14 and 15, the hard mask 21 and the dummy gate 20 are removed. The hard mask 21 is made of, for example, SiN. Therefore, the hard mask 21 is selectively etched using a chemical such as hydrogen fluoride, which can selectively wet etch SiN relative to SiO and Si. The dummy gate 20 is made of, for example, polysilicon (p-Si) or amorphous silicon (α-Si). Therefore, a method capable of selectively etching polysilicon (p-Si) or amorphous silicon (α-Si), such as plasma etching, is used.

[0054] Next, the entire surface of the substrate 11 is filled with a resist layer 22, and then the resist layer 22 is patterned so as to open only the region where the second semiconductor element 200 is to be formed, as shown in FIGS. 16 and 17 . Next, the SiGe layers 12, 14, and 17 of the second semiconductor element 200 shown in FIGS. 16 and 17 are selectively etched. The dummy gate insulating film 19 is also removed in this process. As a result, the interlayer spaces between the Si layers 201, 15A, and 203 of the second semiconductor element 200 are exposed, as shown in FIGS. 18 and 19 . The selective etching of the SiGe layers 12, 14, and 17 can be performed, for example, by dry etching using a mixed gas containing hydrogen fluoride and oxygen, or by wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0055] Next, as shown in FIGS. 20 and 21 , the impurity-implanted Si layer 15A is selectively removed. In this process, the Si layers 201 and 203 are wet-etched using tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (TMY), which can selectively remove the impurity-implanted Si layer 15A. This process leaves the Si layer 202 between the inner spacers 207 and in contact with the source region 208 or the drain region 209. Furthermore, in the process of selectively removing the Si layer 15A, the amount of the Si layer 202 remaining between the inner spacers 207 is adjusted by adjusting the conditions and time. When the Si layer 202 is completely removed, the source region 208 and the drain region 209 are exposed inside the device. In this case, the source region 208 and the drain region 209 may be damaged during the process of removing the Si layer 15A, which may degrade the characteristics of the semiconductor device. Furthermore, if subsequent manufacturing steps are performed with the source region 208 and the drain region 209 exposed, the source region 208 and the drain region 209 are likely to be damaged, and the characteristics of the semiconductor element are likely to deteriorate. For this reason, in the selective removal step of the Si layer 15A, it is preferable to leave at least a part of the Si layer 202 between the stacked layers of the inner spacer 207 so that the source region 208 and the drain region 209 are not exposed.

[0056] Next, after the resist layer 22 is peeled off, an insulating layer 23 is formed on the entire surface of the substrate 11 as shown in Fig. 22 and Fig. 23. The insulating layer 23 is made of, for example, SiO ２ The insulating layer 23 is formed by, for example, CVD or the like. The insulating layer 23 is a film that will become the gate insulating film 210 in the second semiconductor element 200 shown in FIGS. 4 and 5. For this reason, the insulating layer 23 is formed to a sufficient thickness so as to be able to withstand the high voltage applied to the second semiconductor element 200.

[0057] Next, the entire surface of the substrate 11 is filled with a resist layer 24, and then the resist layer 24 is patterned so as to open only the first semiconductor element 100, as shown in FIGS. 24 and 25. Then, as shown in FIGS. 26 and 27, the insulating layer 23 of the first semiconductor element 100 is selectively removed. In this process, the dummy gate insulating film 19 is also removed. This exposes the Si layer 103 of the first semiconductor element 100 and the inner walls of the sidewalls 106.

[0058] Next, the SiGe layers 12, 14, and 17 of the first semiconductor element 100 shown in Figures 26 and 27 are selectively etched. As a result, the interlayer spaces between the Si layers 101, 102, and 103 of the first semiconductor element 100 are exposed as shown in Figures 28 and 29. The selective etching of the SiGe layers 12, 14, and 17 is performed by, for example, dry etching using a mixed gas containing hydrogen fluoride and oxygen, or wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0059] 30 and 31, the resist layer 24 is removed to expose the second semiconductor element 200. Then, as shown in FIGS. 32 and 33, a high-dielectric-constant material layer 25 is formed on the entire surface of the substrate 11. The high-dielectric-constant material layer 25 is made of, for example, hafnium dioxide (HfO ２ The high dielectric constant material layer 25 is formed of, for example, hafnium oxynitride (HfON), etc. The high dielectric constant material layer 25 is formed by, for example, ALD (Atomic Layer Deposition) or the like.

[0060] Next, as shown in FIGS. 34 and 35 , a metal layer 26 is formed on the high-dielectric-constant material layer 25. The metal layer 26 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium (Nb), tungsten (W), or the like. The metal layer 26 is formed, for example, by CVD. Through this process, in the first semiconductor element 100, gate electrodes 113, 114, and 115 (see FIG. 2 ) made of the metal layer 104 are formed between the substrate 11 and the Si layers 101, 102, and 103, respectively, with the high-dielectric-constant material layer 105 interposed therebetween. In addition, in the second semiconductor element 200, gate electrodes 213 and 214 (see FIG. 2 ) made of the metal layer 204 are formed between the substrate 11 and the Si layers 201 and 203, respectively, with the high-dielectric-constant material layer 205 interposed therebetween.

[0061] Next, as shown in FIGS. 36 and 37 , the insulating layer 23, the high-dielectric-constant material layer 25, and the metal layer 26 above the insulating layer 41 are removed. Furthermore, the surfaces of the insulating layer 41, the insulating layer 23, the high-dielectric-constant material layer 25, and the metal layer 26 are planarized. Removal of the insulating layer 23, the high-dielectric-constant material layer 25, and the metal layer 26 is performed, for example, by CMP. As a result, a gate electrode 112 made of the high-dielectric-constant material layer 105 and the metal layer 104 is formed in the first semiconductor element 100. Furthermore, a gate electrode 212 made of the high-dielectric-constant material layer and the metal layer 204 is formed in the second semiconductor element 200. Furthermore, in the second semiconductor element 200, the insulating layer 23 with its surface planarized becomes the insulating film 210. Through the above steps, the semiconductor device 10 shown in FIGS. 2-5 can be manufactured, in which the first semiconductor element 100 and the second semiconductor element 200 are formed on the substrate 11.

[0062] In the above-described method for manufacturing the semiconductor device 10, epitaxial growth of the Si layer and the SiGe layer can be performed in common for the first semiconductor element 100 and the second semiconductor element 200. This facilitates control of the process for forming the Si / SiGe stack and the process for processing the Si / SiGe stack. Furthermore, since there is no significant difference in the thickness of the SiGe layer, the insulating layer can be easily formed on the wall surface when forming the inner spacers 107 and 207. Furthermore, after forming the source regions 108 and 208 and the drain regions 109 and 209, there is no oxidation process, which can cause device degradation. This prevents performance degradation of the semiconductor device.

[0063] [Modification of Manufacturing Method] Next, a modification of the manufacturing method of the semiconductor device 10 will be described. This modification of the manufacturing method is performed in the same manner as the manufacturing method of the semiconductor device described above, except that the ion implantation into the Si layer 15 ( FIGS. 8 and 9 ) and the removal of the Si layer 15A into which the impurities have been implanted ( FIGS. 20 and 21 ) are changed. Therefore, in the following description of the modification, only the step of implanting impurity ions into the Si layer 15 (ion implantation step) and the step of selectively removing the Si layer 15A into which the impurities have been implanted (selective removal step) will be described.

[0064] In a modified manufacturing method, first, in the ion implantation step shown in FIGS. 8 and 9 , a mask (not shown) is formed to cover the edge of the Si layer 15 in the region where the second semiconductor element 200 will be formed. Then, impurities are implanted only in the central portion of the Si layer 15 to form the Si layer 15A. Here, the edge of the Si layer 15 preferably refers to a region of the second semiconductor element 200 that is equal to or thinner than the inner spacer 207. That is, a mask is preferably formed in the region of the Si layer 202 that is to remain between the stacked inner spacers 207. Then, in the selective removal step of the Si layer 15A, only the central portion of the Si layer 15A into which the impurities have been implanted is selectively removed. As a result, the Si layer 202 remains between the layers of the inner spacer 207. Note that the Si layer 202 formed by this manufacturing method is made of Si that does not contain the implanted impurities.

[0065] In the above-described method for manufacturing the semiconductor device 10, the ion implantation process of impurities into the Si layer and the selective removal process of the impurity-implanted Si layer are performed on the second layer (middle layer) of three stacked Si layers. However, the Si layer to which the ion implantation process and the selective removal process are performed is not limited to the second layer. For example, if the semiconductor device has two stacked Si layers, the ion implantation process and the selective removal process may be performed on the first Si layer. Furthermore, in a configuration in which four or more Si layers are stacked, the ion implantation process and the selective removal process may be performed on every other Si layer. That is, the ion implantation process and the selective removal process may be performed on even-numbered Si layers or odd-numbered Si layers.

[0066] 3. Second Embodiment of Semiconductor Device Next, a second embodiment of the semiconductor device will be described. The semiconductor device of the second embodiment described below has a configuration similar to that of the semiconductor device of the first embodiment described above. Therefore, a description of the configuration similar to that of the semiconductor device of the first embodiment described above will be omitted.

[0067] [Semiconductor Device of Second Embodiment] Figures 38 and 39 show the configuration of a semiconductor device of a second embodiment. Figure 38 corresponds to a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 1 taken along line X1. Figure 39 corresponds to a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 1 taken along line X2. In the description of the second embodiment, the configurations of the cross-sectional view (cross-sectional view in the gate width direction) and the cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in Figure 1 will not be shown. Similar to Figures 38 and 39, the cross-sectional view in the gate width direction also has a configuration in which the first semiconductor element 100 and the second semiconductor element 200 shown in Figure 3 or Figure 5 are stacked.

[0068] In the semiconductor device of the second embodiment, a first semiconductor element 100A shown in FIG. 38 and a second semiconductor element 200A shown in FIG. 39 are formed on a common substrate 11. The first semiconductor element 100A shown in FIG. 38 has a third semiconductor element 100B and a fourth semiconductor element 100C, each having a configuration similar to that of the first semiconductor element 100 shown in FIG. 2 , stacked on the substrate 11. The first semiconductor element 100A has a fourth semiconductor element 100C formed on the third semiconductor element 100B. The first semiconductor element 100A also has an MDI (middle dielectric isolation) 130 formed on the third semiconductor element 100B. The fourth semiconductor element 100C is then provided on the MDI 130. The third semiconductor element 100B has inner spacers 107 formed as sidewalls of the gate electrode 112. Furthermore, the fourth semiconductor element 100C is formed on the MDI 130 rather than directly on the substrate 11.

[0069] The second semiconductor element 200A shown in FIG. 39 has a fifth semiconductor element 200B and a sixth semiconductor element 200C stacked on a substrate 11. The second semiconductor element 200A has a sixth semiconductor element 200C formed on the fifth semiconductor element 200B. The second semiconductor element 200A also has an MDI (middle dielectric isolation) 230 formed on the fifth semiconductor element 200B. The sixth semiconductor element 200C is then provided on the MDI 230. The fifth semiconductor element 200B has inner spacers 207 formed as sidewalls of the gate electrode 212. The sixth semiconductor element 200C is formed on the MDI 230, not directly on the substrate 11.

[0070] In the semiconductor device of the second embodiment, the third semiconductor element 100B and the fourth semiconductor element 100C of the first semiconductor element 100A may be any combination of PMOS and NMOS, PMOS and PMOS, or NMOS and NMOS. Similarly, the fifth semiconductor element 200B and the sixth semiconductor element 200C of the second semiconductor element 200A may be any combination of PMOS and NMOS, PMOS and PMOS, or NMOS and NMOS.

[0071] The semiconductor device of the second embodiment has the same effects as the semiconductor device of the first embodiment. Furthermore, the semiconductor device of the second embodiment does not include an additional SiGe layer with a different Ge concentration during epitaxial growth of the Si / SiGe stack. This makes it possible to realize a structure using a SASI (Self-Aligned Substrate Isolation) process, which utilizes the difference in etching rate of the SiGe layer due to the difference in Ge concentration, or a monolithic CFET (Monolithic Complementary Field Effect Transistor) using MDI.

[0072] [Manufacturing Method] Next, a method for manufacturing the semiconductor device of the second embodiment will be described. The semiconductor device of the second embodiment can be manufactured by repeating the same steps as the method for manufacturing the semiconductor device of the first embodiment and the modified example of the manufacturing method. Therefore, in the following description, only the main points of the method for manufacturing the semiconductor device of the second embodiment will be described.

[0073] First, referring to FIG. 40 , a process of ion implanting a high concentration of impurities into the Si layer 15 will be described. This process corresponds to the process shown in FIGS. 8-11 in the semiconductor device manufacturing method of the first embodiment. First, a SiGe layer 12, a Si layer 13, a SiGe layer 14, and a Si layer 15 are stacked on a substrate 11. Then, a resist layer 16 is patterned and formed on the Si layer 15, except for the region where the second semiconductor element 200A will be formed. Furthermore, using the resist layer 16 as a mask, the Si layer 15 in the region where the second semiconductor element 200A will be formed is subjected to high concentration ion implantation, annealing, and surface treatment, thereby forming an impurity-implanted Si layer 15A. Next, after peeling off the resist layer 16, a SiGe layer 17 and a Si layer 18 are stacked on the Si layers 15 and 15A. Furthermore, a SiGe layer 30, an MDI 31, a SiGe layer 32, a Si layer 33, a SiGe layer 34, and a Si layer 35 are stacked on the Si layer 18. A resist layer 36 is then patterned and formed on the Si layer 35, except for the region where the second semiconductor element 200A will be formed. Furthermore, using the resist layer 36 as a mask, the Si layer 35 in the region where the second semiconductor element 200A will be formed is subjected to high-concentration ion implantation, annealing, and surface treatment, forming an impurity-implanted Si layer 35A. Next, after peeling off the resist layer 36, a SiGe layer 37 and a Si layer 38 are stacked on the Si layers 15 and 15A.

[0074] Next, referring to FIG. 41 , the process of removing the impurity-implanted Si layers 15A and 35A will be described. This process corresponds to the processes shown in FIGS. 16-21 in the semiconductor device manufacturing method of the first embodiment described above. In particular, FIG. 41 corresponds to the process shown in FIGS. 20 and 21 . First, a resist layer 22 is patterned to open only the second semiconductor element 200A. Then, the SiGe layers 12, 14, 17, 30, 32, 34, and 37 of the second semiconductor element 200A are selectively etched to expose the spaces between the Si layers 201, 202, and 203 of the second semiconductor element 200A. Next, the impurity-implanted Si layers 15A and 35A are selectively removed. This process leaves the Si layer 202 between the stacked inner spacers 207 and in contact with the source region 208 or the drain region 209.

[0075] 40 and 41, the semiconductor device of the second embodiment can be manufactured by appropriately applying the steps shown in Figures 6 to 39 in the method for manufacturing the semiconductor device of the first embodiment described above. Furthermore, the method for manufacturing the semiconductor device of the second embodiment also provides the same effects as the method for manufacturing the semiconductor device of the first embodiment described above.

[0076] The present invention is not limited to the configurations described in the above-described embodiments, and various modifications and changes are possible without departing from the scope of the present invention.

[0077] 10 semiconductor device, 11 substrate, 112, 113, 114, 115, 212, 213, 214 gate electrode, 12, 14, 17, 30, 32, 34, 37 SiGe layer, 13, 15, 15A, 18, 33, 35, 35A, 38, 101, 102, 103, 201, 202, 203 Si layer, 16, 22, 24, 36 resist layer, 19 dummy gate insulating film, 20 dummy gate, 21 hard mask, 210 gate insulating film, 23, 41 insulating layer, 25, 105, 205 high dielectric constant material layer, 26, 104, 204 metal layer, 31, 130, 230 MDI, 42 STI, 100, 100A first semiconductor element, 100B Third semiconductor element, 100C Fourth semiconductor element, 106, 206, 216 Sidewall, 107, 207 Inner spacer, 108, 208 Source region, 109, 209 Drain region, 200, 200A Second semiconductor element, 200B Fifth semiconductor element, 200C Sixth semiconductor element

Claims

1. A semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, wherein the first semiconductor element includes: a first laminate including a first semiconductor layer and a first gate electrode covering the periphery of the first semiconductor layer in a cross section in the gate width direction of the first semiconductor element; a first gate insulating film interposed between the first semiconductor layer and the first gate electrode; a first source / drain region formed on a side surface in the gate length direction of the first laminate; and a first insulating layer formed between side surfaces of the first gate electrode and the first source / drain region disposed between layers of the first semiconductor layer. The second semiconductor element includes: a second laminate including a second semiconductor layer and a second gate electrode covering the periphery of the second semiconductor layer in a cross section in the gate width direction of the second semiconductor element; a second gate insulating film, thicker than the first gate insulating film, interposed between the second semiconductor layer and the second gate electrode; a second source / drain region formed on a side surface in the gate length direction of the second laminate; and a third semiconductor layer and a second insulating layer formed between side surfaces of the second gate electrode and the second source / drain region disposed between layers of the second semiconductor layer. Semiconductor device.

2. The semiconductor device according to claim 1, wherein in the second semiconductor element, the second insulating layer is separated in the stacking direction of the second laminate by the third semiconductor layer.

3. The semiconductor device according to claim 1, wherein in the second semiconductor element, a center in the height direction of the second gate electrode disposed between layers of the second semiconductor layer with reference to the upper surface of the substrate and a center in the height direction of the third semiconductor layer are formed at the same height.

4. The semiconductor device according to claim 1, wherein the first semiconductor element includes the first semiconductor layer at the same height as the third semiconductor layer of the second semiconductor element with reference to the upper surface of the substrate.

5. The semiconductor device according to claim 1, wherein in the second semiconductor element, a distance between the upper surface of the substrate and the lowermost second semiconductor layer is larger than a distance between the lowermost semiconductor layer and the third semiconductor layer.

6. The semiconductor device according to claim 1, wherein, in the first semiconductor element, the distance between the upper surface of the substrate and the lowermost first semiconductor layer is larger than the distance between the lowermost first semiconductor layer and the second first semiconductor layer.

7. The semiconductor device according to claim 1, wherein the first semiconductor element includes the first semiconductor layer at the same height as the second semiconductor layer of the second semiconductor element with reference to the upper surface of the substrate.

8. The semiconductor device according to claim 1, wherein the third semiconductor layer has a thickness in the plane direction of the substrate that is equal to or less than that of the second insulating layer.

9. The first semiconductor element includes a third semiconductor element and a fourth semiconductor element formed on the third semiconductor element. The two semiconductor elements have a stacked configuration including a fifth semiconductor element and a sixth semiconductor element formed on the fifth semiconductor element. The third semiconductor element and the fourth semiconductor element include a first stacked body, a first source / drain region, and a first insulating layer. In a cross-section of the first semiconductor element in the gate width direction, the first semiconductor element has a first gate electrode that covers the periphery of the first semiconductor layer. The fifth semiconductor element and the sixth semiconductor element include a second stacked body, a second source / drain region, a third semiconductor layer, and a second insulating layer. In a cross-section of the second semiconductor element in the gate width direction, the second semiconductor element has a second gate electrode that covers the periphery of the second semiconductor layer. The semiconductor device according to claim 1.

10. A method of manufacturing a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, the method including: forming a Si / SiGe stack by laminating a semiconductor layer and a SiGe layer in a formation region of the first semiconductor element and a formation region of the second semiconductor element; ion-implanting impurities into the semiconductor layer in the formation region of the second semiconductor element; forming an insulating layer on sidewalls of the SiGe layer; removing the SiGe layer in the formation region of the first semiconductor element; forming a first gate electrode through a first gate insulating film in the formation region of the first semiconductor element; removing the SiGe layer in the formation region of the second semiconductor element; removing the semiconductor layer into which impurities have been ion-implanted so that the semiconductor layer remains only between the insulating layers; forming a second gate insulating film thicker than the first gate insulating film in the formation region of the second semiconductor element; and forming a second gate electrode on the gate insulating film of the second semiconductor element.

Images