Solid-state imaging device, comparator, and electronic apparatus

Abstract

[Problem] To reduce noise in a comparator. [Solution] This solid-state imaging device comprises a light receiving element, a first amplification circuit, and a second amplification circuit. The first amplification circuit amplifies and outputs a difference between a reference signal and an input signal that is output from the light receiving element. The second amplifier circuit includes an amplification transistor that amplifies and outputs a first amplified signal output from the first amplification circuit. The second amplification circuit opens or short-circuits a first end and a second end of a first impedance element connected between the amplification transistor and a positive-side power supply line on the basis of an analog gain of the reference signal, whereby a logic threshold is controlled.

Description

Solid-state imaging device, comparator, and electronic device

[0001] The present disclosure relates to a solid-state imaging device, a comparator, and an electronic device.

[0002] Advances in semiconductor technology have led to the miniaturization and improved performance of sensors, and the resulting improvements in image sensor resolution and speed have been remarkable. These improvements in resolution and speed remain highly desired. In particular, image sensors often have bottlenecks due to the increasing performance of other functions. While high speed is desirable, issues remain in terms of circuit area and power consumption. Furthermore, maintaining image quality and even improving it have become paramount, leading to a growing demand for low noise.

[0003] While there has been extensive research into reducing the transconductance of a comparator's active load without increasing the bandwidth-limiting capacitance, such techniques involve, for example, adding a bypass current source to reduce the current flowing through the active load, thereby reducing the transconductance. Furthermore, while gain switching has been performed at the same level in both the current mirror and the downstream amplifier circuit that make up the comparator, this approach has the drawback of potentially increasing the circuit area.

[0004] Japanese Patent Publication No. 2020-113892

[0005] Therefore, one non-limiting problem to be solved by the embodiments of the present disclosure is to provide a low-noise comparator and an image sensor equipped with the comparator. The problem to be solved by the embodiments of the present disclosure can also be, as some further non-limiting examples, a problem corresponding to the effects described in the embodiments. In other words, a problem corresponding to at least one of the effects described in the description of the embodiments of the present disclosure can be the problem to be solved by the present disclosure.

[0006] According to one embodiment, a solid-state imaging device includes a light receiving element, a first amplifier circuit, and a second amplifier circuit. The first amplifier circuit amplifies and outputs the difference between a reference signal and an input signal output from the light receiving element. The second amplifier circuit includes an amplifier transistor that amplifies and outputs the first amplified signal output from the first amplifier circuit. The second amplifier circuit controls a logical threshold value based on the analog gain of the reference signal by opening or shorting a first terminal and a second terminal of a first impedance element connected between the amplifier transistor and a positive power supply line.

[0007] The first impedance element may be a transistor.

[0008] A variable bias voltage may be applied to a driving end of the first impedance element.

[0009] The device may further include a bias voltage generation circuit that generates the variable bias voltage, and the bias voltage generation circuit may include a second impedance element having the same characteristics as the first impedance element, and the second impedance element may be diode-connected and have a drive end connected to the drive end of the first impedance element.

[0010] The second amplifier circuit may short-circuit the first terminal and the second terminal of the first impedance element at the signal output timing when the analog gain of the reference signal is low gain, and may open the first terminal and the second terminal of the first impedance element at the signal output timing when the analog gain of the reference signal is high gain.

[0011] The second amplifier circuit may include a constant current source circuit connected between the amplifier transistor and a negative power supply line.

[0012] The second amplifier circuit may include a sample-and-hold circuit in a constant current source circuit connected between the amplifier transistor and a negative power supply line.

[0013] The first amplifier circuit may include a circuit at its input end for attenuating the Vsl signal in stages.

[0014] The first impedance element may be formed of a transistor having a variable ratio of channel width to channel length.

[0015] The first impedance element may include a plurality of transistors, and the ratio of the channel width to the channel length may be changed depending on whether the plurality of transistors are connected in parallel or in series.

[0016] The first impedance element may be a variable resistor.

[0017] According to one embodiment, a comparator includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit amplifies and outputs a difference between a reference signal and an input signal. The second amplifier circuit includes an amplifier transistor that amplifies and outputs a first amplified signal output by the first amplifier circuit. The second amplifier circuit controls a logic threshold by opening or shorting a first terminal and a second terminal of a first impedance element connected between the amplifier transistor and a positive power supply line based on the analog gain of the reference signal.

[0018] According to one embodiment, an electronic device includes a light receiving element, a first amplifier circuit, and a second amplifier circuit. The first amplifier circuit amplifies and outputs the difference between a reference signal and an input signal output from the light receiving element. The second amplifier circuit includes an amplifier transistor that amplifies and outputs the first amplified signal output from the first amplifier circuit. The second amplifier circuit controls a logic threshold by opening or shorting a first terminal and a second terminal of a first impedance element connected between the amplifier transistor and a positive power supply line based on the analog gain of the reference signal.

[0019] 1 is a block diagram schematically showing a solid-state imaging device according to an embodiment; FIG. 1 is a diagram schematically showing a semiconductor substrate on which a solid-state imaging device according to an embodiment is mounted; FIG. 2 is a diagram schematically showing a semiconductor substrate on which a solid-state imaging device according to an embodiment is mounted; FIG. 3 is a circuit diagram showing an example of a comparator according to an embodiment; FIG. 4 is a diagram showing an example of a timing chart according to an embodiment; FIG. 5 is a diagram showing an example of a timing chart according to an embodiment;

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0021] FIG. 1 is a diagram illustrating a portion of a solid-state imaging device (image sensor) according to an embodiment. The solid-state imaging device 1 includes at least a first driving circuit 10, a second driving circuit 12, a pixel array 14, an analog-to-digital converter (ADC 16), and a logic circuit 18. The solid-state imaging device 1 may be configured without some of these components, or may include other necessary components. The solid-state imaging device 1 may also include other components, such as an input / output interface for inputting and outputting signals and a memory circuit for temporarily or non-temporarily storing data.

[0022] The first drive circuit 10 is a circuit that selects which line of the pixel array 14 the pixels 140 belong to and which pixels 140 are to be driven.

[0023] The second drive circuit 12 is a circuit that controls which column of pixels 140 should be output from among the pixels 140 that belong to the line selected by the first drive circuit 10 provided in the pixel array 14. The solid-state imaging device 1 outputs from the pixels 140 that belong to the column specified by the second drive circuit 12 in the line selected and driven by the first drive circuit 10.

[0024] The pixel array 14 is an area in which pixels 140 are arranged. The pixels 140 are arranged in a two-dimensional array along the line direction and column direction within the pixel array 14. The pixel 140 includes a light receiving element, performs photoelectric conversion on light incident on the pixel 140, and outputs an analog signal based on the intensity of the incident light.

[0025] The ADC 16 is a circuit that converts the analog signal output from the pixel 140 into a digital signal and outputs the digital signal. The ADC 16 converts the analog signal into a digital signal by, for example, comparing the analog signal output from the pixel 140 with a ramp signal that is a reference signal, and counting the time from when the ramp signal starts to be output to when the signal resulting from the comparison is inverted.

[0026] The digital signal generated by the ADC 16 is output to the logic circuit 18. The logic circuit 18 performs various processes on the digital signal and outputs it as image data. The logic circuit 18 can perform, for example, color adjustment, signal processing, image processing, and optionally machine learning processing to generate image data or perform recognition processing.

[0027] 2 is a diagram showing an example of the arrangement of a pixel array 14 and an ADC 16 according to an embodiment. The solid-state imaging device 1 may be formed as a stacked semiconductor substrate 2. As an example, the solid-state imaging device 1 is mounted on a semiconductor substrate 2 in which a first substrate 20 and a second substrate 22 are stacked. Note that a stacked structure of three or more layers is not excluded. For example, a separate layer may be stacked and formed for a memory circuit.

[0028] These substrates may be stacked by any method, such as CoC (Chip on Chip), CoW (Chip on Wafer), WoW (Wafer on Wafer), etc. Furthermore, connections between layers can be realized by any method, such as via holes, micro-dumps, etc.

[0029] The first substrate 20 includes at least a pixel array 14. The pixel array 14 outputs a signal based on the intensity of a signal photoelectrically converted by a light receiving element to a signal line provided for each column, and the analog signal is transmitted to the second substrate 22 via the signal line provided for each column.

[0030] The second substrate 22 includes at least the ADC 16. The ADC 16 may include a column ADC 160 for each signal line of each column in the pixel array 14. Note that one column ADC 160 may be provided for multiple columns, or multiple column ADCs 160 may be provided for one column.

[0031] The column ADC 160 converts analog signals output from the pixels 140 belonging to the column into digital signals and outputs them, and image data is formed in the subsequent logic circuit.

[0032] 3 is a diagram showing another example of the arrangement of a pixel array 14 and an ADC 16 according to an embodiment. The solid-state imaging device 1 is formed as a semiconductor substrate 2 in which a first substrate 20 and a second substrate 22 are stacked, similar to FIG.

[0033] 3, the ADC 16 is configured to include a pixel ADC 162 provided for each pixel 140. The pixel ADC 162 converts the analog signal output from the corresponding pixel 140 into a digital signal and outputs the digital signal.

[0034] Although the above example illustrates a case where a column ADC and a pixel ADC are provided, the configuration of the solid-state imaging device 1 in the present disclosure is not limited to this. For example, the solid-state imaging device 1 may be configured such that the pixel array 14 is divided into a plurality of areas and an area ADC is provided for each of these divided areas, or may be configured such that an ADC processes output from any number of pixels 140.

[0035] Next, a few non-limiting examples of comparators that achieve low noise according to the present disclosure will be described.

[0036] (First embodiment)

[0037] 4 is a diagram illustrating an example of a comparator 3 according to an embodiment. The comparator 3 includes a first amplifier circuit 30 and a second amplifier circuit 32. The comparator 3 is a circuit that compares a ramp signal Vramp, which is a reference signal, with an input signal Vsl from a light receiving element, and outputs the result at an appropriate timing.

[0038] As shown in the figure, for example, the ramp signal Vramp is applied to the gate of a p-type MOSFET and then applied to the gate of transistor Md1 of the first amplifier circuit 30 via the drain of a diode-connected n-type MOSFET that shares a source with the p-type MOSFET. The drain of this n-type MOSFET may be connected to the positive power supply line via a constant current source.

[0039] The first amplifier circuit 30 includes, for example, transistors Md1 and Md2 that form an input pair and transistors Ma1 and Ma2 that form a current mirror. The transistors Md1 and Md2 are, for example, n-type MOSFETs that share a common source and are connected to the negative power supply line via a current source. A signal related to a reference signal, which is a ramp signal, is input to the gate of the transistor Md1, and an input signal Vsl from the light receiving element is input to the gate of the transistor Md2.

[0040] At the reference signal input stage, a constant current source may be connected between the positive power supply voltage and the reference signal, as shown in the figure. A capacitor C1 may be provided to appropriately store the offset voltage from the light receiving element and suppress high-frequency components.

[0041] Transistors Ma1 and Ma2 are p-type MOSFETs that share a gate. The source of transistor Ma1 is connected to the positive power supply line and the drain is connected to the drain of transistor Md1. The source of transistor Ma2 is connected to the positive power supply line and the drain is connected to the drain of transistor Md2.

[0042] The first amplifier circuit 30 compares the input signals and outputs a current based on the comparison result from the drains of the transistors Ma2 and Md2. The drain of the transistor Ma2 is connected to the switch XAZ1. The switch XAZ1 is turned on when the signal is output and turned off when initialization is performed.

[0043] The drain of this transistor Ma2 is also connected between the gate of the transistor Md2 and the capacitor C1 via a switch AZ1 that is turned off at the signal output timing and turned on at the initialization timing.

[0044] The first amplifier circuit 30 outputs a signal from the drain of the transistor Ma1 via the switch AZ1. The switch AZ1 is a switch that turns off when a signal is output and turns on when initialization is performed. The switches AZ1 and XAZ1 are exclusively turned on so that they are never turned on at the same time.

[0045] The first amplifier circuit 30 outputs the comparison result between the ramp signal and the input signal from the drains of the transistors Ma2 and Md2 via the switch XAZ1 to the second amplifier circuit 32. This comparison result may be charged via the switch AZ to a capacitor C2 provided between the drain of the transistor Ma2 and the positive power supply voltage.

[0046] The second amplifier circuit 32 is formed, for example, with a transistor Ma3 and a transistor Md3.

[0047] The transistor Ma3 is, for example, a p-type MOSFET, and receives the output from the first amplifier circuit 30 at its gate and outputs a signal Vout obtained by amplifying the comparison result from its drain. The drain of the transistor Ma3 may be connected to the negative power supply line via a constant current source.

[0048] The transistor Md3 is, for example, an n-type MOSFET, and its source is connected to the source of the transistor Ma3, and its drain is connected to the positive power supply line. The switch EN is connected between the drain and source of the transistor Md3, and opens or shorts the drain-source of the transistor Md3 depending on the timing.

[0049] A variable bias voltage Vbias is applied to the gate of transistor Md3 via switch SH. This gate may be connected to the positive power supply line via capacitor C3 to charge the bias voltage Vbias.

[0050] This first amplifier circuit 30 can be used in various solid-state imaging devices or electronic devices.

[0051] FIG. 5 is a diagram showing an example of a timing chart when the ramp signal of the circuit in FIG. 4 has a low gain.

[0052] First, before the ramp signal and input signal are applied to the first amplifier circuit 30, the circuit is initialized. During initialization, the switches AZ, AZ1, EN, and SH are turned on, discharging the potentials charged in the respective capacitors to the reference potential. At this timing, the switch XAZ1 is turned off.

[0053] Before the input of the ramp signal starts, the switches AZ, AZ1, and SH are turned off.

[0054] Since the switch EN is on, the drain and source of the transistor Md3 remain shorted, i.e., the source of the transistor Ma3 is connected to the positive power supply line, and the potential of this source is set to the positive power supply voltage Vdd.

[0055] When the ramp signal has a low gain, the accuracy of the signal can be improved by making the amplitude of the signal sufficiently large in this way.

[0056] The switch EN may be turned on until application of the ramp signal, that is, until output of the comparison result of the input signal is completed, and then turned off before the next initialization.

[0057] FIG. 6 is a diagram showing an example of a timing chart when the ramp signal of the circuit in FIG. 4 has a high gain.

[0058] Unlike in Figure 5, after the initialization of the first amplifier circuit 30 is completed, the switch EN is turned off. By turning off the switch EN, the drain-source of transistor Md3 is opened, and the source voltage of transistor Md3 is applied to the source of transistor Ma3. Because a bias voltage Vbias is applied to the gate of transistor Md3, a voltage based on this bias voltage Vbias, the threshold voltage of transistor Md3, and the current flowing through transistor Md3 becomes the voltage applied to the source of transistor Ma3.

[0059] As a result, the potential of the source of transistor Ma3 becomes lower than when the gain is low. Because the potential of the source of transistor Ma3 is lowered, the logic threshold for the signal applied to the gate of transistor Ma3 becomes higher than when the gain is low. The logic threshold here represents the absolute value of the difference between the gate voltage of transistor Ma3 and the positive power supply voltage Vdd when the output of the second amplifier circuit 32 is inverted.

[0060] At high gains, the amplitude of the ramp signal becomes small, so even if the logical threshold value of the input of the second amplifier circuit 32 is increased, it is possible to design the circuit appropriately so that the MOSFET of the transistor Md2 to which the input signal is applied does not enter the linear region before the output of the first amplifier circuit 30 reaches the input of the second amplifier circuit 32.

[0061] Thus, according to this embodiment, when the analog gain of the ramp signal is low, the drain and source of transistor Md3 are shorted at the signal output timing, and when the analog gain is high, the drain and source of transistor Md3 are open at the signal output timing. Here, the signal output timing refers to the timing that includes both the reset phase and data phase in the comparison and amplification of the ramp signal, which is a reference signal, with the input signal.

[0062] By performing this operation, the comparator 3 according to this embodiment does not increase the logical threshold value of the transistor Ma3 at low gains, but can increase the logical threshold value of the transistor Ma3 at high gains. As a result, by appropriately controlling the bandwidth of the signal output by the first amplifier circuit 30, it is possible to output a signal in which the effects of noise are suppressed even at high gains.

[0063] For example, the timing at which the output signal of the second amplifier circuit 32 inverts is influenced by the signal output by the first amplifier circuit 30. By using the above operation, it is possible to lengthen the time until the output signal of the second amplifier circuit 32 inverts, thereby lengthening the time at which the output of the first amplifier circuit 30 is output, and by taking a moving average in the time direction, it is possible to further average out noise and reduce the influence of noise on the output signal.

[0064] In both low gain and high gain modes, the switch EN is turned on at the initialization timing because a current mirror is formed between the load (transistor Ma1) of the first amplifier circuit 30 and the input (transistor Ma3) of the second amplifier circuit 32, and by passing a desired current through the second amplifier circuit 32, the same current is also passed through the current source on the load side of the second amplifier circuit 32. For example, as will be described later, when the current source on the load side is equipped with a sample-and-hold circuit formed by an n-type MOSFET, this operation can initialize the potential of this n-type MOSFET.

[0065] (Second embodiment)

[0066] Each of the embodiments described below can be implemented in combination with the first embodiment described above and the embodiments described below, as long as no contradictions are present.

[0067] 7 is a circuit diagram showing an example of a comparator according to an embodiment. The second amplifier circuit 32 may include a sample-and-hold circuit having a switch AZ2, a transistor Md4, and a capacitor C4 as a current source connected to the drain of the transistor Ma3.

[0068] For example, switch AZ2 can be turned on and off at the same timing as switch AZ1, etc., which indicate the timing of initialization in Figures 5 and 6. As another example, switch AZ2 can be turned off earlier than switch AZ1.

[0069] When switch AZ2 is turned on, an appropriate potential is set at the gate of transistor Md4 by capacitor C4, and this potential is maintained when switch AZ2 is turned off.

[0070] In this way, the second amplifier circuit 32 can also use a sample-and-hold circuit as a constant current source. By forming a current source using a sample-and-hold circuit, mismatch with the current of the first amplifier circuit 30 can be suppressed, and a more desirable current can be supplied from the drain of the transistor Ma3.

[0071] (Third embodiment)

[0072] 8 is a circuit diagram showing an example of a comparator according to an embodiment. As shown in this figure, the input stage of the first amplifier circuit 30 for the input signal Vsl may be configured to be controlled by multiple switches and multiple capacitors.

[0073] The switches connected to each capacitor selectively connect one terminal of the capacitor to either the input signal Vsl or the negative voltage Vss depending on the dynamic range of the input signal Vsl. This control allows the voltage change between the reset phase and data phase of the input signal Vsl to be attenuated before it is applied to the gate of transistor Md2.

[0074] In this way, the comparator 3 may also include a circuit that attenuates the input signal Vsl in stages at the input terminal of the first amplifier circuit 30.

[0075] According to this embodiment, by connecting a part of the initialization capacitance between the differential pair gate on the input signal side and the input signal Vsl to a negative power supply, for example, the ground voltage, the input signal Vsl can be attenuated by capacitive voltage division. As a result, even when the dynamic range of the input signal Vsl is wide, AD conversion of large signals can be achieved without saturating them.

[0076] The number of divisions into each capacitance and the method of connecting the switches do not have to be as shown in the drawings, and any configuration that can achieve similar operations may be used.

[0077] (Fourth embodiment)

[0078] 9 is a diagram illustrating an example of a comparator according to an embodiment. The second amplifier circuit 32 may include a clamp circuit at the input terminal of the bias voltage Vbias. In addition to the configurations of the above-described embodiments, the second amplifier circuit 32 may further include transistors Md5 and Md6 and a switch EN1.

[0079] The switch EN1 is a switch that turns on and off in synchronization with the switch EN.

[0080] The transistor Md5 is, for example, an n-type MOSFET, with a bias voltage Vbias applied to its gate, its drain connected to the positive power supply line, and its source connected to the positive power supply line via the switch EN1.

[0081] Transistor Md6 is, for example, an n-type MOSFET, and its gate is connected to the drain of transistor Ma3, i.e., the output terminal of the second amplifier circuit 32, its drain is connected to the source of transistor Md5, and its source is connected to the gate of transistor Ma3, i.e., the output terminal of the first amplifier circuit 30.

[0082] Transistor Md5 operates in the same manner as transistor Md3 at low and high gains, depending on switch EN1. Transistor Md6 has its drain connected to the positive power supply voltage either via transistor Md5 or not, so it appropriately controls the gate potential of transistor Ma3 in response to the signal output from second amplifier circuit 32.

[0083] If the potential continues to drop and the differential pair stops operating after the output signal of the second amplifier circuit 32 is inverted, the inversion of the output of the second amplifier circuit 32 itself is controlled normally, but current fluctuations may cause interference between columns. Even in such a case, the second amplifier circuit 32 of this embodiment can control the output of the first amplifier circuit 30 by using the transistor Md6 so that it does not fall below a predetermined value.

[0084] That is, the transistor Md5 in this configuration is not an essential component, and it is sufficient that the configuration includes at least the transistor Md6.

[0085] On the other hand, by including transistor Md5, it is possible to link the clamp voltage by transistor Md6 when the logical threshold value of transistor Ma3 is changed, and therefore, by including transistor Md5, it is possible to more appropriately control the clamp performance of transistor Md6 for the output signal of the first amplifier circuit 30 according to the output.

[0086] (Fifth embodiment)

[0087] 10 is a diagram showing an example of a desirable bias voltage generating circuit in the second amplifier circuit 32 of this embodiment. The bias voltage generating circuit 34 according to this embodiment is also effective when combined with other embodiments.

[0088] The bias voltage generation circuit 34 includes, for example, transistors Ma4 and Ma5, a transistor Md7, a variable resistor R1, and a capacitor C5. The capacitor C5 has a capacitance for maintaining the potential of the bias voltage Vbias and is connected between the output terminal of the bias voltage generation circuit 34 and the positive power supply line.

[0089] The transistors Ma4 and Ma5 are, for example, p-type MOSFETs, and form a current mirror. The source of the transistor Ma4 is connected to the positive power supply line, and the drain is connected to the negative power supply line via a constant current source. The source of the transistor Ma5 is connected to the positive power supply line, and the drain is connected to the negative power supply line via the transistor Md7 and a constant current source.

[0090] This current mirror causes transistor Ma5 to output a current proportional to the current from the constant current source connected from its drain to transistor Ma4.

[0091] Transistor Md7 is, for example, an n-type MOSFET, whose drain is connected to the drain of transistor Ma5, whose source is connected to the positive power supply line via variable resistor R1, and whose source is also connected to the negative power supply line via a constant current source.

[0092] This transistor Md7 is preferably a transistor having the same characteristics as the transistor Md3, which makes it possible to cancel fluctuations in the output of the transistor Md3 due to temperature changes and the like.

[0093] However, this is not essential, and it is also possible to provide an appropriate impedance element to control the potential of the drain of the transistor Ma5 instead of the transistor Md7.

[0094] Since the output of the first amplifier circuit 30 is based on the positive voltage Vdd of the power supply line, the voltage output by the bias voltage generation circuit 34 can be generated using this power supply voltage, thereby enabling control without reducing the power supply noise rejection rate. For this reason, it is desirable that the bias voltage generation circuit 34 be a circuit that uses the same power supply voltage as the first amplifier circuit 30, as shown in FIG.

[0095] This bias voltage generating circuit 34 can appropriately cancel out temperature and process dependency without reducing the power supply noise rejection rate.

[0096] The output bias voltage Vbias can be controlled by adjusting the source voltage of transistor Md7 via the voltage drop across variable resistor R1. Therefore, by appropriately selecting the resistance value of variable resistor R1, it is possible to appropriately control the bias voltage Vbias.

[0097] (Sixth embodiment)

[0098] 11 is a diagram showing an example of the comparator 3 according to this embodiment. The capacitor C2 of the second amplifier circuit 32 may be connected to the output terminal side of the first amplifier circuit 30 of the switch XAZ1.

[0099] This embodiment also provides the same effects as the above-described embodiments.

[0100] (Seventh embodiment)

[0101] 12 is a diagram illustrating an example of a comparator 3 according to an embodiment. As shown in this diagram, the transistor Md3 can be replaced with another impedance element, such as a variable resistor R2. In this case, too, the logic threshold of the transistor Ma3 can be appropriately controlled by adjusting the resistance value.

[0102] By using the variable resistor R2 as the impedance element instead of the transistor Ma3, it is not necessary to generate and supply a bias voltage.

[0103] Furthermore, instead of resistors, it is possible to use diodes, diode-connected transistors (n-type MOSFETs or p-type MOSFETs), or other elements as impedance elements. These replacements can be selected arbitrarily depending on the accuracy of the logic threshold setting and the degree of freedom in layout.

[0104] (Eighth embodiment)

[0105] 13 is a diagram illustrating an example of a comparator 3 according to an embodiment. As shown in this diagram, the second amplifier circuit 32 may be configured to include a transistor Ma6 that can be connected in parallel or series with the transistor Ma3.

[0106] Transistor Ma6 is, for example, a p-type MOSFET, whose gate is connected to the gate of transistor Ma3, whose second terminal (the lower terminal in the figure) is connected to the positive power supply line via switch Sw1, and whose first terminal (the upper terminal in the figure) is connected to the drain of transistor Ma3 via switch Sw2 and to the positive power supply line via switch Sw3.

[0107] Switches Sw1 and Sw2 are turned on and off synchronously. Switch Sw3 operates exclusively with at least switches Sw1 and Sw2 so that their on-timings do not overlap. Switch switching controls the ratio of the channel width to the channel length of the amplifying transistor, which is the output transistor of the second amplifier circuit 32.

[0108] At low gain, by turning on switches Sw1 and Sw2 and turning off switch Sw3, transistors Ma3 and Ma6 are connected in parallel between the positive power supply line and the output terminal of second amplifier circuit 32. As a result, at low gain, the output transistor formed by transistors Ma3 and Ma6 is virtually connected in the channel width direction, increasing the channel width / channel length ratio.

[0109] At high gain, by turning off the switches Sw1 and Sw2 and turning on the switch Sw3, the transistors Ma3 and Ma6 are connected in series between the positive power supply line and the output terminal of the second amplifier circuit 32. As a result, at high gain, the output transistor formed by the transistors Ma3 and Ma6 is virtually connected in the channel length direction, lowering the channel width / channel length ratio.

[0110] As a result, it is possible to control the output transistor (amplifying transistor) of the second amplifier circuit 32 so that the overdrive voltage is low when the gain is low, and to narrow the noise bandwidth and reduce thermal noise when the gain is high. As described above, in this embodiment as well, it is possible to appropriately suppress noise when the gain is high, similar to the previous embodiments.

[0111] (Ninth embodiment)

[0112] 14 is a diagram showing an example of a comparator 3 according to an embodiment. As shown in this diagram, a variable resistor R3 can be used instead of the n-type MOSFET on the input side of the ramp signal, which is a reference signal.

[0113] By using a variable resistor instead of an n-type MOSFET in the input stage of the reference signal, it becomes possible to easily control the voltage of the reference signal output.

[0114] It is also possible to omit this n-type MOSFET or variable resistor R3. The reference signal is controlled by a p-type MOSFET in the input stage. In this case, the ramp signal may be directly controlled by the circuit that outputs the ramp signal as the reference signal. This eliminates the need for additional elements in the column, allowing for greater flexibility in layout.

[0115] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0116] 15 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 15, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0117] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 15 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. Other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0118] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0119] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0120] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0121] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0122] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a time-of-flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0123] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.

[0124] 16 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 installed on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0125] 16 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0126] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0127] Returning to FIG. 15 , the explanation continues. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or text on the road surface. Based on the received information, the outside-vehicle information detection unit 7400 may also perform environment recognition processing for recognizing rainfall, fog, road conditions, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle.

[0128] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0129] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the driver's state is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0130] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 may be implemented by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger using the input unit 7800 and outputs the input signal to the integrated control unit 7600. Passengers and the like operate this input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0131] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0132] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as a wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal located near the vehicle (e.g., a terminal of a driver, pedestrian, or store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0133] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in vehicles. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE 802.11p and an upper layer IEEE 1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0134] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0135] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0136] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle device I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0137] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0138] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0139] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0140] The audio / image output unit 7670 transmits at least one audio and / or image output signal to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 15 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may also be other devices, such as headphones, a wearable device such as a glasses-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals, such as reproduced audio data or acoustic data, into analog signals and audibly outputs the analog signals.

[0141] In the example shown in FIG. 15 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In the above description, some or all of the functions performed by one control unit may be performed by another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0142] A computer program for realizing each function of the solid-state imaging device 1 according to this embodiment described with reference to FIG. 1 can be implemented in any control unit or the like. A computer-readable recording medium storing such a computer program can also be provided. The recording medium can be, for example, a magnetic disk, an optical disk, a magneto-optical disk, or a flash memory. The computer program may also be distributed, for example, via a network, without using a recording medium.

[0143] In the vehicle control system 7000 described above, the solid-state imaging device 1 according to this embodiment described using FIG. 1 can be applied to at least one of the imaging unit 7410, the outside vehicle information detection unit 7420, or the driver state detection unit 7430 of the application example shown in FIG. 15.

[0144] Furthermore, at least some of the components of the solid-state imaging device 1 described with reference to Fig. 1 may be implemented in a module (for example, an integrated circuit module configured on a single die) for the integrated control unit 7600 shown in Fig. 15. Alternatively, the solid-state imaging device 1 described with reference to Fig. 1 may be implemented by a plurality of control units of the vehicle control system 7000 shown in Fig. 15.

[0145] The above-described embodiment may be modified as follows.

[0146] (1) A solid-state imaging device comprising: a light receiving element; a first amplifier circuit that amplifies and outputs the difference between a reference signal and an input signal output from the light receiving element; and a second amplifier circuit that includes an amplifier transistor that amplifies and outputs the first amplified signal output from the first amplifier circuit, wherein the second amplifier circuit controls a logical threshold value by opening or shorting a first end and a second end of a first impedance element connected between the amplifier transistor and a positive power supply line based on the analog gain of the reference signal.

[0147] (2) The solid-state imaging device according to (1), wherein the first impedance element is a transistor.

[0148] (3) The solid-state imaging device according to (2), wherein a variable bias voltage is applied to a driving end of the first impedance element.

[0149] (4) The solid-state imaging device according to (3), further comprising: a bias voltage generation circuit that generates the variable bias voltage; the bias voltage generation circuit comprising a second impedance element having the same characteristics as the first impedance element; the second impedance element being diode-connected and having a drive end connected to a drive end of the first impedance element.

[0150] (5) A solid-state imaging device according to any one of (1) to (4), wherein the second amplifier circuit shorts the first terminal and the second terminal of the first impedance element at the signal output timing when the analog gain of the reference signal is low gain, and opens the first terminal and the second terminal of the first impedance element at the signal output timing when the analog gain of the reference signal is high gain.

[0151] (6) The solid-state imaging device according to any one of (1) to (5), wherein the second amplifier circuit includes a constant current source circuit connected between the amplifier transistor and a negative power supply line.

[0152] (7) The solid-state imaging device according to any one of (1) to (5), wherein the second amplifier circuit includes a sample-and-hold circuit in a constant current source circuit connected between the amplifier transistor and a negative power supply line.

[0153] (8) The solid-state imaging device according to any one of (1) to (7), wherein the first amplifier circuit includes, at an input terminal thereof, a circuit for attenuating a Vsl signal in stages.

[0154] (9) The solid-state imaging device according to any one of (2) to (4), wherein the first impedance element is formed of a transistor in which the ratio of the channel width to the channel length can be changed.

[0155] (10) The solid-state imaging device according to (9), wherein the first impedance element includes a plurality of transistors, and the ratio of the channel width to the channel length is changed depending on whether the plurality of transistors are connected in parallel or in series.

[0156] (11) The solid-state imaging device according to any one of (1) to (7), wherein the first impedance element is a variable resistor.

[0157] (12) A comparator comprising: a first amplifier circuit that amplifies and outputs a difference between a reference signal and an input signal; and a second amplifier circuit that includes an amplifier transistor that amplifies and outputs a first amplified signal output by the first amplifier circuit, wherein the second amplifier circuit controls a logic threshold by opening or shorting a first terminal and a second terminal of a first impedance element connected between the amplifier transistor and a positive power supply line based on an analog gain of the reference signal. At least one of the first amplifier circuit and the second amplifier circuit may have a configuration similar to that of (1) to (11).

[0158] (13) An electronic device comprising: a light receiving element; a first amplifier circuit that amplifies and outputs the difference between a reference signal and an input signal output from the light receiving element; and a second amplifier circuit that includes an amplifier transistor that amplifies and outputs the first amplified signal output from the first amplifier circuit, wherein the second amplifier circuit controls a logic threshold by opening or shorting a first end and a second end of a first impedance element connected between the amplifier transistor and a positive power supply line based on the analog gain of the reference signal. At least one of the first amplifier circuit and the second amplifier circuit can have a configuration similar to that of (1) to (11).

[0159] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0160] 1: solid-state imaging device, 10: first drive circuit, 12: second drive circuit, 14: pixel array, 140: pixel, 16: ADC, 160: column ADC, 162: pixel ADC, 18: logic circuit, 2: semiconductor substrate, 20: first substrate, 22: second substrate, 3: comparator, 30: first amplifier circuit, 32: second amplifier circuit, 34: bias voltage generation circuit, Ma1, Ma2, Ma3, Ma4, Ma5, Ma6: transistors, Md1, Md2, Md3, Md4, Md5, Md6, Md7: transistors, C1, C2, C3, C4, C5: capacitors, R1, R2, R3: variable resistors

Claims

1. A solid-state imaging device comprising: a light-receiving element; a first amplification circuit that amplifies and outputs a difference between a reference signal and an input signal output from the light-receiving element; and a second amplification circuit including an amplification transistor that amplifies and outputs a first amplified signal output from the first amplification circuit, wherein the second amplification circuit controls a logic threshold value by releasing or short-circuiting a first end and a second end of a first impedance element connected between the amplification transistor and a positive power supply line based on an analog gain of the reference signal.

2. The solid-state imaging device according to claim 1, wherein the first impedance element is a transistor.

3. The solid-state imaging device according to claim 2, wherein a variable bias voltage is applied to a driving end of the first impedance element.

4. The solid-state imaging device according to claim 3, further comprising a bias voltage generation circuit that generates the variable bias voltage, wherein the bias voltage generation circuit includes a second impedance element having the same characteristics as the first impedance element, and the second impedance element is diode-connected and a driving end thereof is connected to the driving end of the first impedance element.

5. The solid-state imaging device according to claim 1, wherein the second amplification circuit short-circuits the first end and the second end of the first impedance element at a signal output timing when the analog gain of the reference signal is a low gain, and releases the first end and the second end of the first impedance element at the signal output timing when the analog gain of the reference signal is a high gain.

6. The solid-state imaging device according to claim 1, wherein the second amplification circuit includes a constant current source circuit connected between the amplification transistor and a negative power supply line.

7. The solid-state imaging device according to claim 1, wherein the second amplification circuit includes a sample-and-hold circuit in a constant current source circuit connected between the amplification transistor and a negative power supply line.

8. The solid-state imaging device according to claim 1, wherein the first amplification circuit includes a circuit that stepwise attenuates a Vsl signal at an input end.

9. The solid-state imaging device according to claim 2, wherein the first impedance element is formed of a transistor whose channel width to channel length ratio can be changed.

10. The first impedance element includes a plurality of transistors, and changes the ratio of the channel width to the channel length depending on whether the connection of the plurality of transistors is a parallel connection or a serial connection. The solid-state imaging device according to claim 9.

11. The first impedance element is a variable resistor. The solid-state imaging device according to claim 1.

12. A first amplifier circuit that amplifies and outputs the difference between a reference signal and an input signal, and a second amplifier circuit that includes an amplification transistor that amplifies and outputs the first amplified signal output by the first amplifier circuit. The second amplifier circuit controls the logic threshold value by releasing or short-circuiting the first end and the second end of a first impedance element connected between the amplification transistor and the positive power supply line based on the analog gain of the reference signal. Comparator.

13. A light receiving element, a first amplifier circuit that amplifies and outputs the difference between a reference signal and an input signal output from the light receiving element, and a second amplifier circuit that includes an amplification transistor that amplifies and outputs the first amplified signal output by the first amplifier circuit. The second amplifier circuit controls the logic threshold value by releasing or short-circuiting the first end and the second end of a first impedance element connected between the amplification transistor and the positive power supply line based on the analog gain of the reference signal. Electronic equipment.

Images