Polar digital transmitter with doherty power combination and fir-filter functionality

Abstract

A digital amplifier, comprising a first amplifier core, comprising a first amplification portion, configured to amplify a first signal according to a first subset of control codes; a second amplification portion, configured to amplify a second signal according to a second subset of control codes, wherein the second signal is an inverse of the first signal; a second amplifier core, comprising: a third amplification portion, configured to amplify a third signal according to the second subset of control codes, wherein the third signal is a delayed first signal; a fourth amplification portion, configured to amplify a fourth signal according to the first subset of control codes, wherein the fourth signal is an inverse of the third signal.

Description

POLAR DIGITAL TRANSMITTER WITH DOHERTY POWER COMBINATIONAND FIR-FILTER FUNCTIONALITYTechnical Field

[0001] Various aspects of this disclosure generally relate to a digital transmitter, exhibiting Doherty power combination and finite impulse response functionality.Background

[0002] Digital transmitters may generate an output with unwanted noise that may conventionally be removed using a Finite Impulse Response (FIR) filter. Some such FIR filters may present additional design challenges and expense that may be unwanted for a given implementation. Moreover, it is known to use a Doherty power combination technique to increase power efficiency (e.g. such as at a 6dB backoff). Conventionally, a digital transmitter could be designed such that the internal modulation procedure and / or output combination exhibited either a FIR filter effect or a Doherty combination, but not both.Brief Description of the Drawings

[0003] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the exemplary principles of the disclosure. In the following description, various exemplary embodiments of the disclosure are described with reference to the following drawings, in which:FIG. 1 depicts an underlying FIR-filter concept;FIG. 2 depicts a switched-capacitor digital power amplifier (DPA);FIG. 3 depicts an alternative combination in which identical, time-delayed outputs are generated by the digital transmitter, but in which the Doherty effect is lost;FIG. 4 depicts a digital transmitter with combined Doherty combiner attributes and FIR filter functionality;FIG. 5 depicts an alternative configuration of the digital transmitter of FIG. 4.FIG. 6 depicts a lower-level schematic of a digital transmitter;FIG. 7 depicts a simulation result of the circuit of FIG. 4 or FIG. 5;FIG. 8 depicts the output power of various circuits; andFIG. 9 depicts a frequency response of various circuits.Description

[0004] The following detailed description refers to the accompanying drawings that show, by way of illustration, exemplary details and embodiments in which aspects of the present disclosure may be practiced.

[0005] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0006] Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures, unless otherwise noted.

[0007] The phrase “at least one” and “one or more” may be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [...], etc.). The phrase "at least one of" with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase "at least one of" with regard to a group of elements may be used herein to mean a selectionof: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of individual listed elements.

[0008] The words “plural” and “multiple” in the description and in the claims expressly refer to a quantity greater than one. Accordingly, any phrases explicitly invoking the aforementioned words (e.g., “plural [elements]”, “multiple [elements]”) referring to a quantity of elements expressly refers to more than one of the said elements. For instance, the phrase “a plurality” may be understood to include a numerical quantity greater than or equal to two (e.g., two, three, four, five, [...], etc.).

[0009] The phrases “group (of)”, “set (of)”, “collection (of)”, “series (of)”, “sequence (of)”, “grouping (of)”, etc., in the description and in the claims, if any, refer to a quantity equal to or greater than one, i.e., one or more. The terms “proper subset”, “reduced subset”, and “lesser subset” refer to a subset of a set that is not equal to the set, illustratively, referring to a subset of a set that contains less elements than the set.

[0010] The term “data” as used herein may be understood to include information in any suitable analog or digital form, e.g., provided as a file, a portion of a file, a set of files, a signal or stream, a portion of a signal or stream, a set of signals or streams, and the like. Further, the term “data” may also be used to mean a reference to information, e.g., in form of a pointer. The term “data”, however, is not limited to the aforementioned examples and may take various forms and represent any information as understood in the art.

[0011] Unless explicitly specified, the term “transmit” encompasses both direct (point-to- point) and indirect transmission (via one or more intermediary points). Similarly, the term “receive” encompasses both direct and indirect reception. Furthermore, the terms “transmit,” “receive,” “communicate,” and other similar terms encompass both physical transmission (e.g., the transmission of radio signals) and logical transmission (e.g., the transmission of digital data over a logical software-level connection). For example, aprocessor or controller may transmit or receive data over a software-level connection with another processor or controller in the form of radio signals, where the physical transmission and reception is handled by radio-layer components such as RF transceivers and antennas, and the logical transmission and reception over the software-level connection is performed by the processors or controllers. The term “communicate” encompasses one or both of transmitting and receiving, i.e., unidirectional or bidirectional communication in one or both of the incoming and outgoing directions. The term “calculate” encompasses both ‘direct’ calculations via a mathematical expression / formula / relationship and ‘indirect’ calculations via lookup or hash tables and other array indexing or searching operations.

[0012] FIR filters are widely used in signal processing, in which the impulse response (or, strictly speaking, also the response to any input signal of a finite length) is also of a finite duration. Such signal responses settle to zero over time. FIR filters are generally realized by combining N + 1 samples of an input feed, wherein the N + 1 samples are identical, except that they are delayed with respect to each other.

[0013] Such a transmit (Tx-FIR technique can be implemented for a transmitter’s out-of-band noise filtering by creating two or more transmitting streams of the same signal. Then the FIR (sine) response can be achieved by delaying the streams relative one to another.

[0014] FIG. 1 depicts an underlying FIR-filter concept. In this figure, an input signal is generated at a phase locked loop 102, and then fed in parallel across two branches of the power combiner with FIR filter capability. The first digital time converter (DTC) 104, generates a signal with a first delay (e.g. which may be no delay, depending on the implementation), and the second DTC 106 generates a signal having a second delay, which is in any event greater than the first delay. The outputs of DTC 104 and DTC 106 are identical, except that the output of DTC 106 is delayed with respect to the output of DTC 104.

[0015] The output of DTC 104 is received by a first transmitter core 108 and the output of the second DTC 106 is received by a second transmitter core 110. These cores (108 and 110) each generate a modulated signal (e.g. si and S(1 -T)), which are then combined in the power combiner 112. As shown, the power combiner’s output is s(t)= F / / ?{s(t)}.This represents a combination of two signals that are delayed with respect to one another, but which are otherwise identical, to form or approximate a single-tap FIR-filter output.

[0016] In relevant part, it is noted that the cores may be configured to process the incoming signal based on received digital power amplifier (DPA) codes. In the example in FIG. 1, either no DPA codes are used, or each side receives the same DPA codes. Such a device can, however, be operated with different DPA codes among the two cores, which provides a Doherty combination effect. A Doherty amplifier includes at least two streams, which are controlled to be amplified at different levels of saturation. In practice, this is achieved using DPA control codes, which, as will be seen below, result in either the first core amplifying according to different control codes than the second core, or it results in a portion of the first core amplifying according to different control codes then another portion of the first core.

[0017] FIG. 2 depicts a switched-capacitor digital power amplifier (DPA), configured to generate a Doherty combination effect. In this figure, a single DTC 202 generates digital time codes for a first signal and a second signal, in which the first signal and the second signal are identical to one another. A first core 208 is controlled according to a first set of DPA codes 204 (displayed illustratively as 0 to 127), and a second core 210 is controlled according to a second set of control codes 206 (displayed illustratively as 127 to 255). Such control codes may be used for amplitude modulation and power control.

[0018] A first output of the first core 208 (see p-part) is combined with the first output of the second core 210 (see n-part), as represented by 212. A second output of the first core 208 (see n-part) is combined with a second output of the second core 210 (see p-part), as represented by 214. In this manner, a polar digital transmitter is established. Moreover, the combinationof these outputs generates a Doherty effect, such that greater efficiency is achieved with saturated inputs. The drawback, however, is that FIR functionality requires the combination of otherwise identical, time-shifted signals. Since the signals in FIG. 2, however, are generated with different DPA codes, they are not identical. Thus, combining these signals together does not generate a FIR filter functionality. In short, FIG. 2 depicts a digital transmitter with Doherty combination.

[0019] In an ideal case (e.g., without second order impairments), it would be expected to have the same impedance conditions between the combiner and the two cores. This may occur if the arrays are full code enabled (255), meaning that both arrays are ON. This would also be expected to occur when the arrays are half code enabled (127), meaning that only the first array is ON. In the latter case, both the p-part and the n-part of the second array function act as a virtual ground to the combiner. This arrangement may ideally allow for the same power efficiency to be achieved at each of full code and half code (6dB backoff).

[0020] FIG. 3 depicts an alternative combination in which identical, time-delayed outputs are generated by the digital transmitter, but in which the Doherty effect is lost. In this figure, a first DTC 302 and a second DTC 303 generate digital codes that are identical to one another but otherwise time-delayed with respect to one another. The first set of digital codes (e.g. from the first DTC 302) is processed in the first core 308 according to the first set of DPA codes 304. The second set of digital codes (e.g., from the second DTC 303) is processed in the second core 310 according to the second set of DPA codes 306. The second set of DPA codes is delayed relative to the first set of DPA codes by 305. A first output (see p-part) of the first core 308 is combined with a first output (see n-part) of the second core 310, as seen by 308. A second output (see n-part) of the first core 308 is combined with a second output (see p-part) of the second core 310. In this manner, the signals are then subject to a combiner 316. In this figure, the output of the first part (p-part) of the first core is identical to the output of the first part of the second core 310, except that these outputs are time-delayed relative to one another.That is, the combination of the time-delayed signals results in a FIR-filter effect, akin to a single-tap FIR filter. The Doherty combiner effect, however, is lost, since the DPA codes that are used within the first core 308 and the second core 310 are identical to one another, except for the corresponding time-delay. That is, although the circuit in this figure includes a straight-forward Tx-FIR filter implementation, its usage completely removes completely the power efficiency at the 6dB Backoff (e.g., the “Doherty” power combination).

[0021] Otherwise stated, and when trying to implement a Tx-FIR functionality in a Polar digital transmitter (DTX), it may be desirable to create two data streams with the same data, but in which one of the two streams is delayed relative to the other stream. Since the data must be exactly the same (except for the delay), exactly the same DPA codes must be used in both arrays. This in turn, however, cancels the “Doherty” power combination.

[0022] Instead, it is desired to keep using the “Doherty” power combination and to create the delay (required for Tx-FIR) by delaying the n-part relative to p-part within an array, as shown in FIG. 4. This arrangement keeps the efficiency and allows FIR functionality.

[0023] FIG. 4 depicts a DTX with combined Doherty combiner attributes and FIR filter functionality. In this configuration, a first DTC 402 generates a first set of digital codes for the transmitter, and a second DTC 403 generates a second set of digital codes for the transmitter. Each of these DTC streams is processed according to two sets of DPA codes For this, see, generally, the DTC1 402 stream being processed by DPA codes 0 to 127 (404) for the p-part of the first core 404, the DTC1 402 stream being processed by DPA codes 128 to 255 (405) for the n-part of the first core 408; the DTC2 403 stream being processed by DPA codes 128 to 255 (407) for the p-part of the second core 410, and the DTC2 403 stream being processed by DPA codes 0 to 127 (406) for the n-part of the second core 410.

[0024] In this manner, the p-part of the first core 408 is combined with the n-part of the first core 408, as shown in 412. These outputs are not time-shifted relative to one another. Instead, they are generated with differing control codes (see 404 and 405), and thus combined togenerate a Doherty effect. Similarly, the p-part of the second core 410 is combined with the n- part of the second core 410, as shown in 414. These outputs are not time-shifted relative to one another. Instead, they are generated with differing control codes (see 406 and 406), and thus combined to generate a Doherty effect. The subsequent combination of these outputs via 416 combines to otherwise identical, time-delayed streams, which results in a FIR filter gain.

[0025] Of note, the parts of the first core 408 and the second core 410, read (from left to right) p, n, p, n. This is slightly altered from the configuration that was displayed in FIGs. 2 and 3. This alteration permits a simplified connection schema, as compared to a similar circuit in which the parts, from left to right, are p, n, n, p.

[0026] At this stage, it is prudent to address a matter of nomenclature. Prior to this point, the term “core” has been used to refer to a grouping of an n-part and a p-part in a single unit, such as 208 being a first core and 206 being a second core, 308 being a first core and 310 being a second core, and 408 being a first core and 410 being a second core. This nomenclature becomes unwieldy or undesirable for the digital transmitter in FIG. 5. For this transmitter, it is more useful to refer to the first core as the p-part of 508 and the n-part of 510, and to refer to the second core as the n-part of 508 and the p-part of 510.

[0027] With that in mind, FIG. 5 depicts an alternative configuration in which the parts of the first core (the p-part of 508 and the n-part of 510) and the second core (the n-part of 508 and the p-part of 510) are configured from left to right as p, n, n, p. In this configuration, a DTC1 502 and a DTC2 503 each generate a signal of digital codes for transmission. The output of DTC1 502 is processed in the p-part of 508 according to DPA codes 0 to 127, and in the n- part of 510 according to DPA codes 128 to 255. The output of DTC2 503 is processed in the n-part of 508 according to DPA codes 0 to 127, and in the p-part of 510 according to DPA codes 128 to 255. In this manner, the output of the p-part of 508 is connected with the output of the n-part of 510, such as through 512. Conversely, the output of the n-part of 508 iscombined with the output of the p-part of 510, such as by 514. These outputs may then be joined by a combiner 516.

[0028] Here it can be seen that 504 and 507 correspond to DPA codes 0 to 127, and 128 to 255, respectively, and that 505 and 506 correspond to delayed versions of DPA codes 0 to 127 and 128 to 255, respectively (see delay circuit 501). In this manner, signals generated from non-delayed DPA codes are combined, and signals generated from delayed DPA codes are combined. Thus, the configuration of FIG 5 is essentially identical to the configuration of FIG. 4, except that the n and p parts of the cores are arranged in FIG. 4 so as to permit simpler connections, and the n and p parts in FIG. 5 are arranged so as to require a more complex set of connections. It is expressly noted that using 0 delay the circuit of FIG. 4 (e.g., no delay between the Al and A2 codes, and no delay between DTC1 and DTC2), brings back the “Legacy” configuration.

[0029] FIG. 6 depicts a lower-level schematic of a digital transmitter. Portion 602 corresponds generally to one side of the digital amplifier of FIG. 4. Turning to the lower-level schematic, the DTC 604 feeds into a p-portion (top) and an n-portion (bottom). The p-portion includes multiple inverter slices, wherein the inverter’s input signal is the result of a NOR gate 607, which itself receives input signals of the DTC signal and an inverse of the DPA codes (data_p_en[0]). Similarly, the DTC 604 also feeds into the n-portion (bottom) of the circuit. The input of the corresponding inverters is a NAND gate 609, whose inputs are the DTC signal and the DPA codes (data_n_en

[0126] ). In this manner, the DPA codes essentially select which / how many inverter slices are selected. Each slice functions as an inverter. The slices, when taken together, function as an amplitude modulator.

[0030] It is noted that although the driving inverter is depicted as a simple inverter of a p-type transistor and an n-type transistor in series, it can alternatively be implemented as a series of cascode inverters. It is also noted that even if all of the n-cells are turned off (e.g. all of the n- slices are off by virtue of the DPA codes used), the result is merely a voltage corresponding toN total * C unit to GND, which has the effect of precluding a floating termination of the transformer.

[0031] FIG. 7 depicts a simulation result of the circuit of FIG. 4 or FIG. 5, demonstrating output power versus power efficiency. In this figure, the results of a polar digital transmitter with a straight-forward (e.g. a conventional) Tx-FIR implementation (e.g. corresponds to FIG. 3) is depicted as 702. The results of a polar digital transmitter with Doherty combiner (e.g. corresponds to FIG. 2) are depicted as 704. The results of the circuit as disclosed in FIG. 4 or FIG. 5 is depicted as 706. It can be seen that the circuit of FIG. 4 or FIG. 5 produces a Doherty effect, which generates increased power efficiency in higher output power ranges, compared to a conventional circuit with a FIR filter and no Doherty combination.

[0032] FIG. 8 depicts the output power of a polar digital transmitter with conventional FIR filter, a polar digital transmitter with Doherty combiner, and the circuit of FIG. 4 and FIG. 5, relative to DPA code. Since all three curves overlap (e.g. line-up), it can be seen that there is no appreciable difference in the output power of these circuits relative to the DPA code used.

[0033] FIG. 9 depicts a frequency response of a circuit without a FIR filter (e.g. without FIR filter functionality) 902, of a circuit with FIR filter functionality 904, and of a circuit with an ideal notch 906. Here is can be seen that the addition of the FIR filter greatly reduces undesired, neighboring frequencies compared to the implementation with the FIR filter.

[0034] While the above descriptions and connected figures may depict components as separate elements, skilled persons will appreciate the various possibilities to combine or integrate discrete elements into a single element. Such may include combining two or more circuits for form a single circuit, mounting two or more circuits onto a common chip or chassis to form an integrated element, executing discrete software components on a common processor core, etc. Conversely, skilled persons will recognize the possibility to separate a single element into two or more discrete elements, such as splitting a single circuit into two or more separate circuits, separating a chip or chassis into discrete elements originally providedthereon, separating a software component into two or more sections and executing each on a separate processor core, etc.

[0035] Further aspects of the disclosure will be made by way of example.

[0036] In Example 1, a digital amplifier, including: a first amplifier core, including: a first amplification portion, configured to amplify a first signal according to a first subset of control codes; a second amplification portion, configured to amplify a second signal according to a second subset of control codes, wherein the second signal is an inverse of the first signal; a second amplifier core, including: a third amplification portion, configured to amplify a third signal according to the second subset of control codes, wherein the third signal is a delayed first signal; a fourth amplification portion, configured to amplify a fourth signal according to the first subset of control codes, wherein the fourth signal is an inverse of the third signal.

[0037] In Example 2, the digital amplifier of Example 1, further including a first output combiner, configured to electrically conductively connect an output of the first amplification portion to an output of the second amplification portion, and a second output combiner, configured to electrically conductively connect an output of the third amplification portion to an output of the fourth amplification portion.

[0038] In Example 3, the digital amplifier of Example 2, further including a third output combiner, configured to combine an output of the first output combiner and an output of the second output combiner.

[0039] In Example 4, the digital amplifier of any one of Examples 1 to 3, further including: a first digital to time converter, configured to generate the first signal and the second signal based on a first plurality of digital codes; and a second digital to time converter, configured to generate the third signal and the fourth based on a second plurality of digital codes; wherein the second digital to time converter is configured to create the third signal as a delayed version of the first signal, and to create the fourth signal as a delayed version of the second signal.

[0040] In Example 5, the digital amplifier of any one of Examples 1 to 4, wherein the first amplification portion includes a plurality of first amplifiers, and wherein each amplifier of the plurality of first amplifiers is configured to receive a control code of the first subset of control codes and to modulate the first signal according to the received control code.

[0041] In Example 6, the digital amplifier of Example 5, wherein the second amplification portion includes a plurality of second amplifiers, and wherein each amplifier of the plurality of second amplifiers is configured to receive a control code of the second subset of control codes and to amplify the second signal according to the received control code.

[0042] In Example 7, the digital amplifier of Example 5 or 6, wherein the third amplification portion includes a plurality of third amplifiers, and wherein each amplifier of the plurality of third amplifiers is configured to receive a control code of the second subset of control codes and to amplify the third signal according to the received control code.

[0043] In Example 8, the digital amplifier of any one of Examples 5 to 7, wherein the fourth amplification portion includes a plurality of fourth amplifiers, and wherein each amplifier of the plurality of fourth amplifiers is configured to receive a control code of the first subset of control codes and to amplify the fourth signal according to the received control code.

[0044] In Example 9, the digital amplifier of any one of Examples 1 to 8, wherein each amplifier of the first amplification portion, the second amplification portion, the third amplification portion, and the fourth amplification portion includes a p-type field effect transistor and an n-type field effect transistor in an inverter configuration.

[0045] In Example 10, the digital amplifier of Example 9, wherein for each p-type field effect transistor and n-type field effect transistor in the push-pull configuration of each of the first amplification portion, the second amplification portion, the third amplification portion, and the fourth amplification portion, the p-type field effect transistor and the n-type field effect transistor have a common gate input.

[0046] In Example 11, the digital amplifier of Example 10, wherein the first amplification portion includes a first gate, configured to receive the first signal and an inverse of the control code of the first subset of control codes; and wherein the second amplification portion includes a second gate, configured to receive the second signal and a control code of the second subset of control codes.

[0047] In Example 12, the digital amplifier of Example 11, wherein the first gate is a NOR gate, configured to receive the first signal and the inverse of the control code of the first subset of control codes, and to generate a logical output for amplification; wherein the first amplification portion further includes an inverter, configured to generate the inverse of the control code of the first subset of control codes.

[0048] In Example 13, the digital amplifier of Example 12, wherein the second gate is a NAND gate, configured to receive the second signal and the control code of the second subset of control codes, and to generate a logical output for amplification.

[0049] In Example 14, the digital amplifier of any one of Examples 1 to 13, wherein the first subset of control codes and the second subset of control codes are disjoint.

[0050] In Example 15, the digital amplifier of any one of Examples 1 to 14, further including a delay circuit, configured to delay the second subset of control codes for the third amplification portion, and to delay the first subset of control codes for the fourth amplification portion.

[0051] In Example 16, the digital amplifier of any one of Examples 1 to 15, wherein a signal to be amplifier by the second amplifier core is a delayed version of a signal to be amplified by the first amplifier core, and wherein the digital amplifier approximates a finite impulse response filter by combining an output of the second amplifier core with an output of the first amplifier core.

[0052] In Example 17, the digital amplifier of any one of Examples 1 to 16, wherein the digital amplifier approximates a Doherty Amplifier by combining a signal amplifiedaccording to the first subset of control codes with a signal amplified according to the second subset of control codes.

[0053] In Example 18, the digital amplifier of any one of Examples 1 to 17, wherein the digital amplifier is a polar amplifier.

[0054] In Example 19, the digital amplifier of any one of Examples 1 to 18, wherein the digital amplifier is a switched capacitor amplifier.

[0055] In Example 20, a digital amplifier, including: a first amplifier core, including: a first amplification means for amplifying a first signal according to a first subset of control codes; a second amplification means, for amplifying a second signal according to a second subset of control codes, wherein the second signal is an inverse of the first signal; a second amplifier core, including: a third amplification means, for amplifying a third signal according to the second subset of control codes, wherein the third signal is a delayed first signal; a fourth amplification means, configured to amplify a fourth signal according to the first subset of control codes, wherein the fourth signal is an inverse of the third signal.

[0056] In Example 21, the digital amplifier of Example 20, further including a first output combiner, for electrically conductively connecting an output of the first amplification portion to an output of the second amplification portion, and a second output combiner for electrically conductively connecting an output of the third amplification portion to an output of the fourth amplification portion.

[0057] In Example 22, the digital amplifier of Example 21, further including a third output combiner, for combining an output of the first output combiner and an output of the second output combiner.

[0058] In Example 23, the digital amplifier of any one of Examples 20 to 22, further including: a first digital to time converter, for generating the first signal and the second signal based on a first plurality of digital codes; and a second digital to time converter, for generating the third signal and the fourth based on a second plurality of digital codes; whereinthe second digital to time converter is for creating the third signal as a delayed version of the first signal, and for creating the fourth signal as a delayed version of the second signal.

[0059] In Example 24, the digital amplifier of any one of Examples 20 to 23, wherein the first amplification portion includes a plurality of first amplifiers, and wherein each amplifier of the plurality of first amplifiers is for receiving a control code of the first subset of control codes and to modulate the first signal according to the received control code.

[0060] In Example 25, the digital amplifier of Example 24, wherein the second amplification portion includes a plurality of second amplifiers, and wherein each amplifier of the plurality of second amplifiers is for receiving a control code of the second subset of control codes and amplifying the second signal according to the received control code.

[0061] In Example 26, the digital amplifier of Example 24 or 25, wherein the third amplification portion includes a plurality of third amplifiers, and wherein each amplifier of the plurality of third amplifiers is for receiving a control code of the second subset of control codes and amplifying the third signal according to the received control code.

[0062] In Example 27, the digital amplifier of any one of Examples 24 to 26, wherein the fourth amplification portion includes a plurality of fourth amplifiers, and wherein each amplifier of the plurality of fourth amplifiers is for receiving a control code of the first subset of control codes and for amplifying the fourth signal according to the received control code.

[0063] In Example 28, the digital amplifier of any one of Examples 20 to 27, wherein each amplifier of the first amplification portion, the second amplification portion, the third amplification portion, and the fourth amplification portion includes a p-type field effect transistor and an n-type field effect transistor in an inverter configuration.

[0064] In Example 29, the digital amplifier of Example 28, wherein for each p-type field effect transistor and n-type field effect transistor in the push-pull configuration of each of the first amplification portion, the second amplification portion, the third amplification portion,and the fourth amplification portion, the p-type field effect transistor and the n-type field effect transistor have a common gate input.

[0065] In Example 30, the digital amplifier of Example 29, wherein the first amplification portion includes a first gate, for receiving the first signal and an inverse of the control code of the first subset of control codes; and wherein the second amplification portion includes a second gate, for receiving the second signal and a control code of the second subset of control codes.

[0066] In Example 31, the digital amplifier of Example 30, wherein the first gate is a NOR gate, for receiving the first signal and the inverse of the control code of the first subset of control codes, and for generating a logical output for amplification; wherein the first amplification portion further includes an inverter, configured to generate the inverse of the control code of the first subset of control codes.

[0067] In Example 32, the digital amplifier of Example 31, wherein the second gate is a NAND gate, for receiving the second signal and the control code of the second subset of control codes, and for generating a logical output for amplification.

[0068] In Example 33, the digital amplifier of any one of Examples 20 to 32, wherein the first subset of control codes and the second subset of control codes are disjoint.

[0069] In Example 34, the digital amplifier of any one of Examples 20 to 33, further including a delay circuit, for delaying the second subset of control codes for the third amplification portion, and delaying the first subset of control codes for the fourth amplification portion.

[0070] In Example 35, the digital amplifier of any one of Examples 20 to 34, wherein a signal to be amplified by the second amplifier core is a delayed version of a signal to be amplified by the first amplifier core, and wherein the digital amplifier approximates a finite impulse response filter by combining an output of the second amplifier core with an output of the first amplifier core.

[0071] In Example 36, the digital amplifier of any one of Examples 20 to 35, wherein the digital amplifier approximates a Doherty Amplifier by combining a signal amplified according to the first subset of control codes with a signal amplified according to the second subset of control codes.

[0072] In Example 37, the digital amplifier of any one of Examples 20 to 36, wherein the digital amplifier is a polar amplifier.

[0073] In Example 38, the digital amplifier of any one of Examples 20 to 37, wherein the digital amplifier is a switched capacitor amplifier.

[0074] In Example 39, a radio frontend is disclosed, wherein the radio frontend comprises the digital amplifier of any one of Examples 1 to 38.

[0075] It is appreciated that implementations of methods detailed herein are demonstrative in nature, and are thus understood as capable of being implemented in a corresponding device. Likewise, it is appreciated that implementations of devices detailed herein are understood as capable of being implemented as a corresponding method. It is thus understood that a device corresponding to a method detailed herein may include one or more components configured to perform each aspect of the related method.

[0076] All acronyms defined in the above description additionally hold in all claims included herein.

Claims

CLAIMSWhat is claimed is:

1. A digital amplifier, comprising: a first amplifier core, comprising: a first amplification portion, configured to amplify a first signal according to a first subset of control codes; a second amplification portion, configured to amplify a second signal according to a second subset of control codes, wherein the second signal is an inverse of the first signal; a second amplifier core, comprising: a third amplification portion, configured to amplify a third signal according to the second subset of control codes, wherein the third signal is a delayed first signal; a fourth amplification portion, configured to amplify a fourth signal according to the first subset of control codes, wherein the fourth signal is an inverse of the third signal.

2. The digital amplifier of claim 1, further comprising a first output combiner, configured to electrically conductively connect an output of the first amplification portion to an output of the second amplification portion, and a second output combiner, configured to electrically conductively connect an output of the third amplification portion to an output of the fourth amplification portion.

3. The digital amplifier of claim 2, further comprising a third output combiner, configured to combine an output of the first output combiner and an output of the second output combiner.

4. The digital amplifier of any one of claims 1 to 3, further comprising:a first digital to time converter, configured to generate the first signal and the second signal based on a first plurality of digital codes; and a second digital to time converter, configured to generate the third signal and the fourth based on a second plurality of digital codes; wherein the second digital to time converter is configured to create the third signal as a delayed version of the first signal, and to create the fourth signal as a delayed version of the second signal.

5. The digital amplifier of any one of claims 1 to 4, wherein the first amplification portion comprises a plurality of first amplifiers, and wherein each amplifier of the plurality of first amplifiers is configured to receive a control code of the first subset of control codes and to modulate the first signal according to the received control code.

6. The digital amplifier of claim 5, wherein the second amplification portion comprises a plurality of second amplifiers, and wherein each amplifier of the plurality of second amplifiers is configured to receive a control code of the second subset of control codes and to amplify the second signal according to the received control code.

7. The digital amplifier of claim 5 or 6, wherein the third amplification portion comprises a plurality of third amplifiers, and wherein each amplifier of the plurality of third amplifiers is configured to receive a control code of the second subset of control codes and to amplify the third signal according to the received control code.

8. The digital amplifier of any one of claims 5 to 7, wherein the fourth amplification portion comprises a plurality of fourth amplifiers, and wherein each amplifier of the plurality offourth amplifiers is configured to receive a control code of the first subset of control codes and to amplify the fourth signal according to the received control code.

9. The digital amplifier of any one of claims 1 to 8, wherein each amplifier of the first amplification portion, the second amplification portion, the third amplification portion, and the fourth amplification portion comprises a p-type field effect transistor and an n-type field effect transistor in an inverter configuration.

10. The digital amplifier of claim 9, wherein for each p-type field effect transistor and n-type field effect transistor in the push-pull configuration of each of the first amplification portion, the second amplification portion, the third amplification portion, and the fourth amplification portion, the p-type field effect transistor and the n-type field effect transistor have a common gate input.

11. The digital amplifier of claim 10, wherein the first amplification portion comprises a first gate, configured to receive the first signal and an inverse of the control code of the first subset of control codes; and wherein the second amplification portion comprises a second gate, configured to receive the second signal and a control code of the second subset of control codes.

12. The digital amplifier of claim 11, wherein the first gate is a NOR gate, configured to receive the first signal and the inverse of the control code of the first subset of control codes, and to generate a logical output for amplification; wherein the first amplification portion further comprises an inverter, configured to generate the inverse of the control code of the first subset of control codes.

13. The digital amplifier of claim 12, wherein the second gate is a NAND gate, configured to receive the second signal and the control code of the second subset of control codes, and to generate a logical output for amplification.

14. The digital amplifier of any one of claims 1 to 13, wherein the first subset of control codes and the second subset of control codes are disjoint.

15. The digital amplifier of any one of claims 1 to 14, further comprising a delay circuit, configured to delay the second subset of control codes for the third amplification portion, and to delay the first subset of control codes for the fourth amplification portion.

16. The digital amplifier of any one of claims 1 to 15, wherein a signal to be amplifier by the second amplifier core is a delayed version of a signal to be amplified by the first amplifier core, and wherein the digital amplifier approximates a finite impulse response filter by combining an output of the second amplifier core with an output of the first amplifier core.

17. The digital amplifier of any one of claims 1 to 16, wherein the digital amplifier approximates a Doherty Amplifier by combining a signal amplified according to the first subset of control codes with a signal amplified according to the second subset of control codes.

18. The digital amplifier of any one of claims 1 to 17, wherein the digital amplifier is a polar amplifier.

19. The digital amplifier of any one of claims 1 to 18, wherein the digital amplifier is a switched capacitor amplifier.

20. A digital amplifier, comprising: a first amplifier core, comprising: a first amplification means for amplifying a first signal according to a first subset of control codes; a second amplification means, for amplifying a second signal according to a second subset of control codes, wherein the second signal is an inverse of the first signal; a second amplifier core, comprising: a third amplification means, for amplifying a third signal according to the second subset of control codes, wherein the third signal is a delayed first signal; a fourth amplification means, for amplifying a fourth signal according to the first subset of control codes, wherein the fourth signal is an inverse of the third signal.

21. The digital amplifier of claim 20, further comprising a first output combiner, for electrically conductively connecting an output of the first amplification portion to an output of the second amplification portion, and a second output combiner for electrically conductively connecting an output of the third amplification portion to an output of the fourth amplification portion.

22. The digital amplifier of claim 21, further comprising a third output combiner, for combining an output of the first output combiner and an output of the second output combiner.

23. The digital amplifier of any one of claims 20 to 22, further comprising: a first digital to time converter, for generating the first signal and the second signal based on a first plurality of digital codes; and 1a second digital to time converter, for generating the third signal and the fourth based on a second plurality of digital codes; wherein the second digital to time converter is for creating the third signal as a delayed version of the first signal, and for creating the fourth signal as a delayed version of the second signal.

24. The digital amplifier of any one of claims 20 to 23, wherein the first amplification portion comprises a plurality of first amplifiers, and wherein each amplifier of the plurality of first amplifiers is for receiving a control code of the first subset of control codes and to modulate the first signal according to the received control code.

25. The digital amplifier of claim 24, wherein the second amplification portion comprises a plurality of second amplifiers, and wherein each amplifier of the plurality of second amplifiers is for receiving a control code of the second subset of control codes and amplifying the second signal according to the received control code.

Images