Integrated circuit chip including arrays of multi-threaded dynamic random access memory unit cells

Abstract

An integrated circuit chip comprising an array of unit cells, each including a plurality of memory strips, each including a plurality of independently accessible DRAM sub-arrays arranged in a row and a corresponding pair of primary single-ended sense amplifier circuits coupled to each of the DRAM sub-arrays. The DRAM sub-arrays of the plurality of memory strips are further arranged in a plurality of columns. Each unit cell further includes a plurality of global bit line sets, each coupled to the primary single-ended sense amplifier circuits of a corresponding column of DRAM sub-arrays, a multiplexer circuit coupled to each of the global bit line sets, wherein the multiplexer circuit selectively couples one of the global bit line sets to a set of global input / output lines, a secondary sense amplifier circuit coupled to the set of global input / output lines, and plural through silicon vias coupled to the secondary sense amplifier circuit.

Description

INTEGRATED CIRCUIT CHIP INCLUDING ARRAYS OF MULTI-THREADEDDYNAMIC RANDOM ACCESS MEMORY UNIT CELLSPriority Applications

[0001] This application claims priority to U.S. Patent Application 19 / 002,251 entitled “Integrated Circuit Chip Including Arrays Of Multi-Threaded Dynamic Random Access Memory Unit Cells” filed December 26, 2024, which is a continuation-in-part of U.S. Patent Application 18 / 399,579 entitled “Dynamic Random Access Memory System Including Single-Ended Sense Amplifiers And Methods For Operating Same”, filed December 28, 2023, and which claims priority to U.S. Provisional Patent Application 63 / 685,629 entitled “Multi-Threaded Dynamic Random Access Memory Systems And Methods Of Operating Same”, filed August 21 , 2024, and claims priority to U.S. Provisional Patent Application 63 / 696,485 entitled “Interconnect Structure For An Array Of Multi-Threaded Dynamic Random Access Memory Systems”, filed September 19, 2024, and claims priority to U.S. Provisional Patent Application 63 / 708,219 entitled “Single-Ended Sense Amplifier Structures And Methods For Operating Same”, filed October 16, 2024, all filed by Richard S. Roy.Field of the Invention

[0002] The present invention relates to dynamic random access memory (DRAM) systems. More specifically, the present invention relates to a DRAM system that includes an integrated circuit chip having an array of independently accessible DRAM unit cells.BACKGROUND

[0003] DRAM has been used in many system configurations to provide data storage for applications such as machine learning. As these applications become more complicated, it becomes more difficult to provide DRAM systems capable of handling all of the access requirements of these applications (e.g., random access bandwidth, latency, power, random access ability, memory capacity and density, refresh). JEDEC standard No. 238A describes specifications for a high bandwidth memory (HBM3) DRAM, which is coupled to a host computer die with a distributed interface. The HBM3 DRAM uses a wide-interface architecture in an attempt to achieve high-speed, low power operation. However, there is a need to have an improved DRAM system thatexhibits an increased random access bandwidth, reduced access latency, reduced operating / standby power, improved random access capability, increased memory capacity capabilities, higher memory density, and an improved refresh scheme. Current HBM architectures focus on extending the current paradigm by increasing the data bandwidth for large data block accesses (with a significant power penalty for the analog circuits required to achieve data rates approaching 10Gb / sec / pin) with very low ability to apply random (or nearly random) addresses at a high rate. It would therefore be desirable to have an improved DRAM system capable of overcoming the abovedescribed deficiencies of conventional DRAM systems.SUMMARY

[0004] Accordingly, the present invention focuses on increasing the number of Sustained Independent Transactions per second (SIT / s), which requires a much higher rate of nearly independent addresses to be applied to a stack of DRAM chips coupled by through silicon via (TSV) structures, while improving the power per transaction significantly. Additional features include significant improvements in power per transaction, latency, and data bandwidth, with little or no penalty in terms of area overhead.

[0005] In accordance with one embodiment, the present invention includes an integrated circuit chip for use in a multi-threaded dynamic random access memory (MTDRAM) system, wherein the integrated circuit chip includes a plurality of independent DRAM unit cells arranged in an array. Each of the unit cells comprises a plurality of DRAM memory strips, wherein each DRAM memory strip includes a plurality of independently accessible DRAM sub-arrays arranged in a row, and a plurality of primary single-ended sense amplifier circuits, wherein each of the DRAM sub-arrays is coupled to a corresponding pair of the primary single-ended sense amplifier circuits. In one embodiment, primary single-ended sense amplifier circuits are shared by adjacent DRAM memory strips. Each of the DRAM sub-arrays includes an array of DRAM bit cells arranged in rows and columns. In addition, the DRAM sub-arrays of the plurality of DRAM memory strips are arranged in a first plurality of columns of DRAM subarrays.

[0006] Each of the unit cells further includes a first plurality of global bit line sets, wherein each of the first plurality of global bit line sets is coupled to a corresponding one of the first plurality of DRAM sub-array columns through the primary single-ended sense amplifier circuits coupled to the DRAM sub-arrays in the corresponding one ofthe first plurality DRAM sub-array columns.

[0007] Each of the unit cells further includes a first multiplexer circuit coupled to each of the first plurality of global bit line sets, wherein the first multiplexer circuit selectively couples one of the first plurality of global bit line sets to a first set of global input / output lines. In a particular embodiment, the global bit lines of each of the first plurality of global bit line sets are evenly distributed across the first multiplexer circuit.

[0008] Each of the unit cells further includes a first secondary sense amplifier circuit coupled to the first set of global input / output lines, and a first set of through silicon vias coupled to the first secondary sense amplifier circuit.

[0009] This configuration advantageously enables the efficient layout of a large number of independent DRAM unit cells (e.g., 2048 or more) on the integrated circuit chip, thereby providing a large data access bandwidth to the integrated circuit chip. The use of single-ended sense amplifier circuits within the unit cells advantageously reduces power consumption associated with accesses to the integrated circuit chip. The use of through silicon vias enables stacked configuration of the integrated circuit chip with similar integrated circuit chips, further increasing DRAM memory capacity.

[0010] In accordance with another embodiment, the DRAM sub-arrays of the plurality of DRAM memory strips are further arranged in a second plurality of columns of DRAM sub-arrays, wherein each of the unit cells further comprises a second plurality of global bit line sets, wherein each of the second plurality of global bit line sets is coupled to a corresponding one of the second plurality of DRAM sub-array columns through the primary single-ended sense amplifier circuits coupled to the DRAM subarrays in the corresponding one of the second plurality of DRAM sub-array columns.

[0011] Each of the unit cells further comprises a second multiplexer circuit coupled to each of the second plurality of global bit line sets, wherein the second multiplexer circuit selectively couples one of the second plurality of global bit line sets to a second set of global input / output lines, a second secondary sense amplifier circuit coupled to the second set of global input / output lines, and a second set of through silicon vias coupled to the second secondary sense amplifier circuit. This configuration advantageously provides two sets of through silicon vias for transferring data to / from each unit cell, further increasing the data access bandwidth of each unit cell. In another embodiment, each of the unit cells further comprises a third set of through silicon vias for receiving access instructions to the unit cell.

[0012] In another embodiment, a first column of unit cells and an adjacent second column of unit cells are oriented such that the through silicon vias of the first andsecond columns of unit cells are located immediately adjacent to one another, advantageously consolidating the locations of the through silicon vias on the integrated circuit chip.

[0013] In another embodiment, the first secondary sense amplifier circuit comprises a plurality of write single-ended sense amplifiers, each coupled to a corresponding one of the global input / output lines of the first set of global input / output lines, and a plurality of read single-ended sense amplifiers, each coupled to a corresponding one of the global input / output lines of the first set of global input / output lines. In addition, each of the through silicon vias in the first set of through silicon vias is coupled to a corresponding pair of the plurality of write single-ended sense amplifiers and a corresponding pair of the plurality of read single-ended sense amplifiers. Each of the plurality of read single-ended sense amplifiers is controlled to simultaneously sample data on a corresponding one of the global input / output lines of the first set of global input / output lines, wherein one half of the plurality of read single-ended sense amplifiers are controlled to simultaneously provide the data sampled on the corresponding one of the global input / output lines of the first set of global input / output lines to the first set of through silicon vias during a first time period, and the other half of the plurality of read single-ended sense amplifiers are controlled to simultaneously provide the data sampled on the corresponding one of the global input / output lines of the first set of global input / output lines to the first set of through silicon vias during a second time period.

[0014] In addition, one half of the plurality of write single-ended sense amplifiers are controlled to sample a first set of data on the first set of through silicon vias during a first time period and hold the first set of data during a second time period, and a second half of the plurality of write single-ended sense amplifiers are controlled to sample a second set of data on the first set of through silicon vias during the second time period. The plurality of write single-ended sense amplifiers are further controlled to simultaneously provide the first and second sets of data on the first set of global input / output lines during a third time period.

[0015] In this embodiment, the data transfer frequency on the first set of through silicon vias is advantageously twice the data transfer frequency on the first set of global input / output lines.

[0016] In another embodiment, each of the DRAM memory strips includes a plurality of main word lines, each extending through all of the plurality of DRAM sub-arrays of the DRAM memory strip. Each of the DRAM memory strips further includes a mainword line driver that activates one of the corresponding plurality of main word lines when the DRAM memory strip is accessed. Each of the DRAM sub-arrays includes a dedicated plurality of sub-word lines, each coupled to a corresponding one of the rows of DRAM cells of the array of DRAM cells. Each of the plurality of DRAM sub-arrays includes a plurality of sub-word line driver circuits (SWDo.o-SWDy.o), each coupled to a corresponding one of the dedicated plurality of sub-word lines. Each of the main word lines is coupled to a corresponding plurality of the sub-word line driver circuits within each DRAM sub-array. For example, each main word line may be coupled to eight sub-word line driver circuits in one embodiment. In one embodiment, each of the DRAM sub-arrays receives a corresponding sub-array enable signal, wherein each of the sub-word line driver circuits in a DRAM sub-array is coupled to receive the corresponding sub-array enable signal. Advantageously, only the DRAM sub-arrays being accessed are enabled, resulting in significant power savings.

[0017] In another embodiment, each of the primary single-ended sense amplifier circuits is only coupled to half of the plurality of columns of DRAM bit cells in a corresponding DRAM sub-array. This advantageously enables the area efficient layout of four DRAM bit cells within the width of a single primary single-ended sense amplifier.

[0018] In another embodiment, an access instruction to the unit cell comprises a unit cell address for selecting the unit cell, a strip address for selecting one of the plurality of DRAM memory strips, a first DRAM sub-array column address for selecting one of the first plurality of columns of DRAM sub-arrays, and a second DRAM sub-array column address for selecting one of the second plurality of columns of DRAM sub-arrays. In another embodiment, the access instruction to the unit cell further comprises a main word line address for selecting one of the main word lines of the selected DRAM memory strip. In another embodiment, the access instruction to the unit cell further comprises a first sub-word line address for selecting one of the plurality of sub-word lines of a selected DRAM sub-array in the first plurality of columns of DRAM sub-arrays, and a second sub-word line address for selecting one of the plurality of sub-word lines of a selected DRAM sub-array in the second plurality of columns of DRAM sub-arrays. This embodiment advantageously provides the flexibility to select different sub-word lines in two different DRAM sub-arrays within a selected DRAM memory strip of the unit cell during a single access.

[0019] In another embodiment, each row of DRAM memory strips extends from a first edge of the unit cell to an opposing second edge of unit cell, wherein the through silicon vias of the unit cell are sparsely populated near the first and second edges of theunit cell, enabling a plurality of metal lines to pass between the through silicon vias of the first, second and third sets of through silicon vias near the first and second edges of the unit cell.

[0020] In another embodiment, each of the DRAM memory strips further comprises a sub-array decoder circuit that selectively enables up to one of the DRAM sub-arrays of the DRAM memory strip included in the first plurality of DRAM sub-array columns, and up to one of the DRAM sub-arrays of the DRAM memory strip included in the second plurality of DRAM sub-array columns.

[0021] Another embodiment of the present invention includes a multi-threaded dynamic random access memory (MTDRAM) processor system that includes: a first integrated circuit chip comprising at least 2048 processor blocks arranged in a first array, and a second integrated circuit chip comprising at least 2048 independent DRAM unit cells arranged in a second array, wherein each of the at least 2048 processor blocks is coupled to a corresponding one of the at least 2048 independent DRAM unit cells of the second array of DRAM unit cells by through silicon via (TSV) structures.

[0022] The present invention will be more fully understood in view of the following description and drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Fig. 1 is a diagram illustrating a multi-threaded dynamic random access memory (MTDRAM) system, in accordance with one embodiment of the present invention.

[0024] Fig. 2 is a top view of an MTDRAM chip of Fig. 1 , illustrating the layout of 2048 included MTDRAM unit cells in accordance with one embodiment of the present invention.

[0025] Fig. 3 is a top view illustrating two horizontally adjacent MTDRAM unit cells on the MTDRAM chip of Fig. 2, including the through-silicon vias (TSVs) associated with these unit cells, in accordance with one embodiment of the present invention.

[0026] Fig. 4 is a side view of two adjacent MTDRAM unit stacks, which include the MTDRAM unit cells of Fig. 3, in accordance with one embodiment of the present invention.

[0027] Fig. 5 is a top view of the 2048 unit stacks included in the MTDRAM system of Fig. 1 in accordance with one embodiment of the present embodiment.

[0028] Fig. 6 is a block diagram of an MTDRAM unit cell in accordance with one embodiment of the present invention.

[0029] Fig. 7 is a block diagram illustrating the first eight rows of an MTDRAM subarray included in the uppermost MTDRAM strip of Fig. 6, along with a corresponding main word line driver, corresponding sub-word line drivers and a corresponding pair of primary sense amplifier sub-circuits, in accordance with one embodiment of the present invention.

[0030] Fig. 8 is a diagram illustrating the manner in which a primary sense amplifier driver circuit controls accesses to single-ended sense amplifiers within a primary sense amplifier sub-circuit in accordance with one embodiment of the present invention.

[0031] Fig. 9 is a block diagram illustrating connections between bit lines, single- ended sense amplifiers and a corresponding global bit line within the MTDRAM unit cell of Fig. 6 in accordance with one embodiment of the present invention.

[0032] Fig. 10 is a diagram illustrating the MTDRAM sub-array of Fig. 7, along with Y-decoder logic used to selectively route data from the primary sense amplifier subcircuits to a set of global bit lines in accordance with one embodiment of the present invention.

[0033] Fig. 11A is a waveform diagram illustrating signals involved in a read access to the MTDRAM sub-array of Fig. 7 in accordance with one embodiment of the present invention.

[0034] Fig. 11 B is a waveform diagram illustrating signals involved in a write access to the MTDRAM sub-array of Fig. 7 in accordance with one embodiment of the present invention.

[0035] Fig. 12 is a diagram illustrating the data channels of the MTDRAM unit cell of Fig. 6 in accordance with one embodiment of the present invention.

[0036] Fig. 13 is a diagram illustrating the manner in which data on global bit lines associated with a first data channel of an MTDRAM unit cell are routed to a multiplexer section in accordance with one embodiment of the present invention.

[0037] Fig. 14 is a diagram illustrating the manner in which the global bit lines of Fig. 10 are distributed to the multiplexer section and the manner in which the multiplexer section routes data on the global bit lines to global input / output (I / O) lines in accordance with one embodiment of the present invention.

[0038] Fig. 15 is a diagram of a secondary sense amplifier that transfers read values from the global I / O lines of Fig. 14 onto the TSVs of a first data channel of the MTDRAM unit cell, and transfers write data values from the first data channel of the MTDRAM unit cell to the global I / O lines of Fig. 14, in accordance with one embodiment of the present invention.

[0039] Fig. 16 is a circuit diagram of an even read secondary sense amplifier circuit of the secondary sense amplifier of Fig. 15, which is used to receive and transmit read data values received on an even global I / O line in accordance with one embodiment of the present invention.

[0040] Fig. 17 is a circuit diagram of an odd read secondary sense amplifier circuit of the secondary sense amplifier of Fig. 15, which is used to receive and transmit read data values received on an odd global I / O line in accordance with one embodiment of the present invention.

[0041] Fig. 18 is a waveform diagram illustrating the operation of the even read secondary sense amplifier circuit of Fig. 15 and the odd read secondary sense amplifier circuit of Fig. 16, in accordance with one embodiment of the present invention.

[0042] Fig. 19 is a circuit diagram of an even write secondary sense amplifier circuit of the secondary sense amplifier of Fig. 15, which is used to receive and transmit write data values received on an even data line of the first data channel in accordance with one embodiment of the present invention.

[0043] Fig. 20 is a circuit diagram of an odd write secondary sense amplifier circuit of the secondary sense amplifier of Fig. 15, which is used to receive and transmit write data values received on an odd data line of the first data channel in accordance with one embodiment of the present invention.

[0044] Fig. 21 is a waveform diagram illustrating the operation of the even write secondary sense amplifier circuit of Fig. 19 and the odd write secondary sense amplifier circuit of Fig. 20, in accordance with one embodiment of the present invention.

[0045] Fig. 22 is a block diagram illustrating the format of an instruction used to access an MTDRAM unit stack in accordance with one embodiment of the present invention.

[0046] Fig. 23 is a diagram illustrating a main word line decoder circuit associated with an MTDRAM strip of an MTDRAM unit cell in accordance with one embodiment of the present invention.

[0047] Fig. 24 is a diagram illustrating a sub-array decoder circuit associated with an MTDRAM strip of an MTDRAM unit cell in accordance with one embodiment of the present invention.

[0048] Fig. 25 is a diagram illustrating the layout of the TSVs required to service an MTDRAM unit stack having four MTDRAM unit cells in accordance with one embodiment of the present invention.

[0049] Fig. 26 is a block diagram of an arrayed processor system, which includes an 8x8 array of MTDRAM processor systems in accordance with one embodiment of the present invention.

[0050] Fig. 27 is a top view of the layout of 2048 processor blocks included on an ASIC controller chip of one of the MTDRAM processor systems of Fig. 26 in accordance with one embodiment of the present invention.

[0051] Fig. 28 is a block diagram generally illustrating horizontal communication paths of a first row of processor blocks on the ASIC controller chip of Fig. 27 in accordance with one embodiment of the present invention.

[0052] Fig. 29 is a block diagram that generally illustrates horizontal transport controllers included in a stacked flash memory system and three horizontally adjacent MTDRAM processor systems of the arrayed processor system of Fig. 26 in accordance with one embodiment of the present invention.

[0053] Fig. 30 is a block diagram illustrating the general routing of the horizontal communication paths associated with the horizontal transport controllers of Fig. 29 within a silicon substrate interconnect structure in accordance with one embodiment of the present invention.

[0054] Fig. 31 is a block diagram of a processor block included on the ASIC controller chip of Fig. 27 in accordance with one embodiment of the present invention.

[0055] Fig. 32 is a block diagram of the first seventeen vertically adjacent processor blocks included in the first column of processor blocks in the ASIC controller chip of Fig. 27 in accordance with one embodiment of the present invention.

[0056] Fig. 33 is a block diagram illustrating the vertical routing of data between a communication management chip, a first column of processor blocks in a first MTDRAM processor system and a first column of processor blocks in a second, vertically adjacent, MTDRAM processor system of the arrayed processor system of Fig. 26, in accordance with one embodiment of the present invention.

[0057] Fig. 34 is a block diagram of an expanded arrayed processor system in accordance with one embodiment of the present invention.

[0058] Fig. 35 is a circuit diagram of single-ended sense amplifiers of a primary sense amplifier circuit, in accordance with an alternate embodiment of the present invention.

[0059] Fig. 36 is a waveform diagram illustrating signals associated with read accesses to bit cells coupled to the single-ended sense amplifiers of Fig. 35 in accordance with one embodiment of the present invention.

[0060] Fig. 37 is a waveform diagram illustrating signals associated with read accesses to bit cells coupled to single-ended sense amplifiers including MST transistors in accordance with a first alternate embodiment of the present invention.

[0061] Fig. 38 is a circuit diagram of single-ended MST sense amplifiers including kick capacitors in accordance with a second alternate embodiment of the present invention.

[0062] Fig. 39 is a waveform diagram illustrating signals associated with read accesses to bit cells coupled to the single-ended sense amplifiers of Fig. 38 in accordance with the second alternate embodiment of the present invention.

[0063] Fig. 40 is a circuit diagram of single-ended MST sense amplifiers including a grounded reference voltage and a negative logic ‘0’ bit cell voltage in accordance with a third alternate embodiment of the present invention.

[0064] Fig. 41 is a waveform diagram illustrating signals associated with read accesses to bit cells coupled to the single-ended sense amplifiers of Fig. 40 in accordance with the third alternate embodiment of the present invention.

[0065] Fig. 42 is a circuit diagram of single-ended MST sense amplifiers including a grounded reference voltage, a negative logic ‘0’ bit cell voltage and kick capacitors in accordance with a fourth alternate embodiment of the present invention.

[0066] Fig. 43 is a waveform diagram illustrating signals associated with read accesses to bit cells coupled to the single-ended sense amplifiers of Fig. 42 in accordance with the fourth alternate embodiment of the present invention.DETAILED DESCRIPTION

[0067] Fig. 1 is block diagram illustrating a multi-threaded dynamic random access memory (MTDRAM) processor system 100, in accordance with one embodiment of the present invention. MTDRAM processor system 100 includes four MTDRAM chips 101- 104 and an ASIC controller chip 105, which are connected in a stack as illustrated.Each of the MTDRAM chips 101-104 includes a corresponding plurality of MTDRAM unit cells 1O1o-1O4o and a plurality of through silicon vias (TSVs) (not shown in Fig. 1 ), which are described in more detail below. The TSVs of MTDRAM chip 101 are connected to a processor array 1O5o of ASIC controller chip 105 with a first plurality of TSV connectors (TSVC) 111. The TSVs of MTDRAM chip 101 also connected to the TSVs of MTDRAM chip 102 using a second plurality of TSV connectors 112. Similarly, the TSVs of MTDRAM chip 102 are also connected to the TSVs of MTDRAM chip 103 using a third plurality of TSV connectors 113, and the TSVs of MTDRAM chip 103 alsoconnected to the TSVs of MTDRAM chip 104 using a fourth plurality of TSV connectors 114. In this manner, MTDRAM chips 101 -104 are connected in a stacked configuration.

[0068] In the first embodiment described herein, each of the MTDRAM chips 101 - 104 includes 2048 independent MTDRAM unit cells, each having a storage capacity of 18 Mbits, such that each of the MTDRAM chips 101-104 has a storage capacity of 32 Gbits. In accordance with the following description, it is understood that the MTDRAM chips can be modified to include other numbers of MTDRAM unit cells having other capacities in other embodiments. Fig. 1 also illustrates X, Y and Z axes, which are consistently used throughout the drawings to more clearly define the MTDRAM system100.

[0069] Fig. 2 is a top view of MTDRAM chip 101 , illustrating the layout of the 2048 included MTDRAM unit cells UCi,i to UCi, 2048 (wherein unit cells UCi,i, UCi.s, UCi,ie, UCl ,24, UCl ,32, UCl ,33, UCl ,64, UCl ,225, UCl ,256, UCl ,481 , UCi ,512, UCl ,993, UCl ,1024, UCl ,2017 and UCi,2048 are specifically labeled, thereby illustrating the numbering convention of the MTDRAM unit cells). The 2048 MTDRAM unit cells UCi,i to UCi, 2048 are organized into 32 columns and 64 rows of unit cells, wherein each row of MTDRAM unit cells extends along the X-axis width of the MTDRAM chip 101 , as illustrated, and each column of MTDRAM unit cells extends along the Y-axis height of the MTDRAM chip101.

[0070] Main TSV regions TSVRi.o to TSVRi.is are centrally located between columns of unit cells, as illustrated. More specifically, the main TSV region TSVRi.o is located between the first pair of MTDRAM unit cell columns (i.e. , between the first column of MTDRAM unit cells and the second column of MTDRAM unit cells). The main TSV region TSVRi.i is located between the second pair of MTDRAM unit cell columns (i.e., between the third column of MTDRAM unit cells and the fourth column of MTDRAM unit cells). This pattern is repeated for the entire MTDRAM chip 101 . Each of the main TSV regions TSVRi.o to TSVRi.is extends along the Y-axis height of the MTDRAM chip 101.

[0071] As described in more detail below, each of the MTDRAM unit cells UCi ,1 to UCi,2048 has a dedicated set of TSVs within an adjacent one of the main TSV regions TSVRi.o to TSVRi.is, wherein this dedicated set of TSVs is used to carry data, address and control information to / from the corresponding MTDRAM unit cell. Although the main TSV regions are located adjacent to the unit cells in Fig. 2, it is understood that other TSVs (not shown in Fig. 2) may extend through other locations within the unitcells (including unused areas of the unit cells that do not include circuitry required by the MTDRAM array structure). The TSVs included in the main TSV regions TSVRi.o to TSVRi,i5 (as well as the other TSVs not located in the main TSV regions) are coupled to the TSV connectors 111 and 112 in the manner illustrated by Fig. 1 .

[0072] Fig. 3 is a top view illustrating the horizontally adjacent MTDRAM unit cells UCi ,1 and UCi,2 of Fig. 2, along with the corresponding portion of main TSV region TSVRi.o located between these unit cells, in accordance with one embodiment of the present invention.

[0073] Each of the MTDRAM unit cells UCi,i to UCi, 2048 includes sixteen 1.125 Mbit MTDRAM strips, wherein each of these strips extends vertically along the height of the unit cell (along the Y-axis). The sixteen MTDRAM strips of each unit cell are laid out in parallel along the Y-axis. As illustrated by Fig. 3, MTDRAM unit cell UCi ,1 includes sixteen MTDRAM strips S(i ,1)0 to S(i ,1)15, and MTDRAM unit cell UCi,2 includes sixteen MTDRAM strips S(i,2)o to S(i ,2)15.

[0074] Each of the MTDRAM unit cells UCi ,1 to UCi, 2048 also includes a multiplexer and a secondary sense amplifier circuit located between the sixteen MTDRAM strips of the unit cell and the corresponding main TSV region. For example, unit cell UCi ,1 includes multiplexer MUXi,i and secondary sense amplifier circuit SSA1 ,1 , which are located between MTDRAM strips S(i ,1)0 to S(i ,1)15 and main TSV region TSVRi.o. Similarly, unit cell UCi,2 includes multiplexer MUXI,2 and secondary sense amplifier circuit SSAI ,2, which are located between MTDRAM strips S(i,2)o to S(i,2)is and main TSV region TSVRi.o.

[0075] Each of the MTDRAM unit cells UCi ,1 to UCi, 2048 also includes a dedicated set of TSVs within its corresponding main TSV region. For example, unit cell UCi ,1 includes a dedicated TSV set TSVi.i within the corresponding main TSV region TSVRi.o, and unit cell UCi,2 includes a dedicated TSV set TSVI,2 within the corresponding main TSV region TSVRi.o.

[0076] In the manner illustrated by Fig. 3, the horizontally adjacent MTDRAM unit cells UCi ,1 and UCi,2 are laid out as mirror images of one another on MTDRAM chip 101 . In the described embodiments, each pair of horizontally adjacent MTDRAM unit cells separated by a main TSV region have the same configuration as MTDRAM unit cells UCi ,1 and UCi,2.

[0077] Although the unit cells UC1.1-UC1.2048 have the same logical configuration in the described embodiment, it is understood that in other embodiments, different unit cells on MTDRAM chip 101 can have different logical configurations. For example, inother embodiments, different unit cells can have different numbers of MTDRAM strips, different numbers of MTDRAM bit cells, different data word widths, different numbers of data channels, etc., in a manner that would be apparent to one of ordinary skill.

[0078] The configuration and operation of the MTDRAM strips S(i ,1 )o-S(i ,1)15, multiplexer MUXi,i and secondary sense amplifier circuit SSAI .I (along with the signals transmitted on the corresponding TSV set TSVi.i) is described in more detail below.

[0079] The MTDRAM chips 102, 103 and 104 have the same layout illustrated for MTDRAM chip 101 in Fig. 2, wherein the 2048 unit cells UCi,i-UCi,2048 of MTDRAM chip 101 are re-numbered as unit cells UC2,i-UC2,2048 in MTDRAM chip 102, unit cells UC3,1 -UC3,2048 in MTDRAM chip 103, and unit cells UC4,i-UC4,2048 in MTDRAM chip 104. Similarly, the main TSV regions TSVRi,o-TSVRi,is of MTDRAM chip 101 are renumbered as main TSV regions TSVR2,O-TSVR2,IS in MTDRAM chip 102, main TSV regions TSVRs.o-TSVRs.is in MTDRAM chip 103, and main TSV regions TSVR4,o- TSVR4.15 in MTDRAM chip 104. The unit cells UCi,x, UC2,x, UCs.x and UC4,x (x= 1 to 2048) of MTDRAM chips 101 -104 are vertically aligned along the Z-axis. Similarly, the main TSV regions TSVRy,o-TSVRy,i5 (y = 1 to 4) are vertically aligned along the Z-axis. This configuration enables vertically aligned MTDRAM unit cells to be connected to form MTDRAM unit stacks, as shown in more detail in Fig. 4.

[0080] Fig. 4 is a side view of two adjacent MTDRAM unit stacks USi and US2 in accordance with one embodiment of the present invention. Unit stack US1 includes four vertically aligned MTDRAM unit cells UCi,i, UC2,1 , UCs,i and UC4,1 in MTDRAM chips 101 , 102, 103 and 104, respectively. The unit cells UCi,i UC2,i UCs,i UC4,i are connected to one another (and processor block 105i) via TSVs in corresponding TSV sets TSVu, TSV2.1, TSVs.i and TSV4.1, respectively, and the TSV connectors 111 -114 (Fig. 1 ). More specifically, unit stack US1 includes an instruction bus INST1 and two independent 36-bit data buses DATA_Ai and DATA_Bi , which are constructed using TSVs in TSV regions TSVi.i TSV2.1 , TSVs.i and TSV4.1 and TSV connectors 111 -114.

[0081] The sixteen strips within each unit cell UCx.i are labeled as strips S(x,i)o to S(x,i)i5, wherein x = 1 to 4. The multiplexer within each unit cell UCx.i is labeled as MUXx.i, wherein x = 1 to 4, and the secondary sense amplifier circuit within each unit cell UCx.i is labeled as SSAx.i , wherein x = 1 to 4.

[0082] Similarly, independent unit stack US2 includes four vertically aligned MTDRAM unit cells UCi,2, UC2.2, UCs,2 and UC4.2 in MTDRAM chips 101 , 102, 103 and 104, respectively. The unit cells UCi,2 UC2,2 UCs,2 UC4,2 are connected to one another (and corresponding processor block 1052) via TSVs in corresponding TSV sets TSVI ,2,TSV2.2, TSV3.2 and TSV4.2, respectively, and the TSV connectors 1 1 1 -1 14 (Fig. 1 ).More specifically, unit stack US2 includes an instruction bus INST2 and two independent 36-bit data buses DATA_A2 and DATA_B2, which are constructed using TSVs in TSV regions TSV1 ,2 TSV2.2, TSV3.2 and TSV4.2 and TSV connectors 1 11 -114.

[0083] The sixteen strips within each unit cell UCx,2 are labeled as strips S(x,2)o to S(x,2)i5, wherein x = 1 to 4. The multiplexer within each unit cell UCx,2 is labeled as MUXX,2, wherein x = 1 to 4, and the secondary sense amplifier within each unit cell UCx,2 is labeled as SSAX,2, wherein x = 1 to 4.

[0084] Although Fig. 4 illustrates two unit stacks US1 and US2, it is understood that a total of 2048 independent unit stacks, each identical to unit stack US1 (or US2), are formed from the unit cells of MTDRAM chips 101 -104. More specifically each unit stack USx includes the four unit cells UCi,x, UC2,x, UCs.x and UC4,x (x = 1 to 2048) of MTDRAM chips 101 , 102, 103 and 104. Fig. 5 is a top view of the 2048 unit stacks US1-US2048 of MTDRAM system 100 in accordance with the present embodiment (wherein unit stacks USi,i, USi.s, USi .ie, US-1 ,24, US-1 ,32, US-1,33, USi ,64, US-1 ,225, USi,256, US 1,481 , US 1 ,512, US 1 ,993, US 1 ,1024, USi ,2oi? and USi,2048 are specifically labeled to illustrate the numbering system).

[0085] MTDRAM unit cell UCi ,i will now be described in more detail. It is understood that each of the other unit cells UC2,i , UCs,i and UC4,i of unit stack US1 can be accessed in the same manner as unit cell UC1 ,1 in response to an instruction provided on instruction bus INST1. As described in more detail below, each of the four unit cells of unit stack US1 can be individually addressed by instructions provided on instruction bus INST1.

[0086] As described in more detail below, processor array 1 O5o can simultaneously access up to two nearly random address locations within each of the unit stacks US1- US2048. Processor array 105o includes a plurality of processor blocks 105i -1052048, which are coupled to corresponding unit stacks US1-US2048, respectively. The following access patterns can be implemented within unit stack US1. In general, an instruction transmitted on instruction bus INST1 can be used to simultaneously access up to two data values in the same MTDRAM strip of unit stack US1 (subject to access limitations imposed by the MTDRAM configuration, which are described in more detail below). Data is routed from / to the unit stack US1 on two independent 36-bit data channels DATA_Ai and DATA_Bi . The following access patterns are generally allowable.

[0087] Processor block 105i can access one data value in any one of the strips S(i ,i)o-S(i ,1)15, S(2,i)o-S(2,i)i5, S(3,i)o-S(3,i)i5 or S(4,i)o-S(4,i)i 5, in any one of the unit cellsUCi ,1 , UC2.1, UC3,1 or UC4,1 of unit stack USi. For example, processor block 105i can access any data value in MTDRAM strip S(i ,1)14 of unit cell UCi,i in response to a single instruction on instruction bus INSTi (subject to access limitations imposed by the MTDRAM configuration).

[0088] Processor block 105i can also simultaneously access two data values in any one of the strips in any one of the unit cells of unit stack USi. As described in more detail below, a first half of each MTDRAM strip is designated to store data associated with the first data channel DATA_Ai , and a second half of each MTDRAM strip is designated to store data associated with the second data channel DATA_Bi .Processor block 105i can simultaneously access a first data value in the first half of MTDRAM strip S(i ,1)14 on the first data channel DATA_Ai, and a second data value in the second half of MTDRAM strip S(i ,1)14 on the second data channel DATA_Bi in response to a single instruction on instruction bus INSTi (subject to access limitations imposed by the MTDRAM configuration). A specific addressing scheme used to access unit stack USi is described in more detail below.

[0089] Note that each of the unit stacks US1-US2048 can be simultaneously and independently accessed in the same manner described above for unit stack USi . Thus, processor array 1 O5o has the address bandwidth to simultaneously access data from up to 4096 nearly random address locations within the unit stacks US1-US2048.

[0090] As mentioned above, the configuration of the MTDRAM unit cells imposes some access limitations. The configuration (and limitations) of the unit cells will now be described in more detail.

[0091] Fig. 6 is a block diagram of MTDRAM unit cell UC1 ,1 in accordance with one embodiment of the present invention. Although Fig. 6 specifically illustrates MTDRAM strips S(i ,1)0, S(i ,1)1 and S(i ,1)15 of unit cell UC1 ,1 , it is understood that the remaining MTDRAM strips S(i ,1)2 to S(i ,1)14 of unit cell UC1 ,1 have the same configuration. Note that the layout of the MTDRAM strips of Fig. 6 are rotated 90 degrees clockwise with respect to the orientation illustrated by Figs. 2 and 3. This rotation is specified by the X- Y-Z axis representation in these figures.

[0092] Each MTDRAM strip S(i ,i)x includes eight corresponding sub-arrays SUBAx, 0- SUBAX,7 (wherein x = 0 to 15 for strips S(i ,1)0 to S(i ,0)15, respectively). Each of the MTDRAM strips S(i,i)o to S(i ,1)15 extends across the height of the unit cell UC1 ,1 along the Y-axis. The sub-arrays of the MTDRAM strips S(i ,1 )o to S(i ,1 )is are arranged in eight sub-array columns C0SA0 to C0SA7, which extend along the X-axis, as illustrated, wherein each sub-array column CoSAy includes sub-arrays SUBAo.y-SUBAis.y (whereiny = 0 to 7 for sub-array columns CoSAo to C0SA7, respectively). As described in more detail below, sub-array columns C0SA0-C0SA3 are dedicated to data channel DATA_Ai of unit stack US1 and sub-array columns C0SA4-C0SA7 are dedicated to data channel DATA_Bi of unit stack US1 in the described embodiments. It is understood that in other embodiments, the sub-array columns C0SA0-C0SA7 can be dedicated to data channels DATA_Ai and DATA_Bi in different manners.

[0093] Each MTDRAM strip S(i ,i)x also includes a centrally located main word line driver circuit MWDx (wherein x = 0 to 15 for strips S(i ,1)0 to S(i ,1)15, respectively). As described in more detail below, each main word line driver circuit is configured to drive an addressed main word line in the corresponding strip.

[0094] Each MTDRAM strip S(i ,i)x also includes a pair of corresponding primary sense amplifier circuits PSAx and PSA(X+i) (wherein x = 0 to 15). For example, MTDRAM strip S(i ,1)0 includes primary sense amplifier circuits PSAo and PSA1. Each primary sense amplifier circuit PSAx is subdivided into eight corresponding primary sense amplifier sub-circuits PSAx,o-PSAx,7 (wherein x = 0 to 15 for strips S(i ,1)0 to S(i ,1)15, respectively). For example, primary sense amplifier circuit PSA1 is subdivided into eight corresponding primary sense amplifier sub-circuits PSAI,O-PSAI,7. Each primary sense amplifier sub-circuit is coupled to one (or two) adjacent MTDRAM sub-arrays, as illustrated. For example, primary sense amplifier sub-circuits PSAo.o to PSAo, 7 of primary sense amplifier circuit PSAo are coupled to adjacent MTDRAM sub-arrays SUBAo, 0 to SUBAo, 7, respectively. Similarly, primary sense amplifier sub-circuits PSAi.o to PSA17 of primary sense amplifier circuit PSA1 are coupled to adjacent MTDRAM sub-arrays SUBAo, 0 to SUBAo, 7, respectively, and adjacent MTDRAM sub-arrays SUBAi.o to SUBAI,7, respectively.

[0095] Vertically adjacent sub-arrays (along the X-axis) share primary sense amplifier sub-circuits. For example, an access to sub-array SUBAo, 0 requires the activation of primary sense amplifier sub-circuits PSAo.o and PSAi.o. Similarly, an access to vertically adjacent sub-array SUBAi.o requires activation of primary sense amplifier sub-circuits PSAi.o and PSA2,o. Thus, sub-arrays SUBAo, 0 and SUBAi.o ‘share’ primary sense amplifier sub-circuit PSAi.o. The time required to cycle (reset) each primary sense amplifier sub-circuit after activation (i.e. , Row Cycle time) is about 32 nanoseconds (ns) in the described embodiment. Thus, after accessing sub-array SUBo.o, a subsequent access to sub-array SUBAo, 0 and / or sub-array SUBAi.o must not occur for 32 ns (i.e., until shared primary sense amplifier sub-circuit PSAi.o has been reset). This is one limitation to implementing entirely random accesses within unit cellUCi ,1. Although the Row Cycle time is listed as about 32 ns, it is understood that the Row Cycle time may be shorter, based on testing of the associated circuitry.

[0096] Each primary sense amplifier sub-circuit (e.g., PSAo.o) includes a plurality (288) of single-ended sense amplifiers and a corresponding primary sense amplifier driver circuit (e.g., PSADo.o), which are described in more detail below in connection with Figs. 7-8. Each primary sense amplifier driver circuit generates signals for controlling the plurality of single-ended sense amplifiers in the corresponding primary sense amplifier sub-circuit.

[0097] Each primary sense amplifier circuit PSAo-PSA also includes a corresponding centrally located region PSARo-PSAR , respectively. Although the primary sense amplifier driver circuits (e.g., PSADo.o) are located within a corresponding primary sense amplifier sub-circuit (e.g., PSAo.o) in the described embodiments, it is understood that some (or all) portions of these primary sense amplifier driver circuits can be located within the centrally located regions PSARo- PSAR in other embodiments. In an alternate embodiment, the primary sense amplifier driver circuits are located on the ASIC controller chip 105, and TSVs carry the required control signals from the primary sense amplifier driver circuits on the ASIC controller chip 105 to the primary sense amplifier sub-circuits PSAo.o to PSA ,?. However, it is understood this embodiment undesirably requires substantially more TSVs within the unit cell UCi ,1.

[0098] As described above in connection with Figs. 3-4, MTDRAM unit cell UCi,i also includes multiplexer MUXi.i and secondary sense amplifier circuit SSAi . Multiplexer MUXi.i includes a first multiplexer circuit MUX(I ,I )A associated with the subarray columns C0SA0-C0SA3 dedicated to data channel DATA_Ai, and a second multiplexer circuit MUX(I ,I)B associated with the sub-array columns C0SA4-C0SA7 dedicated to data channel DATA_Bi.

[0099] Secondary sense amplifier circuit SSAI .I includes a first 72-bit secondary sense amplifier section SSA(i,i)A, which is coupled to first multiplexer circuit MUX(i,i)A, and is dedicated to data channel DATA_Ai. Secondary sense amplifier circuit SSAi.i also includes a second 72-bit secondary sense amplifier section SSA(i ,i)B, which is coupled to second multiplexer circuit MUX(i,i)B, and is dedicated to data channel DATA_Bi. Secondary sense amplifier circuit SSAi.i also includes a centrally located secondary sense amplifier driver circuit SSADi.i that generates signals for controlling the secondary sense amplifier sections SSA(U)A and SSA(i,i)B. The operation andcontrol of multiplexer MUXi,i and secondary sense amplifier circuit SSAi,i is described in more detail below.

[0100] Fig. 7 is a diagram illustrating the first eight rows of sub-array SUBAo, o, a corresponding main word line driver MWD (included in main word line driver circuit MWDo), and the corresponding primary sense amplifier sub-circuits PSAo.o and PSAi.o.

[0101] In the embodiments described herein, each of the MTDRAM sub-arrays includes 256 rows and 576 columns of MTDRAM bit cells. Although other numbers of rows / columns are possible in other embodiments, the selected number of rows and columns provides advantages with the configuration of unit cell UCi ,1 , which will become apparent in view of the following description.

[0102] As illustrated by Fig. 7, the first eight rows of sub-array SUBAo, o include a single main word line MWLo and eight associated sub-word lines SWLo.o to SWLy.o. Each of the sub-word lines SWLo.o, to SWLy.o is coupled to a corresponding row of 576 corresponding MTDRAM bit cells within the sub-array SUBAo, o. For example, sub-word line SWLo.o is coupled to MTDRAM bit cells bco.o to bco,575, as illustrated. Bit cell bco.o is illustrated to show the configuration of the corresponding bit cell pass gate transistor Go and bit cell capacitor Co. In the described embodiments, all bit cells have the same construction.

[0103] The 576 data bits associated with each sub-word line correspond with eight 72-bit values. In various embodiments, these 72-bit values may include: eight 8-bit data values and an 8-bit error correction code (ECC) value, eight 8-bit data values and an 8-bit packet header value, or two separate 36-bit data values.

[0104] Sub-word lines SWLo.o to SWLy.o are selectively driven by sub-word line driver circuits SWDo.o to SWDy.o, respectively. At most, only one of the eight sub-word line driver circuits SWDo.o to SWDy.o is activated for an access to sub-array SUBAo, o. Each of the sub-word line driver circuits SWDo.o to SWDy.o is centrally located within the sub-array SUBAo, o (along the Y-axis), wherein the sub-word line driver circuits SWDo.o to SWDy.o are vertically aligned in a column (along the X-axis), as illustrated by Fig. 7.

[0105] Each of the sub-word line driver circuits SWDo.o to SWDy.o is coupled to receive the signal on the corresponding main word line MWLo. To access the data associated with one of the sub-word lines SWLo.o to SWLy.o, the main word line MWLo is activated, along with the corresponding sub-word line driver circuit associated with the accessed sub-word line.

[0106] Each of the sub-word line driver circuits SWDo.o to SWDy.o is also coupled to receive a sub-array enable signal EN_SUBAo,o, which is applied to each of the sub-word line driver circuits in sub-array SUBAo, o. Sub-word line driver circuits SWDo.o to SWD?,o are further coupled to receive sub-word line address signals SWLA[0] to SWLA[7], respectively. Each sub-word line driver circuit SWDx.o (x = 0 to 7) is configured to activate a sub-word line voltage on the corresponding sub-word line SWLx.o in response to receiving an activated main word line signal MWLo, an activated sub-word line address signal SWLA[X] and an activated sub-array enable signal EN_SUBAo,o. One specific manner in which the sub-word line driver circuits SWDo.o to SWD?,o operate is described in more detail in commonly owned, co-pending U.S.Patent Application Serial No. 18 / 399,579, which is hereby incorporated by reference in its entirety.

[0107] The illustrated circuitry associated with the first eight rows of sub-array SUBAo, o is repeated along the X-axis (32 times), such that the entire sub-array SUBAo, o includes 32 main word lines, 256 sub-word line driver circuits and 256 sub-word lines. Thus, each of the main word lines is coupled to a corresponding set of eight sub-word line driver circuits (similar to sub-word line driver circuits SWDo.o to SWD7,o). Each set of eight sub-word line driver circuits is coupled to receive the eight corresponding subword line address signals SWLA[0] to SWLA[7] (in the same order illustrated by Fig. 7). Each of the 256 sub-word line driver circuits in sub-array SUBAo, o is further coupled to receive the same sub-array enable signal EN_SUBAo,o. As described in more detail below, each of the sub-arrays of a unit stack is independently enabled by a corresponding sub-array enable signal.

[0108] Each of the 32 main word lines associated with the sub-array SUBAo, o extends along the Y-axis to each of the sub-arrays included in the same strip S(i , o (i.e. , each of the main word lines extends along the Y-axis height of the unit cell UCi,i). For example, the main word line MWLo extends to each of the sub-arrays SUBAo, 1 to SUBAo, 7 of MTDRAM strip S(i , o. In the embodiments described herein, an access to unit cell UCi,i results in the activation of a single one of the 512 main word lines within the unit cell. As described in more detail below, this activated main word line is specified by a 12-bit main word line address value MWL[11 :0] and a 16-bit strip address value STRIP[15:0] on the instruction bus INSTi.

[0109] In the embodiments described herein, the sub-arrays SUBAx,o-SUBAx,3 (x = 0 to 15) located to the left-side of the centrally located main word line driver circuits MWD0-MWD15 (Fig. 6) are coupled to receive a first sub-word line address value SWLA[7:0], which is associated with the first data channel DATA_Ai . The sub-arrays SUBAX,4-SUBAX,7 (x = 0 to 15) located to the right-side of the centrally located mainword line driver circuits MWD0-MWD15 (Fig. 6) are coupled to receive a second subword line address value SWLB[7:0], which is associated with the second data channel DATA_Bi.

[0110] Thus, to access unit cell UC1 ,1 , a single main word line (e.g., MWLo) is activated within one of the strips (e.g., strip S(i ,1)0), a first word sub-word line (defined by SWLA[7:0]) associated with the activated main word line is activated within a left-side sub-array within the selected strip (e.g., SUBAo, 0), and a second sub-word line (defined by SWLB[7:0]) associated with the activated main word line is activated within a right- side sub-array within the selected strip (e.g., SUBAA.O), wherein the first sub-word line and second sub-word line can have different (or the same) addresses. Providing independent sub word line address values SWLA[7:0] and SWLB[7:0] advantageously provides flexibility in addressing the unit cell UC1 ,1. In an alternate embodiment, a single sub-word line address value is used to access the unit cell UCi,i , thereby reducing the number of TSVs required in the instruction bus INST1 by 8.

[0111] Using a single main word line address value and a single strip address value for both data channels DATA_Ai and DATA_Bi provides limitations to random address accessing within the unit stack US1. In alternate embodiments, independent main word line addresses (and / or independent strip addresses) are provided for the left-side subarrays and the right-side sub-arrays of the unit stack, thereby reducing or eliminating the above-described random access limitations. It is understood that additional TSVs would be required to route the independent main word line addresses (and / or independent strip addresses) in such embodiments.

[0112] As described above, an access to an MTDRAM strip requires the activation of a main word line that extends along the entire length of the MTDRAM strip. Prior to performing a subsequent access to a different sub-array column (CoSA) within the same strip, the previously activated main word line must be pre-charged to its initial (deactivated) state. This main word line pre-charge operation limits the access rate to the MTDRAM strip. In accordance with one embodiment, the main word line precharge operation requires 4 ns (while accesses may occur at a rate of 1 GHz, or at a period of 1 ns). In this case, once a strip is accessed, a new address within the same strip cannot be accessed again for 4 ns. The required main word line pre-charge operation is a further limitation to random accessing of the unit stack US1.

[0113] Each column of bit cells in sub-array SUBAo, 0 is coupled to a corresponding bit line. More specifically, all 256 bit cells located in the same column as bit cell bco.x are coupled to bit line blo,x (wherein x = 0 to 575). Bit lines blo.y (wherein y representseven values from 0 and 575) are coupled to corresponding single-ended sense amplifiers in primary sense amplifier sub-circuit PSAo.o. More specifically, the ‘even’ bit lines blo.o, bio, 2, ... bio, 574 of sub-array SUBAo, 0 are coupled to corresponding single- ended sense amplifiers SAo.o, SAo,2, ... SAo, 574, respectively, in primary sense amplifier sub-circuit PSAo.o.

[0114] Bit lines blo.z (wherein z represents odd values from 0 and 575) are coupled to corresponding single-ended sense amplifiers in primary sense amplifier sub-circuit PSAi.o. More specifically, the ‘odd’ bit lines blo , bio, 3, ... bio, 575 of sub-array SUBAo, 0 are coupled to corresponding single-ended sense amplifiers SAo.i , SAo,3, ... SAo, 575, respectively, in primary sense amplifier sub-circuit PSAi.o.

[0115] The ‘odd’ bit lines bh , bio, 3, ... bh,575 of vertically adjacent sub-array SUBAi.o are also coupled to corresponding single-ended sense amplifiers SAo.i, SAo,3, ...SAo ,575, respectively, in primary sense amplifier sub-circuit PSAi,o (thereby allowing the primary sense amplifier sub-circuit PSAi.o to be shared by sub-arrays SUBAo, 0 and SUBAi.o).

[0116] Primary sense amplifier driver circuits PSADo.o and PSADi.o are centrally located within primary sense amplifier sub-circuits PSAo.o and PSAi.o, respectively, as illustrated in Fig. 7. These driver circuits PSADo.o and PSADi.o are vertically aligned with the sub-word line driver circuits SWDo.o to SWD7,o along the X-axis, advantageously simplifying the layout of associated sub-array column C0SA0. Primary sense amplifier driver circuits PSADo.o and PSADi.o are coupled to receive the subarray enable signal EN_SUBAo.o, which is activated when sub-array SUBAo, 0 is accessed. Primary sense amplifier driver circuit PSADi.o is also coupled to receive the sub-array enable signal EN_SUBAi,o, which is activated when sub-array SUBAi.o is accessed.

[0117] Fig. 8 is a diagram illustrating the manner in which the primary sense amplifier driver circuit PSADi.o controls accesses to single-ended sense amplifiers SAo.i and SAo, 3 within primary sense amplifier sub-circuit PSAi.o in accordance with one embodiment of the present invention. It is understood that the control signals generated by primary sense amplifier driver circuit PSADi.o are provided to all of the single-ended sense amplifiers of primary sense amplifier sub-circuit PSAi.o in parallel. It is also understood that the single-ended sense amplifiers SAo.i and SAo, 3 (along with any of the other single-ended sense amplifiers included in the unit cell UC1 ,1 ) can be replaced with any of the single-ended sense amplifiers described below in connection with Figs. 35 to 41 in alternate embodiments of the present invention.

[0118] Single-ended sense amplifier SAo.i includes p-channel transistors P1 -P2, n- channel transistors N1-N2, N11 -N12 and N20, internal sense amplifier nodes INTO and INTO#, thick oxide, high voltage NMOS transistors 801 and 803, and bit line voltage kick capacitors 821 and 823, which are connected as illustrated. Similarly, single- ended sense amplifier SAo,3 includes p-channel transistors P3-P4, n-channel transistors N3-N4, N13-N14 and N22, internal sense amplifier nodes INT2 and INT2#, thick oxide, high voltage NMOS transistors 802 and 804, and bit line voltage kick capacitors 822 and 824, which are connected as illustrated.

[0119] Single-ended sense amplifiers SAo.i and SAo,3 operate in response to control signals provided by primary sense amplifier driver circuit PSADi.o, including kick control signal Vk (which is provided to capacitors 821 -824, as illustrated), PCOM and NCOM (which are provided to latch circuits formed by transistors P1 -P4 and N1 -N4, as illustrated), ISOso and ISOsi (which are isolation signals provided to transistors 801 -802 and 803-804, as illustrated), and pre-charge signals PREo and PREi , which are provided to transistors N11 -N14 as illustrated). The specific timing of the abovedescribed control signals and the corresponding operation of the single-ended sense amplifiers SAo.i and SAo,3 is described in detail in U.S. Patent Application Serial No. 18 / 399,579, which is hereby incorporated by reference in its entirety. The operation and control of the single-ended sense amplifiers SAo.i and SAo,3 in response to the above-described control signals is also described in more detail below in connection with Figs. 11 A and 11 B. In one embodiment, primary sense amplifier driver circuit PSADi.o generates the timing of the above-described control signals in response to a clock signal (CLK) provided on a TSV of the instruction bus INSTi. Advantageously, only the enabled primary sense amplifier driver circuits are activated to generate the required control signals, resulting in significant power savings within unit cell UCi,i.

[0120] As described above, single-ended sense amplifier SAo.i is coupled to ‘odd’ bit line blo.i of sub-array SUBAo, o, and ‘odd’ bit line bh,i of sub-array SUBAi.o. Similarly, single-ended sense amplifier SAo,3 is coupled to ‘odd’ bit line bio, 3 of sub-array SUBAo, o, and ‘odd’ bit line bh ,3 of sub-array SUBAi.o.

[0121] If the sub-array enable signal EN_SUBAo,o is activated (indicating an access to sub-array SUBAo, 0), then primary sense amplifier driver circuit PSADi.o enables generation of the control signals ISOso, Vk, PCOM, NCOM, PREo and PRE1 , such that the bit lines blo and bio, 3 of sub-array SUBAo, 0 are effectively coupled to single-ended sense amplifiers SAo.i and SAo,3, respectively. During this access, primary sense amplifier driver circuit PSADi.o deactivates the isolation control signal ISOsi , effectivelyde-coupling the bit lines bh,i and bh ,3 of sub-array SUBAi.o from the single-ended sense amplifiers SAo.i and SAo,3, respectively. Note that each of the single-ended sense amplifiers SAo.i and SAo,3 latches a data bit entirely in response to the signal developed on a single bit line.

[0122] Conversely, if the sub-array enable signal EN_SUBAi,o is activated (indicating an access to sub-array SUBAi.o), then primary sense amplifier driver circuit PSADi.o enables generation of the control signals ISOsi , Vk, PCOM, NCOM, PREo and PRE1 , such that the bit lines bh ,1 and bh ,3 of sub-array SUBAi.o are effectively coupled to single-ended sense amplifiers SAo.i and SAo,3, respectively. During this access, primary sense amplifier driver circuit PSADi.o deactivates the isolation control signal ISOso, effectively de-coupling the bit lines blo and bio, 3 of sub-array SUBAo, 0 from the single-ended sense amplifiers SAo.i and SAo,3, respectively.

[0123] In the manner described above, only primary sense amplifier sub-circuits associated with accessed sub-arrays are activated during an access to unit cell UC1 ,1 , advantageously resulting in significant power savings.

[0124] In an alternate embodiment, primary sense amplifier driver PSADi.o generates a first kick control voltage (e.g., VKI), which is activated and applied to kick transistors 821 and 822 when the EN_SUBAo,o signal is activated, and a second kick control voltage (e.g., VK2), which is activated and applied to kick transistors 823 and 824 when the EN_SUBAi,o signal is activated, thereby resulting in further power savings within unit cell UC1 ,1. Note that this embodiment requires additional decoding circuitry within primary sense amplifier driver circuit PSADi.o.

[0125] In the described examples, the data transfer rate between the sub-arrays and the primary sense amplifier sub-circuits is 1 GHz. However, it is understood that higher data transfer rates can be implemented in other embodiments, based on real silicon performance capability for a given silicon technology. Other considerations may require slower data transfer rates in other embodiments.

[0126] Returning now to Fig. 7, a read access to sub-array SUBAo, 0 results in 288 data bits being transferred from the bit cells associated with an addressed sub-word line to primary sense amplifier sub-circuit PSAo.o, and also results in 288 data bits being transferred from the bit cells associated with the addressed sub-word line to primary sense amplifier sub-circuit PSAi.o. As described above, each of these data bits is latched into a single-ended sense amplifier. Although the present example describes a read access to sub-array SUBAo, 0, (i.e., through data channel DATA_Ai) it is understood that a simultaneous (parallel) read access may be performed to one of theright-side sub-arrays SUBAo, 4 to SUBAo, 7 (i.e., through data channel DATA_Bi).Moreover, although the present example describes a read access, it is understood that write accesses are similarly performed within the unit cell UC1 ,1.

[0127] Data stored in the primary sense amplifier circuits is selectively routed to global bit lines (GBLs), which extend along the X-axis through the unit cell UC1 ,1. The global bit lines extend from the primary sense amplifier circuits to the multiplexer circuit MUXi,i in a manner described in more detail below.

[0128] Fig. 9 is a block diagram illustrating the first eight bit line-to-primary sense amplifier connections in the first three strips S(i,i)o-S(i ,1)2 of unit cell UCi,i, along with the associated global bit line GBLo. In the first strip S(i ,1)0, the even bit lines blo.o, bio, 2, bio, 4 and bio, 6 are coupled to corresponding single-ended sense amplifiers SAo.o, SAo,2, SAO,4 and SAo,6 in primary sense amplifier sub-circuit PSAo.o. The odd bit lines blo , bio, 3, bio, 5 and bio, 7 of the first strip S(i ,1 )o are coupled to corresponding single-ended sense amplifiers SAo.i , SAo,3, SAo.s and SAo,7 in primary sense amplifier sub-circuit PSAi.o.

[0129] In the second strip S(i,i)i , the odd bit lines bh ,1 , bh,3, bh,s and bh ,7 are coupled to corresponding single-ended sense amplifiers SAo.i, SAo,3, SAo.s and SAo,7 in primary sense amplifier sub-circuit PSAi.o. The even bit lines bh ,0, bh ,2, bh ,4 and bh ,6 of the second strip S(i ,1)1 are coupled to corresponding single-ended sense amplifiers SAi.o, SAI ,2, SAI ,4 and SAI ,6 in primary sense amplifier sub-circuit PSA2,o.

[0130] In the third strip S(i ,1)2, the even bit lines bfc.o, bl2,2, bl2,4 and bl2,e are coupled to corresponding single-ended sense amplifiers SAi.o, SAI ,2, SAI ,4 and SAI ,6 in primary sense amplifier sub-circuit PSA2,o. The odd bit lines bh,i , bl2,3, bh,5 and bl2,7 of the third strip S(i,i)2 are coupled to corresponding single-ended sense amplifiers SAi,i , SAI ,3, SA1 ,5 and SAI ,7 in primary sense amplifier sub-circuit PSA2,o.

[0131] As described in more detail below, the routing of data between the single- ended sense amplifiers of unit cell UC1 ,1 and corresponding global bit lines is controlled by Y-address signals Y-DEC[7:0], In general, the Y-address signals Y-DEC[0], Y- DEC[2], Y-DEC[4] and Y-DEC[6] control output routing from primary sense amplifier circuits PSAo, PSA2, PSA4, PSAs, PSAs, PSA10, PSA12, PSA14 and PSA16 and the Y- address signals Y-DEC

[0001] , Y-DEC[3], Y-DEC[5] and Y-DEC[7] control output routing from primary sense amplifier circuits PSA1 , PSA3, PSAs, PSA7, PSA9, PSA11, PSA13 and PSA15.

[0132] Fig. 10 is a block diagram illustrating MTDRAM sub-array SUBAo, 0 the corresponding primary sense amplifier sub-circuits PSAi.o and PSAi,i and thecorresponding global bit lines GBL0-GBL71 in accordance with one embodiment of the present invention. The global bit lines GBL0-GBL71 are shared by all of the sub-arrays in sub-array column C0SA0. Fig. 10 illustrates the manner in which the Y-address signals Y-DEC[7:0] route data from the single-ended sense amplifiers of primary sense amplifier sub-circuits PSAo.o and PSAi.o to global bit lines GBL0-GBL71 in accordance with one embodiment of the present invention.

[0133] As described above, a read access to a row of sub-array SUBAo, 0 results in 288 data bits being transferred to primary sense amplifier sub-circuit PSAi.o on the even bit lines of sub-array SUBAo, 0, and 288 data bits being transferred to primary sense amplifier sub-circuit PSAi,i on the odd bit lines of sub-array SUBAo, 0. As illustrated in Fig. 10, primary sense amplifier sub-circuit PSAi.o includes 288 single- ended sense amplifiers SAO.Y (wherein Y = even numbers from 0 to 574) and primary sense amplifier sub-circuit PSAi,i includes 288 single-ended sense amplifiers SAo.z (wherein Z = odd numbers from 1 to 575), which store data read from a row of bit cells in sub-array SUBAo, 0.

[0134] Column select circuitry within primary sense amplifier sub-circuits PSAi.o and PSAi,i is controlled to selectively route a 72-bit data value onto global bit lines GBLo- GBL71 in response to a pre-decoded Y-address value Y-DEC[0:7] provided on the instruction bus INST1.

[0135] As illustrated by Fig. 10, each global bit line GBL is coupled to eight corresponding single-ended sense amplifiers in primary sense amplifier sub-circuits PSAi.o and PSAi . For example, global bit line GBLo is coupled to four single-ended sense amplifiers SAo.o, SAo,2, SAo,4 and SAo,6 in primary sense amplifier sub-circuit PSAi.o and four single-ended sense amplifiers SAo.i , SAo,3, SAo.s and SAo,7 in primary sense amplifier sub-circuit PSAi . Each of these eight single-ended sense amplifiers SAO,O-SAO,7 is coupled to the global bit line GBLo by a corresponding transistor, which is controlled by the Y-address values Y-DEC[0] to Y-DEC[7], respectively. Note that Fig. 8 illustrates exemplary transistors N20 and N22, which couple the single-ended sense amplifiers SAo.i and SAo,3 to global bit line GBLo in response to the Y-address values Y- DEC

[0001] and Y-DEC[3], respectively. Thus, if the Y-address value Y-DEC

[0001] is activated (and the Y-address values Y-DEC[0] and Y-DEC[2:7] are deactivated), then the data value stored in single-ended sense amplifier SAo.i is transmitted onto global bit line GBLo (through turned on transistor N20).

[0136] The above-described pattern is repeated for successive sets of eight single- ended sense amplifiers, as illustrated, whereby a 72-bit data value is transmitted ontoglobal bit lines GBL0-GBL71. It is noted that a burst read access of up to eight 72-bit data values can be performed for data stored in primary sense amplifier sub-circuits PSAi.o and PSAI .I by changing (e.g., incrementing) the Y-address value Y-DEC[0:7] over successive cycles, without reactivating the primary sense amplifier sub-circuits PSAi.o and PSAi . As described in more detail below, the Y-address value Y-DEC[0:7] is controlled by the processor block 105i (via instruction bus INST1).

[0137] Note that global bit lines GBL0-GBL71 are shared by all of the sub-arrays in sub-array column C0SA0. As described in more detail below, each of the eight subarray columns C0SA0-C0SA7 of unit cell UC1 ,1 has a corresponding set of 72 global bit lines. In the embodiments described herein, all of the primary sense amplifiers of a unit stack share the same Y-address value Y-DEC[0:7],

[0138] As illustrated by Figs. 9 and 10, when sub-array SUBAi.o of strip S(i ,1)1 is accessed, single-ended sense amplifiers in primary sense amplifier sub-circuit PSAi.o are selectively coupled to global bit lines GBL0-GBL71 in response to the Y-address signals Y-DEC[1], Y-DEC[3], Y-DEC[5] and Y-DEC[7], and single-ended sense amplifiers in primary sense amplifier sub-circuit PSA2,o are selectively coupled to global bit lines GBL0-GBL71 in response to the Y-address signals Y-DEC[0], Y-DEC[2], Y- DEC[4] and Y-DEC[6], Using this pattern, each of the primary sense amplifier circuits PSAo-PSA only needs to receive four Y-address signals, advantageously reducing routing congestion within the unit cell UC1 ,1.

[0139] The timing of Y-address value Y-DEC[0:7] (and the timing of the read / write signals on the global bit lines) is different during read accesses and write accesses.

[0140] Fig. 11A is a waveform diagram illustrating the control signals used to read a (logic high) data value from bit cell bco of sub-array SUBAo, 0 into single-ended sense amplifier SAo.i, and then transfer this data value from the single-ended sense amplifier SAo,i to global bit line GBLo, in accordance with one embodiment. In general, the precharge signals PREo and PRE1 are activated (high) to pre-charge the single-ended sense amplifier SAo.i prior to time T1 . At time T1 , the pre-charge control voltage PREo is driven to GND, thereby turning off n-channel transistors N11 and N13, such that the internal sense amplifier nodes INTO and INT2 are no longer actively pulled to GND through transistors N11 and N13.

[0141] At time T2, the sub-word line SWLo.o, is driven high by the corresponding sub-word line driver circuit SWDo.o (in response to the MWLo, SWLA[0] and EN_SUBAo,o signals), thereby enabling the bit cell bco to provide positive charge onto corresponding bit line blo . At time T3, the kick voltage VK is activated low, therebyfurther developing the signal on the bit line blo,i. At time T4, the ISOso signal is activated, thereby coupling the bit line blo.i to internal node INTo of single-ended sense amplifier SAo,i. At time T5, the pre-charge signal PREi and the ISOso signal are deactivated, and the PCOM and NCOM voltages are activated, effectively enabling the single-ended sense amplifier SAo.i to latch a logic high data value (i.e. , a full read voltage is developed across the internal nodes INTO and INTO# of single-ended sense amplifier SAo,i). At time T6, the ISOso signal is re-activated, such that the read voltage developed on internal node INTO is driven onto bit line blo,i to refresh the bit cell bco,o. Shortly after time T6 (i.e., at time T7), the Y-address signal associated with bit line blo (i.e., Y-DEC[1]) is activated high (e.g., 1.1V), thereby coupling the internal node INTO to global bit line GBLo. Under these conditions, the voltage on global bit line GBLo is driven to a logic high voltage of about 250 mV (due to the capacitance of the global bit line structure, which is described in more detail below). Note that a read data voltage of about -200 mV is provided on the global bit line GBLo when a logic low data value is read from bit cell bco,i. The operation of the single-ended sense amplifier SAo.i is described in more detail in U.S. Patent Application Serial No. 18 / 399,579, which is hereby incorporated by reference in its entirety. Note that the Y-DEC[1] and GBLo signals are deactivated around time T9.

[0142] Fig. 11 B is a waveform diagram illustrating the control signals used to write a logic high data value from global bit line GBLo into single-ended sense amplifier SAo.i, and then transfer this data value from the single-ended sense amplifier SAo.i onto bit line blo.i and into bit cell bco in accordance with one embodiment. Processing proceeds in a similar manner as the read access of Fig. 11A between time T1 to T5, with exceptions noted below. In the illustrated embodiment, bit cell bco stores a logic low data value, such that the voltage on bit line blo is initially pulled down below 0V when the sub-word line SWLo.o is activated at time T2. Also at time T2, a write driver circuit within the secondary sense amplifier circuit SSAi,i (described in more detail below), drives a logic high write data value (250 mV) onto global bit line GBLo. Also at time T2, the Y-address signal associated with bit line blo (i.e., Y-DEC[1]) is activated high (e.g., 1.1V), thereby coupling the internal node INTO to global bit line GBLo. Under these conditions, the internal node INTO is driven to a voltage of 250 mV. At time T3, the activated kick voltage Vk drives the voltage on bit line blo down to -40mV. The ISOso signal is activated between time T4 and T5, whereby the 250 mV voltage on the internal node INTO is applied to bit line blo . Advantageously, the single-ended sense amplifier SAo.i is not activated until time T5 (i.e., PCOM and NCOM do not transitionT1until time T5). As a result, the write driver circuit does not need to flip the state of the single-ended sense amplifier SAo.i (i.e. , the write driver circuit only needs to overcome the relatively small voltage (-40mV) initially developed on the bit line blo.i at time T4).

[0143] At time T5, the pre-charge signal PREi and the ISOso signal are deactivated, and the PCOM and NCOM voltages are activated, effectively enabling the single-ended sense amplifier SAo.i to latch a logic high write data value (i.e., a full write voltage is developed across the internal nodes INTO and INTO# of single-ended sense amplifier SAo,i ). At time T6, the ISOso signal is re-activated, such that the write voltage developed on internal node INTO is driven onto bit line blo,i to write bit cell bco,i . Signal processing proceeds in the manner illustrated by Fig. 1 1 B to complete the write access. Note that the write driver circuit drives a voltage of -200 mV on the global bit line GBLo to write a logic low data value to bit cell bco,i. Note that the Y-DEC

[0001] and GBLo signals are deactivated around time T9.

[0144] Fig. 12 is a diagram illustrating the data channels of unit cell UCi ,i in accordance with one embodiment of the invention. As described above in connection with Fig. 10, each of the sub-array columns C0SA0-C0SA7 includes a set of 72 global bit lines, which extend in parallel along the X-axis through strips S(i ,i)o-S(i ,1)15. More specifically, sub-array columns C0SA0, C0SA1 , C0SA2, C0SA3, C0SA4, C0SA5, CoSAe and C0SA7 include 72-bit global bit line sets GBL0-GBL71 , GBL72-GBL143, GBL144- GBL215, GBL216-GBL287, GBL288-GBL359, GBL360-GBL431 , GBL432-GBL503 and GBL504- GBL575, respectively, as illustrated. These global bit lines GBL0-GBL575 are coupled to multiplexer MUXi,i . More specifically, global bit lines GBL0-GBL287 (which are associated with the left-side sub-arrays) are coupled to a first multiplexer section MUX(i,i)A of multiplexer MUXi,i , which is dedicated to data channel DATA_Ai of unit stack US1. Similarly, global bit lines GBL288-GBL575 (which are associated with the right-side sub-arrays) are coupled to a second multiplexer section MUX(I,IJB of multiplexer MUXi,i, which is dedicated to data channel DATA_Bi of unit stack US1.

[0145] If there is a read access to unit cell UC1 ,1 on data channel DATA_Ai , multiplexer section MUX(i,i)A is controlled to route a 72-bit data value from one of the 72-bit global bit line sets GBL0-GBL71 , GBL72-GBL143, GBL144-GBL215 or GBL216-GBL287 on global input / output (I / O) lines GIO0-GIO71.

[0146] Similarly, if there is a read access to unit cell UC1 ,1 on data channel DATA_Bi , multiplexer section MUX(i,i)B is controlled to route a 72-bit data value from one of the 72-bit global bit line sets GBL288-GBL359, GBL360-GBL431 , GBL432-GBL503 or GBL504-GBL575 on global I / O lines GIO72-GIO143.

[0147] Global I / O lines GIO0-GIO143 are coupled to secondary sense amplifier circuit SSAi,i. More specifically, global input / output lines GIO0-GIO71 are coupled to a first secondary sense amplifier section SSA(U)A of secondary sense amplifier circuit SSA1 ,1 , which is dedicated to data channel DATA_Ai of unit stack US1. Similarly, global input / output lines GIO72-GIO143 are coupled to a second secondary sense amplifier section SSA(U)B of secondary sense amplifier circuit SSAu , which is dedicated to data channel DATA_Bi of unit stack US1.

[0148] If there is a read access to unit cell UC1 ,1 on data channel DATA_Ai, secondary sense amplifier section SSA(U)A is controlled to route a 72-bit data value received from multiplexer section MUX(i,i)A to data channel DATA_Ai as two 36-bit data values. As described in more detail below, the secondary sense amplifier section SSA(i,i)A routes these two 36-bit data values at twice the frequency (2GHz) that the 72- bit data values are read from the sub-arrays (1 GHz). The 36-bit data values routed by the secondary sense amplifier section SSA(U)A are labeled DATA_Ai[0:35] in Fig. 12.

[0149] Similarly, if there is a read access to unit cell UC1 ,1 on data channel DATA_Bi, secondary sense amplifier section SSA(U)B is controlled to amplify and route a 72-bit data value received from multiplexer section MUX(i,i)B to data channel DATA_Bi as two 36-bit data values in the same manner that multiplexer section MUX(i,i)A amplifies and routes 72-bit data values to data channel DATA_Ai. The 36-bit data values routed by the secondary sense amplifier section SSA(U)B are labeled DATA_Bi[0:35] in Fig. 12.

[0150] It is understood that the secondary sense amplifier section SSA(U)A drives the output data values DATA_Ai[0:35] onto 36 corresponding TSVs in TSV set TSVi.i (and the secondary sense amplifier section SSA(U)B similarly drives the output data values DATA_Bi[0:35] onto 36 corresponding TSVs in TSV set TSVi.i).

[0151] Note that in other embodiments, the secondary sense amplifier sections SSA(i,i)A and SSA(i,i)B can route the received 72-bit data values in other manners. For example, in an alternate embodiment, secondary sense amplifier sections SSA(U)A and SSA(i,i)B may be configured to route the 72-bit data values received from multiplexer sections MUX(i,i)A and MUX(i,i)B to data channels DATA_Ai and DATA_Bi as four 18- bit data values a frequency of 4GHz. In this embodiment, the number of TSVs required to implement the corresponding unit stack US1 is advantageously reduced (by 36).

[0152] Further note that the read data paths described above are reversed for write operations (wherein secondary sense amplifier sections SSA(U)A and SSA(i,i)B include write driver circuits, which are described in more detail below).

[0153] Fig. 13 is a diagram illustrating the manner in which the signals on the global bit lines GBL0-GBL287 are routed to the multiplexer section MUX(i,i)A in accordance with one embodiment of the present invention. It is understood that the signals on global bit lines GBL288-GBL575 are routed to the multiplexer section MUX(i,i)B in the same manner.

[0154] In general, the global bit lines GBL0-GBL287 extend in parallel along the X- axis width of the strips S(i ,1 )o-S(i ,1)15, as illustrated. The signals of each set of 72 global bit lines are distributed horizontally along the X-Axis width of the multiplexer MUX(I ,I)A, in eight 9-bit groups. In one embodiment, horizontal metal lines (along the Y-axis) are used to distribute the signals from the global bit lines.

[0155] For example, a set of 36 metal lines MLo distribute the signals on global bit lines GBL0-GBL35 along the Y-axis, as illustrated. Nine of these 36 metal lines MLo distribute global bit lines GBLo-GBLs to the left (in the negative direction along the Y- axis), and 27 of these 36 metal lines distribute global bit lines GBL9-GBL35 to the right (in the positive direction along the Y-axis). Thus, the required layout height of the metal lines MLo along the X-axis is only 27 metal lines high.

[0156] Similarly, a set of 36 metal lines ML1 distribute the signals on global bit lines GBL36-GBL71 along the Y-axis, as illustrated. All 36 of these metal lines ML1 distribute global bit lines GBL36-GBL71 to the right (in the positive direction along the Y-axis). Thus, the required layout height of the metal lines ML1 along the X-axis is 36 metal lines high.

[0157] A set of 36 metal lines ML2 distribute the signals on global bit lines GBL72- GBL 107 along the Y-axis, as illustrated. Nine of these 36 metal lines ML2 distribute global bit lines GBL99-GBL107 to the right (in the positive direction along the Y-axis), and 27 of these 36 metal lines distribute global bit lines GBL72-GBL98 to the left (in the negative direction along the Y-axis). Thus, the required layout height of the metal lines ML2 along the X-axis is only 27 metal lines high.

[0158] Similarly, a set of 36 metal lines ML3 distribute the signals on global bit lines GBL 108-GBL143 along the Y-axis, as illustrated. All 36 of these metal lines ML3 distribute global bit lines GBL108-GBL143 to the right (in the positive direction along the Y-axis). Thus, the required layout height of the metal lines ML3 along the X-axis is 36 metal lines high.

[0159] A set of 36 metal lines ML4 distribute the signals on global bit lines GBL144- GBL 179 along the Y-axis in a pattern having a height of 36 metal lines along the X-axis, as illustrated.

[0160] A set of 36 metal lines MLs distribute the signals on global bit lines GBL o- GBL215 in a pattern having a height of 27 metal lines along the X-axis, as illustrated. In the illustrated embodiment, the set of metal lines MLs are located at the same latitude as the set of metal lines MLo, such that the set of metal lines MLs do not add to the required height of the metal line structure along the X-axis.

[0161] A set of 36 metal lines MLs distribute the signals on global bit lines GBL216- GBL251 along the Y-axis in a pattern having a height of 36 metal lines along the X-axis, as illustrated.

[0162] A set of 36 metal lines ML? distribute the signals on global bit lines GBL252- GBL287 in a pattern having a height of 27 metal lines along the X-axis, as illustrated. In the illustrated embodiment, the set of metal lines ML? are located at the same latitude as the set of metal lines ML2, such that the set of metal lines ML? do not add to the required height of the metal line structure along the X-axis.

[0163] The configuration of Fig. 13 requires a total of 27 + 27 + 36 + 36 + 36 + 36, or 198 horizontal metal line tracks, each extending in parallel with the Y-axis. Note that sufficient area for these 198 horizontal metal line tracks is provided by limiting the main word line configuration to one (metal) word line per eight sub-word lines as set forth above in connection with Fig. 7 (wherein the sub-word lines SWLo,o-SWL?,o are implemented using conductive polysilicon structures, rather than metal layer lines). The pitch between the metal main word lines (MWL) (along the X-axis) is equal to the height of 4 bit cells (along the X-axis), so the above-described configuration (of one metal main word line for each eight rows of bit cells) advantageously reduces the number of main word line tracks required within the unit cell by a factor of 2, thereby freeing up the necessary horizontal tracks for routing the global bit lines in the manner illustrated by Fig. 13.

[0164] The configuration of Fig. 13 requires 288 x 2 or 576 vertical metal lines, including 288 global bit lines GBL0-GBL287 and 288 metal lines that extend vertically along the X-axis from the metal line sets ML0-ML7 to the multiplexer section MUX(i,i)A.

[0165] Fig. 14 is a diagram illustrating the manner in which the global bit lines GBLo- GBL287 are distributed to the multiplexer section MUX(i,i)A in accordance with the present embodiment. Multiplexer section MUX(i,i)A includes eight 4-to-1 multiplexers MUXAO-MUXA7, wherein each of these multiplexers is coupled to 9 global bit lines from each of the four sub-array columns C0SA0-C0SA3. For example, multiplexer MUXAO is coupled to the nine global bit lines GBLo-GBLs of sub-array column C0SA0, the nine global bit lines GBL72-GBL80 of sub-array column C0SA1, the nine global bit linesGBL i44-GBLi52 of sub-array column C0SA2, and th© nine global bit lines GBL216-GBL224 of sub-array column C0SA3. This pattern is repeated for the remaining multiplexers MUXAI -MUXA7.

[0166] Multiplexers MUXAO-MUXA? are controlled by a pre-decoded sub-array column address COSAA[3:0], wherein the address values COSAA[0], COSAA

[0001] , COSAA[2] and COSAA[3], when activated, connect the global bit lines from sub-array columns C0SA0, C0SA1, C0SA2 and C0SA3, respectively, to the global I / O lines GIOo- GIO71. For example, a sub-array column address COSAA[3:0] of ‘000T will cause multiplexers MUXAO-MUXA7 to connect the global bit lines GBL0-GBL71 of sub-array column C0SA0 to the global I / O lines GIO0-GIO71. The pre-decoded sub-array column address COSAA[3:0] is provided on the instruction bus INST1.

[0167] It is understood that multiplexer MUX(i,i)B operates in the same manner as multiplexer MUX(i,i)A, although multiplexer MUX(i,i)B operates in response to the signals on global bit lines GBL288-GBL575, and is controlled by a separate pre-decoded subarray column address COSAB[3:0] (wherein the address values COSAB[0], COSAB

[0001] , COSAB[2] and COSAB[3], when activated, connect the global bit lines from sub-array columns C0SA4, C0SA5, CoSAe and C0SA7, respectively, to the global I / O lines GIO72- GIO143). The pre-decoded sub-array column address COSAB[3:0] is provided on the instruction bus INST1.

[0168] Fig. 15 is a diagram of secondary sense amplifier section SSA(U)A in accordance with one embodiment of the present invention. It is understood that secondary sense amplifier section SSA(i,i)B is configured and operates in the same manner as secondary sense amplifier circuit SSA(i,i)A. Secondary sense amplifier circuit SSA(i,i)A includes thirty-six identical ‘even’ read secondary sense amplifier circuits RSAo, RSA2, ... RSA70, which are coupled to receive read data values from ‘even’ global I / O lines GlOo, GIO2, ... GIO70, respectively, and thirty-six identical ‘odd’ read secondary sense amplifier circuits RSA1, RSA3, ... RSA71 , which are coupled to receive read data values from ‘odd’ global I / O lines GIO1 , GIO3, ... GIO71 , respectively. Each consecutive pair of even / odd read secondary sense amplifier circuits is coupled to a corresponding single bit (TSV) of the data bus DATA_Ai[0:35], For example, the even and odd read secondary sense amplifiers RSAo and RSA1 coupled to global input output lines GlOo and GIO1 , respectively, are commonly coupled to a TSV (of set TSVi,i) that carries the data bus signal DATA_Ai[0].

[0169] As described in more detail below, 72-bit read data on global I / O lines GIOo- GIO71 is transferred to secondary sense amplifier circuit SSA(U)A at a data rate of 1GHz, and 36-bit data is read from secondary sense amplifier circuit SSA(U)A at a data rate of 2 GHz. This advantageously minimizes the required number of TSVs required to transfer read data from unit stack USi to ASIC processor block 105i .

[0170] Secondary sense amplifier circuit SSA(U)A also includes thirty-six identical ‘even’ write secondary sense amplifier circuits WSAo, WSA2, ... WSA70, which are coupled to provide write data values to ‘even’ global I / O lines GlOo, GIO2, ... GIO70, respectively, and thirty-six identical ‘odd’ write secondary sense amplifier circuits WSA1, WSA3, ... WSA71, which are coupled to provide write data values to ‘odd’ global I / O lines GIO1 , GIO3, ... GIO71, respectively. Each consecutive pair of even / odd write secondary sense amplifier circuits is coupled to a corresponding single bit (TSV) of the data bus DATA_Ai[0:35], For example, the even and odd write secondary sense amplifiers WSAo and WSA1 coupled to global input output lines GlOo and GIO1, respectively, are commonly coupled to a TSV (of set TSVi,i) that carries the data bus signal DATA_Ai[0].

[0171] As described in more detail below, 36-bit write data on data bus DATA_Ai[0:35] is transferred to secondary sense amplifier section SSA(U)A at a data rate of 2 GHz, and 72-bit write data is transferred from secondary sense amplifier section SSA(U)A to global I / O lines GIO0-GIO71 at a data rate of 1 GHz. This advantageously minimizes the required number of TSVs required to transfer write data from ASIC processor block 105i to unit stack US1.

[0172] Figs. 16 and 17 are circuit diagrams of ‘even’ read secondary sense amplifier circuit RSAo and ‘odd’ read secondary sense amplifier circuit RSA1 , respectively, in accordance with one embodiment of the present invention. Because each of these read secondary sense amplifier circuits operate in response to the signal received on a single global I / O line, these read secondary sense amplifiers are ‘single-ended sense amplifiers’ as described herein.

[0173] Even read secondary sense amplifier circuit RSAo includes n-channel transistors 1601 -1608, p-channel transistors 1610-1613 and capacitors 1630-1631 , which are connected as illustrated in Fig. 16. N-channel transistors 1605-1606 and p- channel transistors 1612-1613 are connected to form a sense amplifier latch 1620 that includes cross-coupled inverters. P-channel transistors 1610 and 1611 form a preamplifier differential pair.

[0174] As illustrated by Fig. 17, odd read secondary sense amplifier circuit RSA1 includes n-channel transistors 1701 -1708, p-channel transistors 1710-1713 and capacitors 1730-1731 , which are connected in the same manner as n-channel transistors 1601 -1608, p-channel transistors 1610-1613 and capacitors 1630-1631 ofeven read secondary sense amplifier circuit RSAo. N-channel transistors 1705-1706 and p-channel transistors 1712-1713 are connected to form a sense amplifier latch 1720 that includes cross-coupled inverters. P-channel transistors 1710 and 1711 form a pre-amplifier differential pair. Odd read secondary sense amplifier circuit RSAi also includes an additional input stage that includes n-channel transistor 1740 and capacitor 1750.

[0175] Fig. 18 is a waveform diagram illustrating the operation of ‘even’ read secondary sense amplifier circuit RSAo and ‘odd’ read secondary sense amplifier circuit RSAi, in accordance with one embodiment of the present invention.

[0176] Although the present embodiment specifies particular voltages as the logic high voltages used to drive the various transistors of RSAo and RSAi, it is understood that other logic high voltages can be specified in other embodiments. In general, it is desirable for the logic high voltage to be as low as possible to achieve power savings, while being high enough to enable the controlled circuits to meet speed and / or headroom requirements. In various embodiments, the logic high voltage has a value in the range of 250 mV to 1 .1 Volts. It is noted that the use of specialized n-channel transistors fabricated in accordance with the MST process (described in commonly owned U.S. Patents 10,109,342 and 10,107,854, which are hereby incorporated by reference in their entireties) allows the logic high voltage to be increased (e.g., up to 200 mV greater than the baseline Vdd supply voltage of 1.1V), effectively overdriving n- channel transistors within RSAo and RSAi.

[0177] In the embodiments described below, the SAMPLE_E, SAMPLE_O, PRE_O and PRE_E control signals have logic high voltages of about 250 mV, the COMP1_E, COMP1_O, COMP2_E and COMP2_O control signals have logic high voltages of about 1.1 V to 1.3 V, and the OUT_ODD and OUT_EVEN control signals have logic high voltages of 250 mV to 350mV.

[0178] At time TO, data values Do and Di are read out of one of the sub-array columns C0SA0-C0SA3, and onto global I / O lines GlOo and GIO1, respectively, in the manner described above.

[0179] At time T1 , the read sample signal SAMPLE_E, which is applied to the gates of n-channel transistors 1601 and 1602 in RSAo and to the gate of n-channel transistor 1740 in RSAi, is activated from a logic low voltage (0V) to a logic high voltage (250m V). Under these conditions, transistors 1601 and 1740 turn on, such that the read data values on global I / O lines GlOo and GIO1 (i.e., Do and Di , respectively) are applied to (and are stored by) capacitors 1630 and 1750, respectively, as the input signals IN_Eand HOLD_O, respectively. In the embodiments described herein, the data values transmitted on the global I / O lines GlOo and GIOi, exhibit a logic low voltage of ground (OV) and a logic high voltage of 250 mV. Capacitor 1750 is large enough to ensure there is no noticeable charge leakage from this device during the time that the sampled data value must be stored as the HOLD_O value (e.g., a few ns).

[0180] Also under these conditions, transistor 1602 turns on, such that the reference voltage VREF is applied to (and is stored by) capacitor 1631 as the reference signal REF_E. In the embodiments described herein, the reference VREF (and therefore the reference signal REF_E) has a voltage a little less than half of the logic high voltage on the global I / O lines (e.g., a little less than 250mV / 2, or about 110 mV in one embodiment). Capacitors 1601 and 1602 are matched, and are large enough that there is no noticeable (e.g., 5% or less) differential signal coupling mismatch to transistors 1610 and 1611.

[0181] The input signal IN_E stored by capacitor 1630 is applied to the gate of p- channel transistor 1610 and the input signal REF_E stored by capacitor 1631 is applied to the gate of p-channel transistor 1611 , as illustrated. In the described embodiments, transistors 1610-1611 are identical, transistors 1601-1602 are identical, and capacitors 1630-1631 are identical, thereby balancing the inputs of read secondary sense amplifier RSAo.

[0182] At time T2, the comparator enable signal COMP1_E is activated from a logic low voltage (0V) to a logic high voltage of about 1.1 to 1 .3 Volts within read secondary sense amplifier circuit RSAo. Under these conditions, differential UP_E and D0WN_E voltages are developed on the drains of p-channel transistors 1610 and 1611 , respectively, wherein the D0WN_E voltage developed on the drain of transistor 1610 is representative of the voltage of the input signal I N_E , and the UP_E voltage on the drain of transistor 1611 is representative of the reference voltage REF_E applied to the gate of transistor 1611. In the described embodiment, the reference voltage REF_E is equal to 110 mV, which is slightly less than half of the logic high voltage of input signal IN_E (250mV).

[0183] If the voltage of the input signal IN_E is less than the reference voltage REF_E (i.e. , if IN_E is = 0V), then the voltage of the UP_E signal will be less than the voltage of the D0WN_E signal. Conversely, if the voltage of the input signal IN_E is greater than the reference voltage REF_E (i.e., if IN_E is = 250 mV), then the voltage of the UP_E signal will be greater than the voltage of the D0WN_E signal.

[0184] At time T2, the comparator enable signal COMP1_E is deactivated from the logic high voltage to a logic low voltage (0V), as illustrated. Also at time T2, the comparator enable signal COMP2_E is activated from a logic low voltage (0V) to a logic high voltage of about 1.1 V to 1 .3 V, thereby enabling sense amplifier latch 1620.

[0185] Under these conditions, sense amplifier latch 1620 amplifies the difference between the differential UP_E and DOWN_E voltages, such that the sense amplifier latch 1620 stores a data value representative of the voltage received on global I / O line GIOo. For example, if the UP_E voltage is less than the DOWN_E voltage, then latch 1620 will pull the DOWN_E voltage up to the voltage of the COMP2_E signal (350 mV), and will pull the UP_E voltage to ground. Conversely, if the UP_E voltage is greater than the D0WN_E voltage, then latch 1620 will pull the D0WN_E voltage down to ground, and will pull the UP_E voltage up to the voltage of the COMP2_E signal (e.g., 1.1V to 1.3V).

[0186] The UP_E and D0WN_E voltages are applied to the gates of n-channel transistors 1607 and 1608, respectively. As described above, when the sense amplifier latch 1620 is enabled, either the UP_E voltage or the D0WN_E voltage will be pulled up to 1 .1 to 1 .3 V, thereby turning on the corresponding n-channel transistor 1607 or 1608, respectively.

[0187] Just prior to time T2, the output control signal OUT_EVEN is driven from ground (0V) to the slightly boosted voltage of 350 mV. Thus, if the UP_E voltage is pulled up to 350 mV, the corresponding n-channel transistor 1607 is turned on, and the DATA_Ai[0] output signal is initially pulled up to 350 mV at the output of read secondary sense amplifier RSAo. Shortly after the sense amplifier latch 1620 is enabled (e.g., at time T4), the output control signal OUT_EVEN is reduced from 350 mV to 250 mV, such that the DATA_Ai[0] output signal is pulled up to 250 mV at the output of read secondary sense amplifier RSAo. The voltage at the output of read secondary sense amplifier RSAo is initially boosted based on the significant capacitance of the DATA_Ai[0] signal line structure (see, e.g., Fig. 4). The duration of this voltage boost is controlled such that the voltage received at the processor block 105i quickly reaches, but does not exceed, 250 mV.

[0188] Maintaining the OUT_EVEN signal at 0V from time TO until just prior to time T3 advantageously minimizes leakage current in n-channel transistor 1607 and reduces the power requirements of read secondary sense amplifier RSAo. However, it is understood that in other embodiments the OUT_EVEN voltage can be maintained at a voltage of 250mV (or 350mV) from time TO to time T3.

[0189] If the DOWN_E voltage is pulled up to the logic high voltage of 1 .1 to 1 ,3V when the sense amplifier latch 1620 is enabled at time T2, the corresponding n-channel transistor 1608 is turned on, and the DATA_Ai[0] output signal is pulled down to ground (0V) at the output of read secondary sense amplifier RSAo.

[0190] At time T5, the COMP2_E signal is deactivated from the logic high voltage (1.1 to 1 ,3V) to a logic low voltage (0V) as illustrated, thereby disabling the sense amplifier latch 1620, such that the secondary sense amplifier SSAEVEN no longer actively drives the DATA_Ai[0] signal. In the illustrated embodiment, the duration from time T2 to T5 (i.e. , the time that the output of the read secondary sense amplifier RSAo is active to drive the data value Do onto DATA_Ai[0]) is 0.5 ns, corresponding with an output data rate of 2GHz.

[0191] Pre-charge operations, which prepare the read secondary sense amplifier RSAo to receive the next data value on global I / O line GlOo, are then performed as follows.

[0192] Shortly after time T5, the PRE_E signal is activated from a logic low state (0V) to a logic high state (250 mV), thereby turning on n-channel pre-charge transistors 1603 and 1604. Under these conditions, the voltages of the UP_E and D0WN_E signals are pulled down to ground, thereby pre-charging these signals. The PRE_E signal is de-activated low (0V) to turn off transistors 1603-1604 prior to the next time the sense amplifier latch 1620 is enabled (e.g., at time T7 in Fig. 18).

[0193] The above-described signal pattern is repeated for successive accesses within read secondary sense amplifier RSAo. Thus, as illustrated by Fig. 18, the next read access from read secondary sense amplifier RSAo is initiated at time T6 (with the activation of the SAMPLE_E signal), and continues with the next read data value D2 being read out as the DATA_Ai[0] signal from time T7 to time T8.

[0194] Turning now to ‘odd’ read secondary sense amplifier RSA1 (Fig. 17) at time T10, the sample signal SAMPLE_O applied to the gates of n-channel transistors 1701 and 1702 is activated from a logic low voltage (0V) to a logic high voltage (250m V). Under this condition, transistor 1701 turns on, such that the data value previously received on global I / O line GIO1 and stored by capacitor 1750 as the HOLD_O voltage is applied to (and stored by) capacitor 1730 as the input signal IN_O.

[0195] Also under these conditions, transistor 1702 turns on, such that the reference voltage VREF is applied to (and is stored by) capacitor 1731 as the reference signal REF_O. As described above, the reference voltage VREF (and therefore the reference signal REF_O) has a voltage of about 110 mV in the described embodiments.

[0196] At time TH , the comparator enable signal COMP1_O is activated from a logic low voltage (0V) to a logic high voltage (1.1 to 1.3V) within odd read secondary sense amplifier circuit RSAi. Under these conditions, differential UP_O and D0WN_0 voltages are developed on the drains of p-channel transistors 1710 and 1711 , respectively, in the same manner the differential UP_E and D0WN_E voltages are developed on the drains of p-channel transistors 1610 and 1611 of the even read secondary sense amplifier RSAo.

[0197] At time T5, the comparator enable signal COMP1_O is deactivated from a logic high voltage (1.1 to 1 ,3V) to a logic low voltage (0V), as illustrated. Also at time T5, the comparator enable signal COMP2_O is activated from a logic low voltage (0V) to a boosted logic high voltage (1.1 to 1 ,3V), thereby enabling sense amplifier latch 1720. Just prior to time T5, the output control signal OUT_ODD is driven from ground (0V) to the slightly boosted voltage of 350 mV.

[0198] Under these conditions, sense amplifier latch 1720 operates in the same manner described above in connection with sense amplifier latch 1620, wherein sense amplifier latch 1720 amplifies the difference between the differential UP_O and D0WN_0 voltages, such that the sense amplifier latch 1720 stores a data value Di representative of the voltage received on global I / O line GIOi.

[0199] The UP_O and D0WN_0 voltages are applied to the gates of n-channel transistors 1707 and 1708, respectively. When the sense amplifier latch 1720 is enabled, either the UP_O voltage or the D0WN_0 voltage will be pulled up to 1.1 to 1.3V, thereby turning on the corresponding n-channel transistor 1707 or 1708, respectively. The OUT_ODD output control signal of read secondary sense amplifier RSAi is controlled in the same manner described above for the OUT_EVEN output control signal of read secondary sense amplifier RSAo. As a result, the read secondary sense amplifier RSAi drives the data value Di received on global I / O line GIOi onto the DATA_Ai[0] signal line starting from time T5.

[0200] At time T7, the COMP2_O signal is deactivated from the boosted logic high state (1.1 to 1.3V) to a logic low state (0V) as illustrated, thereby disabling the sense amplifier latch 1720, such that the read secondary sense amplifier RSAi no longer actively drives the DATA_Ai[0] signal. In the illustrated embodiment, the duration from time T5 to T7 (i.e. , the time that the output of the read secondary sense amplifier RSAi is active to drive the data value Di onto DATA_Ai[0]) is 0.5 ns, corresponding with an output data rate of 2GHz.

[0201] Pre-charge operations within read secondary sense amplifier RSAi are the same as the above-described pre-charge operations within read secondary sense amplifier RSAo. In fact, it is noted that the signals used to operate the ‘even’ read secondary sense amplifier RSAo between time TO and time T8 are identical to the signals used to operate the ‘odd’ secondary sense amplifier RSAi between time T3 and time T9.

[0202] It is further noted that the above-described operations are successively repeated in Fig. 18, wherein the next read data value D2 received on global I / O line GlOo is read out onto the DATA_Ai[0] signal line during the time period from T7 to time T8, and the next data value D3 received on global I / O line GIO1 is read out onto the DATA_Ai[0] signal line during the time period from T8 to time T9

[0203] Although Figs. 16-18 describe the transfer of data from the general I / O lines GlOo and GIO1 to the corresponding DATA_Ai[0] signal line, it is understood that data is transferred from all of the general I / O lines GIO0-GIO71 to the corresponding DATA_Ai[0:35] signal lines in parallel. In this manner, 36-bit read data is provided on the DATA_Ai[0:35] TSVs at a frequency of 2GHz. It is further understood that if the DATA_Bi channel is also accessed, data is also transferred from all of the general I / O lines GIO72-GIO143 to the corresponding DATA_Bi[0:35] TSVs in parallel (such that 36- bit read data is also provided on DATA_Bi[0:35] signal lines at a frequency of 2GHz).

[0204] Multiplexing the 72-bit data received on the global I / O lines GIO0-GIO71 (and / or GIO72-GIO143) at 1 GHz to 36-bit data on the TSVs associated with data bus DATA_Ai[0:71 ] (and / or DATA_Bi[0:71 ]) at 2GHz advantageously reduces the number of TSVs required to implement unit stack US1, while maintaining a relatively low data transfer frequency on these TSVs. Moreover, operating data buses DATA_Ai[0:71 ] and DATA_Bi[0:71 ] at a signal swing of 250mV advantageously minimizes the power requirements of data transmission on the corresponding TSVs.

[0205] Although the read operations have been described in connection with specific control voltages, it is understood that control voltages having other voltage levels can be used in other embodiments, corresponding with the particular characteristics of the unit cell UC1 ,1 (and unit stack US1). For example, although the logic high voltage on the global bit lines are specified as 250 mV, and the reference voltage VREF has been specified as 110 mV in the embodiments described above, it is understood that in other embodiments, these voltages may be scaled upward or downward. For example, in one embodiment (which implements transistors fabricated in accordance with MSTprocess technology), the logic high voltage on the global bit lines may be specified at 110 mV, and the reference voltage VREF may be specified at 45 mV.

[0206] Figs. 19 and 20 are circuit diagrams of ‘even’ write secondary sense amplifier circuit WSAo and ‘odd’ write secondary sense amplifier circuit WSAi, respectively, in accordance with one embodiment of the present invention. Because each of these write secondary sense amplifier circuits operate in response to the signal received on a single data line, these write secondary sense amplifiers are ‘single-ended sense amplifiers’ as described herein.

[0207] Write secondary sense amplifier circuit WSAo includes n-channel transistors 1901-1909 and 1940, p-channel transistors 1910-1915, and capacitors 1930-1931 and 1950, which are connected as illustrated by Fig. 19. N-channel transistors 1905-1906 and p-channel transistors 1912-1913 are connected to form a sense amplifier latch 1920 that includes cross-coupled inverters. P-channel transistors 1910 and 1911 form a pre-amplifier differential pair. N-channel transistor 1940 and capacitor 1950 form an additional input stage for ‘even’ data values to be provided to general I / O signal line GIOo. N-channel transistor 1909 and P-channel transistor 1914 are very small devices that form an inverter 1960, which along with p-channel transistor 1915, operate as a keeper circuit in a manner described in more detail below.

[0208] As illustrated by Fig. 20, ‘odd’ write secondary sense amplifier circuit WSAi includes n-channel transistors 2001-2009, p-channel transistors 2010-2015, and capacitors 2030-2031 , which are connected in the same manner as n-channel transistors 1901-1909, p-channel transistors 1910-1915, and capacitors 1930-1931 of ‘even’ write secondary sense amplifier circuit WSAo. Thus, n-channel transistors 2005- 2006 and p-channel transistors 2012-2013 are connected to form a sense amplifier latch 2020 that includes cross-coupled inverters. P-channel transistors 2010 and 2011 form a pre-amplifier differential pair. P-channel transistor 2014 and n-channel transistor 2009 form an inverter 2060, which along with p-channel transistor 2015, operate as a keeper circuit in a manner described in more detail below.

[0209] Fig. 21 is a waveform diagram illustrating the operation of ‘even’ write secondary sense amplifier circuit WSAo and ‘odd’ write secondary sense amplifier circuit WSAi, in accordance with one embodiment of the present invention.

[0210] At time TO, even write data value Do is provided by processor block 105i on the data bus DATA_Ai as the data signal DATA_Ai[0].

[0211] At time T1 , the write sample signal wSAMPLE_E, which is applied to the gate of n-channel transistor 1940 in WSAo, is activated from a logic low voltage (0V) to alogic high voltage (250mV or higher). Under these conditions, transistor 1940 turns on, such that the write data value Do on DATA_Ai[0] is applied to (and is stored by) capacitor 1950, as the input signal HOLD_E. In the embodiments described herein, the data values transmitted on the data bus DATA_Ai exhibit a logic low voltage of ground (0V) and a logic high voltage of about 250 mV. Capacitor 1950 is large enough to ensure there is no noticeable charge leakage from this device during the time that the sampled data value must be stored as the HOLD_E value (e.g., a few ns).

[0212] At time T2, odd write data value Di is provided by processor block 105i on the data bus DATA_Ai as the data signal DATA_Ai[0].

[0213] At time T3, the write sample signal wSAMPLE_O, which is applied to the gates of n-channel transistors 1901 -1902 in WSAo and to the gates of n-channel transistors 2001-2002 in WSAi, is activated from a logic low voltage (0V) to a logic high voltage (250mV or higher). Under these conditions, transistor 1901 withing WSAo turns on, thereby transferring the data value Do stored in capacitor 1950 as the HOLD_E signal is applied to (and stored by) capacitor 1930 as the write input signal wlN_E. Also under these conditions, transistor 2001 within WSAi turns on, such that the data value Di on DATA_Ai[0] is applied to (and is stored by) capacitor 2030, as the write input signal wlN_0.

[0214] Also under these conditions, transistors 1902 and 2002 turn on, such that the reference voltage VREF is applied to (and is stored by) capacitors 1931 and 2031 as the reference signals wREF_E and wREF_O, respectively. In the embodiments described herein, the reference VREF (and therefore the reference signals wREF_E and wREF_O) has a voltage a little less than half of the logic high voltage on the DATA_Ai bus (e.g., a little less than 250mV / 2, or about 110 mV in one embodiment).

[0215] Within WSAo, the input signal wlN_E stored by capacitor 1930 is applied to the gate of p-channel transistor 1910 and the input signal wREF_E stored by capacitor 1931 is applied to the gate of p-channel transistor 1911 , as illustrated by Fig. 19. Similarly, within WSAi, the input signal wlN_0 stored by capacitor 2030 is applied to the gate of p-channel transistor 2010 and the input signal wREF_0 stored by capacitor 2031 is applied to the gate of p-channel transistor 2011 , as illustrated by Fig. 20.

[0216] In the described embodiments, transistors 1910-1911 and 2010-2011 are identical, transistors 1901-1902 and 2001-2002 are identical, and capacitors 1930-1931 and 2030-2031 are identical are identical, thereby balancing the inputs of write secondary sense amplifiers WSA0-WSA1.

[0217] At time T4, the write comparator enable signal wCOMPI is activated from a logic low voltage (0V) to a logic high voltage (e.g., 1.1 to 1 ,3V) within write secondary sense amplifier circuits WSAo and WSAi . Under these conditions, differential wD0WN_E and wUP_E voltages are developed on the drains of p-channel transistors 1910 and 1911 , respectively, within WSAo, and differential wD0WN_0 and wUP_O voltages are developed on the drains of p-channel transistors 2010 and 2011 , respectively, within WSAi.

[0218] If the voltage of the input signal wlN_E is less than the reference voltage wREF_E (i.e., if wlN_E is = 0V), then the voltage of the wD0WN_E signal will be greater than the voltage of the wUP_E signal. Conversely, if the voltage of the input signal wlN_E is greater than the reference voltage wREF_E (i.e., if wlN_E is = 250 mV), then the voltage of the wD0WN_E signal will be less than the voltage of the wUP_E signal. The wUP_0 and wD0WN_0 signals are generated in a similar manner within WSAi in response to the wlN_0 and wREF_O signals.

[0219] At time T5, the comparator enable signal wCOMPI is deactivated from the logic high voltage to a logic low voltage (0V), as illustrated. Also at time T5, the comparator enable signal wC0MP2 is activated from a logic low voltage (0V) to a logic high voltage (e.g., 1.1 to 1.3V), thereby enabling sense amplifier latches 1920 and 2020 within WSAo and WSAi, respectively.

[0220] Under these conditions, sense amplifier latch 1920 amplifies the difference between the differential wUP_E and wD0WN_E voltages, such that the sense amplifier latch 1920 stores a data value representative of the data value Do received on data bus DATA_Ai. For example, if the wUP_E voltage is less than the wD0WN_E voltage, then latch 1920 will pull the wUP_E voltage down to ground, and will pull the wD0WN_E voltage up to the voltage of the wC0MP2 signal (1.1 to 1 ,3V). Conversely, if the wUP_E voltage is greater than the wD0WN_E voltage, then latch 1920 will pull the wD0WN_E voltage down to ground, and will pull the wUP_E voltage up to the voltage of the wC0MP2 signal (1.1 to 1 ,3V). The wUP_0 and wD0WN_0 signals are generated in a similar manner within WSAi in response to the wUP_0 and wD0WN_0 signals.

[0221] The wUP_E and wD0WN_E voltages are applied to the gates of n-channel transistors 1907 and 1908, respectively. As described above, when the sense amplifier latch 1920 is enabled, either the wUP_E voltage or the wD0WN_E voltage will be pulled up to 1.1 to 1.3V, thereby turning on the corresponding n-channel transistor 1907or 1908, respectively. The wllP_0 and wD0WN_0 signals control the corresponding n-channel transistors 2007 and 2008, respectively, in a similar manner within WSAi.

[0222] Just prior to time T5, the write input control signal wIN is driven from ground (0V) to the slightly boosted voltage of 350 mV. Thus, if the wD0WN_E voltage is pulled up to 1 .1 to 1 ,3V, the corresponding n-channel transistor 1908 is turned on, thereby coupling the global I / O line GlOo to ground. In this manner, the data value Do (Do = 0) is driven onto the global I / O line GlOo starting at time Ts. Note that the ground voltage applied to GlOo turns on p-channel transistor 1914 within inverter 1960, such that the Vdd supply voltage (1.1 to 1.3 V) is applied to the gate of p-channel transistor 1915, thereby turning off this transistor 1915. As a result, the keeper circuit formed by inverter 1960 and p-channel transistor is turned off when a logic low write data value is driven onto global I / O line GlOo.

[0223] Conversely, if the wllP_E voltage is pulled up to 1.1 to 1 ,3V, the corresponding transistor 1907 is turned on, thereby coupling the global I / O line GlOo to the wIN voltage of 350mV. In this manner, the data value Do (Do = 1 ) is driven onto the global I / O line GlOo starting at time Ts. Note that the logic high voltage (350 mV) applied to GlOo turns on p-channel transistor 1909 within inverter 1960, such that the ground voltage is applied to the gate of p-channel transistor 1915, thereby turning on this transistor 1915. The turned on p-channel transistor 1915 keeps the voltage on the global I / O line GlOo at the wIN voltage of 350 mV. In this manner, the keeper circuit formed by inverter 1960 and p-channel transistor is turned on when a logic high write data value is driven onto global I / O line GlOo.

[0224] Within WSAi, n-channel transistors 2007-2008, inverter 2060 and p-channel transistor 2015 operate in the above described manner to drive the data value Di onto global I / O line GIOi, starting at time T5.

[0225] At time T7, the wC0MP2 signal is deactivated (to ground), effectively disabling sense amplifier latches 1920 and 2020 within WSAo and WSAi, respectively. Shortly after time T7, the wPRE signal is activated, thereby pre-charging the sense amplifier latches 1920 and 2020 to ground, ahead of the next write operation.However, the data values Do and Di remain on the respective global I / O lines GlOo and GIOi until time T10. More specifically, global I / O lines GlOo and GIOi that were actively pulled to ground between time T5 and T7 will remain at ground until time T10, because there is no mechanism within WSAo or WSAi to pull the global I / O lines GlOo and GIOi up from ground (and the capacitances associated with the global I / O lines GlOo andGIOi and the global bit lines GBL inhibit any sudden voltage changes on these global I / O lines).

[0226] Global I / O lines GlOo and GIOi that were actively pulled to the positive wIN voltage (350 mV) between time T5 and T7 will be held at this positive wIN voltage by the corresponding keeper circuit until time T 10. For example, if the global I / O line GlOo is actively pulled up to the wIN voltage (350mV) between times T5 and T7, then the n- channel transistor 1909 of inverter 1960 and the p-channel transistor 1915 are turned on in the manner described above. When the n-channel transistor 1907 is turned off (in response to the wllP_E signal being pre-charged to ground shortly after time T7), the global I / O line GlOo continues to be held to the wIN voltage (350 mV) through turned on p-channel transistor 1915. Note that the small transistors (1909 and 1914) used to implement inverter 1960 allows this inverter 1960 to be easily overdriven in response to the next received write data value.

[0227] In the illustrated embodiment, the period between time TO and time T2 (i.e. , the period of the data value Do driven onto DATA_A1 [0]) is 0.5 ns, corresponding with an input data rate of 2 GHz on data bus DATA_Ai, and the period between time T5 and time T10 is 1 ns, corresponding with an input data rate of 1 GHz on global input / output lines GlOo and GIOi.

[0228] At time T5, the above described process begins again, wherein the next write data value D2 provided on data bus line DATA_Ai[0] at time T5 is stored in capacitor 1950 of WSAo in response to the activated wSAMPLE_E signal at time T6, and wherein the next write data value D3 provided on data bus line DATA_Ai[0] at time T7 is stored in capacitor 2030 of WSA1 in response to the activated wSAMPLE_O signal at time T8, and wherein the write data values D2 and D3 are driven onto global I / O lines GlOo and GIOi , respectively, from time T10 to time T13.

[0229] Although Figs. 19-21 describe the transfer of write input data from the DATA_Ai[0] signal line (TSV) to the corresponding general I / O lines GlOo and GIOi , it is understood that write input data is transferred from all of the DATA_Ai[0:35] signal lines to the corresponding general I / O lines GIO0-GIO71 in parallel. In this manner, 36- bit write data is provided on the DATA_Ai[0:35] signal lines at a frequency of 2GHz and 72-bit write data is provided on general I / O lines GIO0-GIO71 at a frequency of 1 GHz. It is further understood that if a write operation is also performed on the DATA_Bi channel, write input data is also transferred from the DATA_Bi[0:35] signal lines to the corresponding general I / O lines GIO72-GIO143 in parallel (such that 36-bit write data isprovided on the DATA_Bi[0:35] signal lines at a frequency of 2GHz, and 72-bit write input data is provided on general I / O lines GIO72-GIO143 at a frequency of 1 GHz).

[0230] Demultiplexing the 36-bit write data values received on DATA_Ai[0:71 ] signal lines (and / or the DATA_Bi[0:71 ] signal lines) at 2 GHz onto the 72-bit global I / O lines GIO0-GIO71 (and / or GIO72-GIO143) at 1 GHz advantageously reduces the number of TSVs required to implement unit stack US1, while maintaining a relatively low data transfer frequency on these TSVs.

[0231] The above-described control signals used to operate the read secondary sense amplifiers and the write secondary sense amplifiers are generated by secondary sense amplifier driver circuit SSADI .I (shown in Fig 6). The secondary sense amplifier driver circuit SSADi.i generates the control signals required to control the read secondary sense amplifiers (i.e., SAMPLE_E, SAMPLE_O, COMP1_E, COMP1_O, COMP2_E, COMP2_E, PRE_E, PRE_O, OUT_EVEN and OUT_ODD) in response to receiving signals on the instruction bus INST1 that specify a read access to unit cell UC1 ,1 (e.g., RW = 0, UC[3:0] = 0001 , CLK). Similarly, the secondary sense amplifier driver circuit SSADi.i generates the control signals required to control the write secondary sense amplifiers (i.e., wSAMPLE_E, wSAMPLE_O, wCOMPI , wC0MP2, wPRE and wIN) in response to receiving signals on the instruction bus INST1 that specify a write access to unit cell UC1 ,1 (e.g., RW = 1 , UC[3:0] = 0001 , CLK). As described above in connection with Fig. 6, the secondary sense amplifier driver circuit SSADi.i is centrally located within the secondary sense amplifier circuit SSAI .I in one embodiment. In one embodiment, secondary sense amplifier driver circuit SSADi.i separately controls the secondary sense amplifier sections SSA(U)A and SSA(i ,i)B, wherein the secondary sense amplifier section SSA(U)A is only activated if there is an access to one of the sub-array columns C0SA0-C0SA3, and the secondary sense amplifier section SSA(i,i)B is only activated if there is an access to one of the sub-array columns C0SA4-C0SA7.ADDRESSING / DATA PATH

[0232] The signals included on the instruction bus INST1 used to access the unit cells UC1 ,1 , UC2,1 , UC3,1 and UC4,i of unit stack US1 will now be described in more detail, along with the access patterns that can be implemented within the unit stack US1. It is understood that any combination (including all) of the unit stacks US1-US2048 of MTDRAM system 100 may be simultaneously and independently accessed in parallel using the addressing implementation described below, advantageously providing high data bandwidth within MDRAM system 100.

[0233] Fig. 22 is a block diagram representation illustrating the format of an instruction 2200 used to access the unit stack USi in accordance with one embodiment of the present invention. Unit stack access instruction 2200 is routed to each of the unit cells UCi ,1 , UC2,1, UC3,1 and UC4,i on dedicated instruction bus INSTi , as illustrated by Fig. 4.

[0234] Instruction 2200 includes a unit cell address field UC[3:0], a strip address field STRIP[15:0] which is shared by data channels DATA_Ai and DATA_Bi, a main word line address field MWL[11 :0] which is shared by data channels DATA_Ai and DATA_Bi , a sub-array column address field COSAA[3:0] associated with data channel DATA_Ai , a sub-array column address field COSAB[3:0] associated with data channel DATA_Bi , a sub-word line address field SWLA[7:0] associated with data channel DATA_Ai , a sub-word line address field SWLB[7:0] associated with data channel DATA_Bi , a Y-column address field Y-DEC[7:0] which is shared by data channels DATA_Ai and DATA_Bi , and a read / write signal field RW which is shared by data channels DATA_Ai and DATA_Bi .

[0235] The unit cell address field UC[3:0] specifies the unit cell (of unit cells UCi ,1 , UC2,i , UC3,i and UC4,i) to be accessed in response to the instruction. The signals of unit cell address field UC[3:0] are fully pre-decoded, such that the signals UC[3], UC[2], UC

[0001] and UC[0], when activated, specify accesses to unit cells UC4,i, UC3,i , UC2,i and UCi ,1 , respectively. The unit cell address UC[3:0] may specify up to one unit cell for an access. For example, an access to unit cell UCi,i is specified by a UC[3:0] value of ‘000T and an access to unit cell UC3,i is specified by a UC[3:0] value of ‘0100’.

[0236] The strip address field STRIP[15:0] specifies which one of the sixteen strips of the selected unit cell is accessed. In the described embodiments, the strip address value STRIP[15:0] specifies a single strip. When activated, the pre-decoded strip address bits STRIP

[0015] to STRIP[0] of instruction 2200 specify strips S(x,i)is to S(x,i)o, respectively, within the addressed unit cell UCx.i (wherein x = 1 to 4). Thus, an access to strip S(i,i)i4 of unit cell UCi,i is specified by a unit cell address value UC[3:0] of ‘000T and a strip address value STRIP[15:0] of ‘0100 0000 0000 0000’. Similarly, an access to strip S(2,i)i of unit cell UC2,i is specified by a unit cell address value UC[3:0] of ‘0010’ and a strip address value STRIP[15:0] of ‘0000 0000 0000 0010’.

[0237] The main word line address field MWL[11 :0] specifies which one of the 32 main word lines of the specified strip is activated. The signals of the main word line address field MWL[11 :0] are partially pre-decoded, wherein the signals MWL[11 :0] are used to select one of thirty-two main word lines within the selected strip. In oneembodiment, the eight main word line address signals MWL[4:11] are used to select one of eight sets of four main word lines, and the four main word line signals MWL[0:3] are used to select one of the four main word lines in the selected set.

[0238] Fig. 23 illustrates the main word line decoder circuit MWDo associated with strip S(i ,1)0 of unit cell UCi,i in accordance with one embodiment. Main word line decoder circuit MWDo includes 3-input AND gates AND0-AND32, which are connected as illustrated. If the received instruction specifies an access to strip S(i ,1 )o of unit cell UC1 ,1 (i.e., UC[0] = 1 and STRIP[0] = 1 ), then AND gate AND32 provides a logic high output signal to each of the 32 AND gates AND0-AND31 of main word line decoder circuit MWDo. Each of the eight main word line address signals MWL[4: 11 ] is provided to a corresponding set of four AND gates. More specifically, MWL[4] is provided to AND gates AN Do-AN D3, MWL[5] is provided to AND gates AND4-AND7, ... and MWL

[0011] is provided to AND gates AND28-AND31. Only one of the signals MWL[4: 11 ] is activated during an access.

[0239] Each of the four main word line address signals MWL[3:0] is provided to an AND gate in each of the eight sets of AND gates. More specifically, the signals MWL[0]-MWL[3] are provided to AND gates AN Do-AN D3, respectively, to AND gates AND4-AND7, respectively, ... and to AND gates AND28-AND31 , respectively. Only one of the signals MWL[3:0] is activated during an access. In this manner, one of the thirty- two main word lines MWL0-MWL31 is activated during an access to strip S(i ,1)0 of unit cell UC1 ,1. Because only two of the main word line address signals MWL[11 :0] are activated during an access, power savings are realized within the unit stack US1. Although a particular circuit has been described for decoding the signals required to activate the main word lines MWL0-MWL32, it is understood that other decoding circuits are possible, and would be apparent to one of ordinary skill.

[0240] It is noted that each of the strips of unit cells UCi,i , UC2,i, UCs.i and UC4,i includes a corresponding centrally located main word line decoder circuit (having the same circuitry as main word line decoder circuit MWDo), as illustrated by Fig. 6 (wherein each of these main word line decoder circuits operates in response to a corresponding strip address bit and a corresponding unit cell address bit). The timing of the main word line address signals MWL[0:11 ] is controlled to provide the desired timing of the main word line signal MWLo. This timing is described in more detail in U.S. Patent Application Serial No. 18 / 399,579, which is hereby incorporated by reference in its entirety.

[0241] The fully pre-decoded sub-array column address field COSAA[3:0] specifies one (or none) of the four sub-array columns C0SA0-C0SA3 associated with data channel DATA_Ai , and the fully pre-decoded sub-array column address field COSAB[3:0] specifies one (or none) of the four sub-array columns C0SA4-C0SA7 associated with data channel DATA_Bi . For example, a sub-array column address COSAA[3:0] having a value of ‘000T indicates that the sub-array column COSAo is selected for an access on data channel DATA_Ai , and a sub-array column address COSAB[3:0] having a value of ‘0010’ indicates that the sub-array column C0SA5 is selected for an access on data channel DATA_Bi .

[0242] The sub-array column address signals COSAA[3:0] and COSAB[3:0] are used in combination with the unit cell signals UC[3:0] and strip address signal STRIP[15:0] to generate the sub-array select signals (e.g., EN_SUBAo,o) used to enable the sub-word line driver circuits and primary sense amplifier sub-circuits in the sub-array(s) to be accessed.

[0243] Fig. 24 illustrates a sub-array decoder circuit 2400 associated with strip S(i ,1)0 of unit cell UC1 ,1 in accordance with one embodiment. In the described embodiment, the sub-array decoder circuit 2400 is centrally located within the strip S(i ,1)0, adjacent to the corresponding main word line decoder circuit MWDo. It is understood that each strip of unit stack US1 has a corresponding sub-array decoder circuit similar to subarray decoder circuit 2400 (wherein each of these sub-array decoder circuits operates in response to a corresponding strip address bit and a corresponding unit cell address bit).

[0244] Sub-array decoder circuit 2400 includes eight NAND gates 2410-2417, as illustrated. Each of these NAND gates 2410-2417 is coupled to the output of AND gate NAND32 (Fig. 23). Thus, sub-array decoder circuit 2400 is activated when the corresponding word line decoder circuit MWDo is activated. NAND gates 2410 to 2413 are also coupled to receive the sub-array column address signals COSAA[0] to COSAA[3], respectively. NAND gates 2414 to 2417 are also coupled to receive the subarray column address signals COSAB[0] to COSAB[3], respectively. The outputs of NAND gates 2410 to 2417 provide the sub-array enable signals EN_SUBAo,o to EN_SUBAO,7, respectively. As described above in connection with Fig. 7, the sub-array enable signals EN_SUBAo,o to EN_SUBAo,7, are provided to enable the sub-word line driver circuits in the sub-arrays SUBAo, 0 to SUBAo, 7, respectively. In the described embodiments, the sub-array enable signals EN_SUBAo,o to EN_SUBAo,7 are activated low (i.e. , enable a corresponding sub-word line driver circuit when having a logic lowvoltage) in a manner consistent with that described in U.S. Patent Application Serial No. 18 / 399,579.

[0245] At most, only one of the sub-array column address signals COSAA[3:0] is activated high, such that only one (or none) of the EN_SUBAo,o, EN_SUBAo,i, EN_SUBAO,2 and EN_SUBAo,3 signals is activated (low) for any given access. Similarly, at most, only one of the sub-array column address signals COSAB[3:0] is activated high, such that only one (or none) of the EN_SUBAo,4, EN_SUBAo,s, EN_SUBAO,6 and EN_SUBAo,7 signals is activated (low) for any given access.

[0246] For example, sub-array column address signals COSAA[3:0] having a value of ‘000T activates the EN_SUBAo,o signal, thereby activating the sub-word line drivers in sub-array SUBAo, o (see, e.g., Fig. 7). Sub-array column address signals COSAB[3:0] having a value of ‘0010’ activates the EN_SUBAo,s signal, thereby activating the subword line drivers in sub-array SUBAo, 5. If the sub-array column address signals COSAA[3:0] have a value of ‘0000’, then none of the sub-arrays SUBAo, o, SUBAo, 1 , SUBAo, 2, or SUBAo, 3, are activated (i.e. , no data is read on the corresponding data channel DATA_Ai). Similarly, sub-array column address signals COSAB[3:0] having a value of ‘0000’, result in no data being read on the corresponding data channel DATA_Bi . The timing of the sub-array column address signals COSAA[3:0] and COSAB[3:0] are controlled to provide the desired timing of the sub-array enable signals EN_SUBAo,o to EN_SUBAO,7. This timing is described in more detail in U.S. Patent Application Serial No. 18 / 399,579, which is hereby incorporated by reference in its entirety.

[0247] As described above in connection with Fig. 7, each main word line is coupled to eight corresponding sub-word lines. For example, main word line MWLo is coupled to eight corresponding sub-word lines SWLo.o to SWI_7,o via sub-word line driver circuits SWDo.o to SWD7,O. The sub-word line address value SWLA[7:0] includes eight predecoded sub-word line address signals, each associated with one of the eight sub-word lines associated with the activated main word line for data channel DATA_Ai . For example, if the instruction 2200 specifies the main word line MWLo of strip S(i , o of subarray SUBAo, o, then an activated sub-word line address signal SWLA[X] is used to activate the sub-word line SWLx.o associated with the activated main word line MWLo. In the described embodiments, the sub-word line address signals SWLA[7:0] and SWLB[7:0] are ‘activated’ to a logic low state. More specifically, a sub-word line address value SWLA[7:0] having a value of ‘1111 1110’ (i.e., SWLA[0] is activated) isused to activate the sub-word line SWLo.o associated with the activated main word line MWLo.

[0248] Each of the sub-word line address values SWLAA[7:0] is provided to a corresponding sub-word line driver circuit associated with the corresponding sub-word line. For example, in Fig. 7, each sub-word line address value SWLAA[X] is provided to a corresponding sub-word line driver circuit SWDx.o (wherein x = 0 to 7).

[0249] When a sub-word line driver circuit receives an activated sub-array enable signal EN_SUBA, an activated main word line signal, and an activated sub-word line address signal, the sub-word line driver circuit drives the corresponding sub-word line to a high state to implement an access to the bit cells coupled to the sub-word line. For example, if the instruction 2200 specifies the main word line MWLo of strip S(i , o of subarray SUBAo, o within unit cell UCi ,1 , and the sub-word line address value SWLA[7:0] specifies the sub-word line SWLo.o associated with the activated main word line MWLo, then the MWLo, EN_SUBAo,o and SWLA[0] signals will all be activated, thereby enabling sub-word line driver SWDo.o to activate sub-word line SWLo.o, thereby accessing bit cells bco.o to bco,575. In one embodiment, the activated sub-word line address value SWLA[0] is controlled to transition to a logic high state, and then transition to a boosted logic high state partway through the access to sub-word line SWLo.o. This process is described in more detail in U.S. Patent Application Serial No. 18 / 399,579, which is hereby incorporated by reference in its entirety.

[0250] As described above in connection with Figs. 7 and 8, data read from bit cells bco.o-bco.575 is latched into the corresponding primary sense amplifier sub-circuits PSAo.o and PSAi.o in response to the activated EN_SUBAo,o signal.

[0251] Similarly, the sub-word line address value SWLB[7:0] is a pre-decoded address value that specifies one of the eight sub-word lines associated with the activated main word line within data channel DATA_Bi . In the described embodiment, the sub-word line address value SWLB[7:0] is independent of the sub-word line address value SWLA[7:0], enabling different sub-word lines to be accessed in data channels DATA_Ai and DATA_Bi . This advantageously provides flexibility in addressing the sub-arrays within these two data channels. In an alternate embodiment, a single subword line address value SWL[7:0] is used to select the sub-word line in both data channels DATA_Ai and DATA_Bi . This embodiment advantageously reduces the number of TSVs required to implement unit stack USi by 8.

[0252] Instruction 2200 also includes a pre-decoded Y-address value Y-DEC[7:0] that selects one of eight 72-bit data values stored in the primary sense amplifier subcircuits in the access, in the manner described above in connection with Figs. 8-10.

[0253] Instruction 2200 also includes a read / write control bit (RW), which indicates whether the corresponding access is a read operation or a write operation.

[0254] Thus, the pre-decoded instruction 2200 requires 65 TSVs in the corresponding TSV region of the unit cell. When added to the 72 TSVs required to implement the two 36-bit data buses DATA_Ai and DATA_Bi, and the TSV required to provide the clock signal CLK, the entire unit stack USi requires a total of 138 TSVs. In the alternate embodiment where both data channels DATA_Ai and DATA_Bi share a single sub-word line address, the unit stack USi only requires a total of 130 TSVs.

[0255] The dimensions of unit cell UCi ,1 , along with the manner in which the TSVs of the unit cell UCi,i are laid out will now be described.Unit cell height

[0256] In accordance with the embodiments described above, each MTDRAM bit cell of unit cell UCi,i (e.g., bit cell bco.o of Fig. 7) has a vertical height along the Y-axis of 0.0243 microns (urn). In the embodiment of Fig. 8, unit cell UCi,i includes 576 columns of bit cells per sub-array, and 8 sub-arrays per strip. In this embodiment, the height along the Y-axis required for the bit cells is about 112 microns (0.0243 urn x 576 bit cells / sub-array x 8 sub-arrays / strip).

[0257] In the embodiment of Fig. 8, each strip of unit cell UCi,i includes 8 sub-word line driver circuits and one main word line driver circuit along the Y-axis. Assuming each sub-word line driver circuit has a height along the Y-axis of about 1 ,86um, and the main word line driver circuit has a height along the Y-axis of about 7um, then the height along the Y-axis required for the sub-word line driver circuits and the main word line driver circuit is about 22um (1 .855 urn x 8 + 7um).

[0258] Thus, the total height of the unit cell UCi,i along the Y-axis is about 134um (112 + 22). Assuming a TSV pitch of 2um, a row of TSVs extending the height of the unit cell UCi,i may include up to about 67 TSVs.

[0259] Fig. 25 is a block diagram illustrating the layout of the 137 TSVs required to service unit cell UCi,i in the manner described above. It is noted that unit cells UC2,i, UC3,1 and UC4,i have the same TSV pattern as unit cell UCi,i to facilitate the required connections of the corresponding unit stack USi. The TSV pattern of Fig. 25 utilizes three rows of TSVs located adjacent to the secondary sense amplifier SSAi . Eachrow of TSVs include 44 or fewer TSVs, easily allowing this TSV pattern to be located within the 134 um height of unit cell UCi,i.

[0260] In the embodiment of Fig. 25, the twelve TSVs carrying the main word line address MWL[11 :0] are centrally located (under the main word line driver circuits MWD). Six of these twelve TSVs are located in open space between the secondary sense amplifier circuits SSA(U)A and SSA(i,i)B and / or in open space between multiplexer circuits MUX(i,i)A and MUX(I,I)B, as illustrated. The remaining six TSVs are located in the three rows of TSV located below the secondary sense amplifier SSAi ,1 , as illustrated.

[0261] The 36 TSVs required to implement the DATA_Ai[35:0] bus are shown as shaded circles in Fig. 25. Note that these TSVs are evenly distributed along the width of the secondary sense amplifier circuit SSA(i,i)A, wherein 9 bits of the DATA_Ai[35:0] bus are located along each of the four sub-array columns C0SA0-C0SA3, thereby minimizing signal delay and power.

[0262] The 36 TSVs required to implement the DATA_Bi[35:0] bus are shown as black-filled circles in Fig. 25. Note that these TSVs are evenly distributed along the width of the secondary sense amplifier circuit SSA(i,i)B, wherein 9 bits of the DATA_Bi[35:0] bus are located along each of the four sub-array columns C0SA4- C0SA7.

[0263] The TSVs required to implement the UC[3:0] address values, the STRIP[15:0] address values, the COSAA[3:0] and COSAB[3:0] address values, the SWLA[7:0] and SWLB[7:0] address values, the Y-DEC[7:0] address values, the RW value and the CLK signal are distributed as illustrated by Fig. 25.

[0264] In accordance with one embodiment, the TSV pattern is selected such that most of the TSVs are centrally located within the unit cell UC1 ,1 (along the Y-axis). That is, the TSV pattern is sparsely populated at the outer edges along the Y-axis (i.e. , under sub-array columns C0SA0-C0SA1 and C0SA6-C0SA7). As described in more detail below, these sparsely populated TSV regions advantageously provide room for routing structures (which extend along the X-axis) on the underlying processor block 105i .

[0265] Having determined the configuration of the TSVs of unit cell UC1 ,1 , the width of the unit cell UC1 ,1 along the X-axis can be determined.Unit cell width

[0266] In accordance with the embodiments described above, each MTDRAM bit cell of unit cell UC1 ,1 (e.g., bit cell bco.o of Fig. 7) has a width along the X-axis of 0.0383um. In the embodiment of Fig. 8, unit cell UC1 ,1 includes 256 rows of bit cells perstrip, and 16 total strips. In this embodiment, the width along the X-axis required for the bit cells is about 156.88 microns (0.0383 urn x 256 bit cells / strip x 16 strips / unit cell).

[0267] In the embodiment of Fig. 6, unit cell UCi,i includes 17 primary sense amplifier circuits PSA0-PSA16. Assuming each primary sense amplifier circuit has a width along the X-axis of about 2.65um, then the width along the X-axis required for the primary sense amplifier circuits is about 45.05um (2.65um x 17).

[0268] In the embodiment of Fig. 6, unit cell UC1 ,1 also includes multiplexer MUXi,i and secondary sense amplifier circuit SSAo.o. In one embodiment, the width of multiplexer MUXi,i and secondary sense amplifier circuit SSAo.o along the X-axis is about 10um (based on the circuitry of Figs. 14-20).

[0269] In accordance with the embodiment of Fig. 25, unit cell UC1 ,1 requires three rows of TSVs, with a pitch of 2 urn. Thus, the required width of the TSV set TSVi.i along the X-axis is about 6um.

[0270] The total required width of unit cell UC1 ,1 along the X-axis is therefore about 222um (156.88um + 45.05um + 10um + 4um + 6um) in the described embodiment.

[0271] Because the MTDRAM chip 101 includes 64 rows and 32 columns of unit cells UC1 ,1 -UC1 ,2048 (Fig. 2), the total required width of chip 101 is about 7.1 mm (32 x 222um) along the X-axis, and the total required height of chip 101 is about 8.6mm (64 x 134um) along the Y-axis. Thus, MTDRAM chip 101 has an advantageous size in view of conventional fabrication practices. This is due to the significant amount of signal predecoding being performed by the ASIC controller chip 105 for accesses to all four MTDRAM chips 101 -104. Furthermore, obsolete functionality, such as self-refresh and other area-consuming features typically included in prior art DRAMs, is either removed completely or is implemented on the ASIC controller chip 105.

[0272] In alternate embodiments of the present invention, the number of sub-arrays per strip and the number of strips per unit cell can be modified to make the unit cell size larger or smaller, as desired. In a ‘tiny cell’ embodiment, the number of sub-arrays per strip is reduced from eight to four, and the number of strips per unit cell is reduced from sixteen to eight. This ‘tiny cell’ configuration increases the number of unit cells per chip from 2048 to 8192, thereby greatly increasing the addressable locations within the MTDRAM system.

[0273] The random access cycle time to the same strip is 4ns, and the random access cycle time to ‘legal’ strips (i.e. , strips that are not subject to pre-charging conditions as described above) is 1 ns. The nearly random access rate of MTDRAM system 100 (for 72-bit data) is therefore 1 GHz / channel x 2 channels / unit stack x 2048unit stacks = 4.096E+12. This nearly random access rate is about 12,800 times greater than the semi-random address rate of 3.2E+08 achieved by conventional HBM3 memory.

[0274] A MTDRAM system that implements the ‘tiny cell’ embodiment will exhibit a nearly random access rate of 1 GHz / channel x 2 channels / unit stack x 8192 unit stacks = 1 .6384E+13, which is about 51 ,200 times greater than the semi-random address rate of 3.2E+08 achieved by conventional HBM3 memory.

[0275] As described above, the data rate on the TSVs that implement the DATA_Ai and DATA_Bi channels is 2 Gb / sec / pin. This data rate is advantageously lower than the data rate of 5.2 Gb / sec / pin associated with a conventional HBM3 memory, advantageously resulting in significant power savings.

[0276] As described above, MTDRAM system 100 includes 72 TSVs to carry data signals per unit stack. Because MTDRAM system 100 includes 2048 unit stacks, a total of 147,456 TSVs are available to carry data in MTDRAM system 100. Because data is transmitted on each of these TSVs at a rate of 2Gb / sec, the total data rate of MTDRAM system is 147,456 x 2 Gb / sec = 294,912 Gb / sec. This total data rate is about 55 times greater than the total data rate of a conventional HBM3 memory system, which exhibits a total data rate of about 5,325 Gb / sec. This total data rate is also about 16 times greater than the total data rate of a conventional HBM3E memory system, which exhibits a total data rate of about 18,842 Gb / sec.

[0277] A MTDRAM system that implements the ‘tiny cell’ embodiment will include 8,192 unit stacks, with a total of 589,824 TSVs available to carry data. With data transmitted on each of these TSVs at a rate of 2Gb / sec, the total data rate of a MTDRAM system the implements the ‘tiny cell’ embodiment is 589,824 x 2 Gb / sec = 1 ,179,648 Gb / sec.

[0278] Fig. 26 is a block diagram of an arrayed processor system 2600 in accordance with one embodiment of the present invention. Arrayed processor system 2600 includes an 8x8 array of MTDRAM processor systems MDPo-MDPes, sixteen stacked flash memory systems FMS0-FMS15, eight communication control chips COMo- COM7, eight power management chips PMC0-PMC7, two high-speed optical communication links OPT0-OPT1 , and power supply / cooling structure 2605. As described in more detail below, the above-described elements of the arrayed processor system 2600 are mounted on (and interconnected by) an interconnect structure 2610 that includes a silicon substrate (e.g., wafer) with a plurality of patterned metal interconnect layers formed thereon.

[0279] In the embodiment illustrated by Fig. 26, each of the MTDRAM processor systems MDPo-MDPes is identical to MTDRAM system 100 (Fig. 1 ). Thus, each of the MTDRAM processor system systems MDPo-MDPes includes an ASIC controller chip and plurality of (4) MTDRAM chips, which are connected in a stack. More specifically, each MTDRAM processor system includes a plurality of (2048) independent unit stacks, wherein each unit stack includes: a processor block on the ASIC controller chip and a corresponding plurality of (4) MTDRAM unit cells (i.e. , one MTDRAM unit cell per MTDRAM chip). In general, each processor block can transfer data to / from its corresponding plurality of 4 MTDRAM unit cells, in the manner described above.

[0280] Because there are so many processor blocks (2048) within each of the MTDRAM processor systems MDPo-MDPes, and there are so many MTDRAM processor systems (64) in arrayed processor system 2600, it is desirable to have an efficient communication system for transmitting data between all of the processor blocks within the arrayed processor system 2600. It is also desirable to have an efficient communication system that allows data to be transmitted between the processor blocks of MTDRAM processor systems MDPo-MDPes and the stacked flash memory systems FSM0-FMS15. It is also desirable to have an efficient communication system that allows data to be transmitted between the processor blocks of MTDRAM processor systems MDP0-MDP63 and the optical communication links OPT0-OPT1. Accordingly, the present invention provides various communication elements within the ASIC controller chips of the MTDRAM processor systems MDPo-MDPes and within the silicon substrate interconnect structure 2610 to enable the data transmissions specified above.

[0281] As described in more detail below, the silicon substrate interconnect structure 2610 includes a set of connections which enable the transmission of data horizontally (along the X-axis) between the plurality of MTDRAM processor systems MDPo-MDPes (and also between the MTDRAM processor systems MDP0-MDP63 and the stacked flash memory systems FMS0-FMS15). The silicon substrate interconnect structure 2610 also includes a set of connections which enable the transmission of data vertically (along the Y-axis) within (and between) the plurality of MTDRAM processor systems MDP0-MDP63 (and also between the MTDRAM processor systems MDPo-MDPes and the communication management chips COM0-COM7).

[0282] As illustrated by Fig. 26, the plurality of stacked flash memory systems FMSo- FMS15 are located at opposite edges of the array of MTDRAM processor systems MDP0-MDP63. In one embodiment, each of the stacked flash memory systems FMSo-FMSis includes an ASIC controller chip coupled to a plurality of flash memory chips in a stacked configuration similar to that described above in connection with MTDRAM system 100. In this embodiment, each of the stacked flash memory systems FMSo- FMS15 includes a plurality of independent flash unit stacks, wherein each flash unit stack includes a corresponding processor block and a corresponding plurality of stacked flash unit cells, which operate in a similar manner as the processor block and MTDRAM unit cells of an MTDRAM unit stack within MTDRAM system 100. That is, the stacked flash memory systems FMS0-FMS15 are similar to the MTDRAM processor systems MDP0-MDP63, wherein the stacked flash memory systems FMS0-FMS15 implement flash memory cells, rather than MTDRAM memory cells. In one embodiment, the flash memory cells operate at a relatively slow access frequency, wherein data read from the flash memory cells is serialized using a high speed interface included in the flash unit cell, and the serialized data is provided to a corresponding processor block. In one embodiment, each of the flash memory chips includes fewer than 2048 stacked flash unit cells, based on given limitations of flash memory technology. In particular embodiments, each of the flash memory chips may include 256 (4x64) to 512 (8x64) flash unit cells.

[0283] As illustrated by Fig. 26, the plurality of communication management chips COM0-COM7 are located at an upper edge of the array of MTDRAM processor systems MDP0-MDP63, wherein a plurality of high speed connections are included within the interconnect structure 2610 to transmit data vertically (along the Y-axis) between the communication management chips COM0-COM7 and the array of MTDRAM processor systems MDPo-MDPes.

[0284] In accordance with another embodiment, the plurality of communication management chips COM0-COM7 are further connected to a plurality of high-speed optical communication links OPT0-OPT1, which allow for the transmission of data between the communication management chips COM0-COM7 and other external (e.g., remote) communication devices. Although high-speed optical links are designated in the present embodiments, it is understood that other high-speed communication links (e.g., satellite communication links) can be used in other embodiments. In one embodiment, the high-speed optical communication links OPT0-OPT1 can transfer data anywhere in the world almost instantaneously.

[0285] In accordance with another embodiment, the plurality of power management chips PMC0-PMC7 receive power (e.g., the required supply voltages) from power supply / cooling structure 2605. Power management chips PMC0-PMC7 distribute thereceived power supply voltages to the other elements of arrayed processor system 2600 via a power distribution network implemented by connections within interconnect structure 2610.

[0286] In addition to routing the required power supply voltages to power management chips PMC0-PMC7, the power supply / cooling structure 2605 also provides the necessary cooling for arrayed processor system 2600. For example, cooling may be provided by forced air and / or forced liquid circulation.

[0287] In accordance with one embodiment, the interconnect structure 2610 includes metal lines formed over a silicon substrate using conventional processing techniques, wherein the array of MTDRAM processor systems, the stacked flash memory systems, communication management chips and power management chips are mounted on the silicon substrate interconnect structure 2610 using conventional bump technology, or any other conventional chip mounting technology compatible with the TSV pitch implemented by the various elements of the arrayed processor system 2600. In a particular embodiment, the silicon substrate interconnect structure 2610 may contain up to 50-100 patterned metal layers (or more) having loose dimensional specifications, when compared to metal layers typically found in a state of the art modern logic chip. That is, the metal widths and spacings necessary to implement interconnect structure 2610 are much larger than the metal widths and spacings required on the MTDRAM chips and ASIC communication chips described herein, advantageously allowing the use of lower cost materials and systems in the fabrication of silicon substrate interconnect structure 2610. In a particular embodiment, silicon substrate interconnect structure 2610 is fabricated on an inexpensive 6 inch silicon wafer, with contact-printed metal layers (which do not require expensive reticles). Advantageously, the silicon substrate interconnect structure 2610 exhibits a similar coefficient of expansion as the attached silicon-based structures (e.g., ASIC controller chip 105 and MTDRAM chips 101-104), increasing reliability of the arrayed processor system 2600. Note that conventional FR4-based interconnect structures exhibit a different coefficient of expansion than silicon-based structures, which can result in failures based on repeated temperature cycling.

[0288] Fig. 27 is a top view representation of the layout of the 2048 processor blocks 105i -1052048 which are included in the 2048 unit stacks US1-US2048, respectively, of MTDRAM processor system MDPo (which has the same configuration as MTDRAM system 100). As described above, data can be transferred locally (along the Z-axis) between each processor block and the MTDRAM unit cells of its corresponding unitstack (e.g., data can be transferred locally between processor block 105i and unit cells UCi,i, UC2,i, UC3,i and UC4.1, within unit stack USi).

[0289] In addition, data can be transferred in an intra-chip manner between each of the processor blocks 105i -1052048 on ASIC controller chip 105. In general, data can be transferred horizontally (along the X-axis) and / or vertically (along the Y-axis) between the 2048 processor blocks 105i -1052048 on ASIC controller chip 105.

[0290] In addition, within arrayed processor system 2600, data can be transferred in an inter-chip manner between the processor blocks included in the ASIC controller chips included in the MTDRAM processor systems MDPo-MDPes, the stacked flash memory systems FMS0-FMS15, and the communication management chips COMo- COM7. The manner in which the inter-chip and intra-chip communications are performed is described in more detail below.

[0291] As illustrated by Fig. 27, a set of sixty-four horizontal transport controllers HTC1-HTC64 are centrally located (along the X-axis) within each of the 64 rows of processor blocks. For example, horizontal transport controller HTC1 is located within processor blocks 105ie and 105i7 of the first row of processor blocks. Although not individually numbered in Fig. 27, it is understood that the sixty-four horizontal transport controllers HTC1-HTC64 are sequentially numbered from top to bottom in Fig. 27.

[0292] In accordance with one embodiment, each of the processor blocks that include the horizontal transport controllers HTC1-HTC64 (e.g., processor blocks 105i6 and 105i7, which include the horizontal transport controller HTC1 in the first row of processor blocks) do not include vertical transport controllers (described below) or other logic, which is present in processor blocks that do not include the horizontal transport controllers HTC1-HTC64. In this manner, the processor blocks that include the horizontal transport controllers HTC1-HTC64 have a different configuration (and functionality) than the other processor blocks of ASIC controller chip 105.

[0293] Fig. 28 generally illustrates the first row of processor blocks of ASIC controller chip 105, including processor blocks 105i -10532. Each of the processor blocks 1051-10532 includes a processor nexus, which is illustrated as a rectangle within the processor block. For example, processor block 105i includes processor nexus 10i . It is understood that each processor nexus controls accesses to the corresponding MTDRAM unit cells of the corresponding MTDRAM unit stack (as well as accesses external to the processor block 105i ). Each processor nexus is also configured to perform various operations (such as comparison operations) on data received from its corresponding MTDRAM unit cells, as well as data received from locations external tothe processor block (e.g., along the horizontal and vertical communication paths described below). In accordance with one embodiment, all (or most) of the processor nexuses on ASIC controller chip 105 have the same configuration, enabling a large plurality of similar operations to be performed in parallel. In another embodiment, all (or most) of the processor nexuses on ASIC controller chip 105 have different configurations, enabling a large plurality of different operations to be performed in parallel. In another embodiment, a combination of these two embodiments may be implemented.

[0294] Horizontal interconnect structures 2801-2802 provide horizontal communication paths (along the X-axis) that allow the processor nexuses within each of the processor blocks 105i -10532 to communicate with one another (and with horizontal transport controller HTCi). More specifically, horizontal interconnect structures 2801- 2802 enable the transmission of data / control information between any of the processor blocks 1051-10532. Horizontal interconnect structures 2801-2802 also enable any of the processor blocks 105i -10532 to transfer data / control information to / from the horizontal transport controller HTCi. Although horizontal interconnect structures 2801-2802 are illustrated as continuous buses in Fig. 28, it is understood that horizontal interconnect structures 2801-2802 are divided into smaller segments (or wheels) to avoid direct long distance signal transmission across the entire ASIC controller chip 105. For example, each smaller segment (or wheel) may facilitate horizontal transmission across up to four processor blocks, with repeaters being used to transmit signals horizontally between segments (wheels), if necessary. The horizontal interconnect structures 2801- 2802 (including the repeaters within these structures) and the horizontal transport controller HTCi are designed to have enough bandwidth to keep data moving continuously through the arrayed processor system 2600, with no gaps or stalls.Design parameters that can be varied to achieve this bandwidth include, but are not limited to, data transmission frequency, data signal swing and data bus width and length. These parameters can further be adjusted in consideration of trade-offs necessitated by power and area limitations.

[0295] As illustrated by Fig. 28, horizontal interconnect structure 2801 extends along an upper edge of the row of processor blocks 105i -10532 and horizontal interconnect structure 2802 extends along a lower edge of the row of processor blocks 105i -10532. Within each of the processor blocks 105i -10532, the corresponding processor nexus is coupled to both of the horizontal interconnect structures 2801-2802, as illustrated. Forexample, processor nexus 10i of processor block 105i is coupled to both of the horizontal interconnect structures 2801 -2802.

[0296] In the illustrated described embodiments, horizontal interconnect structures 2801 and 2802 each include a plurality of bus lines which are fabricated in the metal layers of ASIC controller chip 105. As described above in connection with Fig. 25, the TSV pattern associated with the MTDRAM unit cells (and therefore the TSV pattern existing in the underlying processor block) is intentionally sparsely populated at the upper and lower edges (along the Y-axis) of each MTDRAM unit cell. This configuration advantageously provides room for locating the metal bus lines of the horizontal interconnect structures 2801 -2802 in the locations illustrated by Fig. 28.

[0297] The horizontal interconnect structures 2801 and 2802 are also coupled to the horizontal transport controller HTCi . As described in more detail below, the horizontal transport controller HTCi is coupled to other horizontal transport controllers external to ASIC controller chip 105, thereby providing horizontal communication paths between the processor blocks 105I-10532 on ASIC controller chip 105 and horizontally aligned processor blocks external to ASIC controller chip 105.

[0298] It is understood that the remaining horizontal transport controllers HTC2- HTC64 of ASIC controller chip 105 are coupled to their corresponding rows of processor blocks in the same manner that horizontal transport controller HTCi is connected to its corresponding row of processor blocks 105i -10532.

[0299] It is further understood that each of the processor blocks 105i -105is and 10518-10532 includes additional circuitry (not shown in Fig. 28), which enables the transfer of data vertically (i.e. , along the Y-axis) between the processor blocks within ASIC controller chip 105. This vertical transport control circuitry, which is included within most of the processor blocks of ASIC controller chip 105 (i.e., the processor blocks that do not include horizontal transport controllers), is described in more detail below in connection with Figs. 30-32.

[0300] Fig. 29 is a block diagram that generally illustrates sixty-four horizontal transport controllers HTCAI to HTCA64 included on the ASIC controller chip 105A of stacked flash memory system FMSo, sixty-four horizontal transport controllers HTCi to HTC64 included on the ASIC controller chip 105 of MTDRAM processor system MDPo, sixty-four horizontal transport controllers HTCBI to HTCB64 included on the ASIC controller chip 105B of MTDRAM processor system MDP1, and sixty-four horizontal transport controllers HTCci to HTCc64 included on the ASIC controller chip 105C of MTDRAM processor system MDP2, in accordance with one embodiment.

[0301] Horizontal communication paths are provided between horizontally adjacent horizontal transport controllers HTCAX, HTCX, HTCBX and HTCcx (wherein X = 1 to 64). For example, horizontal communication path 2901 extends between horizontal transport controllers HTCAI and HTCi, horizontal communication path 2902 extends between horizontal transport controllers HTCi and HTCBI , horizontal communication path 2903 extends between horizontal transport controllers HTCBI and HTCci.Similarly, horizontal communication path 2911 extends between horizontal transport controllers HTCA64 and HTC64, horizontal communication path 2912 extends between horizontal transport controllers HTC64 and HTCB64, and horizontal communication path 2913 extends between horizontal transport controllers HTCB64 and HTCc64. Although Fig. 29 only illustrates horizontal communication paths 2901-2903 associated with horizontal transport controllers HTCAI , HTCI , HTCBI and HTCci of the first row of horizontal transport controllers, and horizontal communication paths 2911-2913 associated with horizontal transport controllers HTCA64, HTC64, HTCB64 and HTCc64 of the sixty-fourth row of horizontal transport controllers, it is understood that all sixty-four rows of horizontal transport controllers have similar horizontal communication paths.

[0302] This pattern continues horizontally across the X-axis width of the arrayed processor system 2600 (i.e. , through MTDRAM processor systems MDP3-MDP7 and stacked flash memory system FMSs). This pattern also continues vertically along the Y-axis (within each row of stacked flash memory system s / MTD RAM processor systems in the arrayed processor system 2600).

[0303] In accordance with one embodiment, the above-described horizontal communication paths of the arrayed processor system 2600 are implemented by metal traces in the underlying silicon substrate interconnect structure 2610. Fig. 30 is a block diagram illustrating the general routing of the horizontal communication paths 2901- 2903 within silicon substrate interconnect structure 2610.

[0304] In one embodiment, data transfer between horizontal transport controllers occurs at an intermediate frequency, which is greater than the operating frequency of the MTDRAM unit cells (e.g., 1 to 2 GHz). The bandwidth of the horizontal communication paths between the horizontally aligned horizontal transport controllers is designed to be high enough to enable the simultaneous transfer of data to / from all processor nexuses within the corresponding row of processor blocks within the arrayed processor system 2600. For example, the horizontal communication path 2902 has a bandwidth capable of transmitting data from horizontal transport controller HTCi (received from all of the processor nexuses of processor blocks 1051-10532) tohorizontal transport controller HTCBI , while simultaneously receiving data from horizontal transport controller HTCBI (received from all of the processor nexuses of the first row of processor blocks within ASIC controller chip 105B). In one embodiment, the horizontal communication paths are designed to exhibit the full bandwidth specified above. However, in alternate embodiments, the horizontal communication paths are designed to exhibit a partial bandwidth (less than the full bandwidth), which is adequate to support the design goals of a particular system that uses the above-described architecture. This configuration advantageously allows for rapid horizontal transfer of data throughout the arrayed processor system 2600.

[0305] Vertical communication paths (along the Y-axis) within arrayed processor system 2600 will now be described.

[0306] Fig. 31 is a block diagram of processor block 105i of ASIC controller chip 105 in accordance with one embodiment of the present invention. Processor block 105i includes processor nexus 10i (which is also illustrated in Fig. 28, along with on-chip horizontal interconnect structures 2801 -2802), TSV connectors 15i (which are coupled to TSV set TSVi,i of unit cell UCi ,1 ) and local vertical transport controller 20i . In general, processor nexus 10i transfers data to / from its corresponding MTDRAM unit cells UCi ,1 , UC2,1 , UC3,1 and UC4,i via TSV set TSVi ,1 in the manner described above. Local vertical transport controller 20i also transfers data to / from processor nexus 10i , as illustrated by interface 25i. In addition, local vertical transport controller 20i transfers data vertically to / from other local vertical transport controllers in the same column as processor block 105i , as illustrated by vertical interconnect structure 35i .

[0307] In the embodiment illustrated by Fig. 27, most (but not all) of the processor blocks 105i -1052048 of ASIC controller chip 105 include the circuit elements illustrated by Fig. 31 . In the illustrated embodiment, the processor blocks that include the horizontal transport controllers HTC1-HTC64 do not include a local vertical transport controller as illustrated by Fig. 31 (because the area required to implement a local vertical transport controller is consumed by the horizontal transport controller). For example, processor blocks 105is and 105ie, which include horizontal transport controller HTC1, do not include local vertical transport controllers.

[0308] In addition to the circuit elements included in processor block 105i , a first subset of the processor blocks of ASIC controller chip 105 also include a regional vertical transport controller, which allows for short vertical communication ‘hops’ within the ASIC controller chip 105 (as well as short vertical communication ‘hops’ to vertically adjacent ASIC controller chips). In the embodiment illustrated by Fig. 27, the firstsubset of processor blocks on ASIC controller chip 105 includes processor blocks 105225-105239 and 105242-105256 (i.e., each of the processor blocks in the 8throw of processor blocks, except for the two centrally located processor blocks within this row), processor blocks 105737-105751 and 105754-105768 (i.e., each of the processor blocks in the 24th row of processor blocks, except for the two centrally located processor blocks within this row), the processor blocks 105i249-105i263 and 1 O5i266-1 O5i28o (i.e., each of the processor blocks in the 40th row of processor blocks, except for the two centrally located processor blocks within this row) and each of the processor blocks 105i76i- 105i 775 and 105-1778- 105i 792 (i.e., each of the processor blocks in the 56throw of processor blocks, except for the two centrally located processor blocks within this row). The processor blocks including a regional vertical transport controller are shown with similar shading in Fig. 27.

[0309] In addition to the circuit elements included in processor block 105i , a second subset of the processor blocks of ASIC controller chip 105 also include a long-distance vertical transport controller, which allows for long vertical communication ‘hops’ from the ASIC controller chip 105 to the vertically aligned communication management chip COMo (Fig. 26). In the embodiment illustrated by Fig. 27, the second subset of processor blocks on ASIC controller chip 105 includes processor blocks 105257-105271 and 105274-105288 (i.e., each of the processor blocks in the 9throw of processor blocks, except for the two centrally located processor blocks within this row), processor blocks 105769-105783 and 105786-1 O58OO (i.e., each of the processor blocks in the 25th row of processor blocks, except for the two centrally located processor blocks within this row), the processor blocks 105i28i-105i295 and 105i298-105i3i2 (i.e., each of the processor blocks in the 41strow of processor blocks, except for the two centrally located processor blocks within this row) and each of the processor blocks 1 O5i793-1 O5iso7 and 1 O5i8io-1051824 (i.e., each of the processor blocks in the 57throw of processor blocks, except for the two centrally located processor blocks within this row). The processor blocks including a long-distance vertical transport controller are shown with similar shading in Fig. 27.

[0310] Fig. 32 is a block diagram of the first seventeen processor blocks 105i , 10533, 10565, 10597, 105129, 105161 , 105193, 105225, 105257, 105289, 105321, 105353, 105385, 105417, 105449, 105481, and 105si3, included in the first column of processor blocks within ASIC controller chip 105.

[0311] Processor blocks 105i, 10533, 10565, 10597, 105i29, 105iei, 105i93, 105225, 105257, 105289, 105321, 105353, 105385, 105417, 105449, 105481 , and 105513 includeprocessor nexuses, IO1- 17, respectively, TSV connector sets 15i-15i7, respectively, and local vertical transport controllers 20i -20i7, respectively. All of the local vertical transport controllers 20i-20s are coupled to one another, and to regional vertical transport controller 30i by local vertical communication path 35i , which is implemented by metal lines on underlying silicon substrate interconnect structure 2610. Similarly, all of the local vertical transport controllers 20g-20i6 are coupled to one another, and to regional vertical transport controller 30i by local vertical communication path 352, which is implemented by metal lines on underlying silicon substrate interconnect structure 2610. Local vertical communication path 35i enables communication (and the transfer of data) between any / all of the local vertical transport controllers 20i-20s (as well as regional vertical transport controller 30i). Similarly, local vertical communication path 352 enables communication (and the transfer of data) between any / all of the local vertical transport controllers 20g-20i6 (as well as regional vertical transport controller 30i). Regional vertical transport controller 30i enables the transfer of data between the local vertical transport controllers 20i-20s and the local vertical transport controllers 20g- 2016.

[0312] The regional vertical transport controller 30i is also coupled to a vertically aligned regional vertical transport controller by a regional vertical communication path 6O1 , which is described in more detail below.

[0313] Although each of the local vertical communication paths 35i and 352 is illustrated as a single continuous bus in Fig. 32, it is understood that local vertical communication paths 35i and 352 are sub-divided into a plurality of smaller segments (or wheels) to enable flexible transmission of data between the corresponding local vertical transport controllers 20i-20s and 20g-20i6 and to avoid direct long distance signal transmission. The local vertical communication paths 35i and 352 and the regional vertical transport controller 30i are designed to have enough bandwidth to keep data moving continuously between the processor nexuses IO1- 16, with no gaps or stalls.

[0314] Local vertical transport controller 2O17 is included in a third set of eight local vertical transport controllers (2O17-2O24), which extend vertically below the first two sets of eight local vertical transport controllers 20i-20s and 20g-20i6. This third set of eight local vertical transport controllers are commonly coupled by another local vertical communication path 35s, which is similar to the above-described local vertical communication paths 35i and 352. In accordance with one embodiment, a vertical bridge circuit 45i is located between the vertical communication paths 352 and 35s.This bridge circuit 45i may be located within processor block 105481 and / or processor block 105513. Vertical bridge circuit 45i receives the information transmitted on both vertical communication paths 352 and 353. If vertical bridge circuit 45i detects information on communication path 35s that addresses one of the processor nexuses 10i-10i6 associated with one of the vertical communication paths 35i or 352, then vertical bridge circuit 45i transmits this information onto vertical communication path 352. Conversely, if vertical bridge circuit 45i detects information on communication path 352 that addresses one of the processor nexuses associated with the vertical communication path 35s, then vertical bridge circuit 45i transmits this information onto vertical communication path 35s.

[0315] In one embodiment, the local vertical communication paths 35i , 352 and 35s, the regional vertical transport controller 30i and the vertical bridge circuit 45i are designed to have enough bandwidth to keep data moving continuously between the processor nexuses IO1- 16, and the next eight vertically located processor nexuses 1017-1024 with no gaps or stalls.

[0316] This pattern is repeated vertically within the first column of processor blocks of ASIC controller chip 105, such that vertical bridge circuits (identical to vertical bridge circuit 45i) are located between the ends of vertical communication paths that end in processor blocks 105993 and 105 25, and between the ends of vertical communication paths that end in processor blocks 1 O5ISO5 and 105i537. This pattern of vertical bridge circuits is also repeated horizontally (along the X-axis) within each column of processor blocks within ASIC controller chip 105.

[0317] In addition, processor block 105257 includes long-distance vertical transport controller 40i. Long-distance vertical transport controller 40i is coupled to regional vertical transport controller 30i via regional vertical communication path 50i , which enables communication (and the transfer of data) between long-distance vertical transport controller 40i and regional vertical transport controller 30i. In one embodiment, regional vertical communication path 50i is implemented by metal lines on underlying silicon substrate interconnect structure 2610. In another embodiment, regional vertical communication path 50i is implemented by lines fabricated on the ASIC controller chip 105. Long-distance vertical transport controller 40i is also coupled to communication management chip COMo through long-distance vertical communication path 70i , which is implemented by metal lines on underlying silicon substrate interconnect structure 2610. In one embodiment, long-distance verticaltransport controller 40i is a PAM4 controller that transfers data to / from communication management chip COMo at a rate of 25-50 GHz.

[0318] In one embodiment, the pattern of Fig. 32 is repeated both horizontally and vertically across the ASIC controller chip 105. Each of the ASIC controller chips included in MTDRAM processor systems MDP1-MDP63 have the same horizontal and vertical routing structures as those described above for the ASIC controller chip 105 of MTDRAM processor system MDPo.

[0319] Although the long-distance vertical transport controllers and the regional vertical transport controllers are located in two adjacent rows of processor blocks in Figs. 27 and 31 , it is understood that the long-distance vertical transport controllers and the regional vertical transport controllers may be fitted within a single row of processor blocks in an alternate embodiment (shortening the lines required to transmit data between these long-distance and regional vertical transport controllers, advantageously saving some power and area).

[0320] Fig. 33 is a block diagram illustrating the vertical routing of data between communication management chip COMo, the first column of processor blocks in ASIC controller chip 105 of MTDRAM processor system MDPo and the first column of processor blocks in the ASIC controller chip 105K of vertically adjacent MTDRAM processor system MDPs.

[0321] Fig. 33 illustrates the regional vertical transport controller 30i present in processor block 105225 and the long-distance vertical transport controller 40i present in processor block 105257, which are described above in connection with Figs. 27 and 32.

[0322] In addition, Fig. 33 illustrates regional vertical transport controllers 302, 30s, and 304, which are present in processor blocks 105737, 105i249, and 1051761 , respectively, on ASIC controller chip 105. Fig. 33 also illustrates regional vertical transport controllers 30s, 30e, 307, and 30s, which are laid out in a manner similar to vertical transport controllers 30i , 302, 30s, and 304, respectively, within ASIC controller chip 105K. In the described embodiment, regional vertical transport controllers 302-30s have the same configuration as regional vertical transport controller 30i.

[0323] Every other vertically adjacent regional vertical transport controller is coupled to one another. Thus, regional vertical transport controllers 30i and 30s are coupled by corresponding regional vertical communication path 6O1 and regional vertical transport controllers 302 and 304 are coupled by corresponding regional vertical communication path 6O2. Similarly, regional vertical transport controller pairs 30s and 30s, 304 and 30e, 30s and 307 and 30e and 30s, are coupled by corresponding regional verticalcommunication paths 6O3, 6O4, 60s and 60e, respectively. This pattern is repeated vertically throughout the arrayed processor system 2600. For example, a regional vertical communication paths 6O7 and 60s further couple regional vertical transport controllers 30? and 30s to corresponding regional vertical transport controllers within MTDRAM processor system MDP16. In the described embodiment, the regional vertical communication paths (e.g., 60i-60s) of arrayed processor system 2600 are implemented by metal traces in the underlying silicon substrate interconnect structure 2610. The regional vertical communication paths specified above enable rapid communication (and the transfer of data) between processor blocks that are separated by large vertical distances (along the Y-axis).

[0324] Although Fig. 33 illustrates regional vertical transport controllers and regional vertical communication paths associated with the first column of processor blocks within the first column of ASIC controller chips within the arrayed processor system 2600, it is understood that all columns of processor blocks within the arrayed processor system 2600 (that are capable of vertical communication) include regional vertical transport controllers and corresponding regional vertical communication paths configured in the manner described above.

[0325] In one embodiment, the regional vertical transport controllers transmit data on the corresponding regional vertical communication paths at an intermediate frequency which is greater than the operating frequency of the MTDRAM unit cells (e.g., 1 to 2 GHz). This advantageously allows for rapid vertical transfer of data throughout the arrayed processor system 2600.

[0326] Fig. 33 also illustrates long-distance vertical transport controllers 402, 40s, and 404, which are present in processor blocks 105769, 105i28i , and 1051793, respectively, on ASIC controller chip 105. Fig. 33 also illustrates long-distance vertical transport controllers 40s, 40e, 407, and 40s, which are laid out in a manner similar to long-distance vertical transport controllers 40i, 402, 40s, and 404, respectively, within ASIC controller chip 105K. In the described embodiment, long-distance vertical transport controllers 402-40s have the same configuration as long-distance vertical transport controller 40i. Long-distance vertical transport controllers 40i-40s are locally coupled to corresponding regional vertical transport controllers 30i-30s, respectively (in the manner illustrated by Fig. 32). In addition, each of the long-distance vertical transport controllers 40i-40s is coupled to communication management chip COMo by a corresponding long-distance vertical communication path 70i-70s, respectively. This pattern repeats vertically throughout the arrayed processor system 2600. For example,four long-distance vertical communication paths couple four corresponding longdistance vertical transport controllers within MTDRAM processor system MDP to communication management chip COMo. As described above, each of the longdistance vertical communication paths (e.g., 70i-70s) of arrayed processor system 2600 are implemented by metal traces in the underlying silicon substrate interconnect structure 2610.

[0327] Although Fig. 33 illustrates long-distance vertical transport controllers and long-distance vertical communication paths associated with the first column of processor blocks within the first column of ASIC controller chips within the arrayed processor system 2600, it is understood that all columns of processor blocks within the arrayed processor system 2600 (that are capable of vertical communication) include long-distance vertical transport controllers and corresponding long-distance vertical communication paths configured in the manner described above.

[0328] The above-described configuration enables flexible routing of data within arrayed processor system 2600. More specifically, data can be transmitted horizontally between any pair of processor blocks in the same row of the arrayed processor system2600 using the horizontal transport mechanisms described in connection with Figs 27- 30. Similarly, data can be transmitted vertically between any pair of processor blocks in the same column of the arrayed processor system 2600 (except for the pair of centrally located columns of processor blocks within each ASIC controller chip) using the vertical transport mechanisms described in connection with Figs. 27 and 31-33. “Diagonal” data transfer between pairs of processor blocks not located in the same row / column of the arrayed processor system 2600 is accomplished using a combination of both the above-described horizontal and vertical transport mechanisms. Data transfer between a processor block of the arrayed processor system 2600 and a processor external to arrayed processor system 2600 is accomplished by transferring data along a communication path that includes a long-distance vertical transport controller, a longdistance vertical communication path, one of the communication management chips COM0-COM7, and one of the optical links OPT0-OPT1.

[0329] In accordance with one variation of the embodiments described above, a plurality of arrayed processor systems, each similar to (or identical to) arrayed processor system 2600 can be interconnected, effectively creating an expanded arrayed processor system. Fig. 34 is a block diagram of an expanded arrayed processor system 3400, which includes arrayed processor systems 2600 (Fig. 26),2601 and 2602. Arrayed processor systems 2601 and 2602 include high-sped opticalcommunication links OPT2-OPT3 and OPT4-OPT5, respectively. Although not illustrated by Fig. 34, it is understood that arrayed processor systems 2601 -2602 also include an array of MTDRAM processor systems (identical or similar to MTDRAM processor systems MDPo-MDPes), communication control chips (identical or similar to communication control chips COM0-COM7), power management chips (identical or similar to power management chips PMC0-PMC7), a power supply / cooling structure (identical or similar to power supply / cooling structure 2605), and optionally, a plurality of stacked flash memory (identical or similar to stacked flash memory systems FMSo- FMS15). Data is transferred between arrayed processor systems 2600-2602 via optical communication links OPTo, OPT2 and OPT3, and / or via optical communication links OPT1 , OPT3 and OPTs, as illustrated.

[0330] In accordance with other embodiments of the present invention, the single- ended sense amplifiers included in the primary sense amplifier circuits can have configurations other than those described above in connection with Figs. 8, 11 A and 11 B.

[0331] Fig. 35 is a circuit diagram of single-ended sense amplifiers SA’0,1 and SA’0,3 of primary sense amplifier circuit PSAi.o in accordance with an alternate embodiment of the present invention. Single ended sense amplifiers SA’0,1 and SA’0,3 are similar to single ended sense amplifiers SAo.i and SAo,3 (Fig. 8), with differences noted below. Single ended sense amplifiers SA’0,1 and SA’0,3 do not include the kick capacitors 821 - 824 of single ended sense amplifiers SAo.i and SAo,3. In addition, single ended sense amplifiers SA’0,1 and SA’0,3 do not require the NCOM control signal (which is coupled to n-channel transistors N1 -N4 of single ended sense amplifiers SAo.i and SAo,s). Rather, the sources of n-channel transistors N1 -N4 are simply connected to ground (0V) in single ended sense amplifiers SA’0,1 and SA’0,3. Advantageously, the primary sense amplifier driver circuit PSADi.o of Fig. 35 does not need to generate the kick voltage signal Vk or the NCOM signal in the manner described above in connection with Figs. 11A-11 B.

[0332] The sources of n-channel pre-charge transistors N12 and N14 are coupled to receive a reference voltage signal Vref in accordance with the present embodiment of the invention. As described in more detail below, the n-channel pre-charge transistors N12 and N14 are controlled to apply the reference voltage signal Vref to the internal nodes INTO# and INT2#, respectively. Note that the primary sense amplifier driver circuit PSADi.o of Fig. 35 generates the reference voltage signal Vref in the present embodiment.

[0333] Before describing the operation of single-ended sense amplifiers SA’0,1 and SA’0,3, the operating characteristics of a conventional dual-ended sense amplifier will be described for comparison purposes. A conventional dual-ended sense amplifier is coupled to a bit line of a bit cell being read, and also to a dummy bit line. This bit line and dummy bit line are pre-charged to an intermediate voltage that is half the logic T voltage written to the bit cell. For example, if the logic T voltage written to the bit cell is 1.1 Volts, then the bit line pre-charge voltage is 550 mV. The DRAM bit cell loses charge over time, and therefore must be periodically refreshed. In one example, the refresh interval of the DRAM bit cell is 32 msec, wherein the T bit cell voltage stored by the bit cell drops by about 14% at the end of the 32 msec refresh interval. In the example described herein, the DRAM bit cell is refreshed by the time the logic T bit cell voltage reaches 0.95 V.

[0334] The change in the bit line voltage (AV) during a read operation is defined by the following equation:AV = (Vbitcell - VBLP) / (1 + CB / CS), wherein Vbitcell is the bit cell voltage stored by the DRAM bit cell at the time of the read operation (e.g., 1.1 to 0.95V), VBLP is the pre-charge voltage of the bit line (e.g., 0.55V), CB is the capacitance of the bit line, and Cs is the capacitance of the DRAM bit cell. Common values for CB / CS are 4, 6 and 8. Thus, in a conventional dual-ended sense amplifier, AV is about 80 mV, 57 mV and 44 mV (at the end of the 32 msec refresh interval) for CB / CS values of 4, 6 and 8, respectively. Note that a bit line being read in one direction (e.g., being pulled up in response to a logic T bit cell) may be located adjacent to other bit lines being read in the opposite direction (e.g., being pulled down in response to a logic ‘0’ bit cell). In this case, the voltage on a bit line being read in one direction can be pulled in the other direction due to bit line coupling. Common bit line coupling estimates include 15%, 25% and 35%. In the example given above for a conventional dual-ended sense amplifier, the above-described AV values of 80 / 57 / 44 mV would be adjusted down to 60 / 43 / 33 mV (for CB / CS values of 4 / 6 / 8, respectively) for an adverse bit line coupling of 25%.

[0335] In accordance with one embodiment, the value of the reference voltage Vref implemented within the single-ended sense amplifiers SA’0,1 and SA’0,3 of Fig. 35 is selected to provide an equivalent AV with respect to the above-described dual-ended sense amplifier. In accordance with the present embodiment, the logic ‘0’ bit cell value is 0 Volts (e.g., bit line blo is pulled down to 0 Volts to write a logic ‘0’ value to the corresponding bit cell bco ). Thus, when reading a logic ‘0’ value from bit cell bco (orbco.3), the voltage on the corresponding bit line blo,i (or bio, 3) will be equal to 0 Volts (without considering adverse bit line coupling). In order to obtain a AV value of 60 / 43 / 33 mV (to match the performance of the above-described dual-ended sense amplifier), the nominal value of Vref should be 60 / 43 / 33 mV (for DRAM systems with CB / CS = 4 / 6 / 8, respectively). In this case, the nominal value of a logic T value read on the bit line blo (or bio, 3) should be equal to 120 / 86 / 66 mV (i.e. , 60 / 43 / 33 mV + 60 / 43 / 33 mV = 120 / 86 / 66 mV). To achieve read bit line voltages of 120 / 86 / 66 mV based on CB / CS values of 4 / 6 / 8, the corresponding bit cell voltages must be at least 600 / 602 / 594 mV (i.e., 120 / 86 / 66 mV x (1 +4) / (1 +6) / (1 +8) = 600 / 602 / 594 mV). In order to ensure a minimum bit cell voltage of at least 600 / 602 / 594 mV at the end of a refresh interval, the DRAM bit cell should initially be written to a bit cell voltage that is about 14% greater, or 698 / 700 / 691 mV. In this instance, the maximum read bit line voltage (assuming the read operation occurs immediately after a refresh operation) is about 140 / 100 / 77 mV (i.e., 698 / 700 / 691 mV divided by (1 +4) / (1 +6) / (1 +8) = 140 / 100 / 77 mV).

[0336] Assuming that a bit line reading a logic ‘0’ value experiences 25% adverse bit line coupling from adjacent bit lines reading logic T values, the bit line reading a logic ‘0’ value may be pulled up from 0 Volts to 35 / 25 / 19 mV (i.e., 140 / 100 / 77 mV x 25% = 35 / 25 / 19 mV). To compensate for this bit line coupling, the value of Vref can be adjusted upward to 95 / 68 / 52 mV (i.e., because the voltage level of a logic ‘0’ bit line can be pulled up from 0 Volts to 35 / 25 / 19 mV by adverse bit line coupling, the nominal value of Vref is adjusted upward from 60 / 43 / 33 mV by adding 35 / 25 / 19 mV to provide 95 / 68 / 52 mV). In this case, the nominal value of a logic T value read on the bit line blo.i (or bio, 3) should be adjusted up to at least 155 / 111 / 85 mV (i.e., 95 / 68 / 52 mV + 60 / 43 / 33 mV = 155 / 111 / 85 mV) to maintain the specified AV values of 60 / 43 / 33 mV. To achieve read bit line voltages of 155 / 111 / 85 mV based on CB / CS values of 4 / 6 / 8, the corresponding bit cell voltages must be at least 775 / 777 / 765 mV (i.e., 155 / 111 / 85 mV x (1 +4) / (1 +6) / (1 +8) = 775 / 777 / 765 mV). In order to ensure a minimum bit cell voltage of at least 775 / 777 / 765 mV at the end of a refresh interval, the DRAM bit cell should initially be written to a bit cell voltage that is about 14% greater, or 901 / 904 / 890 mV. In this instance, the maximum read bit line voltage (assuming the read operation occurs immediately after a refresh operation) is about 180 / 129 / 99 mV for CB / CS values of 4 / 6 / 8, respectively (i.e., 901 / 904 / 890 mV divided by (1 +4) / (1 +6) / (1 +8) = 180 / 129 / 99 mV).

[0337] Assuming 25% adverse bit line coupling from adjacent bit lines reading logic T values, a bit line reading a logic ‘0’ value may be pulled up from 0 Volts to 45 / 32 / 25mV (i.e., 180 / 129 / 99 mV x 25% = 45 / 32 / 25 mV). Again, to compensate for this bit line coupling, the value of Vref can be adjusted upward to 105 / 75 / 58 mV (i.e., because the voltage level of a logic ‘0’ bit line can be pulled up from 0 Volts to 45 / 32 / 25 mV by adverse bit line coupling, the value of Vref is adjusted to 60 / 43 / 33 mV + 45 / 32 / 25 mV = 105 / 75 / 58 mV).

[0338] As described above, adjusting the value of Vref may necessitate adjusting the nominal voltage of a logic T value read on a bit line, the logic T bit cell voltage, and the bit cell coupling voltage (which in turn, necessitates adjusting the value of Vref). Over a plurality of iterations, these adjustments converge to a final set of values, wherein the final iteration is selected in view of the required accuracy of the particular application. In the present example, four iterations results in a bit line coupling voltage of 49 / 35 / 27 mV, a reference voltage Vref of 109 / 78 / 60 mV, a nominal logic T read bit line voltage of 169 / 121 / 93 mV and a full DRAM bit cell voltage of 983 / 985 / 973 mV (for CB / CS of 4 / 6 / 8, respectively). Having determined these voltages (to establish a AV equivalency with a conventional dual-ended sense amplifier), the operation of single- ended sense amplifiers SA’0,1 and SA’0,3 will now be described.

[0339] In the examples provided below, read accesses are performed to bit cells bco.i and bco,3 coupled to bit lines blo,i and bio, 3, respectively, wherein the bit cell bco stores a logic T bit cell voltage, and the bit cell bco,3 stores a logic ‘0’ bit cell voltage. Bit cells bco.i and bco,3 are coupled to receive a common sub-word line signal SWLo.o, as illustrated.

[0340] Fig. 36 is a waveform diagram illustrating signals associated with a read access to bit cells bco and bco,3.

[0341] At time TO, the sub-word line SWLo.o is at a logic low state (0V) and the reference voltage signal Vref is at ground (0V). The pre-charge control voltages PREo and PRE1 are activated high (1 V), thereby turning on the pre-charge transistors N11- N14. Under these conditions, the internal nodes INT0 / INT0# and INT2 / INT2# are all pulled down to ground. The ISOso and ISOsi signals are deactivated low (0V), thereby isolating the single-ended sense amplifiers SAo.i and SAo,3 from the bit lines blo,i and bio, 3 (and the bit lines bh ,1 and bh ,3). The PCOM signal is held at logic low state (0V) and the bit lines blo,i and bio, 3 are pre-charged to ground (0V).

[0342] The read operation starts at time T1 . Just prior to time T1 , the reference voltage signal Vref is driven to a predetermined positive voltage, thereby pre-charging the voltages on internal nodes INTO# and INT2# to the predetermined reference voltage Vref of 109 / 78 / 60 mV (for CB / CS of 4 / 6 / 8, respectively). As described in more detailbelow, the read voltages developed on the bit lines blo and bio, 3 are compared with the reference voltage Vref within the sense amplifier circuits SA’0,1 and SA’0,3, respectively.

[0343] Because there is no / negligible current flow on bit lines reading a logic ‘0’ value (because the bit lines are pre-charged to OV, and remain near OV during a read operation), there is no significant adverse bit line coupling associated with bit lines reading a logic T value. Thus, when reading a logic T value from bit cell bco (or bco,3), in order to obtain a AV value of 60 / 43 / 33 mV (to match the performance of the above-described dual-ended sense amplifier), the voltage developed on the read bit line should therefore be at least as great as the sum of the Vref reference voltage of 109 / 78 / 60 mV plus the AV value of 60 / 43 / 33 mV, or 169 / 121 / 93 mV. A logic ‘1 ’ bit read line voltage of 169 / 121 / 93 mV translates to a bit cell voltage of 845 / 847 / 837 mV for CB / CS = 4 / 6 / 8 (i.e., 169 / 121 / 93 mV x (1 +Cb / Cs) = 845 / 847 / 837 mV). In order to ensure a minimum bit cell voltage of 845 / 847 / 837 mV at the end of a refresh interval, the bit cell should initially be written to a full bit cell voltage that is about 14% greater, or 983 / 985 / 973 mV (for CB / CS = 4 / 6 / 8).

[0344] Returning to Fig. 36, at time T1 , the sub-word line SWLo.o is activated high (1 ,5V). Under these conditions, read voltages are developed on the bit lines blo and bio, 3, wherein these read voltages are dependent upon the data values stored by the corresponding bit cells coupled to these bit lines. In the illustrated embodiment, bit line blo.i begins to be pulled up from the bit line pre-charge voltage of 0V towards the logic T read bit line voltage level (e.g., 169 / 121 / 93 mV or more, as described above). Although bit line bio, 3 should be held at a logic ‘0’ value equal to 0 Volts, in a worst case situation, bit line bio, 3 is surrounded by a plurality of adjacent bit lines all being pulled up to a logic “1” read voltage level. In this case, bit line bio, 3 begins to be slightly pulled up from the bit line pre-charge voltage of 0V, due to adverse bit line coupling with the logic T read voltages being developed on adjacent bit line blo and other adjacent bit lines. As described above, this adverse bit line coupling may pull up the voltage on bit line bio, 3 to a voltage as high as about 49 / 35 / 27 mV (for CB / CS = 4 / 6 / 8).

[0345] Also at time T1 , the pre-charge control signal PREo is deactivated low (0V), thereby turning off n-channel transistors N11 and N13, such that the internal nodes INTO and INT2 are no longer actively pulled down to ground.

[0346] At time T2 (shortly after time T 1 ), the ISOso signal is activated high (1 ,5V), thereby turning on n-channel transistors 801 and 802, such that the read voltages developed on bit lines blo and bio, 3 are applied to internal nodes INTO and INT2, respectively. Thus, as illustrated by Fig. 36, the voltage on internal node INTO beginsto increase toward the logic T read bit line voltage of 169 / 121 / 93 mV, and the voltage on internal node INT2 begins to increase toward 49 / 35 / 27 mV (in the worst case) due to adverse bit line coupling.

[0347] The voltages on nodes INTO and INT2 are allowed to develop until time T3. By time T3, the voltages on bit line blo,i and internal node INTO have reached a read bit line voltage of at least 169 / 121 / 93 mV (described above) , and the voltage on internal node INT2 reaches as high as 49 / 35 / 27 mV (worst case) due to adverse bit line coupling. At time T3, the pre-charge control signal PREi is deactivated low, thereby turning off transistors N12 and N14, such that the internal nodes INTO# and INT2# are no longer actively driven to the reference voltage Vref of 109 / 78 / 60 mV.

[0348] Also at time T3, the ISOso signal is deactivated low (0V), thereby turning off n-channel transistors 801 and 802, temporarily isolating bit lines blo.i and bio, 3 from the internal nodes INTO and INT2, respectively.

[0349] At time T4 (immediately after de-activating the pre-charge control signal PREi and the ISOso signals), the PCOM signal is activated to the logic high bit cell voltage (983 / 985 / 973 mV), thereby activating the single ended sense amplifier circuits SAo,i and SAo,3. Under these conditions, sense amplifier circuit SA’0,1 amplifies the voltage difference between the signals on internal nodes INTO and INTO#, and sense amplifier circuit SAo,3 amplifies the voltage difference between the signals on internal nodes INT2 and INT2#. In the illustrated example, the voltage on internal node INTO is at least 169 / 121 / 93 mV, and the reference voltage on node INTO# is 109 / 78 / 60 mV (for a AV of 60 / 43 / 33 mV). Within single-ended sense amplifier SA’0,1, the relatively low voltage on internal node INTO# causes transistor P2 to turn on first as the PCOM voltage transitions high, which increases the differential voltage between internal nodes INTO and INTO#, until the voltage on internal node INTO becomes high enough to cause transistor N1 to turn on.

[0350] As a result, the voltage on internal node INTO is pulled up to the full PCOM voltage of 983 / 985 / 973 mV, and the voltage on node INTO# is pulled down to ground (0V). Note that during this initial sensing phase, it is important to balance the capacitances of internal nodes INTO and INTO#. Turning off isolation transistor 801 during this initial sensing phase temporarily decouples the capacitance of bit line bloj from internal node INTO, such that the capacitance of internal node INTO more nearly matches the capacitance of INTO# during this initial sensing phase.

[0351] Similarly, sense amplifier circuit SAo,3 amplifies the voltage difference between the signals on internal nodes INT2 and INT2#. In the illustrated example, thevoltage on internal node INT2 is 49 / 35 / 27 mV due to worst case adverse bit line coupling of adjacent logic T bit lines, and the reference voltage on internal node INT2# is 109 / 78 / 60 mV (for a AV of 60 / 43 / 33 mV). Within single-ended sense amplifier SAo,3, the relatively low voltage on internal node INT2 causes transistor P3 to turn on first as the PCOM voltage transitions high, which increases the differential voltage between internal nodes INT2 and INT2#, until the voltage on the internal node INT2# becomes high enough to cause transistor N4 to turn on. As a result, the voltage on internal node INT2# is pulled up to the full PCOM voltage of 983 / 985 / 973 mV, and the voltage on node INT2 is pulled down to ground (0V).

[0352] At time T5 (after a full signal swing of 983 / 985 / 973 mV is developed across each pair of internal nodes INT0 / INT0# and INT2 / INT2#), the ISOso signal is reactivated high (1.5V), thereby turning on isolation transistors 801 and 802 and recoupling bit lines blo.i and bio, 3 to internal nodes INTO and INT2, respectively. Under these conditions, bit lines blo and bio, 3 are driven to 983 / 985 / 973 mV and 0V, respectively, thereby refreshing the data values in the corresponding bit cells bco and bco,3, respectively. Although the example of Fig. 36 shows that the isolation transistors 801 and 802 are re-activated after the full signal swing of 983 / 985 / 973 mV has been developed across each pair of internal nodes INT0 / INT0# and INT2 / INT2#, in an alternate embodiment, the isolation transistors 801 and 802 are re-activated when the signal swing across each pair of internal nodes is less than the full signal swing of 983 / 985 / 973 mV, but large enough to overcome the capacitances introduced by bit lines blo.i and bio, 3 when the isolation transistors 801 and 802 are re-activated. Also at time T5, the reference voltage signal Vref is driven to ground (for power savings).

[0353] At time T6, the sub-word line SWLo.o is deactivated, thereby turning off the access transistors of bit cells bco.iand bco,3 (isolating the bit lines blo and bio, 3 from the cell capacitors of bit cells bco and bco,3). At this time, the data values read from bit cells bco.i and bco,3 have been restored to these bit cells.

[0354] At time T7, the PCOM control signal is driven to ground. As a result, the INTO and INT2# voltages are also driven to ground. At this time, the INTO node is still coupled to bit line blo (through isolation transistor 801 ), so the voltage on bit line blo is also driven to ground. Bit line bio, 3 remains at ground during this time, such that bit lines blo.i and bio, 3 are both pre-charged to ground.

[0355] At time T8, the ISOso voltage is driven to ground, turning off isolation transistors 801 and 802, and isolating the primary sense amplifiers SA’0,1 and SA’0,3 from bit lines blo and bio, 3. At time T9, the pre-charge control voltages PREo and PRE1are driven from ground to 1V to pre-charge the sense amplifiers SA’0,1 and SA’0,3, wherein INTO, INTO#, INT2 and INT2# are actively pulled to ground by transistors N11 , N12, N13, and N14, respectively.

[0356] The single-ended sense amplifier specified by Fig. 36 provides bit line CV2f power savings of at least about 20% when compared with the conventional dual-ended sense amplifier, when reading a logic T value. That is, the bit line CV2f power of the single-ended sense amplifier of Fig. 36 divided by CV2f power of a dual-ended sense amplifier is at least equal to (0.985x0.985) / (1.1x1.1 ), or 0.80. The single-ended sense amplifier specified by Fig. 36 provides power savings of 100% when compared with a conventional dual-ended sense amplifier, when reading a logic ‘0’ value (because the bit line being read is maintained at / near ground for the entire read operation, thereby consuming no / negligible power). Assuming that read operations, on average, include half logic T values and half logic ‘0’ values, the single-ended sense amplifier specified by Fig. 36 achieves an average power savings of about 60% (100% x 50 + 20% x 50 = 60%), or a power reduction of about 2.5x, with respect to a conventional dual-ended sense amplifier.

[0357] Note that in the embodiment illustrated by Fig. 36, the isolation transistors 801-802 (as well as the transistor driving the sub-word line SWLo.o) must be thick oxide transistors that can be overdriven such that the read voltages developed on the bit lines can be provided to the sense amplifier latches, and the full positive voltages developed by the sense amplifier latches can be driven onto the bit lines. Embodiments described below advantageously do not require the thick oxide transistors of the embodiment specified by Fig. 36.First alternate embodiment

[0358] In a first alternate embodiment, the n-channel transistors N1-N4 and the p- channel transistors P1-P4 are fabricated in accordance with MST technology, which includes a superlattice channel extending between source and drain regions of these transistors. This technology is described in more detail in commonly owned U.S. Patents 10,109,342 and 10,107,854, and commonly owned U.S. Patent Application Serial No. 18 / 311 ,465, which are hereby incorporated by reference in their entirety. Fabricating transistors N1-N4 and P1-P4 with MST technology advantageously allows these transistors to exhibit more precisely defined threshold voltages. As a result, sense amplifiers that implement transistors fabricated with MST technology (hereinafter referred to as ‘MST sense amplifiers’) can more reliably detect a specific bit cell voltage. As a result, the variation of AV values capable of being reliably sensed byMST sense amplifiers SA’0,1 and SA’0,3 are significantly reduced (e.g., about half).Thus, while non-MST sense amplifiers (e.g., the sense amplifiers described above in connection with the embodiment of Fig. 36) may exhibit a AV value of 60 / 43 / 33 mV, MST sense amplifiers (e.g., the sense amplifiers described below in connection with the embodiment of Fig. 37) advantageously exhibit an improved AV value range of about 30 / 21 / 16 mV (for CB / CS values of 4 / 6 / 8, respectively). That is, the MST sense amplifiers are able to reliably operate at a AV value range that is about half of the AV value range of a non-MST sense amplifier.

[0359] Fig. 37 is a waveform diagram illustrating signals associated with read accesses to bit cells bco and bco,3, in a first alternate embodiment wherein the n- channel transistors N1-N4 and p-channel transistors P1-P4 are fabricated to include superlattice channel in accordance with MST technology (i.e. , sense amplifiers SA’0,1 and SA’0,3 are MST sense amplifiers).

[0360] The waveform diagram of Fig. 37 is similar to the waveform diagram of Fig.36, with differences noted below. Because the waveform diagram of Fig. 37 corresponds with the use of MST sense amplifiers having a AV value of 30 / 21 / 16 mV, the nominal value of Vref should initially be 30 / 21 / 16 mV. Assuming 25% adverse bit line coupling from adjacent bit lines being pulled up to a logic T voltage level, the adjusted value of Vref can be calculated as 54 / 38 / 29 mV (over three iterations using the method described above). More specifically, the voltage level of a logic ‘0’ read bit line can be pulled up from 0 Volts to 24 / 17 / 13 mV by adverse 25% bit line coupling, such that the adjusted value of Vref is equal to 30 / 21 / 16 mV + 24 / 17 / 13 mV, or 54 / 38 / 29 mV (for CB / CS values of 4 / 6 / 8, respectively).

[0361] When reading a logic T value from bit cell bco (or bco.s), in order to obtain a AV value of 30 / 21 / 16 mV, the voltage developed on the read bit line should therefore be at least as great as the Vref reference voltage of 54 / 38 / 29 mV plus the AV value of 30 / 21 / 16 mV, or 84 / 59 / 45 mV at the end of the refresh interval.

[0362] The logic T read bit line voltage of 84 / 59 / 45 mV translates to bit cell voltages of 420 / 413 / 405 mV for CB / CS = 4 / 6 / 8 (i.e., 84 / 59 / 45 mV x (1 +Cb / Cs) = 420 / 413 / 405 mV). In order to ensure a minimum bit cell voltage of 420 / 413 / 405 mV at the end of a refresh interval, the bit cell should initially be written to a bit cell voltage that is about 14% greater, or 488 / 480 / 471 mV. Because the logic T bit cell voltage is only 488 / 480 / 471 mV, the isolation transistors 801-802 (and the transistor driving the subword line voltage SWLo.o) can be implemented conventional logic transistors, and do not need to be thick oxide transistors (as required in the embodiment of Fig. 36). Inaddition, the sub-word line voltage SWLo.o (and ISOso and ISOsi voltages) can be reduced to a voltage of 1V or lower. More specifically, the sub-word line voltage SWLo.o (and ISOso and ISOsi voltages) only needs to be high enough to ensure that the logic T bit cell voltage of 488 / 480 / 471 mV is written back to the bit cell.

[0363] The waveform diagram of Fig. 37 illustrates the adjusted reference voltage Vref of 54 / 38 / 29 mV, the adjusted worst case bit line coupling voltage of 24 / 17 / 13 mV, the logic T read bit line voltage of 84 / 59 / 45 mV, and the logic T bit cell voltage of 488 / 480 / 471 mV achieved due to the use of MST sense amplifiers . The timing of the various signals is the same as that described above in connection with the waveform diagram of Fig. 36.

[0364] The single-ended sense amplifier specified by Fig. 37 provides bit line CV2f power savings of about 80% when compared with the conventional dual-ended sense amplifier, when reading a logic T value. That is, the bit line CV2f power of the single- ended sense amplifier of Fig. 37 divided by CV2f power of a dual-ended sense amplifier is equal to at least (0.488x0.488) / (1.1x1.1 ), or 0.20. The single-ended sense amplifier specified by Fig. 37 provides power savings of 100% when compared with a conventional dual-ended sense amplifier, when reading a logic ‘0’ value (because the bit line being read is maintained at / near ground for the entire read operation, thereby consuming no / negligible power). Assuming that read operations, on average, include half logic T values and half logic ‘0’ values, the single-ended sense amplifier specified by Fig. 37 achieves an average power savings of 90% (100% x 50 + 80% x 50 = 90%), or a power reduction of about 10x, with respect to a conventional dual-ended sense amplifier.Second alternate embodiment

[0365] Fig. 38 is a circuit diagram of single-ended MST sense amplifiers SA”o,i and SA”O,3 in accordance with a second alternate embodiment of the present invention. Single-ended MST sense amplifiers SA”o,i and SA”o,3 are similar to single-ended sense amplifiers SA’0,1 and SA’0,3 (Fig. 35), with differences noted below. Within single-ended MST sense amplifiers SA”o,i and SA”o,3, n-channel transistors N1 -N4 and the p- channel transistors P1 -P4 are fabricated in accordance with MST technology (i.e., with superlattice channels extending between the source and drain regions of these transistors), such that the single-ended MST sense amplifiers SA”o,i and SA”o,3 exhibit a AV value range of 30 / 21 / 16 mV (in the manner described above in connection with Fig. 37). In addition, single-ended MST sense amplifiers SA”o,i and SA”o,3 include kickcapacitors 821 , 822, 823 and 824, which are coupled to bit lines blo.i , bio, 3, bh,i and bh,3, respectively.

[0366] Fig. 39 is a waveform diagram illustrating signals associated with read accesses to bit cells bco and bco,3 in single-ended MST sense amplifiers SA”o,i and SA”O,3 in accordance with the second alternate embodiment of the present invention. The waveform diagram of Fig. 39 is similar to the waveform diagram of Fig. 37, with differences noted below.

[0367] Because the waveform diagram of Fig. 37 corresponds with the use of MST sense amplifiers having a AV value of 30 / 21 / 16 mV, the nominal value of Vref should initially be 30 / 21 / 16 mV. Assuming 25% adverse bit line coupling from adjacent bit lines being pulled up to a logic T voltage level, the adjusted value of Vref can be calculated as 54 / 38 / 29 mV (over three iterations using the method described above). More specifically, the voltage level of a logic ‘0’ read bit line can be pulled up from 0 Volts to 24 / 17 / 13 mV by adverse 25% bit line coupling, such that the adjusted value of Vref is equal to 30 / 21 / 16 mV + 24 / 17 / 13 mV, or 54 / 38 / 29 mV (for CB / CS values of 4 / 6 / 8, respectively).

[0368] Moreover, in the embodiment of Figs. 38-39, each of the kick capacitors 821- 824 is designed to kick down the voltage on the associated bit lines by half of the adjusted Vref reference voltage of 54 / 38 / 29 mV during read operations. More specifically, kick capacitors 821 and 822 are selected to kick down the voltages on bit lines blo.i and bio, 3, respectively, by -27 / -19 / -14.5 mV during read accesses to bit cells bco.i and bco,3. As a result, the reference voltage Vref required by the single-ended MST sense amplifiers SA”o,i and SA”o,3 is similarly reduced from 54 / 38 / 29 mV to 27 / 19 / 14.5 mV (i.e., 54 / 38 / 29 mV - 27 / 19 / 14.5 mV = 27 / 19 / 14.5 mV). In the embodiment of Figs. 38-39, the kick capacitors are controlled to kick down the voltages on bit lines blo and bio, 3 between time T2 and time T3 (i.e., at time T2.5). In one embodiment, the kick capacitors are switched on as close to time T3 as possible.

[0369] Given a reference voltage Vref of 27 / 19 / 14.5 mV, the logic T bit line read voltage required by the single-ended MST sense amplifiers SA”o,i and SA”o,3 to obtain a AV value range of 30 / 21 / 16 mV is 57 / 40 / 30.5 mV (i.e., 30 / 21 / 16 mV + 27 / 19 / 14.5 mV = 57 / 40 / 30.5 mV). These logic T bit line read voltages are illustrated in Fig. 39. Note that these logic T bit line read voltages provide the appropriate AV value of 30 / 21 / 16 mV when compared to the reference voltage Vref of 27 / 19 / 14.5 mV.

[0370] The logic T bit line read voltage of 57 / 40 / 30.5 mV translates to bit cell voltages of 285 / 280 / 275 mV for CB / CS = 4 / 6 / 8 (i.e., 57 / 40 / 30.5 mV x (1 +Cb / Cs) =285 / 280 / 275 mV). In order to ensure a minimum bit cell voltage of 285 / 280 / 275 mV at the end of a refresh interval, the bit cell should initially be written to a bit cell voltage that is about 14% greater, or 331 / 326 / 320 mV. Because the logic T bit cell voltage is only 331 / 326 / 320 mV, the isolation transistors 801-802 (and the transistor driving the sub-word line voltage SWLo.o) can be implemented conventional logic transistors, and do not need to be thick oxide transistors (as required in the embodiment of Fig. 36). In addition, the sub-word line voltage SWLo.o (and the ISOso and ISOsi voltages) can be reduced to a voltage of 1V or lower. More specifically, the sub-word line voltage SWLo.o (and the ISOso and ISOsi voltages) only needs to be high enough to ensure that the logic T bit cell voltage of 331 / 326 / 320 mV is written to the bit cell.

[0371] As described above, the voltage level of a logic ‘0’ bit line (e.g., bit line bio, 3 in the example of Fig. 38) can be pulled up from 0 Volts to 24 / 17 / 13 mV due to adverse 25% bit line coupling. Because the kick capacitor 822 kicks down the voltages on bit line bio, 3 by -27 / 19 / 14.5 mV a during read access to bit cells bco,3, the logic ‘0’ bit line read voltage is adjusted to -3 / -2 / -1 .5 mV (i.e. , 24 / 17 / 13 mV - 27 / 19 / 14.5 mV = -3 / -2 / -1 .5 mV). These logic ‘0’ bit line read voltages are illustrated in Fig. 39. Note that these logic ‘0’ bit line read voltages provide the appropriate AV value of 30 / 21 / 16 mV when compared to the reference voltage Vref of 27 / 19 / 14.5 mV. Because there is no / negligible current flow on bit lines reading a logic ‘0’ value (because the bit lines are pre-charged to 0V, and remain near 0V during a read operation), there is no significant adverse bit line coupling associated with bit lines reading a logic T value.

[0372] The single-ended sense amplifier specified by Figs. 38-39 provides bit line CV2f power savings of at least about 91 % when compared with the conventional dualended sense amplifier, when reading a logic T value. That is, the bit line CV2f power of the single-ended sense amplifier of Fig. 39 divided by CV2f power of a dual-ended sense amplifier is at least (0.331x0.331 ) / (1.1x1.1 ), or 0.091. The single-ended sense amplifier specified by Fig. 39 provides power savings of 100% when compared with a conventional dual-ended sense amplifier, when reading a logic ‘0’ value (because the bit line being read is maintained near ground for the entire read operation, thereby consuming no / negligible power). Assuming that read operations, on average, include half logic T values and half logic ‘0’ values, the single-ended sense amplifier specified by Fig. 39 achieves an average power savings of 95.5% (100% x 50 + 91 % x 50 = 95.5%), or a power reduction of about 22x, with respect to a conventional dual-ended sense amplifier.

[0373] Note that the single-ended sense amplifiers SA”o,i and SA”o,3 of Figs. 38-39 are controlled in a manner similar to the single-ended sense amplifiers SA’0,1 and SA’0,3 of Figs. 35-37. That is, the timing of the SWLo.o, Vref, PREo, ISOso , PRE1 and PCOM signals is consistent throughout the operation of these single-ended sense amplifiers.Third alternate embodiment

[0374] Fig. 40 is a circuit diagram of single-ended MST sense amplifiers SA’”o,i and SA”’O,3 in accordance with a third alternate embodiment of the present invention.Single-ended MST sense amplifiers SA’”o,i and SA”’o,3 are similar to single-ended sense amplifiers SA’0,1 and SA’0,3 (Fig. 35), with similarities and differences noted below.

[0375] Within single-ended MST sense amplifiers SA’”o,i and SA’”o,3, n-channel transistors N1 -N4 and the p-channel transistors P1 -P4 are fabricated in accordance with MST technology (including superlattice channels that extend between source and drain regions of these transistors), such that the single-ended MST sense amplifiers SA’”o,i and SA’”o,3 exhibit a AV value range of 30 / 21 / 16 mV (for CB / CS = 4 / 6 / 8, respectively).

[0376] Within single-ended sense amplifiers SA’”o,i and SA’”o,3, the reference voltage Vref is set to ground (0V), and the sources of n-channel transistors N1 -N4 are coupled to receive an NCOM control signal from primary sense amplifier driver PSADi.o (rather than ground). In addition, the logic ‘0’ bit cell voltage is set to -200 mV (instead of 0V). As shown in Fig. 41 , the logic ‘0’ bit cell voltage of -200 mV is achieved by pulling the NCOM control signal down to -200 mV during the sensing operations.

[0377] Fig. 41 is a waveform diagram illustrating signals associated with read accesses to bit cells bco and bco,3 in single-ended MST sense amplifiers SA’”o,i and SA’”O,3 in accordance with the third alternate embodiment of the present invention. The waveform diagram of Fig. 41 is similar to the waveform diagram of Fig. 37, with differences noted below.

[0378] Having specified a nominal ’0’ bit cell voltage of -200 mV, nominal logic ‘0’ read bit line voltages are -40 / -29 / -22 mV for CB / CS values of 4 / 6 / 8 (i.e. , -200mV (1 + CB / CS) = -40 / -29 / -22 mV for CB / CS values of 4 / 6 / 8). Assuming that a bit line reading a logic ‘0’ value experiences 25% adverse bit line coupling from a plurality of adjacent bit lines reading logic T values, a bit line reading a logic ‘0’ value may be pulled up by 10 / 7 / 6 mV (i.e., 40 / 29 / 22 mV x 0.25) That is, a logic ‘0’ read bit line voltage will be pulled up to -30 / -22 / -16 mV. Note that with the reference voltage Vref set at 0 Volts,the logic ‘0’ read bit line voltages of -30 / -22 / -16 mV meet the specified AV values of the single-ended sense amplifiers SA”’o,i and SA”’o,3 (i.e., AV = 30 / 21 / 16 mV).

[0379] As described above, the reference voltage Vref is set to ground in the present embodiment. In order to obtain a AV value of 30 / 21 / 16 mV for a logic T read data value, the nominal value of a logic T value read on the bit line blo.i (or bio, 3) should at least be equal to 30 / 21 / 16 mV (i.e., 0 mV + 30 / 21 / 16 mV = 30 / 21 / 16 mV). Assuming 25% adverse bit line coupling from adjacent bit lines being pulled down to a logic ‘0’ read value (i.e., a negative voltage level), the nominal value of a logic T value read on the bit line blo (or bio, 3) should therefore be adjusted to 40 / 28 / 21 mV (i.e., 30 / 21 / 16 mV divided by 0.75 = 40 / 28 / 21 mV) to compensate for this adverse bit line coupling. A logic T bit line voltage of 40 / 28 / 21 mV translates to bit cell voltages of 200 / 196 / 189 mV for CB / CS values of 4 / 6 / 8 (i.e., 40 / 28 / 21 mV x (1 + CB / CS) = 200 / 196 / 189 mV). In order to ensure a minimum bit cell voltage of 200 / 196 / 189 mV at the end of a refresh interval, the bit cell should initially be written to a bit cell voltage that is about 14% greater, or 233 / 228 / 220 mV. Because the logic T bit cell voltage is only 233 / 228 / 220 mV, the isolation transistors 801-802 (and the transistor driving the sub-word line voltage SWLo.o) can be implemented conventional logic transistors, and do not need to be thick oxide transistors. More specifically, the sub-word line voltage SWLo.o (and ISOso and ISOsi voltages) only needs to be high enough to ensure that the logic T bit cell voltage of 233 / 228 / 220 mV is written to the bit cell.

[0380] The single-ended sense amplifier specified by Figs. 40-41 provides bit line CV2f power savings of about 95.5% when reading a logic T value (compared with the conventional dual-ended sense amplifier). That is, the logic T bit line CV2f power of the single-ended sense amplifier of Fig. 39 divided by the logic T bit line CV2f power of a dual-ended sense amplifier is equal to (0.233x0.233) / (1.1x1.1 ), or 0.045.

[0381] The single-ended sense amplifier specified by Figs. 40-41 provides bit line CV2f power savings of about 96.7% when reading a logic ‘0’ value (compared with the conventional dual-ended sense amplifier). That is, the logic ‘0’ bit line CV2f power of the single-ended sense amplifier of Fig. 39 divided by the logic ‘0’ bit line CV2f power of a dual-ended sense amplifier is equal to (-0.200x-0.200) / (1.1x1.1 ), or 0.033.

[0382] Assuming that read operations, on average, include half logic T values and half logic ‘0’ values, the single-ended sense amplifier specified by Fig. 40 achieves an average power savings of 96.1 % (95.5% x 50 + 96.7% x 50 =96.1%), or a power reduction of about 26x, with respect to a conventional dual-ended sense amplifier.

[0383] Note that the single-ended sense amplifiers SA”’o,i and SA”’o,3 of Figs. 39-40 are controlled in a manner similar to the single-ended sense amplifiers SA’0,1 and SA’0,3 of Figs. 35-37. That is, the timing of the SWLo.o, PREo, ISOso , PRE1 and PCOM signals is consistent throughout the operation of these single-ended sense amplifiers. Note that when the single-ended sense amplifiers SA”’o,i and SA”’o,3 are enabled at time T4 (i.e. , when the PCOM signal is driven from 0V to 233 / 228 / 220 mV), the NCOM signal is driven from 0V down to a negative voltage of -200 mV. This advantageously allows the INT2 node and the bit line bio, 3 to be driven to -200 mV to properly refresh the bit cell voltage of bit cell bco,3.Fourth alternate embodiment

[0384] Fig. 42 is a circuit diagram of single-ended MST sense amplifiers SA””o,i and SA””O,3 in accordance with a fourth alternate embodiment of the present invention. Single-ended MST sense amplifiers SA””o,i and SA””o,3 are similar to single-ended sense amplifiers SA”’o,i and SA”’o,3 (Fig. 40), with similarities and differences noted below.

[0385] Within single-ended MST sense amplifiers SA””o,i and SA””o,3, n-channel transistors N1 -N4 and the p-channel transistors P1 -P4 are fabricated in accordance with MST technology (including superlattice channels that extend between source and drain regions of these transistors), such that the single-ended MST sense amplifiers SA””o,i and SA””o,3 exhibit a AV value range of 30 / 21 / 16 mV.

[0386] Within single-ended sense amplifiers SA””o,i and SA””o,3, the reference voltage Vref is set to ground (0V), and the NCOM control signal is pulled down to -100 mV (instead of -200 mV) to activate the single-ended sense amplifiers SA””o,i and SA””O,3. Thus, the logic ‘0’ bit cell voltage is set to -100 mV (instead of -200 mV).

[0387] In addition, single-ended MST sense amplifiers SA””o,i and SA””o,3 include kick capacitors 821 , 822, 823 and 824, which are coupled to bit lines blo , bio, 3, bh,i and bh ,3, respectively. As described in more detail below, each of the kick capacitors 821 - 824 is designed to kick down the voltage on the associated bit lines during read operations.

[0388] Fig. 43 is a waveform diagram illustrating signals associated with read accesses to bit cells bco and bco,3 in single-ended MST sense amplifiers SA””o,i and SA””O,3 in accordance with the fourth alternate embodiment of the present invention. The waveform diagram of Fig. 43 is similar to the waveform diagram of Fig. 41 , with differences noted below.

[0389] Having specified a nominal ’0’ bit cell voltage of -100 mV, nominal logic ‘0’ read bit line voltages are -20 / -14 / -11 mV for CB / CS values of 4 / 6 / 8 (i.e. , -100mV (1 + CB / CS) = -20 / -14 / -11 mV for CB / CS values of 4 / 6 / 8). Assuming that a bit line reading a logic ‘0’ value experiences 25% adverse bit line coupling from a plurality of adjacent bit lines reading logic T values, a bit line reading a logic ‘0’ value may be pulled up by 5 / 4 / 3 mV (i.e., 20 / 14 / 11 mV x 0.25) That is, a logic ‘0’ read bit line voltage will be pulled up to -15 / -10 / -8 mV. Note that with a reference voltage Vref equal to 0 Volts, these logic ‘0’ read bit line voltages do not meet the specified AV values of the single-ended sense amplifiers SA””o,i and SA””o,3 (i.e., AV = 30 / 21 / 16 mV). In order to obtain the AV values of 30 / 21 / 16 mV required to read a logic ‘0’ read data value, the switched kick capacitors 821-822 are activated to kick the voltages on the corresponding bit lines blo,i and bio, 3 down by -15 / -11 / -8 mV for CB / CS values of 4 / 6 / 8, respectively. As a result, the logic ‘0’ bit line voltage is kicked down from -15 / -10 / -8 mV to -30 / -21 / -16 mV (i.e., -15 / - 10 / -8 mV - 15 / 11 / 8 mV = -30 / -21 / -16 mV), thereby meeting the specified AV values of the single-ended sense amplifiers SA””o,i and SA””o,3 (i.e., AV = 30 / 21 / 16 mV). In the embodiment of Figs. 42-43, the kick capacitors 821-822 are controlled to kick the voltages on bit lines blo,i and bio, 3 between time T2 and time T3 (i.e., at time T2.5). In one embodiment, the kick capacitors are switched on as close to time T3 as possible.

[0390] As described above, the reference voltage Vref is set to ground in the present embodiment. In order to obtain a AV value of 30 / 21 / 16 mV for a logic T read data value, the nominal value of a logic T value read on the bit line bloj (or bio, 3) should at least be equal to 30 / 21 / 16 mV (i.e., 0 mV + 30 / 21 / 16 mV = 30 / 21 / 16 mV). Assuming 25% adverse bit line coupling from adjacent bit lines being pulled down to a logic ‘0’ read value (i.e., a negative voltage level), the nominal value of a logic T value read on the bit line bloj (or bio, 3) should therefore be adjusted to 40 / 28 / 21 mV (i.e., 30 / 21 / 16 mV divided by 0.75 = 40 / 28 / 21 mV) to compensate for this adverse bit line coupling. The nominal value of a logic T value read on the bit line bloj (or bio, 3) should also be adjusted upward by 15 / 11 / 8 mV to compensate for the kick down voltages applied by kick capacitors 821-822. More specifically, the nominal value of a logic T value read on the bit line blo (or bio, 3) should therefore be adjusted to 55 / 39 / 29 mV (i.e., 40 / 28 / 21 mV + 15 / 11 / 8 mV = 55 / 39 / 29 mV) to compensate for kick capacitor voltages.

[0391] A logic T bit line voltage of 55 / 39 / 29 mV translates to bit cell voltages of 275 / 273 / 261 mV for CB / CS values of 4 / 6 / 8 (i.e., 55 / 39 / 29 mV x (1 + CB / CS) = 275 / 273 / 261 mV). In order to ensure a minimum bit cell voltage of 275 / 273 / 261 mV at the end of a refresh interval, the bit cell should initially be written to a bit cell voltagethat is about 14% greater, or 320 / 317 / 304 mV. Because the logic T bit cell voltage is only 320 / 317 / 304 mV, the isolation transistors 801 -802 (and the transistor driving the sub-word line voltage SWLo.o) can be implemented conventional logic transistors, and do not need to be thick oxide transistors. More specifically, the sub-word line voltage SWLo.o (and ISOso and ISOsi voltages) only needs to be high enough to ensure that the logic T bit cell voltage of 320 / 317 / 304 mV is written to the bit cell.

[0392] The single-ended sense amplifier specified by Figs. 42-43 provides bit line CV2f power savings of about 91 .5% when reading a logic T value (compared with the conventional dual-ended sense amplifier). That is, the logic T bit line CV2f power of the single-ended sense amplifier of Fig. 39 divided by the logic T bit line CV2f power of a dual-ended sense amplifier is equal to (0.320x0.320) / (1.1x1.1 ), or 0.085.

[0393] The single-ended sense amplifier specified by Figs. 40-41 provides bit line CV2f power savings of about 99.2% when reading a logic ‘0’ value (compared with the conventional dual-ended sense amplifier). That is, the logic ‘0’ bit line CV2f power of the single-ended sense amplifier of Fig. 39 divided by the logic ‘0’ bit line CV2f power of a dual-ended sense amplifier is equal to (-0.100x-0.100) / (1.1x1.1 ), or 0.008.

[0394] Assuming that read operations, on average, include half logic T values and half logic ‘0’ values, the single-ended sense amplifier specified by Fig. 40 achieves an average power savings of 95.4% (91 .5% x 50 + 99.2% x 50 =95.4%), or a power reduction of about 22x, with respect to a conventional dual-ended sense amplifier.

[0395] Note that the single-ended sense amplifiers SA””o,i and SA””o,3 of Figs. 42- 43 are controlled in a manner similar to the single-ended sense amplifiers SA”o,iand SA”O,3 of Figs. 38-39. That is, the timing of the SWLo.o, PREo, ISOso , PREi and PCOM signals is consistent throughout the operation of these single-ended sense amplifiers. Note that when the single-ended sense amplifiers SA””o,i and SA””o,3 are enabled at time T4 (i.e., when the PCOM signal is driven from 0V to 320 / 317 / 304 mV), the NCOM signal is driven from 0V down to a negative voltage of -100 mV. This advantageously allows the INT2 node and the bit line bio, 3 to be driven to -100 mV to properly refresh the bit cell voltage of bit cell bco,3.

[0396] In the embodiments described above, the voltage required to be applied to the capacitor plate of the DRAM bit cells bco and bco,3 (i.e., Vplate) is significantly reduced, because the logic T bit cell voltage is significantly reduced. In the embodiments described above, the bit cell voltage is reduced from 1.1V (for a conventional dual-ended sense amplifier) to about 985 mV (for the single-ended sense amplifier of Figs. 35-36), about 488mV (for the single-ended sense amplifier of Fig. 37),about 331 mV (for the single-ended sense amplifier of Figs. 38-39), about 233 mV (for the single-ended sense amplifier of Figs. 40-41 ), and about 320 mV (for the single- ended sense amplifier of Figs. 42-43). Assuming capacitor plate voltage Vplate is half of the bit cell voltage, the capacitor plate voltage can be reduced from 550 mV (for a conventional dual-ended sense amplifier) to about 493 mV, 244 mV, 166 mV, 117 mV and 160 mV for the single-ended sense amplifiers of the above described embodiments. The reduced voltages across the DRAM bit cell capacitors may advantageously enable the use of different capacitor materials / structures within the DRAM bit cells. In addition, the single-ended sense amplifiers described above enable the fabrication of a DRAM bit cell having a 4F2unit cell area because there are no dummy bit lines running through the bit cell array / sense amplifier region.

[0397] Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Accordingly, the present invention is limited only by the following claims.

Claims

CLAIMSI claim:1 . An integrated circuit chip comprising: a plurality of unit cells arranged in an array having a plurality of rows and columns, wherein each of the unit cells comprises: a plurality of DRAM memory strips (S(i ,1)0— S(i ,1)15), each comprising: a plurality of independently accessible DRAM sub-arrays arranged in a row, wherein each of the DRAM sub-arrays includes an array of DRAM bit cells arranged in rows and columns, wherein the DRAM subarrays of the plurality of DRAM memory strips are further arranged in a first plurality of columns of DRAM sub-arrays; and a plurality of primary single-ended sense amplifier circuits, wherein each of the plurality of DRAM sub-arrays is coupled to a corresponding pair of the plurality of primary single-ended sense amplifier circuits; a first plurality of global bit line sets, wherein each of the first plurality of global bit line sets is coupled to a corresponding one of the first plurality of columns of DRAM sub-arrays through the primary single-ended sense amplifier circuits coupled to the DRAM sub-arrays in the corresponding one of the first plurality of columns of DRAM sub-arrays; a first multiplexer circuit coupled to each of the first plurality of global bit line sets, wherein the first multiplexer circuit selectively couples one of the first plurality of global bit line sets to a first set of global input / output lines; a first secondary sense amplifier circuit coupled to the first set of global input / output lines; and a first set of through silicon vias coupled to the first secondary sense amplifier circuit.

2. The integrated circuit chip of claim 1 , wherein the DRAM sub-arrays of the plurality of DRAM memory strips are further arranged in a second plurality of columns of DRAM sub-arrays, wherein each of the unit cells further comprises: a second plurality of global bit line sets, wherein each of the second plurality of global bit line sets is coupled to a corresponding one of the second plurality of columns of DRAM sub-arrays through the primary single-ended sense amplifier circuits coupled to the DRAM sub-arrays in the corresponding one of the second plurality of columns of DRAM sub-arrays;a second multiplexer circuit coupled to each of the second plurality of global bit line sets, wherein the second multiplexer circuit selectively couples one of the second plurality of global bit line sets to a second set of global input / output lines; a second secondary sense amplifier circuit coupled to the second set of global input / output lines; and a second set of through silicon vias coupled to the second secondary sense amplifier circuit.

3. The integrated circuit chip of claim 1 , wherein a first column of unit cells of the plurality of columns of unit cells, and an adjacent second column of unit cells of the plurality of columns of unit cells are oriented such that the first sets of through silicon vias of the unit cells of the first column of unit cells are located immediately adjacent to the first sets of through silicon vias of the unit cells of the second column of unit cells.

4. The integrated circuit chip of claim 1 , wherein the first secondary sense amplifier circuit comprises a plurality of write single-ended sense amplifiers, each coupled to a corresponding one of the global input / output lines of the first set of global input / output lines, and a plurality of read single-ended sense amplifiers, each coupled to a corresponding one of the global input / output lines of the first set of global input / output lines.

5. The integrated circuit chip of claim 4, wherein each of the through silicon vias in the first set of through silicon vias is coupled to a corresponding pair of the plurality of write single-ended sense amplifiers and a corresponding pair of the plurality of read single-ended sense amplifiers.

6. The integrated circuit chip of claim 4, wherein each of the plurality of read single-ended sense amplifiers is controlled to simultaneously sample data on a corresponding one of the global input / output lines of the first set of global input / output lines, wherein a first half of the plurality of read single-ended sense amplifiers is controlled to simultaneously provide the data sampled on the corresponding one of the global input / output lines of the first set of global input / output lines to the first set of through silicon vias during a first time period, andwherein a second half of the plurality of read single-ended sense amplifiers is controlled to simultaneously provide the data sampled on the corresponding one of the global input / output lines of the first set of global input / output lines to the first set of through silicon vias during a second time period.

7. The integrated circuit chip of claim 4, wherein a first half of the plurality of write single-ended sense amplifiers are controlled to sample a first set of data on the first set of through silicon vias during a first time period and hold the first set of data during a second time period, wherein a second half of the plurality of write single-ended sense amplifiers are controlled to sample a second set of data on the first set of through silicon vias during the second time period, and wherein the plurality of write single-ended sense amplifiers are controlled to simultaneously provide the first and second sets of data on the first set of global input / output lines during a third time period.

8. The integrated circuit chip of claim 1 , wherein each of the DRAM memory strips includes a plurality of main word lines, each extending through all of the plurality of DRAM sub-arrays of the DRAM memory strip.

9. The integrated circuit chip of claim 8, wherein each of the plurality of DRAM memory strips further comprises a main word line driver that activates one of the corresponding plurality of main word lines when the DRAM memory strip is accessed.

10. The integrated circuit chip of claim 8, wherein each of the plurality of DRAM sub-arrays includes a dedicated plurality of sub-word lines, each coupled to a corresponding one of the rows of DRAM cells of the array of DRAM cells.11 . The integrated circuit chip of claim 10, wherein each of the plurality of DRAM sub-arrays includes a plurality of sub-word line driver circuits, each coupled to a corresponding one of the dedicated plurality of sub-word lines of the DRAM sub-array.

12. The integrated circuit chip of claim 11 , wherein each of the main word lines is coupled to a corresponding plurality of the sub-word line driver circuits within each of the plurality of DRAM sub-arrays.

13. The integrated circuit chip of claim 12, wherein each of the main word lines is coupled to eight of the sub-word line driver circuits within each of the plurality of DRAM sub-arrays.

14. The integrated circuit chip of claim 11 , wherein each of the plurality of DRAM sub-arrays receives a corresponding sub-array enable signal, wherein each of the sub-word line driver circuits of each of the plurality of DRAM sub-arrays is coupled to receive the corresponding sub-array enable signal.

15. The integrated circuit chip of claim 14, wherein adjacent DRAM subarrays in each of the first plurality of columns of DRAM sub-arrays share one of the plurality of primary single-ended sense amplifier circuits.

16. The integrated circuit chip of claim 15, wherein each of the primary single- ended sense amplifier circuits is coupled to half of the plurality of columns of DRAM bit cells in the corresponding DRAM sub-array.

17. The integrated circuit chip of claim 15, wherein each of the primary single- ended sense amplifier circuits comprises a plurality of single-ended sense amplifiers.

18. The integrated circuit chip of claim 17 wherein each of the first plurality of global bit line sets comprises a plurality of global bit lines, each coupled to a plurality of the single-ended sense amplifiers in the primary single-ended sense amplifier circuits coupled to the DRAM sub-arrays in a column of the first plurality of columns of DRAM sub-arrays.

19. The integrated circuit chip of claim 15, wherein each of the primary single- ended sense amplifier circuits comprises a primary sense amplifier driver circuit (PSADi.o), coupled to receive the sub-array enable signal (EN_SUBAo,o, EN_SUBAi,o) of the corresponding DRAM sub-array.

20. The integrated circuit chip of claim 1 , wherein the global bit lines of each of the first plurality of global bit line sets are evenly distributed across the first multiplexer circuit.21 . The integrated circuit chip of claim 2, wherein each of the unit cells further comprises a third set of through silicon vias for receiving an access instruction to the unit cell.

22. The integrated circuit chip of claim 21 , wherein the access instruction to the unit cell comprises: a unit cell address for selecting the unit cell; a strip address for selecting one of the plurality of DRAM memory strips; a first DRAM sub-array column address for selecting one of the first plurality of columns of DRAM sub-arrays; and a second DRAM sub-array column address for selecting one of the second plurality of columns of DRAM sub-arrays.

23. The integrated circuit chip of claim 22, wherein each of the DRAM memory strips includes a plurality of main word lines, each extending through all of the plurality of DRAM sub-arrays of the DRAM memory strip, wherein the access instruction to the unit cell further comprises a main word line address for selecting one of the plurality of main word lines.

24. The integrated circuit of claim 23, wherein each of the plurality of DRAM sub-arrays includes a dedicated plurality of sub-word lines, each coupled to a corresponding one of the rows of DRAM cells of the DRAM sub-array, wherein the access instruction to the unit cell further comprises: a first sub-word line address for selecting one of the plurality of sub-word lines of the first plurality of columns of DRAM sub-arrays; and a second sub-word line address for selecting one of the plurality of subword lines of the second plurality of columns of DRAM sub-arrays.

25. The integrated circuit chip of claim 21 , wherein each row of DRAM memory strips extends from a first edge of the unit cell to an opposing second edge of unit cell, wherein the first, second and third sets of through silicon vias are sparsely populated near the first and second edges of the unit cell, enabling a plurality of metal lines to pass between the through silicon vias of the first, second and third sets of through silicon vias near the first and second edges of the unit cell.

26. The integrated circuit chip of claim 2, wherein each of the plurality of DRAM memory strips further comprises a sub-array decoder circuit that selectively enables up to one of the DRAM sub-arrays of the DRAM memory strip included in the first plurality of columns of DRAM sub-arrays and up to one of the DRAM sub-arrays of the DRAM memory strip included in the second plurality of columns of DRAM subarrays.

27. A multi-threaded dynamic random access memory (MTDRAM) processor system comprising: a first integrated circuit chip comprising at least 2048 processor blocks arranged in a first array; and a second integrated circuit chip comprising at least 2048 independent dynamic random access memory (DRAM) unit cells arranged in a second array, wherein each of the at least 2048 processor blocks is coupled to a corresponding one of the at least 2048 independent DRAM unit cells of the second array of DRAM unit cells by through silicon via (TSV) structures.

28. The MTDRAM processor system of claim 27, further comprising: a third integrated circuit chip comprising at least 2048 independent DRAM unit cells arranged in a third array, wherein each of the at least 2048 processor blocks is coupled to a corresponding one of the at least 2048 independent DRAM unit cells of the third array by through silicon via (TSV) structures.

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