Solar cell and preparation method therefor, and photovoltaic module

Abstract

The present invention relates to a solar cell and a preparation method therefor, and a photovoltaic module. The solar cell comprises: an N-type substrate; a patterned first passivation contact structure, which is arranged on a light-receiving surface of the substrate, and comprises a first dielectric layer having a thickness less than or equal to 2 nm and an N-type first doped polysilicon layer; a second passivation contact structure, which is arranged on the entire backlight surface of the substrate, and comprises a second dielectric layer having a thickness greater than 2 nm and having a through hole and a P-type second doped polysilicon layer having a doping concentration of 5×1018 to 3×1020 atom / cm3; a first functional layer on the substrate and the first passivation contact structure; a second functional layer on the second doped polysilicon layer; a first electrode, which penetrates the first functional layer to make ohmic contact with the first doped polysilicon layer; and a second electrode, which penetrates the second functional layer to make ohmic contact with the second doped polysilicon layer.

Description

Solar cell and preparation method thereof, photovoltaic module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 5, 2024, with application number 202410017395.X and application name “Solar cells and their preparation methods, photovoltaic modules”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0003] Passivated contact solar cells (PCCs) are a type of solar cell with relatively high photoelectric conversion efficiency and are well-suited for industrial deployment. However, when using industrial production processes to manufacture PCCs, their photoelectric conversion efficiency has reached a bottleneck, currently around 25.1%. Limited by front-side recombination losses and current transmission losses, this type of solar cell faces significant challenges in further improving its photoelectric conversion efficiency. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a solar cell and a preparation method thereof, and a photovoltaic module to solve the problem that the existing technology is difficult to break through the photoelectric conversion efficiency barrier of passivated contact solar cells.

[0005] In a first aspect, the present application provides a solar cell, comprising:

[0006] a substrate having an N-type conductivity;

[0007] a patterned first passivation contact structure, disposed on the light-receiving surface of the substrate, the first passivation contact structure comprising a first dielectric layer proximal to the substrate and a first doped polysilicon layer distal to the substrate, the first doped polysilicon layer having the N-type conductivity; wherein the thickness of the first dielectric layer is less than or equal to 2 nm;

[0008] A second passivation contact structure for the entire surface is provided on the backlight surface of the substrate, the second passivation contact structure includes a second dielectric layer close to the substrate and a second doped polysilicon layer away from the substrate, the second doped polysilicon layer has a P-type conductivity type different from the N-type conductivity type, so that the second doped polysilicon layer and the substrate form a PN junction; wherein the thickness of the second dielectric layer is greater than 2 nm, the second dielectric layer has a through hole connecting the substrate and the second doped polysilicon layer, and the doping concentration of the P-type conductive element in the second doped polysilicon layer is 5×10 18 atom / cm 3 ~3×1020 atom / cm 3 ;

[0009] a first functional layer, provided on the light-receiving surface of the substrate and a side of the first doped polysilicon layer away from the substrate;

[0010] a second functional layer, provided on a side of the second doped polysilicon layer away from the substrate;

[0011] a first electrode, penetrating the first functional layer and making ohmic contact with the first doped polysilicon layer; a patterned region of the first passivation contact structure and a patterned region of the first electrode being arranged correspondingly;

[0012] The second electrode penetrates the second functional layer and is in ohmic contact with the second doped polysilicon layer.

[0013] Furthermore, the substrate in the area covered by the first passivation contact structure is 0.5 μm to 1.5 μm thicker than the substrate in the area not covered by the first passivation contact structure.

[0014] Furthermore, the diameter of the through hole is 50nm to 500nm, and the number of the through holes is 1×10 4 pieces / cm 2 ~1.6×10 8 pieces / cm 2 .

[0015] Furthermore, the thickness of the first doped polysilicon layer is 40 nm to 200 nm.

[0016] Furthermore, the thickness of the second doped polysilicon layer is 200 nm to 400 nm.

[0017] Furthermore, the first doped polysilicon layer is doped with an N-type conductive element, and the N-type conductive element includes at least one of phosphorus, germanium or selenium.

[0018] Furthermore, the P-type conductive element includes at least one of boron, indium or gallium.

[0019] Furthermore, the line width of the first passivation contact structure is 20 μm to 110 μm.

[0020] Furthermore, the first functional layer includes a first passivation layer disposed close to the substrate and a first anti-reflection layer disposed away from the substrate.

[0021] Furthermore, the second functional layer includes a second passivation layer disposed close to the second doped polysilicon layer and a second anti-reflection layer disposed away from the second doped polysilicon layer.

[0022] Furthermore, the ratio of the number of gate lines of the second electrode to the number of gate lines of the first electrode is 1.2-1.6:1.

[0023] In a second aspect, an embodiment of the present application provides a method for preparing a solar cell according to the first aspect, the method comprising the following steps:

[0024] Forming a passivation contact structure: sequentially disposing the first dielectric layer and the first doped amorphous silicon layer on the light-receiving surface of the substrate to form the first passivation contact structure, and sequentially disposing the second dielectric layer and the second doped amorphous silicon layer on the backlight surface of the substrate to form the second passivation contact structure, wherein the thickness of the first dielectric layer is less than or equal to 2 nm, and the thickness of the second dielectric layer is greater than 2 nm;

[0025] Annealing and patterning: annealing the substrate on which the first passivation contact structure and / or the second passivation contact structure are formed, so that the first doped amorphous silicon layer is transformed into the first doped polysilicon layer, and / or the second doped amorphous silicon layer is transformed into the second doped polysilicon layer, and patterning the first passivation contact structure is performed to obtain a patterned first passivation contact structure;

[0026] Post-processing: forming the first functional layer on the light-receiving surface of the substrate and the patterned first doped polysilicon layer, forming the second functional layer on the second doped polysilicon layer, making the first electrode on the first functional layer, and making the second electrode on the second functional layer.

[0027] Furthermore, the step of forming a passivation contact structure includes:

[0028] Alkali polishing: polishing the light-receiving surface and the backlight surface of the substrate using a first alkaline agent;

[0029] Depositing the second passivation contact structure: depositing the second dielectric layer and the second doped amorphous silicon layer in sequence on the backlight side of the substrate;

[0030] Texturing: firstly, using a first acid agent to remove the second doped amorphous silicon layer and the second dielectric layer that are plated around the light-receiving surface and the edge, and then using a second alkaline agent to texturing the light-receiving surface of the substrate;

[0031] Depositing the first passivation contact structure: depositing the first dielectric layer and the first doped amorphous silicon layer in sequence on the light-receiving surface after texturing.

[0032] Furthermore, the step of depositing the second passivation contact structure includes: depositing the second dielectric layer, the back intrinsic layer, the back doping layer doped with the P-type conductive element, and the back mask layer in sequence on the backlight surface after alkali polishing by a PECVD process;

[0033] The texturing step comprises: first using the first acid agent to remove the back mask layer, the back doping layer, the back intrinsic layer and the second dielectric layer that are plated around the light-receiving surface and the edge, and then using the second alkaline agent to texturize the light-receiving surface;

[0034] The step of depositing the first passivation contact structure includes: depositing the first dielectric layer, the front intrinsic layer, and the front doped layer doped with N-type conductive elements in sequence on the light-receiving surface after texturing by using a PECVD process.

[0035] Furthermore, the steps of annealing and patterning include:

[0036] Printing: Printing a patterned alkali-resistant paste on a preset area of ​​the front doping layer, and drying to solidify the alkali-resistant paste;

[0037] Cleaning: first, using a third alkaline agent to etch away the first doped amorphous silicon layer, the first dielectric layer, and a portion of the substrate that are not covered in the preset area on one side of the light-receiving surface, and then using a second acid agent to etch away the alkali-resistant slurry and the back mask layer located on the backlight side, so that the light-receiving surface of the substrate is formed with a patterned first dielectric layer and a patterned first doped amorphous silicon layer, and the substrate located in the preset area is 0.5 μm to 1.5 μm thicker than the substrate located in the preset area that is not covered, and the backlight side of the substrate is formed with the entire second dielectric layer and the second doped amorphous silicon layer;

[0038] Annealing: in an inert atmosphere, at 850°C to 1000°C for 90 minutes to 150 minutes, so that the first doped amorphous silicon layer is transformed into the first doped polycrystalline silicon layer, the second doped amorphous silicon layer is transformed into the second doped polycrystalline silicon layer, and the PN junction is formed between the substrate and the second doped polycrystalline silicon layer.

[0039] Furthermore, in the printing step, the width of the printed patterned alkali-resistant slurry is 20 μm to 110 μm, the drying temperature after printing is 150° C. to 250° C., and the drying time is 8s to 12s.

[0040] Furthermore, in the cleaning step, the third alkaline agent comprises an alkali metal hydroxide and a texturing additive in a volume ratio of 1:1 to 3:1, and the etching temperature using the third alkaline agent is 70° C. to 90° C., and the etching time is 1 minute to 3 minutes.

[0041] Furthermore, in the cleaning step, the second acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0042] Furthermore, the step of depositing the second passivation contact structure includes: forming the second dielectric layer on the backlight surface after alkali polishing by a thermal oxidation process, forming a back intrinsic amorphous silicon layer by an LPCVD process, and then doping the back intrinsic amorphous silicon layer with a P-type conductive element by a diffusion process to transform the back intrinsic amorphous silicon layer into the second doped polysilicon layer;

[0043] The texturing step comprises: first using the first acid agent to remove the second doped amorphous silicon layer and the second dielectric layer that are plated around the light-receiving surface and the edge, and then using the second alkaline agent to texturing the light-receiving surface;

[0044] The step of depositing the first passivation contact structure includes: depositing the first dielectric layer, the front intrinsic layer, the front doped layer doped with N-type conductive elements, and the front mask layer in sequence on the light-receiving surface after texturing by the PECVD process.

[0045] Furthermore, the steps of annealing and patterning include:

[0046] Annealing: annealing in an inert atmosphere at 850° C. to 950° C. for 90 min to 150 min to transform the first doped amorphous silicon layer into the first doped polycrystalline silicon layer;

[0047] Printing: Printing a patterned acid-resistant paste on a preset area of ​​the front mask layer, and drying to solidify the acid-resistant paste;

[0048] Cleaning: first use a third acid to etch and remove the front mask layer that is not covered by the preset area on the light-receiving side, then use a fourth alkaline agent to etch and remove the first doped polysilicon layer, the first dielectric layer, and the acid-resistant slurry that are not covered by the preset area on the light-receiving side, and use a fourth acid to remove the remaining front mask layer, so that the light-receiving surface of the substrate forms a patterned first dielectric layer and a patterned first doped amorphous silicon layer, and the backlight surface of the substrate forms the second dielectric layer and the second doped polysilicon layer on the front side.

[0049] Furthermore, in the printing step, the width of the printed patterned acid-resistant paste is 20 μm to 110 μm, the drying temperature after printing is 150° C. to 250° C., and the drying time is 8s to 12s.

[0050] Furthermore, in the cleaning step, the third acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0051] Furthermore, in the cleaning step, the fourth alkaline agent comprises an alkali metal hydroxide and a texturing additive in a volume ratio of 1:1 to 3:1, and the etching temperature using the fourth alkaline agent is 70° C. to 90° C., and the etching time is 1 min to 3 min.

[0052] Furthermore, in the cleaning step, the fourth acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0053] Furthermore, the step of forming a passivation contact structure includes:

[0054] Texturing: texturing the substrate using a fifth alkaline agent;

[0055] Depositing the first passivation contact structure: depositing the first dielectric layer and the first doped amorphous silicon layer in sequence on the light-receiving surface after texturing;

[0056] Alkali polishing: using a fifth acid agent to remove a portion of the first doped amorphous silicon layer that is plated around the backlight surface, and then using a sixth alkaline agent to polish the backlight surface of the substrate, and remove the remaining portion of the first doped amorphous silicon layer and the first dielectric layer that are plated around the back surface and edge;

[0057] Depositing the second passivation contact structure: depositing the second dielectric layer and the second doped amorphous silicon layer in sequence on the backlight surface.

[0058] Furthermore, the step of depositing the first passivation contact structure includes: depositing the first dielectric layer, the front intrinsic layer, the front doped layer doped with N-type conductive elements, and the front mask layer in sequence on the light-receiving surface after texturing by a PECVD process;

[0059] The alkaline polishing step includes: first using the fifth acid agent to remove the front mask layer plated around the backlight surface, then using the sixth alkaline agent to polish the backlight surface of the substrate, and removing the front doped layer, the front intrinsic layer and the first dielectric layer plated around the back and edge;

[0060] The step of depositing the second passivation contact structure includes: depositing the second dielectric layer, the back intrinsic layer, the back doped layer doped with P-type conductive elements, and the back mask layer in sequence on the backlight surface after alkali polishing by PECVD process.

[0061] Furthermore, the steps of annealing and patterning include:

[0062] Annealing: annealing the substrate on which the first passivation contact structure and the second passivation contact structure are formed, in an inert atmosphere at 850° C. to 1000° C. for 90 min to 150 min;

[0063] Printing: printing a patterned acid-resistant paste in the preset area of ​​the front mask layer, and drying to solidify the acid-resistant paste;

[0064] Cleaning: first use the sixth acid agent to etch and remove the front mask layer that is not covered by the preset area in the light-receiving surface, then use the seventh alkaline agent to etch and remove the acid-resistant slurry, and remove the first dielectric layer and the first doped amorphous silicon layer that are not covered by the preset area in the light-receiving surface, and then use the seventh acid agent to remove the front mask layer and the back mask layer.

[0065] Furthermore, in the printing step, the width of the printed patterned acid-resistant paste is 20 μm to 110 μm, the drying temperature after printing is 150° C. to 250° C., and the drying time is 8s to 12s.

[0066] Furthermore, in the cleaning step, the sixth acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0067] Furthermore, in the cleaning step, the seventh alkaline agent comprises an alkali metal hydroxide and a texturing additive in a volume ratio of 1:1 to 3:1, and the etching temperature using the seventh alkaline agent is 70° C. to 90° C., and the etching time is 1 min to 3 min.

[0068] Furthermore, in the cleaning step, the seventh acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0069] Furthermore, the first functional layer includes a first passivation layer and a first anti-reflection layer, and the second functional layer includes a second passivation layer and a second anti-reflection layer; and the post-processing step includes:

[0070] Depositing the first passivation layer and the second passivation layer on the light-receiving surface and the backlight surface respectively using an ALD process;

[0071] Depositing the first anti-reflection layer on the first passivation layer and depositing the second anti-reflection layer on the second passivation layer by using a PECVD process;

[0072] Printing a first electrode on the front surface to make ohmic contact between the first electrode and the first doped polysilicon layer located in the preset area;

[0073] A second electrode is printed on the back surface to make ohmic contact between the second electrode and the second doped polysilicon layer.

[0074] Furthermore, in the ALD process, the deposition temperature is 200° C. to 280° C., and the thicknesses of the deposited first passivation layer and the second passivation layer are 3 nm to 5 nm, respectively.

[0075] In a third aspect, the embodiments of the present application also provide a photovoltaic module, which includes the solar cell described in the first aspect, or the photovoltaic module includes the solar cell prepared by the preparation method described in the second aspect.

[0076] Compared with the prior art, the present invention has the following beneficial effects:

[0077] This application provides a composite functional solar cell that has both double-sided passivation contacts and a PN junction structure formed on the backlight side, with a localized passivation contact structure on the front side and a full-surface passivation contact structure on the backside. Due to the multiple structural features of the front side, where the localized passivation contact structure is only provided in the patterned area where the first electrode is provided, the full-surface passivation contact structure is used on the backside, and a decoupled PN junction formed on the backside between the second doped polysilicon layer and the substrate is formed, the solar cell of this embodiment can simultaneously achieve low front-side recombination losses and current transmission losses, thereby increasing the solar cell's photoelectric conversion efficiency to over 25.6%.

[0078] More importantly, based on the above structural features, the embodiments of the present application control the thickness of the film layers used for carrier transmission and passivation in the passivation contact structure on the light-receiving side and the back-light side respectively, and cooperate with the structural features of N-type doping on the front side and P-type doping and heavy doping on the back side to achieve effective transmission of electrons on the light-receiving side and holes on the back-light side. Among them, on the light-receiving side, a first dielectric layer with a thickness of less than or equal to 2nm is used. The very thin first dielectric layer can achieve the transmission of very small electrons through quantum tunneling. On the back-light side, a second dielectric layer with a thickness greater than 2nm is used to work together with a second doped polysilicon layer with a P-type heavy doping located on the back-light side. Although under this thickness condition, carriers can hardly pass through the second dielectric layer through the quantum tunneling effect, the through-holes of the second dielectric layer can be used as a directly conductive transmission channel, and the characteristic that the P-type heavily doped polysilicon layer has a strong repulsive effect on electrons is utilized to ensure that larger holes can be selectively transmitted in the through-holes, while smaller electrons are blocked, thereby achieving direct transmission of holes between the second doped polysilicon layer and the substrate. In addition, since the second dielectric layer is thicker, it also has a good passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0080] FIG1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

[0081] FIG2 is an enlarged schematic diagram of the structure at point A in FIG1 ;

[0082] FIG3 is a process flow chart of the method for preparing the solar cell of Example 1;

[0083] FIG4 is a process flow chart of the method for preparing the solar cell of Example 2;

[0084] FIG5 is a process flow chart of the method for preparing the solar cell of Example 3.

[0085] Description of the drawings: 1. Substrate; 2. First passivation contact structure; 21. First dielectric layer; 22. First doped polysilicon layer; 3. Second passivation contact structure; 31. Second dielectric layer; 311. Through hole; 32. Second doped polysilicon layer; 4. First functional layer; 41. First passivation layer; 42. First anti-reflection layer; 5. Second functional layer; 51. Second passivation layer; 52. Second anti-reflection layer; 6. First electrode; 7. Second electrode. DETAILED DESCRIPTION

[0086] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0087] In the present invention, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe the present invention and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0088] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0089] Furthermore, the terms "installed," "disposed," "provided with," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0090] Furthermore, the terms "first," "second," and the like are primarily used to distinguish between different devices, elements, or components (which may or may not be of the same type and configuration), and are not intended to indicate or imply the relative importance or quantity of the devices, elements, or components indicated. Unless otherwise specified, "plurality" means two or more.

[0091] The passivated contact solar cell in the related art uses a boron-diffused emitter on the light-receiving side and a tunneling layer and first-doped polysilicon layer on the backlight side. While these passivated contact solar cells, intended for industrial mass production, exhibit excellent high-temperature resistance, their photoelectric conversion efficiency has reached a bottleneck and remains at approximately 25.1%. This is primarily because the emitter on the front side of the passivated contact solar cell must balance the effects of Auger recombination and current transmission losses.

[0092] Among them, since the front of the passivated contact solar cell is a boron diffusion emitter, if the current transmission loss is reduced by reducing the boron diffusion square resistance on the front, the Auger recombination loss on the front will be greatly increased at the same time; if the resistance is reduced by adding metallized grid lines and thus the current transmission loss is reduced, the metallized grid lines will block more sunlight, resulting in the light not being absorbed by the silicon wafer, which will still affect the improvement of the photoelectric conversion efficiency. It can be seen that it is difficult for the current passivated contact solar cell to achieve both the reduction of current transmission loss and the reduction of recombination loss at the same time, and therefore restricts the further improvement of the photoelectric conversion efficiency of the passivated contact solar cell. Based on the analysis of the above technical problems, the embodiments of the present application provide a solar cell and its preparation method, and a photovoltaic module, which further improves the photoelectric conversion efficiency of the solar cell by preparing a solar cell with a double-sided passivated contact structure and forming a PN junction on the back, and makes the manufacturing process of this solar cell suitable for industrial application, rather than just staying in the stage of laboratory research and unable to be industrialized.

[0093] In a first aspect, an embodiment of the present application provides a solar cell, as shown in FIG1 , which is a schematic structural diagram of a solar cell according to an embodiment of the present application. The solar cell comprises:

[0094] Substrate 1, substrate 1 has N-type conductivity;

[0095] A patterned first passivation contact structure 2 is provided on the light-receiving surface of the substrate 1. The first passivation contact structure 2 includes a first dielectric layer 21 close to the substrate 1 and a first doped polysilicon layer 22 away from the substrate 1. The first doped polysilicon layer 22 has an N-type conductivity. The thickness of the first dielectric layer 21 is less than or equal to 2 nm.

[0096] The entire second passivation contact structure 3 is provided on the backlight side of the substrate 1. The second passivation contact structure 3 includes a second dielectric layer 31 close to the substrate 1 and a second doped polysilicon layer 32 away from the substrate 1. The second doped polysilicon layer 32 has a P-type conductivity type different from the N-type conductivity type, so that the second doped polysilicon layer 32 forms a PN junction with the substrate 1. The thickness of the second dielectric layer 31 is greater than 2 nm. The second dielectric layer 31 has a through hole 311 connecting the substrate 1 and the second doped polysilicon layer 32. The doping concentration of the P-type conductive element in the second doped polysilicon layer is 5×10 18 atom / cm 3 ~3×10 20 atom / cm 3 ;

[0097] The first functional layer 4 is provided on the light-receiving surface of the substrate 1 and the side of the first doped polysilicon layer 22 away from the substrate 1;

[0098] The second functional layer 5 is provided on a side of the second doped polysilicon layer 32 away from the substrate 1;

[0099] The first electrode 6 penetrates the first functional layer 4 and makes ohmic contact with the first doped polysilicon layer 22; the patterned area of ​​the first passivation contact structure 2 is arranged corresponding to the patterned area of ​​the first electrode 6;

[0100] The second electrode 7 penetrates the second functional layer 5 and is in ohmic contact with the second doped polysilicon layer 32 .

[0101] The materials of the first and second dielectric layers may include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate, and is a film with excellent durability for subsequent high-temperature processes.

[0102] The thickness of the first dielectric layer 21 is less than or equal to 2 nm, preferably less than or equal to 1.5 nm. With such a thin thickness, electrons generated by light irradiating the light-receiving surface can act as carriers and tunnel through the first dielectric layer 21 via a tunneling mechanism, thereby achieving electron collection. It is understood that during the manufacturing process, the first dielectric layer 21 of this thickness may produce some cracked pinholes due to the annealing operation. These pinholes can also serve as channels for electron transmission, allowing electrons to be transmitted and conducted through both tunneling mechanisms and direct conduction mechanisms. Exemplarily, the thickness of the first dielectric layer 21 is 0.8 nm to 2.0 nm, including any value within this thickness range. For example, the thickness of the first dielectric layer 21 is 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.5 nm, 1.6 nm, 1.8 nm, or 2.0 nm. Furthermore, the first dielectric layer 21 can also serve as a diffusion barrier to prevent dopants in the first doped polysilicon layer (i.e., the N-type conductive element used to dope the first doped polysilicon layer) from diffusing into the semiconductor substrate.

[0103] Among them, the thickness of the second dielectric layer 31 is greater than 2nm. Under this thickness condition, it is difficult for electrons to pass through the film layer through the tunneling mechanism. As holes are larger in volume than electrons, it is even more difficult for them to pass through the film layer through the tunneling mechanism. Therefore, the present application realizes the transmission of holes on the backlight surface by opening a through hole 311 in the second dielectric layer 31 that runs through the film thickness direction and adopts a heavily doped P-type heavily doped polysilicon layer. Exemplarily, the thickness of the second dielectric layer can be 2.3nm, 2.5nm, 2.8nm, 3.0nm, 3.2nm, 3.5nm, 3.8nm or 4.0nm. In addition, the above-mentioned second dielectric layer 31 can also be used as a diffusion barrier to prevent the dopant of the second doped polysilicon layer (i.e., the P-type conductive element used to dope the second doped polysilicon layer) from diffusing into the semiconductor substrate.

[0104] The doping concentration of the P-type conductive element in the second doped polysilicon layer is 5×10 18 atom / cm 3 ~3×10 20 atom / cm 3 Within this doping concentration range, the second doped polysilicon layer has a high doping content of P-type conductive elements, which is a case of heavy doping. The present application has found that when a thicker second dielectric layer with a thickness greater than 2nm is provided on the back side, it works together with the P-type second doped polysilicon layer with the above doping concentration to have a good selectivity effect on holes, and effectively solves the problem that small-volume electrons always have a higher probability of passing through than large-volume holes. Exemplarily, the above doping concentration includes any point value within the above numerical range, for example, the doping concentration of the P-type conductive element in the second doped polysilicon layer is 5×10 18 atom / cm 3 , 6×10 18 atom / cm 3 , 8×10 18 atom / cm 3 , 1×10 19 atom / cm 3 , 5×10 19 atom / cm 3 , 8×10 19 atom / cm 3 , 1×10 20 atom / cm 3 or 3×10 20 atom / cm 3 .

[0105] The entire second passivation contact structure 3 means that, unlike the patterned first passivation contact structure 2 , the second passivation contact structure 3 covers the backlight surface of the N-type substrate 1 , thereby forming a relatively complete film structure rather than a partially passivated patterned structure.

[0106] Among them, the patterned area of ​​the first passivation contact structure is set corresponding to the patterned area of ​​the first electrode, which means that the patterned area of ​​the first passivation contact structure and the patterned area of ​​the first electrode are set correspondingly in position, and the line width dimensions are the same or similar. For example, the patterned line widths of the two can be set to be the same, or can be set to the line width of the first passivation contact structure slightly larger than the line width of the first electrode, thereby ensuring that the first electrode mainly made of metal material only contacts the first passivation contact structure, and does not contact the silicon wafer, while also ensuring the alignment effect of the first electrode and the first passivation contact structure.

[0107] The present invention provides a solar cell with multiple structural and functional features, featuring a double-sided passivated contact structure and a decoupling PN junction structure on the backlight side. The double-sided passivated contact structure has a localized passivated contact structure on the light-receiving side, while the backlight side has a full-surface passivated contact structure. Due to these multiple structural features, the solar cell of the present invention achieves both low front-side recombination loss and low current transmission loss, increasing the solar cell's photoelectric conversion efficiency to over 25.6%.

[0108] On the one hand, because the solar cell of the embodiment of the present application has a first passivation contact structure 2 and a second passivation contact structure 3 on the light-receiving side and the backlight side of the substrate 1, respectively, and the conductivity type of the second doped polysilicon layer 32 in the second passivation contact structure 3 on the backlight side is different from the conductivity type of the substrate 1, it not only has a passivation contact function, but also forms a PN junction relative to the substrate 1. This is equivalent to forming a passivation contact structure and a PN junction structure—a passivation contact PN junction structure—on the backlight side of the solar cell. In this way, because this passivation contact PN junction structure can decouple the contact layer system from the light absorber, and is no longer arranged near the surface of the substrate 1 as in the prior art, where the light-receiving side boron diffusion PN junction is formed, it can effectively solve the problem of high Auger recombination of the light-receiving side PN junction, thereby avoiding the contradiction between the boron diffusion resistance and Auger recombination loss of the light-receiving side PN junction. It should be noted that although in the related art, when a first dielectric layer and a first doped polysilicon layer are formed on the backlight side of substrate 1 (for example, a polysilicon layer doped with phosphorus is formed on the backlight side), the first dielectric layer and the first doped polysilicon layer can form a passivation contact structure, there are still strong electronic and chemical interactions between this structure and substrate 1, which can cause band bending and diffusion effects. Therefore, the doped polysilicon layer in this structure is not decoupled from substrate 1, but rather still has a strong connection.

[0109] In addition to the advantageous feature of decoupling, since the present application sets a passivated contact PN junction structure on the backlight surface, there is no shading problem, so the current transmission loss can be further reduced by increasing the number of metallized grid lines on the backlight surface. It can be seen that compared to setting a PN junction on the light-receiving surface, which requires considering many restrictions such as the number and area of ​​metallized grid lines, the embodiment of the present application sets a passivated contact PN junction structure on the backlight surface. In addition to having advantages in reducing Auger recombination losses, it also has the advantage of further reducing current transmission losses without affecting light absorption. That is: by setting a passivated contact PN junction structure on the backlight surface, the embodiment of the present application can simultaneously reduce Auger recombination losses and current transmission losses, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0110] On the other hand, while forming a passivation contact PN junction structure on the backlight side of the solar cell, the embodiment of the present application also forms a patterned first passivation contact structure 2 on the light-receiving side, which is provided only in the metallized area corresponding to the first electrode 6. That is, a first dielectric layer 21 and a first doped polysilicon layer 22 are provided below the first electrode 6. In the area where the first electrode 6 is not provided, there is no first dielectric layer 21 and first doped polysilicon layer 22, and only the first functional layer 4 (such as an anti-reflection layer and / or passivation layer) is retained. By forming a local passivation contact structure on the light-receiving side in this manner, the problem of high Auger recombination caused by the entire light-receiving side being doped with boron, especially heavily doped, is overcome, and the problem of metal recombination caused by metallization of the light-receiving side is reduced.

[0111] Furthermore, since the light-receiving surface adopts a local passivation contact structure, other areas of the light-receiving surface only need to be provided with conventional other functional layers (such as a passivation layer, an anti-reflection layer, etc.). Therefore, the first passivation contact structure 2 on the light-receiving surface can provide an effective passivation effect while reducing the parasitic absorption problem caused by the first doped polysilicon layer 22 in the first passivation contact structure 2, thereby improving the short-circuit current performance of the solar cell and further optimizing the photoelectric conversion efficiency of the solar cell. In this way, since a local passivation contact structure is formed on the light-receiving surface of the solar cell, the cell performance can be optimized from two aspects: overcoming recombination loss and reducing backlight surface resistance, thereby improving the photoelectric conversion efficiency of the solar cell. Since a full-surface passivation contact PN junction structure is formed on the backlight surface of the solar cell, it can not only reduce the recombination loss of the light-receiving surface, but also conduct electricity through the entire substrate 1, reducing the minority carrier transmission loss toward the local metal contact at the front end, improving the fill factor, and further promoting the improvement of the photoelectric conversion efficiency of the solar cell.

[0112] More importantly, based on the above-mentioned structural features, the embodiments of the present application control the different thicknesses of the film layers used for carrier transmission and passivation in the passivation contact structure on the light-receiving side and the backlight side, respectively, and combine the structural features of N-type doping on the front side and P-type doping and heavy doping on the back side to achieve effective transmission of carriers on the front and back sides. In this solar cell with a specific doping type, since the second doped polysilicon layer 32 on the backlight side is a P-type heavily doped polysilicon layer, when the solar cell is working, the second dielectric layer 31 located between the second doped polysilicon layer 32 and the N-type substrate 1 is mainly used to transmit holes. This application takes into account that the size of holes is larger than that of electrons, and it is difficult for them to pass through the film layer using the quantum tunneling effect at an extremely thin film thickness like electrons. Therefore, while thickening the second dielectric layer 31 on the backlight side and opening a through hole 311, the second doped polysilicon layer is also heavily doped. Thus, since the heavily P-type doped second doped polysilicon layer strongly repels electrons, holes can pass through smoothly and selectively repel electrons, thereby ensuring effective hole transmission through the through-holes 311. Furthermore, since the thickness of the second dielectric layer 31 without through-holes 311 is greater than 2 nm, it provides a good passivation effect and reduces the impact of the through-holes 311 on the passivation effect.

[0113] As for the first doped polysilicon layer 22 on the light-receiving surface, it is a first doped polysilicon layer. Therefore, when the solar cell is in operation, the first dielectric layer 21 located between the first doped polysilicon layer and the N-type substrate 1 is primarily used to transmit electrons. In this application, the thickness of the first dielectric layer 21 is set to be less than or equal to a relatively thin thickness of 2 nm, preferably less than or equal to 1.5 nm, to achieve electron tunneling by utilizing the quantum tunneling effect.

[0114] The film layer structure of the second passivation contact structure 3 is introduced below.

[0115] The second passivation contact structure 3 is disposed on the backlight side of the substrate 1. It is not a patterned passivation contact structure, but rather a full-surface passivation contact structure. The structure used to transmit carriers in the second passivation contact structure 3 is a second dielectric layer 31. This second dielectric layer 31 has a through hole 311 extending through it. This structural feature, combined with the heavily doped second doped polysilicon layer 32, enables the through hole 311 to selectively allow holes to pass through while blocking electrons.

[0116] In the second dielectric layer 31 of the second passivation contact structure 3, the diameter of the through hole 311 is 50 nm to 500 nm, and the number of the through holes 311 is 1×10 4 pieces / cm 2 ~1.6×10 8 pieces / cm 2The diameter of the through hole 311 is 50 nm to 500 nm, including any value within the numerical range. For example, the diameter of the through hole 311 is 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm. The number of through holes 311 is 1×10 4 pieces / cm 2 ~1.6×10 8 pieces / cm 2 Including any point value within this numerical range, for example, the number of through holes 311 is 1×10 4 pieces / cm 2 , 5×10 4 pieces / cm 2 , 1×10 5 pieces / cm 2 , 5×10 5 pieces / cm 2 , 1×10 6 pieces / cm 2 , 5×10 6 pieces / cm 2 , 1×10 7 pieces / cm 2 , 5×10 7 pieces / cm 2 or 1×10 8 pieces / cm 2 .

[0117] Controlling both the diameter and number of through-holes 311 within the aforementioned ranges helps ensure a better balance between hole transmission and passivation. If the diameter of through-holes 311 is too small or the number of through-holes 311 is too small, fewer holes can be directly transmitted through through-holes 311. If the diameter of through-holes 311 is too large or the number of through-holes 311 is too large, the passivation effect of the second dielectric layer 31 is likely to be compromised.

[0118] In addition, the thickness of the second doped polysilicon layer 32 is 200 nm to 400 nm. The P-type conductive element doped in the second doped polysilicon layer 32 includes at least one of boron, indium, or gallium, preferably boron. The thickness of the second doped polysilicon layer 32 is 200 nm to 400 nm, including any value within this numerical range. For example, the thickness of the second doped polysilicon layer 32 is 200 nm, 220 nm, 250 nm, 280 nm, 300 nm, 320 nm, 350 nm, or 400 nm.

[0119] The film layer structure of the first passivation contact structure 2 is introduced below.

[0120] The line width of the first passivation contact structure 2 is 20μm to 110μm. Since the first passivation contact structure 2 is located below the first electrode 6 and has a patterned structure with the same position as the first electrode 6, the first passivation structure contact has a line width that is compatible with the first electrode 6, specifically slightly wider than the line width of the first electrode 6. Within the above-mentioned line width range, the first passivation contact structure 2 can not only play a certain role in carrier transport and passivation, but also reduce the doping amount on the light-receiving surface of the substrate 1 by reducing the front doping to doping similar to the gate line pattern, thereby better overcoming the Auger recombination problem caused by doping diffusion. It can be understood that the line width of the first dielectric layer 21 and the line width of the first doped polysilicon layer 22 in the first passivation contact structure 2 are both within the above-mentioned line width range.

[0121] Furthermore, as shown in FIG2 , which is an enlarged schematic diagram of the structure at point A in FIG1 , the substrate 1 in the area covered by the patterned first passivation contact structure 2 is 0.5 μm to 1.5 μm thicker than the substrate in the area not covered by the first passivation contact structure. That is, in the area not covered by the patterned first passivation contact structure 2, the thickness of the substrate 1 is relatively thin. This structural arrangement ensures that when the patterned first passivation contact structure 2 is formed, the area of ​​the first passivation contact structure 2 that does not need to be retained can be fully etched away, leaving no residue on the substrate 1, thereby preventing light absorption on the substrate surface and affecting the photoelectric conversion efficiency.

[0122] In addition, the thickness of the first doped polysilicon layer 22 is 40nm to 200nm, and the N-type conductive element doped in the first doped polysilicon layer 22 includes at least one of phosphorus, germanium or selenium, preferably phosphorus. Exemplarily, the thickness of the first doped polysilicon layer 22 is 40nm, 50nm, 70nm, 100nm, 120nm, 150nm, 180nm or 200nm. In the double-sided passivation contact structure of the present application, the thickness of the second doped polysilicon layer on the backlight side is set to be thicker than the thickness of the first doped polysilicon layer on the light-receiving side to achieve the same or similar square resistance. Taking the example of doping phosphorus in the first doped polysilicon layer 22 on the light-receiving side and doping boron in the second doped polysilicon layer 32 on the backlight side, the solid solubility of phosphorus in the first doped polysilicon layer 22 is much higher than the solid solubility of boron in the second doped polysilicon layer 32. Therefore, the thickness of the second doped polysilicon layer is set thicker, which is conducive to doping more boron elements, so that the square resistance of the backlight side and the light-receiving side reaches the same or similar level.

[0123] The functional layers and electrodes are introduced below.

[0124] On the light-receiving side of the substrate 1, the first functional layer 4 includes a first passivation layer 41 disposed proximate to the substrate 1 and a first anti-reflection layer 42 disposed distally from the substrate 1. The thickness of the first passivation layer 41 is 3 nm to 5 nm, for example, 3 nm, 4 nm, or 5 nm. The thickness of the first anti-reflection layer 42 is 75 nm to 85 nm, for example, 75 nm, 78 nm, 80 nm, 82 nm, or 85 nm. The refractive index of the first anti-reflection layer 42 is 1.95 to 2.00. The first passivation layer 41 may be a composite of one or more sublayers. The first passivation layer 41 is preferably an aluminum oxide layer, but may also be a composite of multiple aluminum oxide sublayers. The first anti-reflection layer 42 may be a composite of one or more sublayers. For example, the first anti-reflection layer 42 may be a single silicon nitride layer, but may also be a composite of multiple silicon nitride layers. Preferably, the first anti-reflection layer 42 comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer disposed sequentially from the inside out (i.e., from the direction proximate to the substrate 1 toward the direction distal from the substrate 1).

[0125] On the backlight side of the substrate 1, the second functional layer 5 includes a second passivation layer 51 disposed adjacent to the second doped polysilicon layer 32 and a second anti-reflection layer 52 disposed distally from the second doped polysilicon layer 32. The second passivation layer 51 has a thickness of 3 nm to 5 nm, for example, 3 nm, 4 nm, or 5 nm. The second anti-reflection layer 52 has a thickness of 75 nm to 80 nm, for example, 75 nm, 76 nm, 77 nm, 78 nm, 79 nm, or 80 nm, and a refractive index of 2.10 to 2.15. The second passivation layer 51 can be a single layer or a composite of multiple sublayers. For example, the second passivation layer 51 can be an aluminum oxide layer or a composite of multiple aluminum oxide sublayers. Providing the second passivation layer 51 on the backlight side of the substrate 1 provides passivation protection for the PN junction located on the backlight side. The second anti-reflection layer 52 may be a single layer or a composite of multiple layers. For example, the second anti-reflection layer 52 may be a single silicon nitride layer or a composite of multiple silicon nitride layers.

[0126] Furthermore, because the PN junction of the embodiment of the present application is formed on the backlight side, the present application can provide more electrode grid lines on the backlight side, so that the ratio of the number of grid lines of the second electrode 7 to the number of grid lines of the first electrode 6 is 1.2 to 1.6:1. In this way, by increasing the number of grid lines on the backlight side, the current transmission capacity can be further improved without causing light blocking problems, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0127] In a second aspect, an embodiment of the present application further provides a method for preparing a solar cell as described in the first aspect, the method for preparing a solar cell comprising the following steps:

[0128] Forming a passivation contact structure: sequentially disposing a first dielectric layer and a first doped amorphous silicon layer on the light-receiving surface of the substrate to form a first passivation contact structure, and sequentially disposing a second dielectric layer and a second doped amorphous silicon layer on the backlight surface of the substrate to form a second passivation contact structure, wherein the thickness of the first dielectric layer is less than or equal to 2 nm, and the thickness of the second dielectric layer is greater than 2 nm;

[0129] Annealing and patterning: annealing the substrate on which the first passivation contact structure and / or the second passivation contact structure are formed, so as to transform the first doped amorphous silicon layer into a first doped polysilicon layer and / or transform the second doped amorphous silicon layer into a second doped polysilicon layer, and patterning the first passivation contact structure to obtain a patterned first passivation contact structure;

[0130] Post-processing: forming a first functional layer on the light-receiving surface of the substrate and the patterned first doped polysilicon layer, forming a second functional layer on the second doped polysilicon layer, making a first electrode on the first functional layer, and making a second electrode on the second functional layer.

[0131] It is understandable that the order of the annealing and patterning steps is not limited. Annealing can be performed first and then patterning, or patterning can be performed first and then annealing.

[0132] Compared to existing solar cells with a PN junction on the front and a fully passivated contact structure on the back, the solar cells prepared using the above method in the embodiments of the present application have higher photoelectric conversion efficiency, open-circuit voltage, and fill factor. Compared to existing IBC solar cells and HJT solar cells, they have similar photoelectric conversion efficiency while having a shorter manufacturing process than these two types of solar cells. This gives the solar cells in the embodiments of the present application the advantages of low manufacturing cost and high photoelectric conversion efficiency for industrial applications.

[0133] The preparation method first forms corresponding passivation contact structures on both the light-receiving side and the backlight side of the substrate, and the passivation contact structure on the backlight side has a conductivity type different from that of the substrate, thereby providing a film layer foundation for obtaining a solar cell having the multiple functional characteristics of a double-sided passivation contact structure, a local passivation contact on the front side, and a PN junction on the back side. Secondly, the first dielectric layer and the first doped amorphous silicon layer on the light-receiving side are annealed and patterned. On the one hand, the patterning process is used to make the first passivation contact structure only located below the first electrode, thereby reducing the recombination loss on the light-receiving side through this local structure. On the other hand, the annealing process is used to transform the doped amorphous silicon layer into a doped polycrystalline silicon layer, thereby truly forming a solar cell having the following structural advantages: a double-sided passivation contact structure with a local passivation contact on the front side and a full-surface passivation contact on the back side, and a PN junction structure on the back side.

[0134] In the preparation method of the embodiment of the present application, the first passivation contact structure on the light-receiving surface can be made first, and then the second passivation contact structure on the backlight surface can be made, or the second passivation contact structure on the backlight surface can be made first, and then the first passivation contact structure on the light-receiving surface can be made.

[0135] In a first optional embodiment, the second passivation contact structure on the backlight side is first formed, and then the first passivation contact structure on the light-receiving side is formed. The steps of forming the passivation contact structure include:

[0136] Alkali polishing: polishing the light-receiving surface and the backlight surface of the substrate using a first alkaline agent;

[0137] Depositing a second passivation contact structure: depositing a second dielectric layer and a second doped amorphous silicon layer in sequence on the backlight side of the substrate;

[0138] Texturing: First, use a first acid agent to remove the second doped amorphous silicon layer and the second dielectric layer that are plated around the light-receiving surface and the edge, and then use a second alkaline agent to texturing the light-receiving surface of the substrate;

[0139] Depositing the first passivation contact structure: depositing a first dielectric layer and a first doped amorphous silicon layer in sequence on the light-receiving surface after texturing.

[0140] This embodiment adopts the method of first depositing the second passivation contact structure on the backlight side and then depositing the first passivation contact structure on the light-receiving side. Unlike the method of first texturing the substrate and then performing boron diffusion on the light-receiving side of the substrate to form a PN junction, this embodiment first polishes the substrate on both sides with a first alkaline agent, then sequentially deposits the second dielectric layer and the second doped amorphous silicon layer on the backlight side of the polished substrate, then texturing the light-receiving side of the substrate, and then sequentially depositing the first dielectric layer and the first doped amorphous silicon layer on the texturized light-receiving side. This results in both a textured structure and the formation of the film layer foundation for the double-sided passivation contact structure.

[0141] In the alkaline polishing step, the first alkaline agent includes an alkali metal hydroxide and an alkaline polishing additive in a volume ratio of 2:1 to 4:1, the alkaline polishing temperature is 70°C to 90°C, and the alkaline polishing time is 5 minutes to 8 minutes. In the texturing step, the first acid agent is a hydrofluoric acid solution and a nitric acid solution in a volume ratio of 1:2 to 5, and the second alkaline agent includes an alkali metal hydroxide and a texturing additive in a volume ratio of 6:1 to 8:1, the texturing temperature is 70°C to 90°C, and the texturing time is 5 minutes to 8 minutes. By using the above reagents to treat the substrate and the coating layer on the light-receiving surface accordingly, the effects of polishing, texturing, and de-coating can be better achieved.

[0142] Among them, the process of depositing the first dielectric layer, the first doped amorphous silicon layer, the second dielectric layer, and the second doped amorphous silicon layer can be PECVD (Plasma Enhanced Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) and other processes.

[0143] The following describes the steps of forming a passivation contact structure, annealing, and patterning when using the PECVD process.

[0144] The step of depositing the second passivation contact structure comprises: depositing a second dielectric layer, a back intrinsic layer, a back doped layer doped with a P-type conductive element, and a back mask layer in sequence on the backlit surface after alkali polishing by a PECVD process;

[0145] The texturing step includes: firstly using a first acid agent to remove the back mask layer, the back doping layer, the back intrinsic layer and the second dielectric layer that are plated around the light-receiving surface and the edge, and then using a second alkaline agent to texturize the light-receiving surface;

[0146] The step of depositing the first passivation contact structure includes: depositing a first dielectric layer, a front intrinsic layer, and a front doped layer doped with an N-type conductive element in sequence on the light-receiving surface after texturing by a PECVD process.

[0147] The above three steps are to deposit the relevant film layers on the backlight side in sequence through the PECVD process after double-sided polishing of the substrate, then texturing and de-coating the light-receiving side, and then deposit the relevant film layers on the light-receiving side in sequence. Since only the first dielectric layer and the N-type second doped amorphous silicon layer need to be deposited when depositing the first doped amorphous silicon layer on the light-receiving side, and there is no need to deposit an additional back mask layer as on the backlight side, the same effect can be achieved, meeting the requirements for subsequent local etching on the light-receiving side. Therefore, reducing the deposition of one mask layer on the light-receiving side is beneficial to reducing the cost of producing the first doped amorphous silicon layer on the light-receiving side.

[0148] The purpose of depositing a back mask layer on the backlight side is to prevent unnecessary damage to the intrinsic layer, doping layer, and other film layers caused by etching and other patterning operations during the subsequent step of patterning the first passivation contact structure on the light-receiving side. In this way, during texturing, the first acid can be used to remove the back mask layer that is plated around the light-receiving side first, and then the other back film layers that are plated around the light-receiving side and the edges can be removed during the texturing process.

[0149] Furthermore, the front doping layer can be one or more layers, for example, the front doping layer includes a first front doping sublayer and a second front doping sublayer, and each layer is doped with an N-type conductive element, and the N-type conductive element is preferably a phosphorus element. Compared with setting only one front doping layer, the method of setting the front doping sublayer in two or more layers can reduce the doping concentration of the N-type conductive element in each layer while ensuring that the total doping concentration reaches a certain level, thereby reducing the probability of lattice distortion caused by the high doping concentration. Similarly, the back doping layer can be one or more layers, for example, the back doping layer includes a first back doping sublayer and a second back doping sublayer, and each layer is doped with a P-type conductive element, and the P-type conductive element is preferably a boron element. When the back doping layer is arranged in layers, it also has similar effects to the layered arrangement of the front doping layer.

[0150] Furthermore, the steps of annealing and patterning include:

[0151] Printing: Printing a patterned alkali-resistant paste on a preset area of ​​the front doping layer, and drying to solidify the alkali-resistant paste;

[0152] Cleaning: first, using a third alkaline agent to etch away the first doped amorphous silicon layer, the first dielectric layer, and a portion of the substrate that are not covered in a preset area on the light-receiving side, and then using a second acid agent to etch away the alkali-resistant slurry and the back mask layer on the backlight side, so that a patterned first dielectric layer and a patterned first doped amorphous silicon layer are formed on the light-receiving side of the substrate, and the substrate in the preset area is 0.5 μm to 1.5 μm thicker than the substrate in the preset area that is not covered, and a second dielectric layer and a second doped amorphous silicon layer are formed on the entire backlight side of the substrate;

[0153] Annealing: In an inert atmosphere, annealing is performed at 850°C to 1000°C for 90 minutes to 150 minutes to transform the first doped amorphous silicon layer into a first doped polysilicon layer, and the second doped amorphous silicon layer into a second doped polysilicon layer, and a PN junction is formed between the substrate and the second doped polysilicon layer.

[0154] Among them, the alkali-resistant slurry can be the alkali-resistant slurry commonly used in this field, or the alkali-resistant slurry composed of the following formula: in parts by weight, the alkali-resistant slurry includes: 80 to 95 parts of propylene modified epoxy resin, 8 to 15 parts of filler, 2 to 5 parts of leveling agent, and 2 to 5 parts of defoaming agent.

[0155] In this embodiment, a patterned alkali-resistant paste is first printed and cured in a predetermined region on the first doped amorphous silicon layer on the light-receiving side. The alkali-resistant paste protects the first doped amorphous silicon layer and the first dielectric layer in the predetermined region by resisting alkali corrosion. Thus, since no front mask layer is provided on the first doped amorphous silicon layer, and only the patterned region of the alkali-resistant paste serves as a protective layer, there is no need to treat the front mask layer with a reagent. Instead, a third alkali agent can be used to directly etch away the first doped amorphous silicon layer and the first dielectric layer outside of the predetermined region, leaving only the first doped amorphous silicon layer and the first dielectric layer in the predetermined region. Furthermore, the use of a second acidic agent serves a dual purpose: first, it removes the alkali-resistant paste, and second, it simultaneously removes the back mask layer on the backlight side. This results in the formation of the first dielectric layer and the first doped amorphous silicon layer on the light-receiving side, which are localized and correspond only to the regions below the first electrode, while the formation of the second dielectric layer and the second doped polycrystalline silicon layer on the backlight side is complete.

[0156] Furthermore, because the third alkaline etching agent is used to remove a portion of the substrate, leaving this portion 0.5 μm to 1.5 μm lower than the substrate within the predetermined region, the unnecessary first doped amorphous silicon layer and first dielectric layer are fully etched away, thereby ensuring that the first passivation contact structure does not retain any light-absorbing residue on the substrate surface. Furthermore, this etching operation also serves as a secondary texturing process, making the textured structure formed on the surface of the etched portion of the substrate more regular in shape and with lower reflectivity. This ensures that only the first doped amorphous silicon layer and first dielectric layer within the predetermined region are protected, ultimately forming an effective patterned first passivation contact structure.

[0157] It can be seen from this that the double-sided passivation contact structure method of first forming the second passivation contact structure by alkali polishing and PECVD process, and then forming the first passivation contact structure by texturing and PECVD process, can not only achieve the dual effects of texturing and removing the front side plating at the same time by using one texturing step, saving process steps, but also, on this basis, no front mask layer is formed when depositing the first passivation contact structure, so that the regional treatment of the front first passivation contact structure can be achieved through subsequent printing of alkali-resistant slurry, etching and cleaning, etc., which can save the step of making the front mask layer, and can also use the second acid etching in the cleaning step to achieve the dual effects of removing the alkali-resistant slurry and the back mask layer in one treatment process. Therefore, the above-mentioned method of the present application can optimize and save multiple process steps, simplify the process flow, and reduce production costs through the close cooperation between different steps.

[0158] The predetermined region refers to the region where the first electrode is subsequently printed, i.e., the metallized region. This region is the region with poor light transmittance in the solar cell. Depositing the first dielectric layer and the first doped polysilicon layer only in this predetermined region can improve the absorption of sunlight from the front side and also help reduce recombination losses. Printing can be performed, for example, by screen printing or laser printing. The annealing temperature is 850°C to 1000°C, including any value within this temperature range, such as 850°C, 870°C, 900°C, 920°C, 940°C, 950°C, 980°C, or 1000°C; the annealing time is 90min to 150min, including any value within this time range, such as 90min, 100min, 110min, 120min, 130min, 140min, or 150min.

[0159] During the printing step, the width of the patterned alkali-resistant paste is 20 μm to 110 μm, and the drying temperature after printing is 150°C to 250°C for 8 to 12 seconds. During the cleaning step, the third alkaline agent comprises an alkali metal hydroxide and a texturing additive in a volume ratio of 1:1 to 3:1. The etching temperature using the third alkaline agent is 70°C to 90°C for 1 to 3 minutes. During the cleaning step, the second acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0160] Preferably, in the cleaning step, a third alkaline agent is first used in a tank texturing machine to etch away the first dielectric layer and the first doped amorphous silicon layer that are not covered in a predetermined area on the light-receiving surface. Then, a second acid is used in an acid tank to etch away the alkali-resistant slurry and the back mask layer on the backlight side, so that the light-receiving surface of the substrate is sequentially the first dielectric layer and the first doped amorphous silicon layer located in the predetermined area, and the backlight side of the substrate is sequentially the second dielectric layer and the second doped amorphous silicon layer on the entire surface. Since only a tank texturing machine is required in this step, and a chain machine is not required, one step is eliminated, which helps reduce equipment and material costs.

[0161] The following introduces the steps of forming a passivation contact structure, annealing treatment and patterning treatment when using the LPCVD process.

[0162] The steps of depositing the second passivation contact structure include: forming a second dielectric layer on the backlight surface after alkaline polishing by a thermal oxidation process, forming a back intrinsic amorphous silicon layer by an LPCVD process, and then doping a P-type conductive element into the back intrinsic amorphous silicon layer by a diffusion process to transform the back intrinsic amorphous silicon layer into a second doped polysilicon layer, and forming a PN junction between the second doped polysilicon layer and the substrate;

[0163] The texturing step includes: firstly using a first acid agent to remove the second doped polysilicon layer and the second dielectric layer that are plated around the light-receiving surface and the edge, and then using a second alkaline agent to texturize the light-receiving surface;

[0164] The step of depositing the first passivation contact structure includes: depositing a first dielectric layer, a front intrinsic layer, a front doped layer doped with N-type conductive elements, and a front mask layer in sequence on the textured light-receiving surface through a PECVD process.

[0165] It can be understood that the LPCVD process forms an intrinsic amorphous silicon layer on the back side, followed by a diffusion process. In addition to transforming the back side intrinsic amorphous silicon layer into a second doped polysilicon layer, a silicon glass layer containing a P-type conductive element is also formed on the surface of the second doped polysilicon layer. For example, if the P-type conductive element is boron, after the boron diffusion process, a boron-doped second doped polysilicon layer and a borosilicate glass layer on its surface are formed on the back side. This borosilicate glass layer acts as a back side mask layer, protecting the second doped polysilicon layer.

[0166] Furthermore, the steps of annealing and patterning include:

[0167] Annealing: in an inert atmosphere, annealing at 850° C. to 950° C. for 90 min to 150 min to transform the first doped amorphous silicon layer into a first doped polycrystalline silicon layer;

[0168] Printing: Printing a patterned acid-resistant paste on a preset area of ​​the front doping layer, and drying to solidify the acid-resistant paste;

[0169] Cleaning: first use a third acid to etch and remove the front mask layer that is not covered in the preset area on the light-receiving side, then use a fourth alkaline agent to etch and remove the first doped polysilicon layer and the first dielectric layer that are not covered in the preset area on the light-receiving side, remove the acid-resistant slurry, and use a fourth acid to remove the remaining front mask layer, so that a patterned first dielectric layer and a patterned first doped amorphous silicon layer are formed on the light-receiving side of the substrate, and a front second dielectric layer and a second doped polysilicon layer are formed on the backlight side of the substrate.

[0170] Among them, the acid-resistant slurry can be the acid-resistant slurry commonly used in this field, or the acid-resistant slurry composed of the following formula: in parts by weight, the acid-resistant slurry includes: 80 to 95 parts of polyester resin, 8 to 15 parts of filler, 2 to 5 parts of leveling agent, and 2 to 5 parts of defoaming agent.

[0171] Among them, in the printing step, the width of the printed graphic acid-resistant paste is 20μm to 110μm, the drying temperature after printing is 150℃ to 250℃, and the drying time is 8s to 12s. In the cleaning step, the third acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%. The fourth alkaline agent includes an alkali metal hydroxide and a texturing additive in a volume ratio of 1:1 to 3:1. The etching temperature using the fourth alkaline agent is 70℃ to 90℃, and the etching time is 1min to 3min. In the cleaning step, the fourth acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0172] It is understandable that in the above cleaning step, in addition to removing the remaining front mask layer, the fourth acid can also simultaneously remove the back mask layer when there is silicon glass as a back mask layer on the second doped polysilicon layer.

[0173] In a second optional embodiment, the first passivation contact structure on the light-receiving side is first formed, and then the second passivation contact structure on the backlight side is formed. The steps of forming the passivation contact structure include:

[0174] Texturing: Use the fifth alkaline agent to texturize the substrate;

[0175] Depositing a first passivation contact structure: depositing a first dielectric layer and a first doped amorphous silicon layer in sequence on the light-receiving surface after texturing;

[0176] Alkali polishing: using a fifth acid agent to remove the portion of the first doped amorphous silicon layer that is plated around the backlight surface, and then using a sixth alkaline agent to polish the backlight surface of the substrate, and remove the remaining portion of the first doped amorphous silicon layer and the first dielectric layer that are plated around the back and edge;

[0177] Depositing a second passivation contact structure: depositing a second dielectric layer and a second doped amorphous silicon layer in sequence on the backlight surface.

[0178] In this embodiment, the light-receiving surface of the substrate is first textured to form a textured structure, and then a first dielectric layer and a first doped amorphous silicon layer are sequentially deposited on the light-receiving surface of the substrate with the textured structure. Then, the backlight surface of the substrate is alkali-polished to achieve the dual effects of polishing the backlight surface and removing the material plated around the backlight surface. Finally, a second dielectric layer and a first doped amorphous silicon layer are sequentially formed on the polished backlight surface.

[0179] Among them, in the texturing step, the fifth alkaline agent includes an alkali metal hydroxide and a texturing additive in a volume ratio of 6:1 to 8:1, the texturing temperature is 70°C to 90°C, and the texturing time is 5 minutes to 8 minutes. In the alkali polishing step, the fifth acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%, the sixth alkaline agent includes an alkali metal hydroxide and an alkali polishing additive in a volume ratio of 2:1 to 4:1, the alkali polishing temperature is 70°C to 90°C, and the alkali polishing time is 5 minutes to 8 minutes. By treating the substrate and its winding coating layer with the above reagents, the effects of texturing, polishing, and de-winding can be better achieved.

[0180] Among them, the process of depositing the first dielectric layer, the first doped amorphous silicon layer, the second dielectric layer, and the second doped amorphous silicon layer can be PECVD (Plasma Enhanced Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) and other processes.

[0181] The following describes the steps of forming a passivation contact structure, annealing, and patterning when using the PECVD process.

[0182] The step of depositing the first passivation contact structure includes: depositing the first passivation contact structure includes: depositing a first dielectric layer, a front intrinsic layer, a front doped layer doped with an N-type conductive element, and a front mask layer in sequence on the light-receiving surface after texturing by a PECVD process;

[0183] The alkaline polishing step includes: first using a fifth acid agent to remove the front mask layer that is plated around the backlight surface, and then using a sixth alkaline agent to polish the backlight surface of the substrate, and remove the front doped layer, the front intrinsic layer and the first dielectric layer that are plated around the back and the edge;

[0184] The step of depositing the second passivation contact structure includes: depositing a second dielectric layer, a back intrinsic layer, a back doped layer doped with P-type conductive elements, and a back mask layer in sequence on the backlight surface after alkali polishing by PECVD process.

[0185] Furthermore, the steps of annealing and patterning include:

[0186] Annealing: annealing the substrate forming the first passivation contact structure and the second passivation contact structure in an inert atmosphere at 850° C. to 1000° C. for 90 min to 150 min;

[0187] Printing: Printing a patterned acid-resistant paste in a predetermined area on the surface of the first doped amorphous silicon layer, and drying the acid-resistant paste to solidify it;

[0188] Cleaning: First use the sixth acid to etch and remove the front mask layer of the light-receiving surface, then use the seventh alkaline agent to etch and remove the acid-resistant slurry, and remove the first dielectric layer and the first doped amorphous silicon layer that are not covered in the preset area of ​​the light-receiving surface, and then use the seventh acid to remove the front mask layer and the back mask layer.

[0189] Among them, the annealing temperature is 850°C to 1000°C, including any value within the temperature range, for example, the annealing temperature is 850°C, 870°C, 900°C, 920°C, 940°C, 950°C, 980°C or 1000°C; the annealing time is 90min to 150min, including any value within the time range, for example, the annealing time is 90min, 100min, 110min, 120min, 130min, 140min or 150min.

[0190] In the printing step, the width of the printed graphic acid-resistant paste is 20μm to 110μm, the drying temperature after printing is 150℃ to 250℃, and the drying time is 8s to 12s. In the cleaning step, the sixth acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%. The seventh alkaline agent includes an alkali metal hydroxide and a texturing additive in a volume ratio of 1:1 to 3:1. The etching temperature using the seventh alkaline agent is 70℃ to 90℃, and the etching time is 1min to 3min. The seventh acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

[0191] The post-processing steps are introduced below.

[0192] The post-processing steps include:

[0193] ALD process is used to deposit a first passivation layer and a second passivation layer on the light-receiving surface and the backlight surface respectively;

[0194] Depositing a first anti-reflection layer on the first passivation layer and a second anti-reflection layer on the second passivation layer by using a PECVD process;

[0195] Printing a first electrode on the front surface to make ohmic contact between the first electrode and the first doped polysilicon layer located in a predetermined area;

[0196] A second electrode is printed on the back surface to make ohmic contact between the second electrode and the second doped polysilicon layer.

[0197] The first electrode is printed on the front side, for example, by printing silver paste on the front side by screen printing, so as to form an ohmic contact with the first doped polysilicon layer on the front side. Similarly, the second electrode is printed on the back side, for example, by printing silver paste on the back side by screen printing, so as to form an ohmic contact with the second doped polysilicon layer on the back side.

[0198] In the ALD process, the deposition temperature is 200° C. to 280° C., and the thicknesses of the deposited first passivation layer and the second passivation layer are 3 nm to 5 nm, respectively.

[0199] In a third aspect, embodiments of the present application provide a photovoltaic module comprising the solar cell described in the first aspect, or a solar cell produced using the method described in the second aspect. The photovoltaic module is formed by connecting a plurality of the aforementioned solar cells in series and / or in parallel and encapsulating them.

[0200] The solar cell prepared in this application and its performance will be further described below in conjunction with the examples, drawings and test data.

[0201] Example 1

[0202] This embodiment provides a solar cell, as shown in FIG3 , which is a process flow chart of a method for preparing the solar cell of this embodiment. The solar cell is prepared by the following preparation method:

[0203] Provide an N-type substrate: An N-type 182-size M10 silicon wafer is used as the N-type substrate, with a resistivity of 1.0Ω·cm to 3.5Ω·cm and a minority carrier lifetime of >1ms; the N-type substrate has a light-receiving surface and a backlight surface disposed opposite to each other, with the light-receiving surface being the light incident surface;

[0204] Alkali polishing: Double-sided polishing of N-type substrates was performed in a tank-type equipment using sodium hydroxide and alkaline polishing additive BP31 in a volume ratio of 3:1 at a temperature of 80°C for 7 minutes.

[0205] The second passivation contact structure is deposited using a PECVD process: a composite film is deposited on the backlit side of the N-type substrate using a tubular PECVD device. The film is deposited to form the second dielectric layer and the second doped amorphous silicon layer at a pressure of 2500mTorr to 3500mTorr and a temperature of 330°C to 450°C.

[0206] Film layer 1: Using PECVD method, 8SLM~15SLM of N2O is introduced, and the deposition time is 350-600s to obtain the second dielectric layer SiO x ;

[0207] Film layer 2: Using PECVD, SiH4 and H2 with a volume ratio of 1:2.5 are introduced for a deposition time of 40s to 90s to deposit the back intrinsic layer as an amorphous thin film layer with a thickness of 5nm to 40nm;

[0208] Layer 3: Using PECVD, SiH4, TMB (trimethylboron), and H2 in a volume ratio of 1:0.3:2.5, the deposition time is 80s to 300s, and a first back-doped layer doped with boron is deposited as an amorphous silicon film with a thickness of 10nm to 80nm.

[0209] Layer 4: PECVD is used to deposit a second back-doped layer of boron-doped amorphous silicon thin film with a thickness of 60 nm to 180 nm, using SiH4, TMB, and H2 in a volume ratio of 1:0.6:2.5 for 500 to 700 seconds.

[0210] Layer 5: Using PECVD, SiH4, NH3, and N2O in a volume ratio of 1:4:7 are introduced for a deposition time of 60s to 200s to deposit a silicon oxynitride film as a back mask layer with a thickness of 5nm to 40nm.

[0211] Texturing: A chain machine is used to remove the back-light mask layer, the second back-side doping layer, the first back-side doping layer, the back-side intrinsic layer, and the second dielectric layer that are plated around the light-receiving surface and the edge using a hydrofluoric acid solution and a nitric acid solution in a volume ratio of 1:2-5. The substrate is then transferred to a tank-type alkaline polishing machine and texturing is performed on the light-receiving surface of the N-type substrate using sodium hydroxide and a texturing additive TS40 in a volume ratio of 7:1 at 80°C for 7 minutes.

[0212] The first passivation contact structure is deposited using a PECVD process: a tubular PECVD device is used to sequentially deposit composite films on the light-receiving surface after texturing. Under conditions of a pressure of 2500mTorr to 3500mTorr and a temperature of 350°C to 450°C, thin films are deposited to form the first dielectric layer and the first doped amorphous silicon layer.

[0213] Film layer 1: Using PECVD, 8SLM to 15SLM of N2O was introduced, and the deposition time was 140s to deposit the first dielectric layer SiO with a thickness of 1.5nm. x ;

[0214] Layer 2: PECVD is used to deposit SiH4 and H2 at a volume ratio of 1:2.5 for 40s to 90s to deposit a front intrinsic layer as an amorphous thin film layer with a thickness of 5nm to 40nm.

[0215] Layer 3: Using PECVD, SiH4, PH3, and H2 in a volume ratio of 1:0.4:2.5, the deposition time is 40s to 90s, and a first front-side doped layer doped with phosphorus is deposited as an amorphous silicon film with a thickness of 5nm to 40nm.

[0216] Layer 4: Using PECVD, SiH4, PH3, and H2 in a volume ratio of 1:0.8:2.5, the deposition time is 250s to 350s, and a second front-side doped layer doped with phosphorus is deposited as an amorphous silicon film with a thickness of 20nm to 80nm.

[0217] Printing: Screen-printing a patterned alkali-resistant paste in a preset area on the surface of the front doped layer. The pattern matches, is similar to, or is identical to the pattern of the screen-printed first electrode, and the line width of the printed alkali-resistant paste is 20 μm to 110 μm, slightly wider than the width of the screen-printed first electrode pattern. After printing, the paste is dried at 150° C. to 250° C. for 10 seconds. The alkali-resistant paste can protect the first dielectric layer and the first doped amorphous silicon layer (i.e., the front intrinsic layer, the first front doped layer, the second front doped layer, and other amorphous silicon thin film layers) located thereunder. The preset area corresponds to the area where the metal electrode is provided in the solar cell.

[0218] Cleaning: First, enter the tank-type texturing machine, use sodium hydroxide and texturing additive TS40 with a volume ratio of 2:1 at a temperature of 80°C, etch for 2 minutes, and etch away the first dielectric layer, the first doped amorphous silicon layer and part of the N-type substrate that are not covered in the preset area of ​​the light-receiving surface; then enter the acid tank, use a hydrofluoric acid solution with a volume percentage of 5% to etch away the alkali-resistant slurry, and remove the back mask layer on the backlight side, retaining the second doped amorphous silicon layer on the backlight side, so that the substrate in the preset area is about 1μm thicker than the substrate not covered in the preset area; after cleaning, the light-receiving surface of the N-type substrate is the first dielectric layer and the first doped amorphous silicon layer in the preset area, and the backlight side of the N-type substrate is the second dielectric layer and the second doped amorphous silicon layer on the entire surface;

[0219] Annealing: Annealing is performed in a tubular annealing furnace in a nitrogen atmosphere of 10 SLM at an annealing temperature of 850°C for 120 minutes, so that the first doped amorphous silicon layer is transformed into a first doped polysilicon layer, and the second doped amorphous silicon layer is transformed into a second doped polysilicon layer. The first dielectric layer and the first doped polysilicon layer form a first passivation contact structure, and the second dielectric layer and the second doped polysilicon layer form a second passivation contact structure. Since the second doped polysilicon layer is doped with a P-type conductive element, a PN junction is formed between the N-type substrate and the P-type second doped polysilicon layer.

[0220] Post-processing:

[0221] Aluminum oxide layers are deposited on the light-receiving surface and the backlight surface as the first passivation layer and the second passivation layer respectively using the ALD process. The deposition temperature is 200°C to 280°C and the thickness is 3nm to 5nm.

[0222] A silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer are sequentially deposited on the first passivation layer using a PECVD process as a first anti-reflection layer, wherein the total thickness of the first anti-reflection layer is 75 nm to 85 nm and the refractive index is 1.95 to 2.00; a silicon nitride layer is deposited on the second passivation layer using a PECVD process as a second anti-reflection layer, wherein the thickness is 75 nm to 80 nm and the refractive index is 2.10 to 2.15;

[0223] Screen printing: Silver paste is sequentially printed on the back side as the second electrode and on the front side as the first electrode. The electrodes are then sintered at 840°C to complete the process. The first electrode penetrates the first anti-reflection layer and the first passivation layer, establishing ohmic contact with the first doped polysilicon layer in a predetermined area. The second electrode penetrates the second anti-reflection layer and the second passivation layer, establishing ohmic contact with the second doped polysilicon layer in a predetermined area. Light is injected into the cell at a process temperature of 700°C. The number of gate lines on the second electrode is 1.6 times that of the first electrode.

[0224] In the solar cell of this embodiment, the film parameters of the passivation contact structure (including film thickness, doping concentration, through-hole parameters, etc.) are specifically shown in Table 1 below.

[0225] Example 2

[0226] This embodiment provides a solar cell, as shown in FIG4 , which is a process flow chart of a method for preparing the solar cell of this embodiment. The solar cell is prepared by the following preparation method:

[0227] Provide an N-type substrate: An N-type 182-inch M10 silicon wafer is used as the N-type substrate, with a resistivity of 1.0Ω·cm to 3.5Ω·cm and a minority carrier lifetime >1ms. The N-type substrate has a light-receiving surface and a back-to-back surface disposed opposite to each other, with the light-receiving surface being the light incident surface.

[0228] Alkali polishing: Double-sided polishing of N-type substrates was performed in a tank-type equipment using sodium hydroxide and alkaline polishing additive BP31 in a volume ratio of 3:1 at a temperature of 80°C for 7 minutes.

[0229] The second passivation contact structure is deposited using the LPCVD process: a tubular LPCVD device is used to deposit a composite film on the backlit side of the N-type substrate, achieving thin film deposition under near-vacuum conditions:

[0230] Film layer 1: Using a high-temperature thermal oxidation process, O2 is introduced at 590°C to 630°C, and the deposition time is 2500s to 4000s to obtain the second dielectric layer;

[0231] Layer 2: Using the LPCVD process, cool to 540°C to 580°C and introduce SiH4 to deposit an intrinsic amorphous silicon layer on the back side. The deposition time is 4500s to 6000s, and the thickness is 250nm to 350nm.

[0232] Film layer three: Boron diffusion is performed in a tubular diffusion furnace with a gas atmosphere of nitrogen, oxygen, and vaporized boron trichloride. The nitrogen concentration is 2-10 SLM, the oxygen concentration is 100-1000 sccm, and the boron trichloride concentration is 50 sccm-200 sccm. The temperature is 850-950°C and the deposition time is 90-150 minutes. The back intrinsic amorphous silicon layer deposited in the previous step is doped with boron to form a boron-doped polysilicon layer, i.e., a P-type second doped polysilicon layer. A PN junction is formed between the N-type substrate and the second doped polysilicon layer.

[0233] Texturing: Use hydrofluoric acid solution and nitric acid solution with a volume ratio of 1:2-5 to remove the second doped polysilicon layer and the second dielectric layer that are plated around the light-receiving surface and edge. Then transfer to a tank-type alkaline polishing machine and use sodium hydroxide and texturing additive TS40 with a volume ratio of 7:1 at a temperature of 80°C for 7 minutes to texturing the front side of the N-type substrate.

[0234] The first passivation contact structure is deposited using a PECVD process: a tubular PECVD device is used to sequentially deposit composite films on the light-receiving surface after texturing. Under conditions of a pressure of 2500mTorr to 3500mTorr and a temperature of 350°C to 450°C, four thin films are deposited to form the first dielectric layer and the first doped amorphous silicon layer:

[0235] Film layer 1: Using PECVD, 8SLM to 15SLM of N2O was introduced, and the deposition time was 140s to deposit the first dielectric layer SiO with a thickness of 1.5nm. x ;

[0236] Layer 2: PECVD is used to deposit the first front intrinsic layer as an amorphous thin film layer with a thickness of 5nm to 40nm by introducing SiH4 and H2 in a volume ratio of 1:2.5 for a deposition time of 40s to 90s.

[0237] Layer 3: Using PECVD, SiH4, PH3, and H2 in a volume ratio of 1:0.4:2.5, the deposition time is 40s to 90s, and a first front-side doped layer doped with phosphorus is deposited as an amorphous silicon film with a thickness of 5nm to 40nm.

[0238] Layer 4: Using PECVD, SiH4, PH3, and H2 in a volume ratio of 1:0.8:2.5, the deposition time is 250s to 350s, and a second front-side doped layer doped with phosphorus is deposited as an amorphous silicon film with a thickness of 20nm to 80nm.

[0239] Layer 5: Using PECVD, SiH4 and N2O with a volume ratio of 1:8 are introduced for a deposition time of 20s to 100s to deposit a silicon oxynitride film as a front mask layer with a thickness of 5nm to 20nm.

[0240] Annealing: The silicon wafer is annealed in a tubular annealing furnace in a nitrogen atmosphere of 2-10 SLM at a temperature of 850°C-950°C for 120 minutes, so that the crystal structure of the deposited amorphous silicon film is transformed to form a phosphorus-doped polysilicon layer.

[0241] Printing: Screen-printing a patterned acid-resistant paste in a preset area on the surface of the front mask layer. The pattern is similar to or identical to the pattern of the screen-printed first electrode, and the line width of the printed acid-resistant paste is 20μm to 110μm, which is slightly wider than the width of the screen-printed first electrode pattern; after printing, drying is carried out at 150°C to 250°C for 10 seconds; wherein the acid-resistant paste can protect the first dielectric layer and the first doped amorphous silicon layer (i.e., the amorphous silicon thin film layers such as the front intrinsic layer, the first front doped layer, and the second front doped layer) located thereunder; wherein the preset area corresponds to the area where the first electrode is provided in the solar cell;

[0242] Cleaning: First, pass through a chain device and use hydrofluoric acid with a volume concentration of 5% to single-sidedly remove the front mask layer that is not covered in the preset area of ​​the light-receiving surface. Then, transfer it to a tank-type texturing machine through a robot arm and use sodium hydroxide and texturing additive TS40 with a volume ratio of 2:1 at a temperature of 80°C for 2 minutes to etch and remove the first dielectric layer, the first doped amorphous silicon layer, and the acid-resistant slurry that are not covered in the preset area of ​​the light-receiving surface. Then, enter the acid tank and use a hydrofluoric acid solution with a volume percentage of 5% to etch and remove the remaining front mask layer and the borosilicate glass formed on the second doped polysilicon layer on the back side due to boron diffusion, retaining the P-type doped amorphous silicon layer on the back side, so that the front side of the N-type substrate is sequentially the first dielectric layer and the N-type doped amorphous silicon layer located in the preset area, and the back side of the N-type substrate is sequentially the second dielectric layer and the P-type doped amorphous silicon layer on the entire surface.

[0243] Post-processing:

[0244] Aluminum oxide layers are deposited on the light-receiving surface and the backlight surface as the first passivation layer and the second passivation layer respectively using the ALD process. The deposition temperature is 200°C to 280°C and the thickness is 3nm to 5nm.

[0245] A silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer are sequentially deposited on the first passivation layer using a PECVD process as a first anti-reflection layer, wherein the total thickness of the first anti-reflection layer is 75 nm to 85 nm and the refractive index is 1.95 to 2.00; a silicon nitride layer is deposited on the second passivation layer using a PECVD process as a second anti-reflection layer, wherein the thickness is 75 nm to 80 nm and the refractive index is 2.10 to 2.15;

[0246] Screen printing: Silver paste is sequentially printed on the back side as the second electrode and on the front side as the first electrode. The electrodes are then sintered at 840°C to complete the process. The first electrode penetrates the first anti-reflection layer and the first passivation layer, establishing ohmic contact with the first doped polysilicon layer in a predetermined area. The second electrode penetrates the second anti-reflection layer and the second passivation layer, establishing ohmic contact with the second doped polysilicon layer in a predetermined area. Light is injected into the cell at a process temperature of 700°C. The number of gate lines on the second electrode is 1.2 times that of the first electrode.

[0247] In the solar cell of this embodiment, the film parameters of the passivation contact structure (including film thickness, doping concentration, through-hole parameters, etc.) are specifically shown in Table 1 below.

[0248] Example 3

[0249] This embodiment provides a solar cell, as shown in FIG5 , which is a process flow chart of a method for preparing the solar cell of this embodiment. The solar cell is prepared by the following preparation method:

[0250] Provide an N-type substrate: An N-type 182-size M10 silicon wafer is used as the N-type substrate, with a resistivity of 1.0Ω·cm to 3.5Ω·cm and a minority carrier lifetime of >1ms; the N-type substrate has a light-receiving surface and a backlight surface disposed opposite to each other, with the light-receiving surface being the light incident surface;

[0251] Texturing: In a tank-type equipment, the light-receiving surface of the N-type substrate is texturized using sodium hydroxide and the texturing additive TS40 in a volume ratio of 7:1 at 80°C for 7 minutes, with a thickness reduction of 5μm.

[0252] The first passivation contact structure is deposited using the PECVD process: a composite film is deposited on the light-receiving surface after texturing using a tubular PECVD device. The film is deposited under conditions of a pressure of 2500mTorr to 3500mTorr and a temperature of 350℃ to 450℃.

[0253] Film layer 1: Using PECVD, 8SLM to 15SLM of N2O was introduced, and the deposition time was 140s to deposit the first dielectric layer SiO with a thickness of 1.5nm. x ;

[0254] Layer 2: PECVD is used to deposit SiH4 and H2 at a volume ratio of 1:2.5 for 40s to 90s to deposit a front intrinsic layer as an amorphous thin film layer with a thickness of 5nm to 40nm.

[0255] Layer 3: Using PECVD, SiH4, PH3, and H2 in a volume ratio of 1:0.4:2.5, the deposition time is 40s to 90s, and a first front-side doped layer doped with phosphorus is deposited as an amorphous silicon film with a thickness of 5nm to 40nm.

[0256] Layer 4: Using PECVD, SiH4, PH3, and H2 in a volume ratio of 1:0.8:2.5, the deposition time is 250s to 350s, and a second front-side doped layer doped with phosphorus is deposited as an amorphous silicon film with a thickness of 20nm to 80nm.

[0257] Layer 5: Using PECVD, SiH4, NH3, and N2O in a volume ratio of 1:4:7 are introduced for a deposition time of 60s to 200s to deposit a silicon oxynitride film as a front mask layer with a thickness of 5nm to 40nm.

[0258] Alkali polishing: A chain HF machine is used to remove the front mask layer that has been plated to the backlight side using a 5% by volume hydrofluoric acid solution. The substrate is then transferred to a tank alkali polishing machine and the backlight side of the N-type substrate is polished using a 3:1 by volume ratio of sodium hydroxide and alkali polishing additive BP31 at a temperature of 80°C for 7 minutes. The second front doped layer, the first front doped layer, the front intrinsic layer, and the first dielectric layer that have been plated to the backlight side and the edge are simultaneously removed.

[0259] The second passivation contact structure is deposited using a PECVD process: a tubular PECVD device is used to deposit a composite film on the backlit side of the N-type substrate. The film is deposited at a pressure of 2500mTorr to 3500mTorr and a temperature of 330°C to 450°C. The total process time is 30 minutes to 60 minutes.

[0260] Film layer 1: Using PECVD, 8SLM to 15SLM of N2O is introduced, the deposition time is 350 to 600s, and the second dielectric layer SiO is deposited with a thickness of 2-5nm. x ;

[0261] Film layer 2: Using PECVD, SiH4 and H2 with a volume ratio of 1:2.5 are introduced for a deposition time of 40s to 90s to deposit the back intrinsic layer as an amorphous thin film layer with a thickness of 5nm to 40nm;

[0262] Layer 3: Using PECVD, SiH4, B2H6, and H2 in a volume ratio of 1:0.3:2.5, the deposition time is 80s to 300s, and a first back-doped layer doped with boron is deposited as an amorphous silicon film with a thickness of 10nm to 80nm.

[0263] Film layer 4: Using PECVD, SiH4, B2H6, and H2 in a volume ratio of 1:0.6:2.5, the deposition time is 500s to 700s, and a second back-doped layer doped with boron is deposited as an amorphous silicon film with a thickness of 60nm to 180nm.

[0264] Layer 5: Using PECVD, SiH4, NH3, and N2O in a volume ratio of 1:4:7 are introduced for a deposition time of 60s to 200s to deposit a silicon oxynitride film as a back mask layer with a thickness of 5nm to 40nm.

[0265] Annealing: Annealing is performed in a tubular annealing furnace at 850°C for 120 minutes in a nitrogen atmosphere of 10 SLM, so that the first doped amorphous silicon layer is transformed into a first doped polysilicon layer, the second doped amorphous silicon layer is transformed into a second doped polysilicon layer, the first dielectric layer and the first doped polysilicon layer form a first passivation contact structure, the second dielectric layer and the second doped polysilicon layer form a second passivation contact structure, and a PN junction is formed between the N-type substrate and the second doped polysilicon layer;

[0266] Printing: Screen-printing a patterned acid-resistant paste in a preset area of ​​the front mask layer, where the pattern is similar to or identical to the pattern of the screen-printed first electrode, and the line width of the printed acid-resistant paste is 20μm to 110μm, which is slightly wider than the width of the screen-printed first electrode pattern; after printing, drying at 150°C to 250°C for 10 seconds; wherein the acid-resistant paste can protect the first dielectric layer and the first doped amorphous silicon layer (i.e., the front mask layer, the front intrinsic layer, the first front doped layer, the second front doped layer, and other thin film layers) located thereunder; wherein the preset area corresponds to the area where the metal electrode is provided in the solar cell;

[0267] Cleaning: First, it passes through a chain device and uses a 5% by volume hydrofluoric acid solution to remove the front mask layer, leaving only the patterned part on the light-receiving surface that is not etched due to the protection of the acid-resistant slurry. Then it enters a tank texturing machine and uses sodium hydroxide and a texturing additive TS40 with a volume ratio of 2:1 at a temperature of 80°C for 2 minutes to etch and remove the first dielectric layer, the first doped amorphous silicon layer, and the acid-resistant slurry that are not covered in the preset area of ​​the light-receiving surface. Then it enters the acid tank and uses a 5% by volume hydrofluoric acid solution to etch and remove the back mask layer on the backlight side and the remaining front mask layer on the light-receiving surface, so that the light-receiving surface of the N-type substrate is sequentially the first dielectric layer and the first doped amorphous silicon layer located in the preset area, and the backlight side of the N-type substrate is sequentially the second dielectric layer and the second doped amorphous silicon layer on the entire surface.

[0268] Post-processing:

[0269] Aluminum oxide layers are deposited on the light-receiving surface and the backlight surface as the first passivation layer and the second passivation layer respectively using the ALD process. The deposition temperature is 200°C to 280°C and the thickness is 3nm to 5nm.

[0270] A silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer are sequentially deposited on the first passivation layer using a PECVD process as a first anti-reflection layer, wherein the total thickness of the first anti-reflection layer is 75 nm to 85 nm and the refractive index is 1.95 to 2.00; a silicon nitride layer is deposited on the second passivation layer using a PECVD process as a second anti-reflection layer, wherein the thickness is 75 nm to 80 nm and the refractive index is 2.10 to 2.15;

[0271] Screen printing: Silver paste is sequentially printed on the back side as the second electrode and on the front side as the first electrode. The electrodes are then sintered at 840°C to complete the process. The first electrode penetrates the first anti-reflection layer and the first passivation layer, establishing ohmic contact with the first doped polysilicon layer in a predetermined area. The second electrode penetrates the second anti-reflection layer and the second passivation layer, establishing ohmic contact with the second doped polysilicon layer in a predetermined area. Light is injected into the cell at a process temperature of 700°C. The number of gate lines on the second electrode is 1.4 times that of the first electrode.

[0272] In the solar cell of this embodiment, the film parameters of the passivation contact structure (including film thickness, doping concentration, through-hole parameters, etc.) are specifically shown in Table 1 below.

[0273] The differences between Examples 4 to 14 and Example 1 are detailed in Table 1 below.

[0274] Comparative Example 1

[0275] This comparative example provides an N-type passivated contact TOPCon solar cell, the preparation method of which includes the following steps:

[0276] Provide an N-type substrate: an N-type 182-inch M10 silicon wafer is used as the N-type substrate, with a resistivity of 0.3Ω·cm to 2.1Ω·cm and a minority carrier lifetime of >1ms; the N-type substrate has a front side and a back side disposed opposite to each other, with the front side being the light incident side;

[0277] Texturing: In a tank-type machine, the front side of an N-type substrate is texturized using sodium hydroxide and a texturing additive, TS40, in a volume ratio of 7:1, at 80°C for 7 minutes, with a thickness reduction of 5μm.

[0278] Boron diffusion: Place the textured N-type substrate into a boron diffusion furnace. Use boron trichloride gas and oxygen at a volume ratio of 1:3 to deposit the boron source at 830°C. Then, heat at 1030°C for 1 hour to form a PN junction. The sheet resistance after diffusion is controlled at 120Ω / sq~140Ω / sq.

[0279] Alkali polishing: A chain HF machine is used with a 5% by volume hydrofluoric acid solution to remove the borosilicate glass with boron expansion on the back side. The machine is then transferred to a tank-type alkali polishing machine through a robot. Sodium hydroxide and alkali polishing additive BP31 are used in a volume ratio of 3:1. The temperature is maintained at 80°C for 7 minutes to perform back polishing to remove the PN junction that was plated on the back and edge during the boron expansion step.

[0280] Forming the tunneling oxide layer and doped polysilicon layer on the back side: A composite film is deposited on the back side of the N-type substrate using a tubular PECVD device at a pressure of 2500mTorr to 3500mTorr. The outermost PECVD mask layer does not need to be grown. Three thin film layers are deposited at a process temperature of 350°C to 450°C. The total deposition time is 35 minutes to 60 minutes, and the coating process time is 705 seconds.

[0281] Layer 1: Using PECVD, 8-15 SLM of nitric oxide is introduced for about 140 seconds to deposit a 1 nm thick tunnel oxide layer SiO x ;

[0282] Layer 2: PECVD was used to deposit an intrinsic amorphous silicon film with a thickness of 20 nm by introducing SiH4 and H2 at a volume ratio of approximately 1:2.5 for approximately 65 seconds.

[0283] Layer 3: PECVD was used to deposit a 100nm thick phosphorus-doped amorphous silicon film by introducing SiH4, PH3, and H2 in a volume ratio of approximately 1:0.8:2.5 for approximately 500s.

[0284] Film layer 4: Using PECVD method, SiH4 and N2O gases were introduced with a volume ratio of about 1:4.5 for about 60 seconds to deposit SiO x Thin film, thickness 20nm;

[0285] Annealing: The silicon wafer is annealed in a tubular annealing furnace in a nitrogen atmosphere of 5 SLM at a temperature of 850°C to 950°C for 120 minutes and an annealing time of 2700 seconds, so that the crystal structure of the deposited amorphous silicon film is transformed to form a phosphorus-doped polysilicon layer.

[0286] Cleaning: First, the front oxide layer is removed on one side using a chain device with a volume concentration of 5% hydrofluoric acid. Then, the film is transferred to a tank-type alkaline polishing machine through a robot arm. Sodium hydroxide and alkaline polishing additive BP31 are used in a volume ratio of 2:1. The temperature is maintained at 80°C for about 2 minutes to remove the doped polysilicon layer that was plated around the front during the aforementioned deposition. Finally, the film is transferred to an acid tank with a volume concentration of 5% hydrofluoric acid to remove the front BSG layer and the back mask layer.

[0287] Front aluminum oxide and silicon nitride film deposition: A 5nm thick aluminum oxide film is deposited by atomic layer deposition (ALD) for passivation. Then, silicon nitride, silicon oxynitride, and silicon oxide films are sequentially deposited on the front surface by PECVD for anti-reflection. The total thickness is controlled at 75nm to 85nm, and the refractive index is 1.95-2.00.

[0288] PECVD deposition of back silicon nitride film: PECVD deposition of SiN x Thin film, used for back film hydrogen passivation, with a thickness of 75nm to 80nm and a refractive index of 2.10-2.15;

[0289] Screen printing: The second electrode of the back silver paste and the first electrode of the front silver paste are printed in sequence, and the electrode production is completed at a sintering process temperature of 840°C; at a process temperature of 700°C, light injection into the battery is completed; wherein, the first electrode is in ohmic contact with the PN junction area, and the second electrode is in ohmic contact with the phosphorus-doped polysilicon layer.

[0290] That is, the preparation method of Comparative Example 1 is to first form a front PN junction on the front side of the N-type substrate by boron diffusion, and then form a passivation contact structure consisting of a first dielectric layer and a phosphorus-doped polysilicon layer on the back side of the N-type substrate by PECVD and annealing operations, so that Comparative Example 1 becomes a passivation contact solar cell.

[0291] Comparative Example 2

[0292] Compared with Example 1, the only difference of this comparative example is that the thickness of the first dielectric layer on the light-receiving surface in this comparative example is 2.2 nm.

[0293] Comparative Example 3

[0294] Compared with Example 1, the only difference of this comparative example is that the thickness of the second dielectric layer on the backlight side in this comparative example is 1.5 nm.

[0295] Comparative Example 4

[0296] Compared with Example 1, the difference of this comparative example is that the doping concentration of the P-type conductive element in the second doped polysilicon layer on the backlight side is 1×10 18 atom / cm 3 .

[0297] Performance testing:

[0298] Doping concentration: obtained by conventional ECV equipment testing (i.e., using the electrochemical capacitance-voltage method to measure the doping concentration distribution).

[0299] Diameter and number of through holes: First, the sample is corroded with TMAH (tetramethylammonium hydroxide) solution to remove the doped polysilicon. The sample with the doped polysilicon removed is then placed under a SEM for observation to test the diameter and number of holes. The number is then divided by the area of ​​observation to obtain the number of holes per unit area.

[0300] Table 1. Film parameters of passivation contact structure in solar cells

[0301] The solar cells of the above examples and comparative examples were tested for performance, including open circuit voltage, short circuit current, and fill factor, using a Halm test and sorting device. The Halm machine is a device that simulates sunlight and is equipped with an electronic load, data acquisition, and computing equipment to test the electrical performance of photovoltaic devices (including solar cells). The silicon wafers used in the control test were 182 mm in size and the calibrated light intensity was 1000 ± 5 W / m 2 ,The experimental test results are shown in Table 2 below, where Eta represents the photoelectric conversion efficiency, Voc represents the open circuit voltage, Jsc represents the short circuit current, and FF represents the fill factor.

[0302] Table 2. Performance test results of solar cells

[0303] From the analysis of the above performance test results in Table 1, we can see that:

[0304] Compared to the passivated contact solar cell in Comparative Example 1, which forms a PN junction on the front and a passivated contact structure only on the back, the solar cells prepared by the preparation methods of Examples 1, 2, and 3 of the present application have a double-sided passivated contact structure, and the front side is a local passivated contact structure and the back side is a full-surface back PN junction structure. The open circuit voltage, fill factor, photoelectric conversion efficiency and other indicators are significantly improved. Among them, since Examples 1 to 3 use double-sided passivated contacts, the metallization composite on the front side is greatly reduced, so the open circuit voltage is increased by about 7mV compared to Comparative Example 1, which is a more obvious improvement. In addition, since the double-sided passivated contacts are used and the back side is a full-surface passivated contact PN junction structure, it is possible to conduct electricity through the entire silicon wafer, reducing the minority carrier transmission loss toward the local metal contact at the front end, so the fill factor is also greatly improved (about 0.8% to 0.9% higher than the fill factor of Comparative Example 1). The combined effect of the above two factors enables the solar cell of the embodiment of the present application to provide a photoelectric conversion efficiency higher than 25.1%, and even more than 25.6%, thereby reducing the cost per watt of the solar cell.

[0305] A further comparison of Examples 1 to 5 shows that the solar cell's photoelectric conversion efficiency increases first and then decreases with increasing thickness of the first dielectric layer, with the highest photoelectric conversion efficiency achieved when the first dielectric layer is 1.5 nm thick. A further comparison with Comparative Example 2 shows that when the first dielectric layer thickness exceeds 2 nm, the open-circuit voltage, fill factor, and photoelectric conversion efficiency all decrease significantly. This indicates that a first dielectric layer thickness of less than or equal to 2 nm significantly improves performance in indicators such as photoelectric conversion efficiency, with a particularly significant improvement observed when the first dielectric layer is 1.5 nm thick.

[0306] Comparing Example 1 with Comparative Example 3, it can be seen that the second dielectric layer in Comparative Example 3 has a thickness of 1.7 nm, but its corresponding photoelectric conversion efficiency is relatively low. This shows that a second dielectric layer thickness greater than 2 nm is required to effectively improve the photoelectric conversion efficiency of the solar cell. Further comparison with Examples 8 and 9 shows that when the second dielectric layer has a thickness of 3.5 nm, the photoelectric conversion efficiency of the solar cell is significantly improved. However, when the second dielectric layer has a thickness of 2.5 nm, as in Example 1, the photoelectric conversion efficiency is even better.

[0307] By comparing Example 1 with Comparative Example 4, it can be seen that the doping concentration of the P-type conductive element in the second doped polysilicon layer will also have a significant impact on the performance of the solar cell, such as the photoelectric conversion efficiency. In Comparative Example 4, the doping concentration of the P-type conductive element in the second doped polysilicon layer is low, which cannot effectively select electrons and holes, affecting the transmission effect of holes as majority carriers on the backlight surface, thereby affecting the improvement of photoelectric conversion efficiency. Further comparison with Example 11 shows that when the doping concentration of the P-type element is a larger 1×10 19 atoms / cm 3 It is more helpful to improve the photoelectric conversion efficiency.

[0308] Comparisons of Example 1, Example 6, and Example 7, and of Example 1, Example 10, and Example 11 show that different thicknesses of the first doped polysilicon layer and the second doped polysilicon layer affect the photovoltaic conversion efficiency of the solar cell to varying degrees, with the thickness of the first doped polysilicon layer having a particularly significant effect. A first doped polysilicon layer having a thickness of 100 nm and a second doped polysilicon layer having a thickness of 300 nm exhibiting a superior improvement in photovoltaic conversion efficiency.

[0309] By comparing Example 1, Example 12 and Example 13, it can be seen that the number of through holes in the second dielectric layer also affects the photoelectric conversion efficiency of the solar cell. In this application, the number of through holes is preferably 1×10 6 pieces / cm 3 When the hole transport effect and the passivation effect are better taken into account,

[0310] The solar cells, preparation methods, and photovoltaic modules disclosed in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A solar cell, characterized in that, The solar cell includes: a substrate having an N-type conductivity type; a patterned first passivation contact structure disposed on the light-receiving surface of the substrate, the first passivation contact structure including a first dielectric layer close to the substrate and a first doped polysilicon layer away from the substrate, the first doped polysilicon layer having the N-type conductivity type; wherein, the thickness of the first dielectric layer is less than or equal to 2 nm; The second passivation contact structure covering the entire surface is disposed on the backlight surface of the substrate. The second passivation contact structure includes a second dielectric layer adjacent to the substrate and a second doped polysilicon layer away from the substrate. The second doped polysilicon layer has a P-type conductivity type different from the N-type conductivity type, so that the second doped polysilicon layer and the substrate form a PN junction. Among them, the thickness of the second dielectric layer is greater than 2 nm. The second dielectric layer has a through hole connecting the substrate and the second doped polysilicon layer. The doping concentration of the P-type conductive element in the second doped polysilicon layer is 5×10 18 atom / cm 3 ~3×10 20 atom / cm 3 ; a first functional layer disposed on the light-receiving surface of the substrate and on the side of the first doped polysilicon layer away from the substrate; a second functional layer disposed on the side of the second doped polysilicon layer away from the substrate; a first electrode that penetrates the first functional layer and makes an ohmic contact with the first doped polysilicon layer; the patterned area of the first passivation contact structure and the patterned area of the first electrode are correspondingly arranged; a second electrode that penetrates the second functional layer and makes an ohmic contact with the second doped polysilicon layer.

2. The solar cell according to claim 1, wherein The substrate within the coverage area of the first passivation contact structure is 0.5 μm to 1.5 μm thicker than the substrate in the area not covered by the first passivation contact structure.

3. The solar cell according to claim 1, characterized in that, The diameter of the through hole is 50 nm to 500 nm, and the number of the through holes is 1×10 4 holes / cm 2 to 1.6×10 8 holes / cm 2 .

4. The solar cell according to claim 1, characterized in that, The thickness of the first doped polysilicon layer is 40 nm to 200 nm.

5. The solar cell according to claim 1, characterized in that, The thickness of the second doped polysilicon layer is 200 nm to 400 nm.

6. The solar cell according to claim 1, characterized in that, The first doped polysilicon layer is doped with an N-type conductive element, and the N-type conductive element includes at least one of phosphorus, germanium, or selenium.

7. The solar cell according to claim 1, characterized in that, The P-type conductive element includes at least one of boron, indium, or gallium.

8. The solar cell according to claim 1, characterized in that, The line width of the first passivation contact structure is 20 μm to 110 μm.

9. The solar cell according to any one of claims 1 to 8, characterized in that, The first functional layer includes a first passivation layer disposed close to the substrate and a first antireflection layer disposed away from the substrate.

10. The solar cell according to any one of claims 1 to 8, characterized in that, The second functional layer includes a second passivation layer disposed close to the second doped polysilicon layer and a second antireflection layer disposed away from the second doped polysilicon layer.

11. The solar cell according to any one of claims 1 to 8, characterized in that, The ratio of the number of grid lines of the second electrode to the number of grid lines of the first electrode is 1.2 to 1.6:

1.

12. A method for preparing a solar cell according to any one of claims 1 to 11, characterized in that, The preparation method includes the following steps: Forming a passivation contact structure: sequentially disposing the first dielectric layer and the first doped amorphous silicon layer on the light-receiving surface of the substrate to form the first passivation contact structure, and sequentially disposing the second dielectric layer and the second doped amorphous silicon layer on the backlight surface of the substrate to form the second passivation contact structure, such that the thickness of the first dielectric layer is less than or equal to 2 nm and the thickness of the second dielectric layer is greater than 2 nm; Annealing treatment and patterning treatment: annealing the substrate formed with the first passivation contact structure and / or the second passivation contact structure to transform the first doped amorphous silicon layer into the first doped polysilicon layer and / or transform the second doped amorphous silicon layer into the second doped polysilicon layer, and performing patterning treatment on the first passivation contact structure to obtain the patterned first passivation contact structure; Post-treatment: Form the first functional layer on the light-receiving surface of the substrate and the patterned first doped polysilicon layer, form the second functional layer on the second doped polysilicon layer, fabricate the first electrode on the first functional layer, and fabricate the second electrode on the second functional layer.

13. The manufacturing method of the solar cell according to claim 12, characterized in that, The step of forming the passivation contact structure includes: Alkaline polishing: Polish the light-receiving surface and the backlight surface of the substrate using a first alkaline agent; Depositing the second passivation contact structure: Sequentially deposit the second dielectric layer and the second doped amorphous silicon layer on the backlight surface of the substrate; Texturing: First, use a first acid agent to remove the second doped amorphous silicon layer and the second dielectric layer that are plated onto the light-receiving surface and the edge, and then use a second alkaline agent to texture the light-receiving surface of the substrate; Depositing the first passivation contact structure: Sequentially deposit the first dielectric layer and the first doped amorphous silicon layer on the light-receiving surface after texturing.

14. The manufacturing method of the solar cell according to claim 13, characterized in that, The step of depositing the second passivation contact structure includes: Sequentially deposit the second dielectric layer, the back surface intrinsic layer, the back surface doped layer doped with the P-type conductive element, and the back surface mask layer on the backlight surface after alkaline polishing through the PECVD process; The step of texturing includes: First, use the first acid agent to remove the back surface mask layer, the back surface doped layer, the back surface intrinsic layer, and the second dielectric layer that are plated onto the light-receiving surface and the edge, and then use the second alkaline agent to texture the light-receiving surface; The step of depositing the first passivation contact structure includes: Sequentially deposit the first dielectric layer, the front surface intrinsic layer, and the front surface doped layer doped with the N-type conductive element on the light-receiving surface after texturing through the PECVD process.

15. The method for preparing a solar cell according to claim 14, wherein The steps of the annealing treatment and the patterning treatment include: Printing: Print a patterned alkali-resistant slurry in a preset area of the front surface doped layer, and dry it to cure the alkali-resistant slurry; Cleaning: First, use a third alkaline agent to etch and remove the first doped amorphous silicon layer, the first dielectric layer, and a part of the substrate that are not covered by the preset area on the light-receiving surface side of the substrate, and then use a second acid agent to etch and remove the alkali-resistant slurry and remove the back surface mask layer located on the backlight surface, so that a patterned first dielectric layer and a patterned first doped amorphous silicon layer are formed on the light-receiving surface of the substrate, and the substrate in the preset area is 0.5 μm to 1.5 μm thicker than the substrate not covered by the preset area, and a whole-surface second dielectric layer and a second doped amorphous silicon layer are formed on the backlight surface of the substrate; Annealing: In an inert atmosphere, at 850 °C to 1000 °C, anneal for 90 min to 150 min, so that the first doped amorphous silicon layer is transformed into the first doped polysilicon layer, the second doped amorphous silicon layer is transformed into the second doped polysilicon layer, and a PN junction is formed between the substrate and the second doped polysilicon layer.

16. The manufacturing method of the solar cell according to claim 15, characterized in that, In the step of printing, the width of the printed patterned alkali-resistant slurry is 20 μm to 110 μm, the drying temperature after printing is 150 °C to 250 °C, and the drying time is 8 s to 12 s.

17. The manufacturing method of the solar cell according to claim 15, characterized in that, In the cleaning step, the third alkali agent includes an alkali metal hydroxide and a texturing additive with a volume ratio of 1:1 to 3:

1. The etching temperature using the third alkali agent is 70°C to 90°C, and the etching time is 1 minute to 3 minutes.

18. The method for preparing a solar cell according to claim 15, wherein, In the cleaning step, the second acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

19. The manufacturing method of the solar cell according to claim 13, characterized in that, The step of depositing the second passivation contact structure includes: first forming the second dielectric layer on the backlight surface after alkali polishing through a thermal oxidation process, then forming an intrinsic amorphous silicon layer on the back through an LPCVD process, and then doping a P-type conductive element into the intrinsic amorphous silicon layer on the back through a diffusion process to transform the intrinsic amorphous silicon layer on the back into the second doped polysilicon layer; The texturing step includes: first using the first acid agent to remove the second doped polysilicon layer and the second dielectric layer that are deposited onto the light-receiving surface and the edge, and then using the second alkali agent to texture the light-receiving surface; The step of depositing the first passivation contact structure includes: sequentially depositing the first dielectric layer, the front intrinsic layer, the front doped layer doped with an N-type conductive element, and the front mask layer on the light-receiving surface after texturing through a PECVD process.

20. The method for preparing a solar cell according to claim 19, wherein, The steps of annealing treatment and patterning include: Annealing: In an inert atmosphere, at 850°C to 950°C for 90 minutes to 150 minutes, to transform the first doped amorphous silicon layer into the first doped polysilicon layer; Printing: Printing a patterned acid-resistant paste in a preset area of the front mask layer, and drying to cure the acid-resistant paste; Cleaning: First using a third acid agent to etch and remove the front mask layer not covered by the preset area on the light-receiving surface side, then using a fourth alkali agent to etch and remove the first doped polysilicon layer, the first dielectric layer, and the acid-resistant paste not covered by the preset area on the light-receiving surface side, and using a fourth acid agent to remove the remaining front mask layer, so that the light-receiving surface of the substrate forms a patterned first dielectric layer and a patterned first doped amorphous silicon layer, and the backlight surface of the substrate forms a positive second dielectric layer and a second doped polysilicon layer.

21. The manufacturing method of the solar cell according to claim 20, characterized in that, In the printing step, the width of the printed patterned acid-resistant paste is 20 μm to 110 μm, and the drying temperature after printing is 150°C to 250°C, and the drying time is 8 s to 12 s.

22. The method for preparing a solar cell according to claim 20, wherein In the cleaning step, the third acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

23. The method for preparing a solar cell according to claim 20, wherein, In the cleaning step, the fourth alkali agent includes an alkali metal hydroxide and a texturing additive with a volume ratio of 1:1 to 3:

1. The etching temperature using the fourth alkali agent is 70°C to 90°C, and the etching time is 1 minute to 3 minutes.

24. The method for preparing a solar cell according to claim 20, wherein In the cleaning step, the fourth acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

25. The method for preparing a solar cell according to claim 12, wherein, The step of forming the passivation contact structure includes: Texturing: Using a fifth alkali agent to texture the substrate; Depositing the first passivation contact structure: Sequentially depositing the first dielectric layer and the first doped amorphous silicon layer on the light-receiving surface after texturing; Alkaline polishing: Use the fifth acid agent to remove part of the first doped amorphous silicon layer that is plated around to the backlight surface, then use the sixth alkaline agent to polish the backlight surface of the substrate, and remove the remaining part of the first doped amorphous silicon layer and the first dielectric layer that are plated around to the backlight surface and the edge; Depositing the second passivation contact structure: Sequentially deposit the second dielectric layer and the second doped amorphous silicon layer on the backlight surface.

26. The method for preparing a solar cell according to claim 25, wherein, The step of depositing the first passivation contact structure includes: Sequentially deposit the first dielectric layer, the front intrinsic layer, the front doped layer doped with N-type conductive elements, and the front mask layer on the light-receiving surface after texturing through the PECVD process; The step of alkaline polishing includes: First use the fifth acid agent to remove the front mask layer that is plated around to the backlight surface, then use the sixth alkaline agent to polish the backlight surface of the substrate, and remove the front doped layer, the front intrinsic layer, and the first dielectric layer that are plated around to the backlight surface and the edge; The step of depositing the second passivation contact structure includes: Sequentially deposit the second dielectric layer, the back intrinsic layer, the back doped layer doped with P-type conductive elements, and the back mask layer on the backlight surface after alkaline polishing through the PECVD process.

27. The manufacturing method of the solar cell according to claim 26, characterized in that, The steps of annealing treatment and patterning treatment include: Annealing: Anneal the substrate on which the first passivation contact structure and the second passivation contact structure are formed. In an inert atmosphere, anneal at 850 °C to 1000 °C for 90 min to 150 min; Printing: Print a patterned acid-resistant paste in a preset area of the front mask layer, and dry it to cure the acid-resistant paste; Cleaning: First use the sixth acid agent to etch and remove the front mask layer that is not covered by the preset area on the light-receiving surface, then use the seventh alkaline agent to etch and remove the acid-resistant paste, and remove the first dielectric layer and the first doped amorphous silicon layer that are not covered by the preset area on the light-receiving surface, and then use the seventh acid agent to remove the front mask layer and the back mask layer.

28. The manufacturing method of the solar cell according to claim 27, characterized in that, In the step of printing, the width of the patterned acid-resistant paste printed is 20 μm to 110 μm, the drying temperature after printing is 150 °C to 250 °C, and the drying time is 8 s to 12 s.

29. The method for preparing a solar cell according to claim 27, characterized in that, In the step of cleaning, the sixth acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

30. The method for preparing a solar cell according to claim 27, wherein In the step of cleaning, the seventh alkaline agent includes an alkali metal hydroxide and a texturing additive with a volume ratio of 1:1 to 3:

1. The temperature for etching with the seventh alkaline agent is 70 °C to 90 °C, and the etching time is 1 min to 3 min.

31. The method for preparing a solar cell according to claim 27, wherein, In the step of cleaning, the seventh acid agent is a hydrofluoric acid solution with a volume percentage of 4% to 6%.

32. The method for preparing a solar cell according to any one of claims 12 to 28, characterized in that, The first functional layer includes a first passivation layer and a first antireflection layer, and the second functional layer includes a second passivation layer and a second antireflection layer; The steps of post-treatment include: Deposit the first passivation layer and the second passivation layer on the light-receiving surface and the backlight surface respectively by ALD process; Deposit the first antireflection layer on the first passivation layer and deposit the second antireflection layer on the second passivation layer by using the PECVD process; Print the first electrode on the light-receiving surface to make an ohmic contact between the first electrode and the first doped polysilicon layer; Print the second electrode on the backlight surface to make an ohmic contact between the second electrode and the second doped polysilicon layer.

33. The method for manufacturing a solar cell according to claim 32, wherein, In the ALD process, the deposition temperature is 200°C to 280°C, and the thicknesses of the first passivation layer and the second passivation layer deposited are 3nm to 5nm respectively.

34. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1 to 11, or the photovoltaic module includes the solar cell prepared by the preparation method of the solar cell according to any one of claims 12 to 33.

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