Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment may comprise: a build-up insulator on which a single or a plurality of insulating layers are stacked; a wiring layer disposed on the build-up insulator and having a plurality of pads; and a post bump disposed on a first pad positioned on a first region of a build-up insulation layer among the plurality of pads. A portion of the upper surface of the first pad includes a recess around the outer circumference of the post bump, and the recess of the first pad may not overlap the post bump in the horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package board including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring body connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005]

[0006] Meanwhile, with the recent advancement of portable electronic devices and other devices, the frequency of signals is increasing to enable high-speed processing of large amounts of information, and circuit boards are becoming more highly integrated to be suitable for high-frequency, high-performance applications.

[0007] These highly integrated circuit boards require miniaturization of circuit patterns to enable signal transmission in an integrated state while minimizing signal transmission loss.

[0008] However, due to the miniaturized circuit pattern, electrical reliability problems such as circuit shorts are occurring due to solder flowing out during the soldering process for mounting semiconductor chips.

[0009] The present invention seeks to provide a circuit board with improved electrical reliability and a semiconductor package including the same.

[0010] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0011] A circuit board according to an embodiment may include a build-up insulator having a single or multiple insulating layers laminated thereon, a wiring layer disposed on the build-up insulator and having a plurality of pads, and a post bump disposed on a first pad located on a first region of the build-up insulating layer among the plurality of pads.

[0012] A portion of the upper surface of the first pad includes a recess around the outer perimeter of the post bump, and the recess of the first pad may not overlap horizontally with the post bump.

[0013] The post bump may include a first metal layer disposed on a first pad and a second metal layer disposed on the first metal layer.

[0014] The first metal layer may include a seed metal layer.

[0015] The second metal layer may not overlap vertically with the recess of the first pad.

[0016] The recess of the first pad may be positioned lower than the second metal layer.

[0017] The recess of the first pad may be positioned lower than the first metal layer.

[0018] The first metal layer may not overlap horizontally with the recess of the first pad.

[0019] The first metal layer may have a side surface having a curved surface.

[0020] The lower side of the curved surface of the first metal layer can contact one end of the recess of the first pad.

[0021] The wiring layer further includes a second pad positioned on a second region of the build-up insulating layer among the plurality of pads, wherein the second pad may not include a seed metal layer.

[0022] The post bumps may include a first post bump that is energized and a second post bump that is not energized.

[0023] Additionally, the embodiment further includes a first protective layer disposed on a portion of the build-up insulating layer and the first pad, and the second metal layer of the post bump may be thicker than the first protective layer.

[0024] A semiconductor package according to an embodiment may include one or more of the circuit boards described above.

[0025] According to the circuit board and the semiconductor package including the same according to the embodiment, electrical reliability can be improved.

[0026] For example, according to an embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface (see FIG. 2), even if solder flow occurs, more solder is retained in the space of the recess (122R1) of the curved surface of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0027] Furthermore, according to the embodiment, by erecting a post bump (170) on the first pad (122a1), space for mounting the chip on the circuit board can be secured. Accordingly, heat generated from the semiconductor package can be more efficiently dissipated, and higher performance can be achieved by using a more integrated chip.

[0028] In addition, according to the embodiment, by erecting a post bump (170) on the first pad (122a1), the solder volume for mounting the chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0029] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, the first metal layer (170S), which is a seed layer, is removed except for the area of ​​the first pad (122a1), and is not placed on the trace (122a3) or the second pad (122a2), thereby preventing electrical short circuits between wiring patterns.

[0030] Additionally, at least a portion of the first protective layer (141) may be placed on the recess (122R1) of the first pad (122a1). Accordingly, the bonding area between the build-up insulator (110) and the first protective layer (141) may be increased, thereby improving adhesion.

[0031] In addition, according to the second circuit board (102) and the second semiconductor package (202) according to the embodiment, by providing the second post bump (170D) which is a dummy post bump, the etching amount of the seed layer in each area of ​​the circuit board can be made uniform, and thereby each post bump can have a uniform height.

[0032] In addition, according to the second circuit board (102) and the second semiconductor package (202) according to the embodiment, the heat dissipation characteristics can be improved through the dummy post bump by providing the second post bump (170D) which is a dummy post bump.

[0033] Also, referring to FIGS. 7 and 9, the embodiment can reduce the solder volume for mounting the chip by forming the second post bump (172) on the first pad (122a1) to be at least twice as thick as the first protective layer (141). For example, according to the embodiment, the first volume (V1) of the third connection portion (213) disposed on the second post bump (172) formed to be thick can be smaller than the second volume (V2) of the first connection portion (211) disposed on the second pad (122a2).

[0034] Accordingly, a short circuit due to a solder bridge can be prevented due to the reduced solder volume of the third connection portion (213) on the second post bump (172) formed thickly, thereby improving electrical reliability, and a finer bump pitch design is possible due to the reduced risk of an electrical short, thereby providing a high-performance semiconductor package.

[0035] In addition, according to the embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), a space for mounting the chip on the circuit board can be secured by about 5 to 30 ㎛ more, and the first separation distance (W1) between adjacent second post bumps (172) can be secured to be smaller than the second separation distance (W2) of the adjacent first connecting portion (211), thereby enabling a finer bump pitch design, thereby providing a high-performance semiconductor package. In addition, by forming thick post bumps (172), heat generated in the semiconductor package can be more efficiently dispersed, and higher performance can be achieved by using more integrated chips.

[0036] Also, referring to FIG. 10, the embodiment can reduce the solder volume for mounting the chip by forming the second post bump (172) on the first pad (122a1) to be at least twice as thick as the first protective layer (141). For example, according to the embodiment, the first volume (V1) of the fourth connecting portion (213CB) disposed on the second post bump (172) formed to be thick can be smaller than the second volume (V2) of the first connecting portion (211) disposed on the second pad (122a2).

[0037] Accordingly, the fourth connection portion (213CB) on the second post bump (172) formed thickly can prevent a short circuit due to a solder bridge due to a reduced solder volume, thereby improving electrical reliability, and a finer bump pitch design is possible due to a reduced risk of an electrical short circuit, thereby providing a high-performance semiconductor package.

[0038]

[0039] In addition, according to the embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), a space for mounting the chip on the circuit board can be secured by about 5 to 30 ㎛ more, and the first separation distance (W1) between adjacent second post bumps (172) can be secured to be smaller than the second separation distance (W2) of the adjacent first connecting portion (211), thereby enabling a finer bump pitch design, thereby providing a high-performance semiconductor package. In addition, by forming thick post bumps (172), heat generated in the semiconductor package can be more efficiently dispersed, and higher performance can be achieved by using more integrated chips.

[0040] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0041] Figure 1a is a cross-sectional view of a circuit board (100) according to an embodiment.

[0042] FIG. 1b is a detailed view of a circuit board (100) according to the embodiment illustrated in FIG. 1a.

[0043] FIG. 2 is an enlarged view of a first area (A1) of a circuit board (100) according to the embodiment illustrated in FIG. 1b.

[0044] Figures 3a to 3c are cross-sectional views of a method for manufacturing a circuit board (100) according to an embodiment.

[0045] Figure 4 is a cross-sectional view of a first semiconductor package (201) according to an embodiment.

[0046] Figure 5 is a cross-sectional view of a second circuit board (102) according to an embodiment.

[0047] Figure 6 is a cross-sectional view of a second semiconductor package (202) according to an embodiment.

[0048] Fig. 7 is a cross-sectional view of a third circuit board (102) according to an embodiment.

[0049] Figures 8a and 8b are cross-sectional views of a manufacturing process of a third circuit board (102) according to an embodiment.

[0050] Fig. 9 is a cross-sectional view of a third semiconductor package (203) according to an embodiment.

[0051] Fig. 10 is a cross-sectional view of a fourth semiconductor package (204) according to an embodiment.

[0052] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0053] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0054] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0055] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0056] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0057] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0058] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0059] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0060] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0061] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0062] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0063]

[0064] (Example)

[0065] FIG. 1a is a cross-sectional view of a circuit board (100) according to an embodiment, and FIG. 1b is a detailed view of the circuit board (100) according to the embodiment shown in FIG. 1a.

[0066] A circuit board (100) according to an embodiment includes a build-up insulator (110), a build-up wiring body (120), and a protective layer (140). The build-up structure including the build-up insulator (110), the build-up wiring body (120), and the protective layer (140) may be referred to as a build-up structure, but is not limited thereto. The build-up structure may function as a laminated circuit for connecting to electronic components / main boards, etc.

[0067]

[0068] Referring to FIG. 1a, the build-up insulator (110) includes a single or multiple insulating layers laminated in a vertical direction, and provides insulating properties between the build-up wiring bodies.

[0069] Additionally, one of the insulating layers of the build-up insulator (110) may be a core layer. If the build-up insulator (110) includes multiple insulating layers, the insulating layer located at the center may be a core layer, but is not limited thereto. More detailed characteristics of the build-up insulator (110) will be described in the subsequent section on manufacturing methods.

[0070]

[0071] Next, the build-up wiring body (120) includes a wiring layer (122) arranged on the surface of each insulating layer constituting the build-up insulator (110) and a via electrode (121) for vertically connecting each wiring layer (122). The via electrode (121) may be referred to as a through electrode, a via, or a via portion.

[0072] The via electrode (121) includes a single or multiple via electrodes formed in a through hole penetrating a single or multiple insulating layers. The via electrode (121) can electrically connect between wiring layers (122) arranged in different layers.

[0073] The metal material forming the via electrode (121) may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material filling may utilize any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing.

[0074]

[0075] Next, the embodiment includes a wiring layer (122) electrically connected to a via electrode (121). The wiring layer (122) can perform the function of transmitting signals and / or power to semiconductor devices arranged on a circuit board and the impedance matching function. The wiring layer (122) may be referred to as a wiring pattern layer, a metal wiring, or a wiring portion.

[0076] For example, the wiring layer (122) includes a first wiring layer (122a) disposed on a build-up insulator (110) and a second wiring layer (122b) disposed under the build-up insulator (110).

[0077] Specifically, referring to FIG. 1B, the wiring layer (122) includes pads and / or traces (or connection patterns) for connecting to via electrodes (121) and / or semiconductor elements and / or capacitors. The traces may be long signal wiring lines connecting between a plurality of pads.

[0078] At this time, the pad of the wiring layer (122) includes a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode and may include a side extension portion for alignment margin.

[0079] For example, the first wiring layer (122a) includes a first pad (122a1) and a second pad (122a2). The first pad (122a1) and the second pad (122a2) are provided singly or in plurality and can function as connection pads. In addition, the wiring layer (122) includes a trace (122a3), which is a signal wiring line connecting the plurality of pads.

[0080] The wiring layer (122) can be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP).

[0081] The wiring layer (122) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the wiring layer (122) may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0082] One of the build-up wiring bodies (120) may have an ETS (Embedded Trace Substrate) structure. For example, the first wiring layer (122a) disposed on the build-up insulator (110) may have an ETS structure. The ETS structure may also be referred to as a buried structure. The ETS structure is advantageous for miniaturization compared to a build-up wiring body having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in the semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0083]

[0084] Next, the embodiment includes a post bump (170) disposed on the first pad (122a1) of the first wiring layer (122a). The post bump (170) of the embodiment may be provided to have the horizontal width described above in consideration of securing the integrity of signal and / or power transmission, mechanical rigidity, and stress with the build-up structure. In addition, the post bump (170) operates to smoothly transmit power and / or signals when another upper circuit board is disposed on the semiconductor element and / or circuit board, thereby smoothly operating the electronic element and / or connecting member. The characteristics of the post bump (170) will be described in detail later based on FIG. 2.

[0085] Next, the embodiment includes a protective layer (140) disposed on the uppermost or lowermost build-up wiring body (120). For example, the protective layer (140) includes a first protective layer (141) disposed on a first wiring layer (122a) and a second protective layer (142) disposed on a second wiring layer (122b).

[0086]

[0087] Next, FIG. 2 is an enlarged view of a first area (A1) of a circuit board (100) according to the embodiment illustrated in FIG. 1b.

[0088] In an embodiment, the post bump (170) includes a first metal layer (170S) and a second metal layer (170P). For example, the post bump (170) includes, but is not limited to, a first metal layer (170S) which is a seed metal layer disposed on the first pad (122a1) and a second metal layer (170P) which is a post metal layer disposed on the first metal layer (170S).

[0089] The first metal layer (170S) may not be disposed on the second pad (122a2) among the wiring layers. For example, the seed metal layer may not be disposed on the second pad (122a2).

[0090] The upper surface of the first pad (122a1) includes a recess (122R1) on the outer periphery of the second metal layer (170P). For example, the upper surface of the first pad (122a1) may include a recess (122R1) having a curved surface on the outer periphery of the second metal layer (170P). In addition, the second metal layer (170P) may not vertically overlap with the recess (122R1) of the first pad (122a1).

[0091] For example, a portion of the upper surface of the first pad (122a1) may include a recess (122R1) having a curvature in the vertical direction as removed by wet etching.

[0092] The recess (122R1) of the first pad (122a1) may be positioned lower than the second metal layer (170P). Accordingly, the second metal layer (170P) may not horizontally overlap with the recess (122R1) of the first pad (122a1).

[0093] Additionally, the recess (122R1) of the first pad (122a1) may be positioned lower than the first metal layer (170S). Accordingly, the first metal layer (170S) may not horizontally overlap with the recess (122R1) of the first pad (122a1).

[0094] The thickness of the second metal layer (170P) may be thicker than the thickness of the first protective layer (141).

[0095] In an embodiment, the vertical cross-sectional shape of the second metal layer (170P) may have a square shape.

[0096]

[0097] Next, in the embodiment, the first metal layer (170S) may have a side surface (SR2) having a curved surface.

[0098] For example, a portion of the side surface of the first metal layer (170S) may include a curved side surface (SR2) having a curvature in the thickness direction as it is removed by wet etching.

[0099] The lower side (SR2) of the curved surface of the first metal layer (170S) can be in contact with one end of the recess (122R1) of the first pad (122a1).

[0100]

[0101] According to an embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, even if solder flow occurs, more solder is retained in the space of the recess (122R1) of the curved surface of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0102] In addition, according to the embodiment, since the first metal layer (170S) has a curved side surface (SR2), even if solder flow occurs, more solder is retained in the space of the curved side surface (SR2) of the first metal layer (170S) and the curved recess (122R1) of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0103] Additionally, according to the embodiment, by erecting a post bump (170) on the first pad (122a1), a space of approximately 5 to 30 μm can be secured for mounting the chip on the circuit board. Accordingly, heat generated from the semiconductor package can be more efficiently dispersed, and higher performance can be achieved by using a more integrated chip.

[0104] In addition, according to the embodiment, by erecting a post bump (170) on the first pad (122a1), the solder volume for mounting the chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0105] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, the first metal layer (170S), which is a seed layer, is removed except for the area of ​​the first pad (122a1), and is not placed on the trace (122a3) or the second pad (122a2), thereby preventing electrical short circuits between wiring patterns.

[0106] Additionally, at least a portion of the first protective layer (141) may be placed on the recess (122R1) of the first pad (122a1). Accordingly, the bonding area between the build-up insulator (110) and the first protective layer (141) may be increased, thereby improving adhesion.

[0107]

[0108] Hereinafter, a method for manufacturing a circuit board (100) according to an embodiment will be described using FIGS. 3a to 3c.

[0109] First, as shown in Fig. 3a, a build-up wiring body (120) is formed on a build-up insulator (110).

[0110] The build-up insulator (110) includes a single or multiple laminated insulating layers and provides insulating properties between the build-up wiring bodies. The build-up insulator (110) may include multiple insulating layers, such as a first insulating layer, a second insulating layer, and a third insulating layer, but is not limited thereto. In addition, one of the insulating layers of the build-up insulator (110) may be a core layer. When the build-up insulator (110) includes multiple insulating layers, the insulating layer located at the center may be a core layer, but is not limited thereto.

[0111] The build-up insulator (110) has a function for arranging the wiring layer (122) or via electrode (121) of the build-up wiring body, and a function for securing insulation between circuits and controlling impedance or insertion loss by the circuit. The build-up insulator (110) includes an insulating layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film, taking into consideration dielectric constant, mechanical rigidity, and processability.

[0112] For example, the insulating layer of the build-up insulator (110) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0113] Also, for example, the insulating layer of the build-up insulator (110) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0114] Additionally, the insulating layer of the build-up insulator (110) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0115] Additionally, the insulation layer of the build-up insulator (110) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0116]

[0117] Next, the build-up wiring body (120) includes a wiring layer (122) arranged on the surface of each insulating layer of the build-up insulator (110) and a via electrode (121) for vertically connecting each wiring layer (122). The wiring layer (122) can perform the function of transmitting signals and / or power to semiconductor elements arranged on a circuit board and the function of impedance matching.

[0118] The via electrode (121) includes a single or multiple via electrodes formed in a through hole penetrating a single or multiple insulating layers. The via electrode (121) can electrically connect between wiring layers (122) arranged in different layers.

[0119] Through-holes can be formed by any of the following methods: mechanical processing, laser processing, or chemical processing. When formed mechanically, methods such as milling, drilling, and routing can be used. When formed by laser processing, UV or CO2 lasers can be used. Chemical processing can utilize chemicals such as aminosilanes and ketones.

[0120] The metal material forming the via electrode (121) may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material filling may utilize any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing.

[0121] Next, the embodiment includes a wiring layer (122) electrically connected to a via electrode (121). For example, the wiring layer (122) includes a first wiring layer (122a) disposed on a build-up insulator (110) and a second wiring layer (122b) disposed under the build-up insulator (110).

[0122] The wiring layer (122) can be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0123] The wiring layer (122) includes pads and / or traces (or connection patterns) for connecting to via electrodes (121) and / or semiconductor elements and / or capacitors. The traces may be long signal wiring lines connecting between a plurality of pads.

[0124] At this time, the pad of the wiring layer (122) includes a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode and may include a side extension portion for alignment margin.

[0125] For example, the wiring layer (122) includes a first pad (122a1) and a second pad (122a2). The first pad (122a1) and the second pad (122a2) are provided singly or in plurality and can function as a connection pad. In addition, the wiring layer (122) includes a trace (122a3).

[0126] The wiring layer (122) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the wiring layer (122) may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0127] One of the build-up wiring bodies (120) may have an ETS (Embedded Trace Substrate) structure. For example, the first wiring layer (122a) disposed on the build-up insulator (110) may have an ETS structure. The ETS structure may also be referred to as a buried structure. The ETS structure is advantageous for miniaturization compared to a build-up wiring body having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in the semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0128]

[0129] Next, the circuit board (100) according to the embodiment includes a post bump (170) (see FIG. 3c) disposed on a pad of the first wiring layer (122a). The post bump (170) of the embodiment may be provided to have the width in the horizontal direction described above in consideration of securing the integrity of signal and / or power transmission, mechanical rigidity, and stress with the build-up structure. The post bump (170) operates to smoothly transmit power and / or signals when another upper circuit board is disposed on the semiconductor element and / or circuit board, thereby smoothly operating the electronic element and / or connecting member.

[0130] The process of forming a post bump (170) provided on a circuit board (100) according to the following embodiment will be described.

[0131] As shown in FIG. 3A, the embodiment may include a post-bump pre-layer (170J) disposed on a build-up insulator (110) and a build-up wiring body (120). The post-bump pre-layer (170J) includes a first pre-metal layer (170S1) and a second pre-metal layer (170P1). The first pre-metal layer (170S1) may be a seed layer, and the second pre-metal layer (170P1) may be an electroplating layer, but is not limited thereto. For example, the first pre-metal layer (170S1) may be a chemical copper plating layer. Alternatively, the first pre-metal layer (170S1) may be a copper foil layer, but is not limited thereto. The second pre-metal layer (170P1) may be an electroplating layer containing copper, but is not limited thereto.

[0132] The order in which the post bump pre-layer (170J) is formed may be formed before the formation of the build-up insulator (110) and the build-up wiring body (120). For example, the build-up wiring body (120) and the build-up insulator (110) may be formed on the post bump pre-layer (170J), but the process order is not limited thereto.

[0133] Next, as shown in Fig. 3b, an etching pattern (301) such as a dry film is formed on the post bump pre-layer (170J), and the second pre-metal layer (170P1) is etched using the etching pattern (301) as a mask to form a second metal layer (170P).

[0134] Next, as shown in FIG. 3c, the etching pattern (301) is removed, and the first preliminary metal layer (170S1) is partially etched to form the first metal layer (170S). For example, the first preliminary metal layer (170S1) may be partially etched using wet etching. Through this, a post bump (170) including the first metal layer (170S) and the second metal layer (170P) is formed.

[0135] Thereafter, a protective layer (140) is formed on the uppermost or lowermost build-up wiring body (120). For example, the protective layer (140) includes a first protective layer (141) disposed on the first wiring layer (122a) and a second protective layer (142) disposed on the second wiring layer (122b).

[0136] The protective layer (140) can prevent problems such as oxidation or peeling of the build-up structure due to external moisture or contaminants. The protective layer can be formed of a material with low wettability to solder to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing bridging and short circuits between adjacent solders.

[0137] The protective layer (140) includes an insulating material, and the protective layer (140) includes various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. The protective layer (140) may be a resist layer, and for example, the protective layer (140) may be a solder resist layer including an organic polymer material. As an example, the protective layer (140) includes an epoxy acrylate series resin. In detail, the protective layer (140) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the protective layer (140) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0138] According to the circuit board according to the embodiment, electrical reliability can be improved.

[0139] For example, according to an embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface (see FIG. 2), even if solder flow occurs, more solder is retained in the space of the recess (122R1) of the curved surface of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0140] Furthermore, according to the embodiment, by erecting a post bump (170) on the first pad (122a1), space for mounting the chip on the circuit board can be secured. Accordingly, heat generated from the semiconductor package can be more efficiently dissipated, and higher performance can be achieved by using a more integrated chip.

[0141] In addition, according to the embodiment, by erecting a post bump (170) on the first pad (122a1), the solder volume for mounting the chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0142] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, the first metal layer (170S), which is a seed layer, is removed except for the area of ​​the first pad (122a1), and is not placed on the trace (122a3) or the second pad (122a2), thereby preventing electrical short circuits between wiring patterns.

[0143] Additionally, at least a portion of the first protective layer (141) may be placed on the recess (122R1) of the first pad (122a1). Accordingly, the bonding area between the build-up insulator (110) and the first protective layer (141) may be increased, thereby improving adhesion.

[0144]

[0145] Next, a first semiconductor package (201) including a circuit board according to an embodiment will be described.

[0146] Figure 4 is a cross-sectional view of a first semiconductor package (201) according to an embodiment.

[0147] A semiconductor package (201) according to the first embodiment may include a circuit board (100) of FIGS. 1A and 1B.

[0148] Referring to FIG. 4, a semiconductor package (201) according to the first embodiment includes a first connection portion (211) disposed on a second pad (122a2) of a circuit board (100), and may also include a first chip (210) or a first element (210) disposed on the first connection portion (211).

[0149] Specifically, the first connection portion (211) is positioned on the second pad (122a2) that vertically overlaps the opening of the first protective layer (241). The first connection portion (211) may be a solder ball, but is not limited thereto.

[0150] A first semiconductor package (201) according to an embodiment may include a first chip (210) or element (210) disposed on a first connection portion (211). The first chip (210) may be a processor chip. For example, the first chip (210) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0151] At this time, the lower surface of the first chip (210) may include a terminal (not shown), and the terminal may be electrically connected to the second pad (122a2) of the circuit board through the first connection portion (211).

[0152] Meanwhile, the first semiconductor package (201) of the embodiment may include a plurality of chips that are arranged and horizontally spaced apart from each other on a single circuit board. For example, the first chip (210) may include a first chip and a second chip that are spaced apart from each other. In addition, the first chip and the second chip may be different types of application processor (AP) chips.

[0153]

[0154] In addition, the first semiconductor package (201) of the embodiment may include a second connection portion (212). The second connection portion (212) may be disposed on a lower surface of the second wiring layer (122b). For example, the second wiring layer (122b) includes at least one pad. And, the pad of the second wiring layer (122b) may vertically overlap with an opening of the second protective layer (142). And, the second connection portion (212) may be disposed under the pad of the second wiring layer (122b) that vertically overlaps with the opening of the second protective layer (142). The second connection portion (212) may be a solder ball, but is not limited thereto. The second connection portion (212) may be for connecting the semiconductor package and a main board (or motherboard) of an external device.

[0155]

[0156] Additionally, the first semiconductor package (201) according to the embodiment further includes an external substrate (220). The external substrate (220) may be an interposer, but is not limited thereto.

[0157] The external substrate (220) includes a plurality of insulating layers (not shown). The external substrate (220) includes a circuit layer disposed on the plurality of insulating layers. The external substrate (220) may be a substrate connecting a semiconductor package on which an AP chip is disposed and a semiconductor package on which a memory chip is disposed. To this end, the circuit layer of the external substrate (220) may be designed to correspond to the terminal specifications of the AP chip and the terminal specifications of the memory chip. Specifically, the width or pitch of the circuit layer of the circuit board on which the AP chip is disposed may be different from the width or pitch of the circuit layer of the circuit board on which the memory chip is disposed. Accordingly, the external substrate (220) may be disposed between a plurality of circuit boards having the same difference in width or pitch as described above to electrically connect them therebetween.

[0158] The external substrate (220) may be placed on the post bump (170) of the circuit board (100). In addition, the first semiconductor package (201) further includes a third connection portion (213). For example, the third connection portion (213) may be placed on the post bump (170). The uppermost end of the post bump (170) may be positioned higher than the upper end of the first chip (210). Through this, the embodiment can prevent the first chip (210) from being damaged when coupled with the external substrate (220).

[0159] Additionally, the first semiconductor package (201) may include a first molding layer (251). The first molding layer (251) may mold the first connection portion (211), the first chip (210), the third connection portion (213), and the external substrate (220). Meanwhile, although not illustrated in FIG. 4, a memory substrate (not illustrated) may be placed on the external substrate (220).

[0160]

[0161] According to a semiconductor package including a circuit board according to an embodiment, electrical reliability can be improved.

[0162] For example, according to an embodiment, by erecting a post bump (170) on the first pad (122a1), space can be secured for mounting the chip on the circuit board. Accordingly, heat generated from the semiconductor package can be more efficiently dissipated, and higher performance can be achieved by using a more integrated chip.

[0163] In addition, according to the embodiment, by erecting a post bump (170) on the first pad (122a1), the solder volume for mounting the chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0164] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface (see FIG. 2), even if solder flow occurs, more solder is retained in the space of the recess (122R1) of the curved surface of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0165] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, the first metal layer (170S), which is a seed layer, is removed except for the area of ​​the first pad (122a1), and is not placed on the trace (122a3) or the second pad (122a2), thereby preventing electrical short circuits between wiring patterns.

[0166] Additionally, at least a portion of the first protective layer (141) may be placed on the recess (122R1) of the first pad (122a1). Accordingly, the bonding area between the build-up insulator (110) and the first protective layer (141) may be increased, thereby improving adhesion.

[0167]

[0168] Next, FIG. 5 is a cross-sectional view of a second circuit board (102) according to an embodiment, and FIG. 6 is a cross-sectional view of a second semiconductor package (202) according to an embodiment.

[0169] The second circuit board (102) and the second semiconductor package (202) can adopt the technical features of the circuit board (100) and the first semiconductor package (201) described above, and the following description will focus on the technical features of the second circuit board (102) and the second semiconductor package (202).

[0170] The post bump (170) of the second circuit board (102) and / or the second semiconductor package (202) includes a first post bump (170A) to which power is applied and a second post bump (170D) to which power is not applied. The second post bump (170D) may be a dummy post bump.

[0171]

[0172] The second post bump (170D) may adopt the technical features of the post bump (170) previously described based on FIG. 2. For example, the second post bump (170D) also includes a first dummy metal layer (not shown) and a second dummy metal layer (not shown). For example, the second post bump (170D) may include a first dummy metal layer, which is a seed metal layer disposed on a first dummy pad (122d1), and a second dummy metal layer, which is a post metal layer disposed on the first dummy metal layer. The upper surface of the first dummy pad (122d1) includes a curved recess (not shown) around the outer periphery of the second dummy metal layer. In addition, the first dummy metal layer may have a side surface (not shown) having a curved surface.

[0173] The second semiconductor package (202) includes an external substrate (220) disposed on the first post bump (170A) via a third connecting portion (231). The external substrate (220) may be an interposer, but is not limited thereto. The external substrate (220) includes a circuit layer disposed on a plurality of insulating layers. The external substrate (220) may be a substrate connecting a semiconductor package on which an AP chip is disposed and a semiconductor package on which a memory chip is disposed.

[0174] The first post bump (170A) can be electrically connected to the wiring layer (122) and the external substrate (220).

[0175] On the other hand, the second post bump (170D) may not be electrically connected to the external substrate (220). In addition, even if the second post bump (170D) is connected to the wiring layer (122), power may not be applied.

[0176] According to the second circuit board (102) and the second semiconductor package (202) according to the embodiment, by providing the second post bump (170D) which is a dummy post bump, the etching amount of the seed layer in each area of ​​the circuit board can be made uniform, and thereby each post bump can have a uniform height.

[0177] In addition, according to the second circuit board (102) and the second semiconductor package (202) according to the embodiment, the heat dissipation characteristics can be improved through the dummy post bump by providing the second post bump (170D) which is a dummy post bump.

[0178]

[0179] Next, FIG. 7 is a cross-sectional view of a third circuit board (103) according to an embodiment, and FIGS. 8a and 8b are cross-sectional views of a manufacturing process of the third circuit board (103) according to an embodiment.

[0180] The third circuit board (103) according to the embodiment can adopt the technical features of the first circuit board (101) and the second circuit board (102) according to the embodiment described above, and the main features of the third circuit board (103) will be described below.

[0181] First, referring to FIG. 7, the third circuit board (103) according to the embodiment includes a build-up insulator (110), a build-up wiring body (120), and a protective layer (140).

[0182] The build-up insulator (110) includes a single or multiple insulating layers laminated in a vertical direction and provides insulating properties between the build-up wiring bodies.

[0183] The build-up wiring body (120) includes a wiring layer (122) arranged on the surface of each insulating layer constituting the build-up insulator (110) and a via electrode (121) for vertically connecting each wiring layer (122). The via electrode (121) may be referred to as a through electrode, a via, or a via portion.

[0184] The wiring layer (122) can perform the function of transmitting signals and / or power to semiconductor devices placed on a circuit board and the impedance matching function. The wiring layer (122) can be referred to as a wiring pattern layer, a metal wiring, or a wiring section.

[0185] The wiring layer (122) includes a first wiring layer (122a) arranged on a build-up insulator (110) and a second wiring layer (122b) arranged under the build-up insulator (110).

[0186] The third circuit board (103) includes a second post bump (172) disposed on the first pad (122a1) of the first wiring layer (122a). The second post bump (172) may be provided to have the horizontal width described above in consideration of securing the integrity of signal and / or power transmission, mechanical rigidity, and stress with the build-up structure.

[0187] The embodiment includes a protective layer (140) disposed on the uppermost or lowermost build-up wiring body (120). For example, the protective layer (140) includes a first protective layer (141) disposed on a first wiring layer (122a) and a second protective layer (142) disposed on a second wiring layer (122b).

[0188]

[0189] The second post bump (172) of the third circuit board (103) includes a first metal layer (170S) and a second post metal layer (170P2). For example, the second post bump (172) includes, but is not limited to, a first metal layer (170S) which is a seed metal layer disposed on the first pad (122a1) and a second post metal layer (170P2) which is a post metal layer disposed on the first metal layer (170S).

[0190] The first metal layer (170S) may not be disposed on the second pad (122a2) among the wiring layers. For example, the seed metal layer may not be disposed on the second pad (122a2).

[0191] Similar to the characteristics of the first circuit board (100) above, the third circuit board (103) also includes a recess (122R1) on the upper surface of the first pad (122a1) along the outer periphery of the second post metal layer (170P2). For example, the upper surface of the first pad (122a1) may include a recess (122R1) having a curved surface along the outer periphery of the second post metal layer (170P2). In addition, the second post metal layer (170P2) may not vertically overlap with the recess (122R1) of the first pad (122a1).

[0192] Additionally, the recess (122R1) of the first pad (122a1) may be positioned lower than the second post metal layer (170P2). Accordingly, the second post metal layer (170P2) may not horizontally overlap with the recess (122R1) of the first pad (122a1).

[0193] Additionally, the recess (122R1) of the first pad (122a1) may be positioned lower than the first metal layer (170S). Accordingly, the first metal layer (170S) may not horizontally overlap with the recess (122R1) of the first pad (122a1). The thickness of the second post metal layer (170P2) may be thicker than the thickness of the first protective layer (141).

[0194] Additionally, the first metal layer (170S) may have a side surface (SR2) having a curved surface. For example, a portion of the side surface of the first metal layer (170S) may be removed by wet etching, thereby including a curved side surface (SR2) having a curvature in the thickness direction. A lower end of the curved side surface (SR2) of the first metal layer (170S) may be in contact with one end of the recess (122R1) of the first pad (122a1).

[0195] According to an embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, even if solder flow occurs, more solder is retained in the space of the recess (122R1) of the curved surface of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0196] In addition, according to the embodiment, since the first metal layer (170S) has a curved side surface (SR2), even if solder flow occurs, more solder is retained in the space of the curved side surface (SR2) of the first metal layer (170S) and the curved recess (122R1) of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0197] Continuing with reference to FIG. 7, the first thickness (T1) of the second post bump (172) may be thicker than the second thickness (T2) of the first metal layer (170S). In addition, the first thickness (T1) of the second post bump (172) may be thicker than the third thickness (T3) of the first protective layer (141). The third thickness (T3) of the first protective layer (141) may be thicker than the second thickness (T2) of the first metal layer (170S).

[0198] For example, the first thickness (T1) of the second post bump (172) may be about 20 to 30 μm, but is not limited thereto. In addition, for example, the second thickness (T2) of the first metal layer (170S) may be about 5 to 10 μm, but is not limited thereto. In addition, for example, the third thickness (T3) of the first protective layer (141) may be about 15 to 20 μm, but is not limited thereto.

[0199]

[0200] According to an embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), the solder volume for mounting the chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0201] In addition, according to the embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), a space of about 5 to 30 μm for mounting the chip on the circuit board can be secured, and accordingly, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package. In addition, by forming the thick post bump (172), heat generated in the semiconductor package can be more efficiently dispersed, and higher performance can be achieved by using a more integrated chip.

[0202] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, the first metal layer (170S), which is a seed layer, is removed except for the area of ​​the first pad (122a1), and is not placed on the trace (122a3) or the second pad (122a2), thereby preventing electrical short circuits between wiring patterns.

[0203] Additionally, at least a portion of the first protective layer (141) may be placed on the recess (122R1) of the first pad (122a1). Accordingly, the bonding area between the build-up insulator (110) and the first protective layer (141) may be increased, thereby improving adhesion.

[0204]

[0205] Hereinafter, a method for manufacturing a third circuit board (103) according to an embodiment will be described using FIGS. 8a and 8b.

[0206] First, as shown in Fig. 8a, a build-up wiring body (120) is formed on a build-up insulator (110).

[0207] The build-up insulator (110) includes a single or multiple laminated insulating layers and provides insulating properties between the build-up wiring bodies. The build-up wiring body (120) includes a wiring layer (122) arranged on the surface of each insulating layer of the build-up insulator (110) and a via electrode (121) for vertically connecting each wiring layer (122).

[0208] The wiring layer (122) includes a first pad (122a1) and a second pad (122a2). The first pad (122a1) and the second pad (122a2) are provided singly or in multiples and can function as connection pads. The wiring layer (122) also includes a trace (122a3).

[0209]

[0210] Next, a second post bump (172) is formed on the pad of the first wiring layer (122a).

[0211] In an embodiment, a post-bump pre-layer (not shown) may be disposed on a build-up insulator (110) and a build-up wiring body (120). The post-bump pre-layer includes a first pre-metal layer (170S1) and a second pre-metal layer (not shown). The first pre-metal layer (170S1) may be a seed layer, and the second pre-metal layer may be an electroplated layer, but is not limited thereto. For example, the first pre-metal layer (170S1) may be a chemical copper plating layer. Alternatively, the first pre-metal layer (170S1) may be a copper foil layer, but is not limited thereto. The second pre-metal layer may be an electroplated layer containing copper, but is not limited thereto.

[0212] The first thickness (T1) of the second preliminary metal layer may be thicker than the second thickness (T2) of the first preliminary metal layer (170S1). For example, the first thickness (T1) of the second preliminary metal layer may be about 20 to 30 μm, but is not limited thereto. In addition, for example, the second thickness (T2) of the first preliminary metal layer (170S1) may be about 5 to 10 μm, but is not limited thereto.

[0213] The order in which the post-bump pre-layer is formed may be formed before the formation of the build-up insulator (110) and the build-up wiring body (120). For example, the build-up wiring body (120) and the build-up insulator (110) may be formed on the post-bump pre-layer, but the process order is not limited thereto.

[0214] Next, a second etching pattern (302) such as a dry film is formed on the post bump pre-layer, and the second pre-metal layer is etched using the second etching pattern (302) as a mask to form a second post metal layer (170P2).

[0215] The mask thickness (Tp) of the second etching pattern (302) may correspond to the first thickness (T1) of the second preliminary metal layer and may be thicker than the second thickness (T2) of the first preliminary metal layer (170S1).

[0216] For example, the mask thickness (Tp) of the second etching pattern (302) may be about 20 to 30 μm, but is not limited thereto.

[0217]

[0218] Next, as shown in FIG. 8b, the second etching pattern (302) is removed, and the first preliminary metal layer (170S1) is partially etched to form the first metal layer (170S). For example, the first preliminary metal layer (170S1) may be partially etched using wet etching. Through this, a second post bump (172) including the first metal layer (170S) and the second post metal layer (170P2) is formed.

[0219] Thereafter, a protective layer (140) is formed on the uppermost or lowermost build-up wiring body (120). For example, the protective layer (140) includes a first protective layer (141) disposed on the first wiring layer (122a) and a second protective layer (142) disposed on the second wiring layer (122b).

[0220] The first thickness (T1) of the second post bump (172) may be thicker than the second thickness (T2) of the first metal layer (170S). In addition, the first thickness (T1) of the second post bump (172) may be thicker than the third thickness (T3) of the first protective layer (141). The third thickness (T3) of the first protective layer (141) may be thicker than the second thickness (T2) of the first metal layer (170S).

[0221] For example, the first thickness (T1) of the second post bump (172) may be about 20 to 30 μm, but is not limited thereto. In addition, for example, the second thickness (T2) of the first metal layer (170S) may be about 5 to 10 μm, but is not limited thereto. In addition, for example, the third thickness (T3) of the first protective layer (141) may be about 15 to 20 μm, but is not limited thereto.

[0222]

[0223] According to an embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), the solder volume for mounting the chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0224] In addition, according to the embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), a space of about 5 to 30 μm for mounting the chip on the circuit board can be secured, and accordingly, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package. In addition, by forming the thick post bump (172), heat generated in the semiconductor package can be more efficiently dispersed, and higher performance can be achieved by using a more integrated chip.

[0225] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface (see FIG. 2), even if solder flow occurs, more solder is retained in the space of the recess (122R1) of the curved surface of the first pad (122a1), thereby preventing solder flow to an adjacent wiring pattern, thereby further improving the electrical reliability of the circuit board.

[0226] In addition, according to the embodiment, since the upper surface of the first pad (122a1) has a recess (122R1) having a curved surface, the first metal layer (170S), which is a seed layer, is removed except for the area of ​​the first pad (122a1), and is not placed on the trace (122a3) or the second pad (122a2), thereby preventing electrical short circuits between wiring patterns.

[0227] Additionally, at least a portion of the first protective layer (141) may be placed on the recess (122R1) of the first pad (122a1). Accordingly, the bonding area between the build-up insulator (110) and the first protective layer (141) may be increased, thereby improving adhesion.

[0228]

[0229] Next, Fig. 9 is a cross-sectional view of a third semiconductor package (203) according to an embodiment.

[0230] The third semiconductor package (203) of the embodiment may include the third circuit board (103) of FIG. 7.

[0231] Referring to FIG. 9, a third semiconductor package (203) according to an embodiment includes a first connection portion (211) disposed on a second pad (122a2) of a third circuit board (103), and may also include a first chip (210) or a first element (210) disposed on the first connection portion (211).

[0232] Specifically, the first connection portion (211) is positioned on the second pad (122a2) that vertically overlaps the opening of the first protective layer (241). The first connection portion (211) may be a solder ball, but is not limited thereto.

[0233] A third semiconductor package (203) according to an embodiment may include a first chip (210) or element (210) disposed on a first connection portion (211). The first chip (210) may be a processor chip. For example, the first chip (210) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0234] At this time, the lower surface of the first chip (210) may include a terminal (not shown), and the terminal may be electrically connected to the second pad (122a2) of the circuit board through the first connection portion (211).

[0235] Meanwhile, the third semiconductor package (203) of the embodiment may include a plurality of chips arranged and spaced apart from each other in the horizontal direction on a single circuit board. For example, the first chip (210) may include a first chip and a second chip that are spaced apart from each other. In addition, the first chip and the second chip may be different types of application processor (AP) chips.

[0236]

[0237] In addition, the third semiconductor package (203) of the embodiment may include a second connection portion (212). The second connection portion (212) may be disposed on a lower surface of the second wiring layer (122b). For example, the second wiring layer (122b) includes at least one pad. And, the pad of the second wiring layer (122b) may vertically overlap with an opening of the second protective layer (142). And, the second connection portion (212) may be disposed under the pad of the second wiring layer (122b) that vertically overlaps with the opening of the second protective layer (142). The second connection portion (212) may be a solder ball, but is not limited thereto. The second connection portion (212) may be for connecting the semiconductor package and a main board (or motherboard) of an external device.

[0238]

[0239] Additionally, the third semiconductor package (203) according to the embodiment further includes an external substrate (220). The external substrate (220) may be an interposer, but is not limited thereto.

[0240] The external substrate (220) includes a plurality of insulating layers (not shown). The external substrate (220) includes a circuit layer disposed on the plurality of insulating layers. The external substrate (220) may be a substrate connecting a semiconductor package on which an AP chip is disposed and a semiconductor package on which a memory chip is disposed. To this end, the circuit layer of the external substrate (220) may be designed to correspond to the terminal specifications of the AP chip and the terminal specifications of the memory chip. Specifically, the width or pitch of the circuit layer of the circuit board on which the AP chip is disposed may be different from the width or pitch of the circuit layer of the circuit board on which the memory chip is disposed. Accordingly, the external substrate (220) may be disposed between a plurality of circuit boards having the same difference in width or pitch as described above to electrically connect them therebetween.

[0241] The external substrate (220) may be placed on the second post bump (172) of the third circuit substrate (103). In addition, the third semiconductor package (203) further includes a third connecting portion (213). For example, the third connecting portion (213) may be placed on the second post bump (172). The uppermost portion of the second post bump (172) may be positioned higher than the upper end of the first chip (210). Through this, the embodiment can prevent the first chip (210) from being damaged when coupled with the external substrate (220).

[0242] Additionally, the third semiconductor package (203) may include a first molding layer (251). The first molding layer (251) may mold the first connection portion (211), the first chip (210), the third connection portion (213), and the external substrate (220). Meanwhile, although not shown in FIG. 4, a memory substrate (not shown) may be placed on the external substrate (220).

[0243]

[0244] According to a semiconductor package including a circuit board according to an embodiment, electrical reliability can be improved.

[0245] For example, according to an embodiment, by forming the second post bump (172) on the first pad (122a1) to be at least twice as thick as the first protective layer (141), the solder volume for mounting the chip can be reduced. For example, according to an embodiment, the first volume (V1) of the third connection portion (213) disposed on the second post bump (172) formed to be thick can be smaller than the second volume (V2) of the first connection portion (211) disposed on the second pad (122a2).

[0246] Accordingly, a short circuit due to a solder bridge can be prevented due to the reduced solder volume of the third connection portion (213) on the second post bump (172) formed thickly, thereby improving electrical reliability, and a finer bump pitch design is possible due to the reduced risk of an electrical short, thereby providing a high-performance semiconductor package.

[0247]

[0248] In addition, according to the embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), a space for mounting the chip on the circuit board can be secured by about 5 to 30 ㎛ more, and the first separation distance (W1) between adjacent second post bumps (172) can be secured to be smaller than the second separation distance (W2) of the adjacent first connecting portion (211), thereby enabling a finer bump pitch design, thereby providing a high-performance semiconductor package. In addition, by forming thick post bumps (172), heat generated in the semiconductor package can be more efficiently dispersed, and higher performance can be achieved by using more integrated chips.

[0249]

[0250] Next, FIG. 10 is a cross-sectional view of a fourth semiconductor package (204) according to an embodiment.

[0251] The fourth semiconductor package (204) of the embodiment can adopt the technical features of the third semiconductor package (203), and the following description will focus on the features of the fourth semiconductor package (24).

[0252] Referring to FIG. 10, a fourth semiconductor package (204) according to an embodiment includes a first connection portion (211) disposed on a second pad (122a2) of a third circuit board (103), and may also include a first chip (210) or a first element (210) disposed on the first connection portion (211). The first connection portion (211) may be a solder ball, but is not limited thereto.

[0253] A fourth semiconductor package (204) according to an embodiment may include a first chip (210) or element (210) disposed on a first connection portion (211). The first chip (210) may be a processor chip.

[0254] Additionally, the fourth semiconductor package (204) according to the embodiment further includes an external substrate (220). The external substrate (220) may be an interposer, but is not limited thereto.

[0255] The external substrate (220) may be placed on the second post bump (172) of the third circuit substrate (103).

[0256] At this time, the fourth semiconductor package (203) further includes a fourth connecting portion (213CB).

[0257] For example, the fourth connecting portion (213CB) may be disposed on the second post bump (172). As illustrated in FIG. 10, the fourth connecting portion (213CB) may include a ball-shaped connecting portion core (213CB1) and a connecting portion adhesive member (213CB2) disposed to surround the outer circumferential surface of the connecting portion core (213CB1). In this case, the connecting portion core (213CB1) may be a copper core, and the connecting portion adhesive member (213CB2) may be solder, and thus, the fourth connecting portion (213CB) may be a copper ball (Cu ball).

[0258] The uppermost portion of the second post bump (172) may be positioned higher than the upper portion of the first chip (210). Through this, the embodiment can prevent the first chip (210) from being damaged when bonded to the external substrate (220). In addition, the fourth semiconductor package (204) may include a first molding layer (251).

[0259]

[0260] According to a semiconductor package including a circuit board according to an embodiment, electrical reliability can be improved.

[0261] For example, according to the fourth semiconductor package (204) according to the embodiment, the solder volume for mounting the chip can be reduced by forming the second post bump (172) on the first pad (122a1) to be at least twice as thick as the first protective layer (141).

[0262] For example, according to an embodiment, the first volume (V1) of the fourth connecting portion (213CB) disposed on the second post bump (172) formed thickly may be smaller than the second volume (V2) of the first connecting portion (211) disposed on the second pad (122a2).

[0263] Accordingly, the fourth connection portion (213CB) on the second post bump (172) formed thickly can prevent a short circuit due to a solder bridge due to a reduced solder volume, thereby improving electrical reliability, and a finer bump pitch design is possible due to a reduced risk of an electrical short circuit, thereby providing a high-performance semiconductor package.

[0264]

[0265] In addition, according to the embodiment, by forming the second post bump (172) on the first pad (122a1) to be more than twice as thick as the first protective layer (141), a space for mounting the chip on the circuit board can be secured by about 5 to 30 ㎛ more, and the first separation distance (W1) between adjacent second post bumps (172) can be secured to be smaller than the second separation distance (W2) of the adjacent first connecting portion (211), thereby enabling a finer bump pitch design, thereby providing a high-performance semiconductor package. In addition, by forming thick post bumps (172), heat generated in the semiconductor package can be more efficiently dispersed, and higher performance can be achieved by using more integrated chips.

[0266] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0267] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0268] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0269] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Build-up insulator with single or multiple insulating layers laminated; A wiring layer disposed on the above build-up insulator and having a plurality of pads; A post bump disposed on a first pad located on a first region of the build-up insulating layer among the plurality of pads; A circuit board, wherein a portion of the upper surface of the first pad includes a recess around the outer perimeter of the post bump, wherein the recess of the first pad does not horizontally overlap with the post bump.

2. In paragraph 1, The above post bump is, A first metal layer disposed on the first pad; and A second metal layer disposed on the first metal layer; A circuit board, wherein the first metal layer includes a seed metal layer.

3. In paragraph 2, A circuit board, wherein the second metal layer does not vertically overlap with the recess of the first pad.

4. In paragraph 2, A circuit board, wherein the recess of the first pad is positioned lower than the second metal layer.

5. In paragraph 2, A circuit board, wherein the recess of the first pad is positioned lower than the first metal layer.

6. In paragraph 2, A circuit board, wherein the first metal layer does not horizontally overlap with the recess of the first pad.

7. In paragraph 2, A circuit board, wherein the first metal layer has a side surface having a curved surface.

8. In paragraph 2, The above wiring layer Further comprising a second pad positioned on the second region of the build-up insulating layer among the plurality of pads; The second pad is a circuit board that does not include a seed metal layer.

9. In paragraph 1, The above post bump is, A circuit board comprising a first post bump to which power is applied and a second post bump to which power is not applied.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

Images