Devices and methods involving a diffusion-dopant profile in semiconductor devices

Abstract

In certain specific examples, methods and semiconductor structures are directed to a semiconductor device developed based on a two-step annealing process. In the first step, diffusion doping is used to apply (which may include, e.g., depositing a doped layer) a dopant towards a target region of a wafer or a transistor-device layer by effecting an early anneal while a thin layer of dopant-inclusive material is formed on, or spun onto, the target region. This may be implemented to provide a diffusion-doped dopant profile into the target region that is characterized in terms of flatness and depth. The second step involves providing a later anneal, while the target region is exposed to an ambient gas, to alter the dopant profile by increasing flatness and depth aspects of dopant profile.

Description

DEVICES AND METHODS INVOLVING A DIFFUSION- DOPANT PROFILE IN SEMICONDUCTOR DEVICESBACKGROUND[0901 Aspects of the present disclosure are related generally to the field of manufacturing of power-type semiconductor devices, and as may be exemplified by uses in connection with power transistors such as a Gallium Oxide power transistor (e.g., Ga2O? MOSFETs and the like), and also in connection with optical elements and diodes (e.g., as may be used for high-voltage applications such as EV charging and solid-state transformers in power grids).

[0002] Using this type of power transistor as an exemplary technology type for ease of discussion, it has been appreciated that GajO^ power transistor research has experienced a huge boom in the past decade thanks to many advantages in material properties. This includes a high critical field of 8 MV / cm, resulting in a very comparative PFoM in the wide-bandgap semiconductor family, various low-cost high-quality substrate wafer production techniques, and a wide bandgap of 4.8 eV, suitable for many extreme environmental applications.Progress has thus far been made toward high-voltage and high-performance Ga^Ch devices by utilizing different techniques to mitigate parasitic breakdown and recovery7channel mobility7. Notably, these limitations include ultra-high breakdown voltages of 8 kV and 10 kV having been measured within lateral MOSFETs and MESFETs, respectively, as well as in heterojunction diodes, featuring a measured average electric field of 6.2 MV / cm. Attractive PFoM (performance figure of merit) numbers are also reported with various device architectures. These results indicate an immense potential of P-Ga2O3 for high-power devices. However, realizing an averaged breakdown field close to 8 MV / cm in a lateral Ga2Os FET poses an immense challenge due to the extrinsic breakdown of surrounding structures.SUMMARY OF VARIOUS ASPECTS AND EXAMPLES[0003 Various examples / embodiments presented by the present disclosure are directed to issues such as those addressed above and / or others which may become apparent from the following disclosure. For example, some of these disclosed aspects are directed to methods and devices that use or leverage from a diffusion-doping process to customize or generate a particular dopant profile for a current-blocking layer (or region, aka CBL) as may be used to mitigate current leakage in a designated areas of a semiconductor device. As will become apparent, however, not all aspects of the present disclosure are so directed or limited.

[0004] In one specific example, a method involves manufacture of a semiconductor device involving at least a two-step annealing process. In the first step, diffusion doping is used to apply (e.g., by implantation, or physical deposition, as surface doping) a dopant towards a target region of a wafer or a transistor-device layer by effecting an early anneal while a thin layer of dopant-inclusive material is formed on, or spun onto, the target region. This may be implemented to provide a diffusion-doped dopant profile (the dopant profile) into the target region that is characterized in terms of flatness and depth. The second step involves providing a later anneal, while the target region is exposed to an ambient gas (e.g., O2 or a mix of gases including (or predominantly including) O2) to alter the dopant profile by increasing flatness and depth aspects of dopant profile.

[0005] Building on the above example, more specific aspects of the above method may include: removing the thin layer after the step of applying and before the step of providing a later anneal, wherein the early anneal is carried out while the thin layer is present and capable of acting as an effective infinite source of the dopant that corresponds to an infinite-source diffusion step into the target region; and the later anneal being carried out by exposing the target region to the ambient gas (e.g., by varying amounts of the ambient gas within a limited time period to optimize dopant profile in terms of at least one of increased flatness and increased depth) once at least a portion of the thin layer is removed, thereby causing only previously-applied dopant, acting as a constant-source diffusion, to alter the dopant profile.

[0006] In yet further specific examples relating to the above characterized examples: the thin layer may be formed to create a dielectric layer having a smooth, planar surface, and the Mg diffusion profile may be formed to include a concentration of the Mg, as a representative type of dopant, at a level on the order of lxl018 / cm3. Also, the above type of method may further include: the step of removing the thin layer by stripping at least a portion (or all) of the thin layer; a step of patterning, via lithography, the thin layer; cleaning the thin layer viaHydrofluoric Acid; and / or paterning, via lithography, the thin layer and, in response, portions of the thin layer may be etched.

[0007] In yet further related specific examples: the wafer or the transistor-device layer includes a Gallium Oxide (Ga2Os) power transistor and the dopant profile forms at least part of a channel blocking layer adjacent a channel in the Ga2Os power transistor; and / or the step of applying the dopant towards the target region includes a spinning process in which a liquid solution is spun towards the target region to facilitate the thin layer being formed with a uniform layer thickness. Also, the step of applying the dopant into the target region may include a spin-on-glass (SOG) process, and the earlier anneal includes curing at a temperature greater than 350 degrees C.

[0008] Also as options to build on such methodology, the above type of later anneal process may involve or include exposing the target region to oxygen and facilitating a formation of the dopant profile that is more of a box-like shape with sharp comers, than a bathtub shape with obtuse comers: exposing, via a rapid thermal annealing process, the target region to drive the dopant into the target region at a temperature greater than 1000 degrees C; an oxygen over-pressure or higher temperature anneal to increase a concentration of the dopant in the dopant profile; and / or with the later anneal process resulting in a concentration of a p-type dopant arranged as a cunent blocking layer (CBL) in a Vertical Diffused Barrier Field-Effect-Transistor (VDBFET), thereby creating a barrier between source and drain contacts of the VDBFET to effective isolation therebetween when the transistor is not actively conducting.

[0009] In certain other examples which may also build on the above-discussed aspects, methods and apparatuses (e.g., semiconductor and / or optical device or component, wafer, partially-manufacture device, etc.) are directed to manufacturing a semiconductor device (and such a device) having a dopant along a surface of a target region, that is part of a wafer or a transistor-device layer. The method comprises: processing the dopant along the surface of the target region by providing an anneal, while the surface of the target region is exposed to an ambient gas, to alter or create a dopant profile that is characterized by flatness and depth aspects of the dopant profile.[00101 In certain specific examples, the present disclosure is directed to a partially- or completely -fabricated semiconductor device that includes a wafer, or transistor-device layer having a target region with a diffusion-doped dopant profile (the dopant profile) that is characterized in terms of flatness and depth, wherein the target region has: a fabrication- processed surface adj acent to the dopant profile target region and facing away from a deepestportion of the dopant profile, and which has molecular traces of an ambient gas proximal the fabrication-processed surface. In more specific examples according to the present disclosure, the above-characterized semiconductor device further includes: a Vertical Diffused Barrier Field-Effect-Transistor (VDBFET) within the wafer, or transistor-device layer, wherein the ambient gas includes oxygen, and the dopant profile is further characterized by a concentration of Mg, at a level on the order of lxlO18 / cm3, and configured as a p-type doping layer to block current between source and drain contacts of the VDBFET when the transistor is not actively conducting.[UOi 1 ] The above discussion is not intended to describe each aspect, embodiment or every implementation of the present disclosure. The figures and detailed description that follow also exemplify various embodiments.BRIEF DESCRIPTION OF FIGURES

[0012] Van ous example embodiments, including experimental examples, may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, each in accordance with the present disclosure, in which:

[0013] FIG. 1 A is a flow diagram illustrating a process of manufacturing a portion of a semiconductor device, according to certain exemplary aspects of the present disclosure;

[0014] FIG. 1 B is a flow diagram illustrating structural changes of the portion of semiconductor device of FIG. 1A, according to certain exemplary aspects of the present disclosure;

[0015] FIG. 1C is a diagram of a semiconductor-device, in the form of a diode, fabricated in accordance with certain exemplary aspects of the present disclosure;

[0016] FIG. 2 is another flow diagram illustrating, via a more specific set of steps used in an experimental embodiment, an example process of manufacturing a portion of a semiconductor device, according to certain exemplary aspects of the present disclosure;

[0017] FIGs. 3A, 3B, 3C and 3D are graphs showing simulated concentration and depth characteristics between semiconductor-device samples manufactured in different ways, including according to certain exemplary aspects of the present disclosure;

[0018] FIG. 4 is a graph showing simulated concentration and depth characteristics of a portion of three semiconductor-device samples manufactured according to certain exemplary- aspects of the present disclosure;

[0019] FIGs. 5A, 5B and 5C are depictions of semiconductor-device samples manufactured according to certain exemplary aspects of the present disclosure; and{0020 ] FIG. 5D is a set of graphed plots showing simulated characteristics of semiconductor-device samples, according to certain exemplary aspects of the present disclosure.

[0021] While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation.DETAILED DESCRIPTION

[0022] Aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems and methods involving devices characterized at least in part by annealing near a target region (e.g., in a vertically-arranged transistor or PN junction), while the surface of the target region is exposed to an ambient gas, to alter or create a dopant profile that is characterized by a dopant profile having certain flatness and depth aspects. While the present disclosure is not necessarily limited to such aspects, an understanding of specific examples in the following description may be understood from discussion in such specific contexts.

[0023] Accordingly, in the following description various specific details are set forth to describe specific examples presented herein. It should be apparent to one skilled in the art, however, that one or more other examples and / or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same connotation and / or reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination.

[0024] Exemplary aspects of the present disclosure are related to a semiconductor device manufactured via a method involving use of a dopant along a surface of a target region (e.g., as part of a wafer, PN junction or a transistor-device layer). The method includes processingthe dopant along the surface of the target region by providing an anneal, while the surface of the target region is exposed to an ambient gas, to alter or create a dopant profile that is characterized by flatness and depth aspects of the dopant profile.

[0025] The lower block of FIG. 1A shows this above-characterized step as defining such a diffusion dopant profile by annealing a target region, which has a dopant along a surface of the target region, thereby driving the dopant into a semiconductor material as appropriate to define the diffusion dopant profile. By using the step depicted in the lower block of FIG. 1 A, a device manufactured in accordance therewith manifests one more certain structural aspects. As one example, to expose at least a portion of the doped (e.g., SOG-type) surface region to the ambient gas, an etching process may be used and, consequently, the etched portion is apparent after the etching step. In another example, the process step of doping, such as by using a high temperature and / or ambient gas as discussed in connection with FIG. IB, such a deep dopant profile (e g., with sharp comers) is readily apparent after being formed.

[0026] In a more specific example, the present disclosure is directed to a related two-step process which involves formation of the dopant along the above-mentioned surface of such a target region. In this example, the first step includes applying, via diffusion doping, a dopant towards a target region of a wafer or a transistor-device layer by effecting an early anneal while a thin layer of dopant-inclusive material is formed on, or spun onto, the target region, thereby providing a diffusion-doped dopant profile (the dopant profile) into the target region that is characterized in terms of flatness and depth. The second step includes providing a later anneal, while the target region is exposed to an ambient gas, to alter the dopant profile by increasing flatness and depth aspects of the dopant profile. The two lower blocks of FIG. 1A describe this two-step process for defining such a diffusion dopant profile, with the first step involving a first anneal process to create a target region having a dopant along a surface portion, and a second anneal, which as above, drives the dopant into a semiconductor material to define and / or optimize the diffusion dopant profile.

[0027] In such a two-step process, the second anneal may involve a much greater temperature than the temperature of the first anneal, and may also involve use of the above- mentioned ambient gas for optimization purposes. Also, as is applicable to each of the above examples, the ambient gas is chosen based on various factors such as the desired characterization of the dopant profile and the related degrees of its flatness and depth into the target region. As such, non-limiting examples of the type of ambient gas for use in this regard may be: Ch (Oxygen), which has been found to be highly-advantageous in variousexperimental example embodiments; H (Hydrogen), another type of gas, and combinations of two or more such gases.

[0028] FIG. IB is a structural flow diagram, corresponding to step of the lower block of FIG. 1 A and to more-specific aspects of the present disclosure, showing at the left side a side view of a partially-fabricated semiconductor device having a doped surface region (e.g., as deposited and / or formed via an initial doping step) with one or more dopants to be diffused into the (substrate) material shown beneath the doped surface region. By using a relatively high temperature (e.g., 700° C - 1000° C or 900° C - 1250° C) and exposure of at least a portion of the doped surface region to an ambient gas. the resultant semiconductor-device structure is shown to the right of FIG. IB, w ith the substrate material have a deep diffusion dopant profile (e.g., characterized as being formed as having more of a box-like shape wdth sharp comers, than a bathtub shape with obtuse comers). In examples involving an earlier step of applying the dopant into the target region, this may be achieved by a spin-on-glass (SOG) process to provide a uniform surface region and with the initial (or earlier) anneal including curing at a temperature greater than 350 degrees C, and in other examples in a range from 300° C - 500° C.

[0029] In certain specific examples, such methodology according to the present disclosure is directed to a partially- or completely -fabricated semiconductor device that includes a wafer, or transistor-device layer having a target region with a diffusion-doped dopant profile (the dopant profile) that is characterized in terms of flatness and depth, wherein the target region has: a fabrication-processed surface adjacent to the dopant profile target region and facing away from a deepest portion of the dopant profile, and which has molecular traces of an ambient gas proximal the fabrication-processed surface. In more specific examples according to the present disclosure, the above-characterized semiconductor device further includes: a Vertical Diffused Barrier Field-Effect-Transistor (VDBFET) w ithin the wafer, or transistor-device layer, wherein the ambient gas includes oxygen, the dopant profile is further characterized by a concentration of Mg (as a representative type of dopant) at a level on the order of lxl018 / cm3, configured as a p-type doping layer to block current between source and drain contacts of the VDBFET when the transistor is not actively conducting. Depending on the specific application and type of device layer material (or substrate), in other examples the dopant material(s) has a certain polarity and / or may include one or more of the following types of dopants: Mg, Zn, Fe, Ca, Cd, Na, Li, Be, Si and Sn.

[0030] As another example of a semiconductor device manufactured according to one of more of the above aspects of the present disclosure, FIG. 1 C illustrates a side-view diagramPN junction arranged as part of a diode. The diode has an anode arranged as part of an upper layer and a cathode as part of a lower layer or portion of a Ga2Ch-based substrate. As depicted above the cathode, the substrate includes, a drift layer as part of a semiconductor device layer or semiconductor wafer (e.g., halide-vapor-phase-epitaxy (HVPE) grown wafer). Above the drift layer is a layer similar to the doped region shown to the right side of FIG. IB, in this example with the dopant being Mg, which may be implemented using the second step of FIG. 1A.[0031 j Consistent with the above aspects, such a manufactured device or method of such manufacture may involve aspects presented and claimed in U.S. Provisional Application Serial No. 63 / 617,349 filed on January' 3, 2024 (STFD.462P1 / S23-506) with Appendices A- C, to which priority is claimed. To the extent permitted, such subject matter is incorporated by reference in its entirety generally and to the extent that further aspects and examples (such as experimental and / more-detailed embodiments) may be useful to supplement and / or clarify.

[0032] FIG. 2 shows another flow diagram, consistent with the type of methodology described above in connection with FIGs. 1 A and IB and also according to aspects of the present disclosure, illustrating a more specific set of steps used in an experimental example embodiment for fabrication of a portion of a semiconductor device. This example, similar to FIG. 1C, uses a Ga2O3-based substrate as indicated at the start depicted by block 210. At block 215 and using Mg as the dopant, a surface region of the substrate is coated using an SOG (spin on glass) process which provides for a smooth, evenly distributed and uniform thin layer as a covering layer over the surface. At block 220, the Mg-SOG is cured at a temperature somewhat greater than 350° C (e.g., less than -400° C or -500° C), and this curing can occur over a time which may vary depending on the profile design requirements. If the entire surface is to be coated (aka “blanket doping”), flow proceeds from block 220 to block 230. If, however, less than all the surface is to be coated, flow proceeds from block 220 to block 225, where the cured Mg-SOG layer may be patterned via lithography and etching, so as to expose one or more portions of the surface to be etched. Next, at block 230, a furnace (and / or rapid thermal) anneal is carried out in N2 at a relatively-high temperature such as above 800° C (or, for example, a temperature between -650° C and -950° C). Flow then proceeds from block 230 to block 235, where the Mg-SOG layer is stripped (e.g., by etching) and typically cleaned. At block 240, another anneal (e.g.. furnace and / or rapid thermal) is earned out in the presence of an ambient gas (e.g., O2) to drive the diffusion deeper into the substrate. Block 245 depicts the fabricated Ga2Os-based substrate, with Mg as the dopant inwell-defined diffusion profile being used in one or more designate applications (e.g., PN diode, super-junction, JFET, VMOS, etc.).

[0033] Proof-of-concept example experimentation, according to the present disclosure, was implemented to assess the methodology discussed above in connection with FIGs. 1A- 1B and FIG. 2. This experimentation showed the diffusion dope results of Mg via SIMS on two types of (LGazOs wafers under different conditions, with the conditions chosen to showcase the importance of each parameter in comparison experiments for such process flow, for example, as shown in FIG. 2. The experimentation was carried out in parallel on a halide-vapor-phase-epitaxy (HVPE) grown epitaxial wafer with a 10 pm drift layer of 2xl 016 / cm3Si doping, and an EFG melt-grown substrate with a 6xl018 / cm3Sn doping (both obtained from a third party ).( 0034] The process used, is as follows. Samples are first coated with the Mg-doped SOG with a Mg concentration of more than 4x 1021 / cm3. The SOG is cured on a hotplate at 350 °C for 10 minutes to drive out the solvent afterward. The sample is then annealed in a furnace at 950 or 1000 °C in N2 for 1 hour. This is the first diffusion anneal step - ‘pre-deposition’, to inject a large amount of Mg into the surface region of the wafer. The annealed SOG layer is then stripped clean with HF. SIMS results are obtained from samples at this stage, which is equivalent to the CBL profile achieved in the first demonstration of VDBEFT (see, e.g., K. Zeng et al., “Vertical Ga 2 O 3 MOSFET With Magnesium Diffused Current Blocking Layer,” IEEE Electron Device Lett., vol. 43, no. 9, pp. 1527-1530, Sep. 2022, doi:10. 1109 / LED.2022.3196035). A second diffusion anneal, as a drive-in step, is performed at a temperature of 1100° C (or in a range from 900° C to 12000C) in an oxygen (O2) ambient with a high gas flow rate at atmosphere pressure (or over-pressure in some instances). For all the samples used for the experiments, after the process flow, their surface was maintained in a pristine condition that is, for all practical / functional purposes, indistinguishable from a new wafer. Therefore, device fabrication following the two-step diffusion doping process can be carried out uninterrupted without any adverse complications regarding surface roughness or degradation.

[0035] For the p-body layer or CBL doping in a vertical power transistor, a density of > 1 x lO18 / cm3may be preferred for certain implementations in which it is desired that such diffusion doping increases the Mg concentration at least 10 times from the 1 x 1017 / cm3result reported in the above-noted IEEE article (“Vertical Ga 2 O 3 MOSFET With Magnesium Diffused Current Blocking Layer”). In the first step furnace annealing, and traditionalapproaches such as increasing the temperature and duration were tested on the HVPE wafer. The substrate wafer was also used to study the effect of different background n-type doping, surface orientation, and grow th techniques on the Mg diffusion. For each of the samples processed using a single-step anneal methodology and annealed at 1000 °C (as opposed to that discussed in connection with FIGs. 1A and FIG. 2 of the present disclosure), the highly doped (>1 xl017 / cm3) region did not penetrate beyond the 100 nm sample surface region for the HVPE samples, and the doping density remained around 1 xl017 / cm3level for the deeper CBL region (> 200 nm depth). This profile is identical to the one reported in the above-noted IEEE article, which has a one-step annealing at 950°C and with the plotted graph of the Mg diffusion dopant profile being formed to have a bathtub shape with obtuse comers, rather than more of a box-like shape with sharp comers which may be desirable for implementing the dopant area as a buffer or current blocking layer (CBL). These results indicate that the increase of annealing temperature to 1000 °C in the first step does not increase the Mg concentration. Furthermore, by increasing the 1000 °C anneal time to 10 hours, compared to a 1-hour anneal, the experimentation led to the further discovery that such increased anneal time does not affect the Mg concentration in the HVPE wafer as well. Overall, one-step annealing with Mg-SOG is not effective in increasing the Mg concentration. In addition, the experimentation indicates that the H closely mirrors the Mg profile, especially where Mg and H moved deeper together in the substrate wafer. This indicates the existence of the Mg-H complex in Ga2Os similar to what was previously observed in GaN structures. Consequently, the experimentation indicates that the lower-than-expected Mg that was injected into the wafers during the first step is not at all activated because of the more favorable bonding formed between Mg and H. In this context, Mg-H complex refers to a molecular structure in which a magnesium (Mg) atom is bonded to a hydrogen (H) atom, often occurring in the fabrication of gallium-based semiconductor materials where the magnesium acts as a dopant and can be readily passivated by hydrogen, thereby forming a neutral complex that limits the electrical conductivity7of the material (e.g., with the hydrogen essentially binding to the magnesium and preventing it from contributing free charge carriers).

[0036] FIGs. 3A, 3B, 3C and 3D are graphs showing simulated concentration and depth characteristics between semiconductor-device samples manufactured in different ways, including samples fabricated according to certain exemplary aspects of the present disclosure. Such aspects include driving a dopant into the w afer or substrate, such as Mg into a Ga2O? wafer or substrate, and disassociating Mg-H complexes. In a specific implementationconsistent with some of the graphs shown in FIGs. 3A-3D, a two-step anneal is utilized where the second anneal step is performed without Mg-SOG for a constant source diffusion, and oxygen is used during a second step anneal to realize the increase of Mg doping and extraction of H simultaneously from the wafer or substrate.

[0037] More specifically, FIGs. 3A-3D are used to illustrate a comparison of SIMS measurement results of Mg and H, with the naming of samples pertaining to the sample type, wherein ‘HVPE’ stands for HVPE wafer(s) and ‘SUB’ represents substrate wafer(s), followed by the number of diffusion steps and the duration of the last step, ambient gas is denoted last (e.g., HVPE lSlh’ refers to HVPE wafer fabricated with 1 (diffusion) Step occurring for 1 hour). FIG. 3 A show a comparison between sample ‘SUB_lS lh’ and ‘SUB_2Slh_O2’, which compares one step diffusion result with two step oxygen diffusion result on the substrate wafer. The resultant plots of FIG. 3 A show that the second oxygen annealing has induced a noticeable increase of Mg in the substrate wafer from ~1 xl017 / cm3to 6><1017 / cm3. With FIG. 3B showing the first 300 nm surface detail of FIG. 3A, the detailed graph in FIG. 3B shows that the H has retracted towards the surface while Mg concentration was increased, effectively disassociating the Mg-H complexes in the wafer during the second step of oxygen annealing.

[0038] The same phenomenon can be observed on HVPE wafers as well, as shown in FIG. 3C, where the Mg concentration is even higher at l x l018 / cm3, achieving a lOx increase via oxygen annealing and a clear separation between Mg and H traces. This can be seen from the FIG. 3C comparison between sample ‘HVPE lSlh' and ‘HVPE_2Slh_O2’, which compares one step diffusion result with two step oxygen diffusion result on the HVPE wafer. Unlike an implanted or a traditional diffused profile, the Mg traces in both FIG. 3A and FIG. 3C featured a strikingly perfect box shape, with an almost flat profile (constant concentration) across the entire CBL region and a steep drop-off around 0.8 pm depth.[003$)] With such a box-like profile, it is shown in Fig. 3D that the presence of oxygen can be important to the increase of Mg. This is apparent from FIG. 3D which shows a comparison between sample ‘HVPE_2Slh_N2’ and ‘HVPE_2Slh_O2’, which compares two step nitrogen diffusion result with two step oxygen diffusion result on the HVPE wafer. 0040] Utilizing the same sample naming, FIG. 4 is a graph showing simulated concentration and depth characteristics of a portion of such semiconductor-device samples, with SIMS measurement results of diffused Mg for HVPE_2S0.5h_O2’, ‘HVPE_2S lh_O2’, and ‘HVPE_2S2h_O2’ samples, which are two-step oxygen diffusion samples with durations of 0.5 hour, 1 hour and 2 hours during the second step. The upper plot, with concentration ofIO18cm'3between 10’1microns and 10° microns, corresponds to the sample ‘HVPE_2Slh_O2’. The middle plot, with similar concentration starting at about 10'1microns, corresponds to the sample ‘HVPE_2S2h_O2’. The lower plot, with concentration closer to 1017cm'3between 10'1microns and 10° microns, corresponds to the sampleHVPE 2Slh 02’.

[0041] If the ambient gas is replaced with nitrogen in the second annealing while keeping all other conditions the same, no increase in the Mg concentration is observed. Although the detailed quantitative mechanism governing the exact amount of diffused Mg via oxygen annealing may depend on other factors not considered in such experimentation, the Mg diffusion is likely enhanced due to the generation of gallium vacancy with the presence of oxygen during the high temperature anneal in the second step. Therefore, an oxygen overpressure or higher temperature anneal may be used, in certain implementations according to the present disclosure, to further increase the Mg concentration. With the significantly increased Mg concentration demonstrated as such via a two-step oxygen annealing, the blocking capability of the Mg diffused CBL can be enhanced in the VDBFET.

[0042] Accordingly, the above-discussed Mg diffusion experimentation, certain exemplary aspects of the present disclosure establish an effective method to drive the Mg into Ga2Os and disassociate the Mg-H complexes.

[0043] FIGs. 5 A, 5B and 5C are side-view depictions of specific arrangements of such dopant diffusion profiles created in semiconductor-device samples, referred to as Vertical Diffused Barrier Field-Effect-Transistor (VDBFET) structures, fabricated according to certain exemplary aspects of the present disclosure. FIG. 5A shows an earlier, partially- fabricated version of the VDBFET structure, with the Mg-doped SOG layer on an upper surface of a Ga2Ch-based substrate, after being processed to include a Si-doped drift layer and, above the drift layer, an Mg-diffused region similar to the doped region shown in FIG. 1C. In this example, Mg-type dopant has been implemented, as the second step of FIG.1 A, using the Mg-driving step (e.g., at an angle of 7° (or from 5° - 10°) from vertical as visualized in FIGs. 5A-5C). FIG. 5B shows a later version of the VDBFET structure, with the Mg-doped SOG layer on the upper surface having been removed (e.g., via etching) and with Si regions having been implanted in upper portions of the Mg-diffused region. FIG. 5C shows a subsequent version of the VDBFET structure with source / drain and gate electrodes, and an AI2O3 (insulating / passivation) layer, over the Si-doped drift layer. In a top-down view (not shown), the gate electrode of the VDBFET structure includes an elongate section separating the source / drain electrodes of the VDBFET structure.{0044] FIG. 5D is a set of graphed plots showing simulated characteristics of such semiconductor-device samples, according to certain exemplary aspects of the present disclosure, with Mg-type dopant processed via a later anneal to result in a desirable dopant diffusion profile, having more of a sharp-comer shape, for a concentration of a p-type dopant arranged as a current blocking layer (CBL) in the VDBFET. The CBL is used to create a barrier between source and drain contacts of the VDBFET to effect isolation therebetween when the transistor is not actively conducting.

[0045] In experimentation efforts related to the above-discussed efforts, in order to increase the concentration of Mg in single crystal and epitaxial Ga2O3 solely via diffusion doping technique, different variations of diffusion methods have been explored. Consistent with the methodology discussed in connection with FIGs. 1 A and 2, one such example methodology includes using a two-step finite source diffusion as a significant improvement over a one-step infinite source diffusion (e.g., similar to that disclosed in the above-cited IEEE article), with the two-step diffusion shown to be effective in increasing the Mg concentration in Ga2O3 by nearly 10 times. Furthermore, it was observed that the ambient gas used in the second step diffusion can play an important role in Mg diffusion for certain specific dopant diffusion profile characterizations.

[0046] In one such experimental effort, the SIMS result is compared between a sample with second-step diffusion in oxygen and another sample in a nitrogen ambient while keeping all other conditions identical. The presence of oxygen gas in the second step annealing is shown to be important to the increase of Mg concentration and the disassociation of the Mg- H complex. Also, the reverse blocking IV characteristics of the example diodes, as fabricated using the later anneal step, with the Mg-diffused current blocking layers were measured and observed to have significantly increased from -500 V to more than 1 kV with the achieved Mg diffusion concentration profiles. The two-step oxygen-assisted Mg diffusion doping technique has been shown to be a powerful doping tool that opens up new avenues for the realization of various high-power Ga2O3 electron devices.

[0047] It is recognized and appreciated that as specific examples, the abovecharacterized figures and discussion are provided to help illustrate certain aspects (and advantages in some instances) which may be used in the manufacture of such structures and devices. These structures and devices include the exemplary structures and devices described in connection with each of the figures as well as other devices, as each such described embodiment has one or more related aspects which may be modified and / or combined withthe other such devices and examples as described hereinabove may also be found in the Appendices of the above-referenced Provisional.

[0048] The skilled artisan would also recognize various terminology' as used in the present disclosure by way of their plain meaning. As examples, the Specification may describe and / or illustrates aspects useful for implementing the examples by way of various semiconductor materials / circuits which may be illustrated as or using terms such as layers, blocks, modules, device, system, unit, controller, and / or other circuit-ty pe depictions. Also, in connection with such descriptions, the term “source” may refer to source and / or drain interchangeably in the case of a transistor structure. Such semiconductor and / or semiconductive materials (including portions of semiconductor structure) and circuit elements and / or related circuitry may be used together with other elements to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It would also be appreciated that terms to exemplify orientation, such as upper / lower, left / right, top / bottom and above / below, may be used herein to refer to relative positions of elements as shown in the figures. Such aspects, materials and / or related circuitry may be used together with other aspects to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It should be understood that the terminology is used for notational convenience only and that in actual use the disclosed structures may be oriented and / or ordered different from the orientation or ordering shown in the figures. Thus, the terms should not be construed in a limiting manner.

[0049] Based upon the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, methods as exemplified in the Figures may involve steps carried out in various orders, with one or more aspects of the embodiments herein retained, or may involve fewer or more steps. Such modifications do not depart from the true spirit and scope of various aspects of the disclosure, including aspects set forth in the claims.

Claims

What is Claimed:

1. A method comprising: applying, via diffusion doping, a dopant towards a target region of a wafer or a transistor-device layer by effecting an early anneal while a thin layer of dopant-inclusive material is formed on, or spun onto, the target region, thereby providing a diffusion-doped dopant profile (the dopant profile) into the target region that is characterized in terms of flatness and depth; and providing a later anneal, while the target region is exposed to an ambient gas. to alter the dopant profile by increasing flatness and depth aspects of dopant profile.

2. The method of claim 1, further including removing the thin layer after the step of applying and before the step of providing a later anneal, wherein the early anneal is carried out while the thin layer is present and capable of acting as an effective infinite source of the dopant that corresponds to an infinite-source diffusion step into the target region.

3. The method of claim 1, wherein the later anneal is carried out by exposing the target region to the ambient gas once at least a portion of the thin layer is removed, thereby causing only previously-applied dopant, acting as a constant-source diffusion, to alter the dopant profile.

4. The method of claim 1, wherein the later anneal is cooperatively carried out by exposing the target region to varying amounts of the ambient gas within a limited time period to optimize dopant profile in terms of at least one of increased flatness and increased depth.

5. The method of claim 1, wherein the thin layer is formed to create a dielectric layer having a smooth, planar surface, and the Mg diffusion profile includes a concentration of the Mg, as the dopant, at a level on the order of lxl018 / cm3.

6. The method of claim 1, wherein the step of applying the dopant towards the target region includes a spinning process in which a liquid solution is spun towards the target region to facilitate the thin layer being formed with a uniform layer thickness.

7. The method of claim 1, wherein the step of applying the dopant into the target region includes a spin-on-glass (SOG) process, and the earlier anneal includes curing at a temperature greater than 350 degrees C.

8. The method of claim 1, further including the step of removing the thin layer by stripping at least a portion of the thin layer.

9. The method of claim 1, wherein the later anneal includes exposing, via a rapid thermal annealing process, the target region to drive the dopant into the target region at a temperature greater than or equal to 1000 degrees C.

10. The method of claim 1, further including a step of patterning, via lithography, the thin layer.1 1. The method of claim 1, further including steps of: patterning, via lithography, the thin layer and, in response, etching portions of the thin layer.

12. The method of claim 1, further including cleaning, via Hydrofluoric Acid, the thin layer.

13. The method of claim 1, wherein the wafer or the transistor-device layer includes a Gallium Oxide (Ga2Os) power transistor and the dopant profile forms at least part of a channel blocking layer adjacent a channel in the Ga2Os power transistor.

14. The method of claim 1, wherein the later anneal includes exposing the target region to oxygen and facilitating a formation of the dopant profile that is more of a box-like shape with sharp comers, than a bathtub shape with obtuse comers.

15. The method of claim 1, wherein the later anneal includes an oxygen over-pressure or higher temperature anneal to increase a concentration of the dopant in the dopant profile.

16. The method of claim 1, wherein the later anneal results in a concentration of a p-type dopant arranged as a current blocking layer (CBL) in a Vertical Diffused Barrier Field- Effect-Transistor (VDBFET), thereby creating a barrier between source and drain contacts ofthe VDBFET to effective isolation therebetween when the VDBFET is not actively conducting.

17. For use in manufacturing a semiconductor device having a dopant along a surface of a target region, that is part of a wafer or a transistor-device layer, a method comprising: processing the dopant along the surface of the target region by providing an anneal, while the surface of the target region is exposed to an ambient gas, to alter or create a dopant profile that is characterized by flatness and depth aspects of the dopant profile.

18. The method claim 17, wherein the dopant: has a certain polarity and includes one or more from among: Mg, Zn, Fe, Ca, Cd, Na, Li, Be, Si and Sn; and is formed to create a current blocking layer (CBL) in a Vertical Diffused Barrier Field-Effect-Transistor (VDBFET), thereby creating a barrier between source and drain contacts of the VDBFET to effective isolation therebetween when the transistor is not actively conducting.

19. A semiconductor device comprising: a wafer, or transistor-device layer having a target region with a diffusion-doped dopant profile (the dopant profile) that is characterized in terms of flatness and depth; the target region having a fabrication-processed surface adjacent to the dopant profile target region and facing away from a deepest portion of the dopant profile; and molecular traces of an ambient gas in the target region proximal the fabrication- processed surface.

20. The semiconductor device of claim 19, further including: a Vertical Diffused Barrier Field-Effect-Transistor (VDBFET) within the wafer, or transistor-device layer, wherein the ambient gas includes oxygen, the dopant profile is further characterized by a concentration of Mg, at a level on the order of lxl018 / cm3, and configured as a p-type doping layer to block current between source and drain contacts of the VDBFET when the transistor is not actively conducting.

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