Dynamic random-access memory array based on tunnel field-effect transistors and control method therefor

Abstract

A dynamic random-access memory array based on tunnel field-effect transistors and a control method therefor. The dynamic random-access memory array is formed by repeatedly arranging storage units in horizontal and vertical directions. Storage units in a same row share a write word line and a read word line, and storage units in a same column share a write bit line and a read bit line. The storage units each comprise a P-type tunnel field-effect transistor as a write transistor, an N-type tunnel field-effect transistor as a read transistor, and a capacitor as an amplification unit. The write transistor, the read transistor, and the capacitor are connected to each other to form a storage node (SN). The write transistor has a gate connected to a write word line, a drain connected to a write bit line, and a source connected to the storage node. The read transistor has a gate connected to the storage node, a drain connected to a read bit line, and a source connected to ground. One end of the capacitor is connected to the storage node and the other end is connected to a read word line.

Description

A dynamic random access memory array based on tunneling field effect transistor and its control method Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a dynamic random access memory array based on a tunneling field effect transistor and a control method thereof. Background Art

[0002] The development of artificial intelligence Internet of Things (AIoT) technology has put forward higher requirements for semiconductor memory. Devices at the edge and node ends of AIoT both require low-power, low-cost, and relatively large-scale memory.

[0003] However, among traditional volatile memories, static random access memory (SRAM) has high hardware cost and static power consumption, while dynamic random access memory (DRAM) has short retention time and high refresh power consumption. Therefore, it is of great significance to invent a volatile memory with low hardware cost and low power consumption. Summary of the Invention

[0004] To address the problems existing in the prior art, the present invention provides a dynamic random access memory array based on tunneling field-effect transistors and a control method thereof. In terms of dynamic random access memory, the present invention can extend the retention time of the dynamic random access memory, reduce the refresh frequency and refresh power consumption; reduce the leakage of the readout bit line in the dynamic random access memory, alleviate the read crosstalk problem, and increase the storage window and array size.

[0005] The technical solutions of the present invention are as follows:

[0006] A dynamic random access memory array based on tunneling field-effect transistors is characterized in that it is composed of memory cells repeatedly arranged in the horizontal and vertical directions, with the memory cells in the same row sharing a write word line WWL and a read word line RWL, and the memory cells in the same column sharing a write bit line WBL and a read bit line RBL.

[0007] The storage unit includes a P-type tunneling field-effect transistor as a write tube, an N-type tunneling field-effect transistor as a read tube, and a capacitor as an amplification unit. The write tube, the read tube and the capacitor are interconnected to form a storage node SN, wherein the gate electrode of the write tube is connected to the write word line WWL, the drain electrode of the write tube is connected to the write bit line WBL, the source electrode of the write tube is connected to the storage node SN, the gate electrode of the read tube is connected to the storage node SN, the drain electrode of the read tube is connected to the read bit line RBL, and the source electrode of the read tube is connected to 0V. The capacitor device as the amplification unit has one end connected to the storage node SN and the other end connected to the read word line RWL.

[0008] The P / N-type tunneling field-effect transistor has a source end comprising a source metal layer and a source semiconductor layer wrapping the source metal layer. The source end of the tunneling field-effect transistor is physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, and has a bidirectional conduction characteristic. The drain end is at a certain distance from the gate boundary, which can suppress the bipolar current of the transistor and reduce the off-state current.

[0009] Furthermore, when the capacitor device as the amplification unit is selected as the gate capacitance of a gate-controlled diode composed of a MOSFET device with source and drain connected, the gate of the MOSFET device is connected to the storage node SN, the source and drain electrodes of the MOSFET device are connected to the read word line RWL, and the substrate electrode of the MOSFET device is separately led out as the electrode CON for regulating the capacitance size.

[0010] Furthermore, the capacitor device used as the amplifying unit is a capacitor with a high dielectric constant, or a capacitor provided in a mature silicon-based CMOS process: a MOM capacitor, a MIM capacitor or a PIP capacitor.

[0011] Furthermore, the peak doping concentration of the source semiconductor layer of the P / N type tunneling field effect transistor is 1e20 cm -3 and above,

[0012] The width of the source semiconductor layer is 5 nm or more wider than the width of the source metal layer in the lateral direction, and the thickness of the source semiconductor layer is 5 nm or more thicker than the thickness of the source metal layer in the longitudinal direction.

[0013] Furthermore, the drain end of the P / N-type tunneling field effect transistor is between 10 nm and 100 nm away from the gate.

[0014] The present invention also provides a method for controlling the tunneling field effect transistor-based dynamic random access memory array, characterized in that it includes four steps: maintaining, writing 1, writing 0, and reading, as follows:

[0015] In the hold state, that is, when there is no write 1, write 0, or read operation, in the dynamic random access memory array, all write word line WWL voltages, write bit line WBL voltages, read word line RWL voltages, and read bit line RBL voltages are 0V; if there is an electrode CON for regulating the capacitance, a constant voltage V is applied to CON. B , and the voltage of CON remains unchanged during the reading and writing processes; in the dynamic random access memory array, if the information stored in a certain storage cell is "0", then the voltage of the corresponding storage node SN is 0V; if the information stored in a certain storage cell is "1", then the voltage of the corresponding storage node SN is V0.

[0016] The steps of selecting a memory cell in the dynamic random access memory array to write 0 are as follows: applying a voltage V1 to the write word line WWL of the selected memory cell, applying a voltage 0V to the write bit line WBL of the selected memory cell, and keeping the voltages of the remaining write word lines WWL, the remaining write bit lines WBL, the read word line RWL, and the read bit line RBL unchanged; at this time, the write transistor in the selected memory cell is turned on, and the voltage 0V is transmitted from the write bit line WBL to the storage node SN; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL of the selected memory cell are both restored to 0V.

[0017] The steps of selecting a memory cell in the dynamic random access memory array to write 1 are as follows: applying voltage V1 to the write word line WWL of the selected memory cell, applying voltage V0 to the write bit line WBL of the selected memory cell, and keeping the voltages of the remaining write word lines WWL, the remaining write bit lines WBL, the read word line RWL, and the read bit line RBL unchanged; at this time, the write transistor in the selected memory cell is turned on, and the voltage V0 is transmitted from the write bit line WBL to the storage node SN; after the writing is completed, the voltages of the write word line WWL and the write bit line WBL of the selected memory cell are both restored to 0V.

[0018] The steps of selecting a memory cell in the dynamic random access memory array for reading are as follows: precharging the voltage of the read bit line RBL of the selected memory cell to a voltage of V2, then placing the RBL in a floating state, applying a voltage of V2 to the write word line WWL of the selected memory cell, applying a voltage of V2 to the read word line RWL of the selected memory cell, and keeping the voltages of the remaining write word lines WWL, the remaining read bit lines RBL, the remaining read word lines RWL, and the write bit line WBL unchanged; at this time, if the information stored in the memory cell is "0", then the read bit line RBL is precharged to a voltage of V2. The output tube current is small, and the read bit line RBL voltage is V3, which becomes V2 after being amplified by the sensitive amplifier. If the information stored in the storage cell is "1", the output tube current is large, and the read bit line RBL voltage drops to V4, which becomes 0V after being amplified by the sensitive amplifier. After the reading is completed, the voltages of all read bit lines RBL are changed to V2, and then the voltages of all write word lines WWL and all read word lines RWL are restored to 0V, and finally the voltages of all read bit lines RBL are restored to 0V. Before and after the reading operation, the voltage of the storage node SN remains unchanged.

[0019] Furthermore, the voltage V0 is between 0V and 2V, which is approximately equal to the turn-on voltage of the readout tube, the voltage V1 is between 0V and -5V, the voltage V2 is between 0V and 5V, the voltage V3 is between 0V and V2, and the voltage V4 is between 0V and V3. The voltage V4 is 200mV or more lower than the voltage V3.

[0020] The present invention discloses a dynamic random access memory array based on a tunneling field effect transistor and a control method thereof. In terms of dynamic random access memory, the present invention can extend the retention time of the dynamic random access memory, reduce the refresh frequency and refresh power consumption; and can also reduce the leakage of the readout bit line in the dynamic random access memory, alleviate the read crosstalk problem, and increase the storage window and array size. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic equivalent circuit diagram of a memory cell according to the present invention, wherein:

[0022] (1) is a schematic equivalent circuit diagram when the amplification unit is the gate capacitance of a MOSFET device;

[0023] (2) A schematic equivalent circuit diagram when the amplification unit is a capacitor and a high dielectric constant capacitor provided in a mature CMOS process;

[0024] In the figure: 1 - write tube; 2 - read tube; 3 - amplifier unit.

[0025] FIG2 is a schematic structural diagram of a tunneling field-effect transistor constituting a memory cell proposed in the present invention;

[0026] In the figure: 04 — gate; 05 — source metal layer; 06 — source semiconductor layer; 07 — drain; 08 — substrate.

[0027] FIG3 is a cross-sectional view of an embodiment of an integrated circuit after fabrication provided by a unit circuit according to the present invention;

[0028] In the figure: 4 — high-resistance silicon substrate; 5 — shallow trench isolation; 6 — upper isolation well; 7 — lower isolation well; 8 — gate dielectric layer; 9 — gate conductive layer of N-type device; 10 — gate conductive layer of P-type device; 11 — compensation isolation layer; 12 — composite main isolation layer; 13 — N+SD region; 14 — P+SD region; 15 — N+ extension region; 16 — P+ extension region; 17 — self-aligned silicide; 18 — inter-contact dielectric layer; 19 — contact hole; 20 — WBL metal interconnect; 21 — WWL metal interconnect; 22 — SN metal interconnect; 23 — RBL metal interconnect; 24 — GND metal interconnect; 25 — inter-metal dielectric layer; 26 — capacitor bottom plate; 27 — capacitor dielectric layer; 28 — capacitor top plate; 29 — metal interconnect via; 30 — RWL metal interconnect.

[0029] FIG. 4 is a schematic diagram of an equivalent circuit embodiment provided by the array structure proposed in the present invention.

[0030] FIG. 5 is a voltage waveform diagram when performing read and write operations on memory cells in an array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] An exemplary embodiment of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the purpose of disclosing the examples is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the examples, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

[0032] FIG1 is a schematic equivalent circuit diagram of a memory cell constituting a dynamic random access memory array proposed by the present invention. The figure shows the connection relationship between the various parts of the proposed memory cell. The write transistor 1 is a P-type tunneling field effect transistor, the gate electrode of the write transistor 1 is connected to the write word line WWL, the drain electrode of the write transistor 1 is connected to the write bit line WBL, and the source electrode of the write transistor 1 is connected to the storage node SN. The read transistor 2 is an N-type tunneling field effect transistor, the gate electrode of the read transistor 2 is connected to the storage node SN, the drain electrode of the read transistor 2 is connected to the read bit line RBL, and the source electrode of the read transistor 2 is connected to 0V. The amplification unit 3 in FIG1 (1) is the gate capacitor of the MOSFET, the gate of the MOSFET is connected to the storage node SN as one end of the capacitor, the source and drain of the MOSFET are connected together as the other end of the capacitor to the read word line RWL, and the substrate electrode of the MOSFET is separately led out as the electrode CON for adjusting the size of the capacitor. The amplification unit 3 in FIG1 (2) is a capacitor provided in a mature silicon-based CMOS process: a MOM capacitor, a MIM capacitor or a PIP capacitor, or a high dielectric constant capacitor, one end of the capacitor is connected to the storage node SN, and the other end of the capacitor is connected to the read word line RWL.

[0033] The tunneling field effect transistor in Figure 1 should meet the following conditions: the P-type tunneling field effect transistor used as a write transistor needs to suppress bipolar current and have an off-state current lower than the off-state current of a silicon-based CMOS device at the same process node, and also needs to have bidirectional conduction characteristics within the required read and write voltage range. The N-type tunneling field effect transistor used as a readout transistor needs to suppress bipolar current and have an off-state current lower than the off-state current of a silicon-based CMOS device at the same process node, and also needs to have a large turn-on voltage so that the turn-on voltage is approximately equal to the storage node voltage V corresponding to "1". SNSince the tunneling field effect transistors reported in existing literature cannot meet the above requirements, the present invention proposes a specific structural description of the tunneling field effect transistor that meets the above requirements. Figure 2 shows the device structure that meets this description. The source end of the tunneling field effect transistor shown in Figure 2 consists of a source metal layer 05 and a source semiconductor layer 06 that wraps the source metal layer 05, and the doping concentration of the source semiconductor layer 06 is as high as 1e20cm -3， The width of source semiconductor layer 06 is 10 nm or greater laterally wider than the width of source metal layer 05, and the thickness of source semiconductor layer 06 is 10 nm or greater vertically thicker than the thickness of source metal layer 05, thereby preventing source semiconductor layer 06 from being completely depleted. The boundary between source metal layer 05 and source semiconductor layer 06 is located near the boundary of gate 04 of the tunneling field-effect transistor, making the source terminal of the tunneling field-effect transistor physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, achieving bidirectional conduction characteristics, and the turn-on voltage can be adjusted by varying the distance between the boundary of gate 04 and the boundaries between gates 05 and 06. The drain terminal 07 of the tunneling field-effect transistor is spaced a distance from gate 04, thereby suppressing bipolar current and ensuring that its off-state current is lower than that of silicon-based CMOS devices of the same process node.

[0034] Figure 3 shows a cross-sectional view of the memory cell in Figure 1 during actual integrated circuit fabrication. The figure illustrates an alternative tunneling field-effect transistor (TFET) structure. Based on existing technologies and the memory structure design requirements proposed in this invention, the TFET can be replaced with other structures. The TFET shown in Figure 3 is a planar device structure fabricated on a high-resistance silicon substrate 4, with the devices isolated by shallow trench isolation 5. A gate dielectric layer 8 and gate conductive layers 9 and 10 form the device's gate region. The side of the gate sidewall with only the compensation isolation layer 11 corresponds to the device's source terminal, while the side of the gate sidewall with the compensation isolation layer 11 and composite main isolation layer 12 corresponds to the device's drain terminal. Self-aligned silicide 17, SD regions 13 and 14, and extension regions 15 and 16 form the device's source and drain terminals. The substrate region of each device includes an upper isolation well 6 and a lower isolation well 7, which isolate leakage current from the same-doping type source and drain regions of adjacent devices through the substrate. The source, gate, and drain electrodes of the device are respectively connected through contact holes 19 and metal interconnects 20, 21, 22, 23, and 24. The device on the left is a P-type tunneling field-effect transistor, which is a write transistor. The gate conductive layer 10 of the P-type device is the gate conductive layer of the device and is connected through the WWL metal interconnect. The N+ SD region 13, the N+ extension region 15, and the self-aligned silicide 17 form the source end of the write transistor, which is connected to the gate electrode of the read transistor and one end of the amplifier unit through the SN metal interconnect 22. The P+ SD region 14, the P+ extension region 16, and the self-aligned silicide 17 form the drain end of the write transistor and is connected through the WBL metal interconnect 20. The device on the right is an N-type tunneling field-effect transistor, which is a read transistor. The gate conductive layer 9 of the N-type device is the gate conductive layer of the device and is connected to the source electrode of the write transistor and one end of the amplifier unit through the SN metal interconnect. The N+ SD region 13, the N+ extension region 15 and the self-aligned silicide 17 form the drain end of the readout tube, which is led out through the RBL metal interconnection line 23. The P+ SD region 14, the P+ extension region 16 and the self-aligned silicide 17 form the source end of the readout tube, which is led out through the GND metal interconnection line 24. MOSFET gate capacitance, MOM capacitance, MIM capacitance and PIP capacitance are all capacitors that can be provided in mature CMOS processes, and a cross-sectional view is not shown here. What is shown here is the case where the amplification unit 3 is a high dielectric constant capacitor. The capacitor is composed of a capacitor bottom plate 26, a capacitor dielectric layer 27 and a capacitor top plate 28, and is located between the metal interconnections of adjacent layers. It will not affect the parameters and performance of the back-end interconnection lines corresponding to the CMOS device. The capacitor dielectric layer is a high dielectric constant dielectric material.

[0035] The proposed memory cells are arranged in a regular and repetitive manner. The schematic equivalent circuit diagram of the memory cells is taken as an example in Figure 1 (2). The schematic equivalent circuit diagram of the dynamic random access memory array structure proposed by the present invention can be obtained as shown in Figure 4. The memory cells in the same row share a write word line WWL, from WWL0 to WWL m , a total of m+1 rows of write word lines WWL. The memory cells in the same row share a read word line RWL, from RWL0 to RWL m , a total of m+1 rows of read word lines RWL. The memory cells in the same column share a write bit line WBL, from WBL0 to WBL n , there are n+1 columns of write bit lines WBL. The memory cells in the same column share a read bit line RBL, from RBL0 to RBL n , a total of n+1 columns of write bit lines RBL.

[0036] For the array structure shown in Figure 4, the proposed method can be used to write and read data from selected memory cells. Figure 5 shows an example of the read and write voltage waveforms. When writing data, the write word line (WWL) voltage for the row containing the selected cell is lowered from 0V to -2.5V, while the WWL voltages for the remaining rows remain at 0V. The write bit line (WBL) voltage corresponding to the memory cell in the selected row to which a "0" is to be written is 0V, while the write bit line (WBL) voltage corresponding to the memory cell to which a "1" is to be written is raised from 0V to 0.5V. After writing is completed, all WWL voltages and WBL voltages return to 0V. The SN node voltage corresponding to the memory cell written with "0" is 0V, and the SN node voltage corresponding to the memory cell written with "1" is 0.5V. When reading information, the write word line WWL voltage of the row where the selected cell is located is pulled up from 0V to 2.5V, and the read bit line RBL voltage corresponding to the memory cells in this row is all precharged to 2.5V, and then RBL is floated. The read word line RWL voltage of the row where the selected cell is located is pulled up from 0V to 2.5V. Due to the voltage coupling effect of the amplification unit, the SN node voltage rises, and the SN node voltage corresponding to the cell storing information "1" is higher than the storage bit line RBL voltage. The SN node voltage corresponding to the cell storing "0" is increased. Therefore, the readout transistor corresponding to the cell storing "1" discharges the RBL faster, resulting in a lower RBL voltage. After passing through the sense amplifier, the RBL voltage is pulled down to 0V. The readout transistor corresponding to the cell storing "0" discharges the RBL more slowly, resulting in a higher RBL voltage. After passing through the sense amplifier, the RBL voltage is pulled up to 2.5V. To ensure that the SN node voltage does not change before and after the readout, after the readout is completed, all RBL voltages are raised to 2.5V, and then all RWL and WWL voltages are restored to 0V. Finally, all RBL voltages are restored to 0V, returning to the hold state.

[0037] Unlike the symmetrical gate capacitance characteristics of MOSFET devices, the tunneling field-effect transistor device of the present invention has an asymmetric gate capacitance characteristic, and its gate-source capacitance is much smaller than the gate-drain capacitance. The source electrode of the tunneling field-effect transistor is connected to the storage node SN. The smaller gate-source capacitance of the tunneling field-effect transistor makes the coupling voltage between the write word line WWL and the storage node SN smaller, which is smaller than the WWL and SN coupling voltage caused when the MOSFET device of the same process node and the same gate area is used as the write transistor. Therefore, using the tunneling field-effect transistor as the write transistor will not deteriorate the write speed and retention time of the memory due to the coupling voltage between WWL and SN. Furthermore, when the tunneling field-effect transistor is in the off state, the tunneling window is closed, which has the advantage of low off-state current. Silicon-based tunneling field-effect transistors have been experimentally proven to have lower off-state current than silicon-based CMOS devices of the same process node. In the memory cell structure proposed by the present invention, in the hold state, only the leakage path from the storage node SN to the write bit line WBL causes the SN node voltage to drop. Using a tunneling field-effect transistor as the write tube, the low off-state current advantage of the tunneling field-effect transistor makes the leakage current from SN to WBL lower, thereby obtaining a longer retention time than when a MOSFET device is used as the write tube, thereby reducing the refresh frequency and refresh power consumption.

[0038] If the readout tube is a MOSFET, due to the low threshold voltage of the MOSFET, when the information stored in the storage cell is "1", the corresponding readout tube is in the open state in the hold state. Regardless of whether the cell is selected or not, the corresponding readout tube will charge and discharge the readout bit line RBL, thereby deteriorating the readout speed and storage window. Moreover, the more cells with "1" stored in the same column of unselected cells, the more serious the negative impact.

[0039] In the circuit structure proposed by the present invention, a tunneling field-effect transistor device serves as a readout transistor. In the hold state, if the information stored in the cell structure is "1," the readout transistor gate voltage is V0, approximately equal to the readout transistor's turn-on voltage, meaning the readout transistor is not turned on. If the information stored in the cell structure is "0," the readout transistor gate voltage is 0V, and the readout transistor is also not turned on. To read the information stored in a particular cell structure, a voltage V2 is applied to RWL. This, coupled by the capacitor acting as an amplifier, raises the SN voltage, thereby turning on the readout transistor and discharging RBL. At this point, the readout transistors of unselected cell structures in the same column are not turned on, and RBL is not charged or discharged. Therefore, the memory cell array proposed by the present invention can reduce read bit line leakage in dynamic random access memory. Only the readout transistors of selected cells in the same column discharge RBL, thereby alleviating read crosstalk and increasing the storage window and array size.

[0040] Although the present invention has been disclosed above with reference to preferred embodiments, this is not intended to limit the present invention. Any person skilled in the art can, without departing from the scope of the present invention, utilize the methods and technical content disclosed above to make many possible changes and modifications to the present invention, or modify the present invention into equivalent embodiments with equivalent variations. Therefore, any simple modifications, equivalent variations, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A dynamic random access memory array based on a tunneling field effect transistor, characterized in that, It is formed by repeating the arrangement of storage cells horizontally and vertically. The storage cells in the same row share a write word line WWL and a read word line RWL, and the storage cells in the same column share a write bit line WBL and a read bit line RBL; The storage cell includes a P-type tunneling field effect transistor as a write transistor, an N-type tunneling field effect transistor as a read transistor, and a capacitor as an amplification unit. The write transistor, read transistor, and capacitor are interconnected to jointly form a storage node SN. Among them, the gate electrode of the write transistor is connected to the write word line WWL, the drain electrode of the write transistor is connected to the write bit line WBL, the source electrode of the write transistor is connected to the storage node SN, the gate electrode of the read transistor is connected to the storage node SN, the drain electrode of the read transistor is connected to the read bit line RBL, the source electrode of the read transistor is connected to 0V, and one end of the capacitor device serving as the amplification unit is connected to the storage node SN and the other end is connected to the read word line RWL; For the P / N-type tunneling field effect transistor, its source end includes a source metal layer and a source semiconductor layer wrapping the source metal layer. The source end of this tunneling field effect transistor is physically equivalent to a series structure of a gate-controlled Schottky junction and a gate-controlled PN junction, and has a bidirectional conduction characteristic; its drain end is at a certain distance from the gate boundary, which can suppress the bipolar current of the transistor and reduce the off-state current.

2. The dynamic random access memory array based on a tunneling field effect transistor according to claim 1, wherein When the capacitor device serving as the amplification unit selects the gate capacitance of a gate-controlled diode composed of MOSFET devices with source-drain connected, the gate electrode of this MOSFET device is connected to the storage node SN, the source-drain electrodes of this MOSFET device are connected to the read word line RWL, and the substrate electrode of this MOSFET device is separately led out as an electrode CON for regulating the capacitance size.

3. The dynamic random access memory array based on a tunneling field effect transistor as claimed in claim 1, wherein The capacitor device serving as the amplification unit selects a capacitor with a high dielectric constant, or selects a capacitor provided in the mature silicon-based CMOS process: MOM capacitor, MIM capacitor, or PIP capacitor.

4. The dynamic random access memory array based on a tunneling field effect transistor according to claim 1, characterized in that, The peak doping concentration of the source semiconductor layer of the P / N type tunneling field effect transistor is 1e20 cm -3 or higher, the width of the source semiconductor layer is 5 nm or more wider than that of the source metal layer in the transverse direction, and the thickness of the source semiconductor layer is 5 nm or more thicker than that of the source metal layer in the longitudinal direction.

5. The dynamic random access memory array based on a tunneling field effect transistor according to claim 1, wherein The drain end of the P / N-type tunneling field effect transistor is between 10 nm and 100 nm away from the gate boundary.

6. A method for controlling a dynamic random access memory array based on a tunneling field effect transistor as claimed in claim 1, characterized in that, It includes four steps: hold, write 1, write 0, and read, which are specifically as follows: In the holding state, that is, when there are no write-1, write-0, and read operations, in the dynamic random access memory array, all write word line (WWL) voltages, write bit line (WBL) voltages, read word line (RWL) voltages, and read bit line (RBL) voltages are 0V; if there is an electrode CON for adjusting the capacitance size, a constant voltage V is applied to CON B , and the voltage of CON remains unchanged during the read and write processes; In this dynamic random access memory array, if the information stored in a certain storage cell is "0", then the voltage of the corresponding storage node SN is 0V; if the information stored in a certain storage cell is "1", then the voltage of the corresponding storage node SN is V0; The steps for writing 0 to a selected storage cell in the dynamic random access memory array are: applying a voltage V1 to the write word line WWL of the selected storage cell, applying a voltage 0V to the write bit line WBL of the selected storage cell, and keeping the voltages of the remaining write word lines WWL, the remaining write bit lines WBL, the read word line RWL, and the read bit line RBL unchanged; At this time, the write transistor in the selected storage cell is turned on, and the voltage 0V is transmitted from the write bit line WBL to the storage node SN; After writing is completed, the voltages of the write word line WWL and the write bit line WBL of the selected storage cell both return to 0V; The steps for writing a "1" to a selected memory cell in the dynamic random access memory array are as follows: Apply voltage V1 to the write word line WWL of the selected memory cell, apply voltage V0 to the write bit line WBL of the selected memory cell, and keep the voltages of the remaining write word lines WWL, the remaining write bit lines WBL, the read word line RWL, and the read bit line RBL unchanged; At this time, the write transistor in the selected memory cell is turned on, and voltage V0 is transferred from the write bit line WBL to the storage node SN; After writing is completed, the voltages of the write word line WWL and the write bit line WBL of the selected memory cell are both restored to 0V; The steps for reading a selected memory cell in the dynamic random access memory array are as follows: Pre-charge the voltage of the read bit line RBL of the selected memory cell to voltage V2, then float the RBL, apply voltage V2 to the write word line WWL of the selected memory cell, apply voltage V2 to the read word line RWL of the selected memory cell, and keep the voltages of the remaining write word lines WWL, the remaining read bit lines RBL, the remaining read word lines RWL, and the write bit line WBL unchanged; At this time, if the information stored in the memory cell is "0", then the read transistor current is small, the voltage of the read bit line RBL is V3, and it becomes V2 after being amplified by the sense amplifier. If the information stored in the memory cell is "1", then the read transistor current is large, the voltage of the read bit line RBL drops to V4, and it becomes 0V after being amplified by the sense amplifier; After reading is completed, change the voltages of all read bit lines RBL to V2, then restore the voltages of all write word lines WWL and all read word lines RWL to 0V, and finally restore the voltages of all read bit lines RBL to 0V; Before and after the read operation, the voltage of the storage node SN remains unchanged; The voltage V0 is between 0V and 2V, approximately equal to the turn-on voltage of the read transistor. The voltage V1 is between 0V and -5V. The voltage V2 is between 0V and 5V. The voltage V3 is between 0V and V2. The voltage V4 is between 0V and V3. The voltage V4 is 200mV or more lower than the voltage V3.

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