Data processing device, data processing method, and data processing program

Abstract

A formal verification execution unit (111): performs static analysis of at least one of RTL data and a netlist of a semiconductor integrated circuit that operates on the basis of clock cycles and to which two or more storage elements are connected; extracts, from the two or more storage elements, a storage element in which the shortest time among the times at which signal transition does not occur is equal to or greater than two clock cycles, as a transition pause storage element; and extracts, from the two or more storage elements, a storage element of a connection source of the transition pause storage element, as a connection source storage element. In addition, the formal verification execution unit (111) determines to set a multi-cycle path between the transition pause storage element and the connection source storage element.

Description

Data processing device, data processing method and data processing program

[0001] The present disclosure relates to a technique for setting a multi-cycle path in a semiconductor integrated circuit.

[0002] In a semiconductor integrated circuit, a signal generally transitions between two storage elements in one clock cycle. However, to simplify the layout of the semiconductor integrated circuit, a multi-cycle path may be set in the semiconductor integrated circuit. A multi-cycle path is a path in which a signal transition between two storage elements may occur in two or more clock cycles. Setting a multi-cycle path in a semiconductor integrated circuit makes it easier to design the semiconductor integrated circuit. Furthermore, setting a multi-cycle path in a semiconductor integrated circuit shortens the process time, reduces the circuit size, and reduces power consumption.

[0003] Patent No. 5645754

[0004] The technology of Patent Document 1 aims to detect multi-cycle paths. In the technology of Patent Document 1, logic verification is performed using verification patterns used in RTL (Register Transfer Level) simulation. Furthermore, in the technology of Patent Document 1, signal transitions are discovered by complex operations based on the results of the logic verification, and multi-cycle paths are set.

[0005] The technology of Patent Document 1 requires logic verification using verification patterns. Therefore, the technology of Patent Document 1 has the problem that if there are insufficient verification patterns, sufficient logic verification cannot be performed and multi-cycle paths cannot be accurately set. Furthermore, Patent Document 1 discovers signal transitions through complex operations based on the results of logic verification. Therefore, the technology of Patent Document 1 has the problem of requiring a large workload.

[0006] One of the main objectives of the present disclosure is to solve the above-mentioned problems. More specifically, a main objective of the present disclosure is to enable accurate setting of multi-cycle paths without using verification patterns and without imposing a burden on the designer of a semiconductor integrated circuit.

[0007] The data processing device according to the present disclosure includes an analysis and extraction unit that performs static analysis of at least one of RTL (Register Transfer Level) data and a netlist of a semiconductor integrated circuit that is connected to two or more storage elements and operates based on clock cycles, extracts storage elements from the two or more storage elements in which the shortest time during which no signal transition occurs is two clock cycles or more as transition pause storage elements, and extracts storage elements that are connection sources of the transition pause storage elements from the two or more storage elements as connection source storage elements; and a multi-cycle path determination unit that determines to set a multi-cycle path between the transition pause storage element and the connection source storage element.

[0008] According to the present disclosure, it is possible to accurately set a multi-cycle path without using a verification pattern and without imposing a burden on the designer of a semiconductor integrated circuit.

[0009] 1 is a diagram showing a part of a semiconductor integrated circuit according to a first embodiment. FIG. 2 is a timing waveform diagram corresponding to the circuit structure of FIG. 1. FIG. 3 is a diagram showing an example of a hardware configuration of a multi-cycle path setting device according to the first embodiment. FIG. 4 is a diagram showing an example of a functional configuration of a multi-cycle path setting device according to the first embodiment. FIG. 5 is a flowchart showing an example of an operation of a multi-cycle path setting device according to the first embodiment. FIG. 6 is a diagram showing an example of RTL data according to the first embodiment. FIG. 7 is a diagram showing an example of properties according to the first embodiment. FIG. 8 is a diagram showing an example of multi-cycle path constraints according to the first embodiment. FIG. 9 is a diagram showing an example of a functional configuration of a multi-cycle path setting device according to a second embodiment. FIG. 10 is a diagram showing an example of properties according to the second embodiment. FIG. 11 is a flowchart showing an example of an operation of a multi-cycle path setting device according to the second embodiment. FIG. 12 is a diagram showing a relationship between analysis result information and updated analysis result information according to the second embodiment. FIG. 13 is a diagram showing an example of updated analysis result information according to the second embodiment. FIG. 14 is a diagram showing an example of integrated analysis result information according to the second embodiment. FIG. 15 is a diagram showing an example of multi-cycle path constraints according to the second embodiment. FIG. 16 is a diagram showing an example of a functional configuration of a multi-cycle path setting device according to a third embodiment. FIG. 17 is a flowchart showing an example of an operation of an enable signal generation unit and a clock gating description adding unit according to the third embodiment. 10 is a diagram showing an example of the functional configuration of a multi-cycle path setting device according to a fourth embodiment.

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following description of the embodiments and the drawings, the same reference numerals denote the same or corresponding parts.

[0011] First Embodiment. ***Outline*** An outline of this embodiment will be described. In this embodiment, a multi-cycle path setting device 100 (described later) acquires RTL data or a netlist of a semiconductor integrated circuit. The semiconductor integrated circuit according to this embodiment has two or more memory elements connected thereto and operates based on clock cycles. FIG. 1 shows a portion of the semiconductor integrated circuit according to this embodiment. It is assumed that the circuit structure shown in FIG. 1 is described in RTL data. In FIG. 1, FF1_reg and FF2_reg are connected via a selector. Note that "FF" stands for "flip-flop." The semiconductor integrated circuit may include a RAM (Random Access Memory) instead of or in addition to the FF. In the following, unless otherwise noted, it is assumed that the semiconductor integrated circuit includes only FFs. The FFs and RAM are examples of memory elements. Also, in FIG. 1, Da is an input signal to FF2_reg. Db is an output signal from FF2_reg.

[0012] The multi-cycle path setting device 100 performs static analysis of RTL data or a netlist. As the static analysis, the multi-cycle path setting device 100 verifies specifications using, for example, a formal verification method. Details of the formal verification method will be described later. The multi-cycle path setting device 100 then extracts, as transition pause memory elements, memory elements whose shortest transition pause time is two clock cycles or more. A period in which no signal transition occurs is called a transition pause time. The multi-cycle path setting device 100 also extracts, as source memory elements, memory elements that are the connection source of the transition pause memory elements. In the circuit structure of FIG. 1 , the multi-cycle path setting device 100 extracts, as transition pause FFs, FFs whose shortest transition pause time is two clock cycles or more. The multi-cycle path setting device 100 also extracts, as source FFs, the connection source FFs of the transition pause FFs.

[0013] FIG. 2 is a timing waveform diagram of the circuit structure of FIG. 1. In FIG. 2, "clk" represents a clock signal. "Da" represents a signal transition of the input signal Da. "Db" represents a signal transition of the output signal Db. "En" represents an enable signal. A signal transition occurs from "Da1" to "Da2," "Da2" to "Da3," and "Da3" to "Da4." No signal transition occurs between "Da1," "Da2," "Da3," and "Da4." The same applies to the output signal Db. In the example of FIG. 2, the shortest transition pause time, i.e., the shortest time during which no signal transition occurs, is "Da3." "Da3" corresponds to two clock cycles. Therefore, the multi-cycle path setting device 100 extracts FF2_REG as a transition pause FF. Furthermore, the multi-cycle path setting device 100 extracts FF1_REG, which is the connection source of FF2_REG, as the connection source FF. Next, the multi-cycle path setting device 100 determines to set a multi-cycle path between the transition pause FF and the connection source FF. In the example of FIGS. 1 and 2 , the multi-cycle path setting device 100 determines to set a multi-cycle path corresponding to two clock cycles between FF1_REG and FF2_REG. Furthermore, the multi-cycle path setting device 100 generates a multi-cycle path constraint for setting a multi-cycle path between FF1_REG and FF2_REG. Then, the multi-cycle path setting device 100 adds the multi-cycle path constraint to the timing constraint file. In this manner, the multi-cycle path setting device 100 accurately sets a multi-cycle path in the semiconductor integrated circuit without using a verification pattern and without imposing a burden on the designer.

[0014] ***Description of Configuration*** Next, an example configuration of the multi-cycle path setting device 100 according to this embodiment will be described. Fig. 3 shows an example hardware configuration of the multi-cycle path setting device 100. Fig. 4 shows an example functional configuration of the multi-cycle path setting device 100.

[0015] First, an example of the hardware configuration of the multi-cycle path setting device 100 will be described with reference to Fig. 3. Fig. 3 shows an example of the configuration of the multi-cycle path setting device 100 according to this embodiment. The multi-cycle path setting device 100 according to this embodiment is a computer. The multi-cycle path setting device 100 corresponds to a data processing device. The operating procedure of the multi-cycle path setting device 100 corresponds to a data processing method. Furthermore, a program that realizes the operation of the multi-cycle path setting device 100 corresponds to a data processing program.

[0016] The multi-cycle path setting device 100 includes, as hardware, a processor 901, a main memory device 902, an auxiliary memory device 903, and a communication device 904. Although not shown, the multi-cycle path setting device 100 may also include input / output devices such as a keyboard, a mouse, and a display. The multi-cycle path setting device 100 also includes, as functional components, a formal verification execution unit 111, a property management unit 112, a multi-cycle path constraint generation unit 113, and a timing constraint file update unit 114. The functions of the formal verification execution unit 111, the property management unit 112, the multi-cycle path constraint generation unit 113, and the timing constraint file update unit 114 are realized, for example, by programs. The auxiliary memory device 903 stores programs that realize the functions of the formal verification execution unit 111, the property management unit 112, the multi-cycle path constraint generation unit 113, and the timing constraint file update unit 114. These programs are loaded from the auxiliary memory device 903 to the main memory device 902. The processor 901 then executes these programs to perform the operations of the formal verification execution unit 111, property management unit 112, multi-cycle path constraint generation unit 113, and timing constraint file update unit 114, which will be described later. Fig. 3 schematically shows a state in which the processor 901 is executing programs that realize the functions of the formal verification execution unit 111, property management unit 112, multi-cycle path constraint generation unit 113, and timing constraint file update unit 114.

[0017] Next, an example of the functional configuration of the multi-cycle path setting device 100 will be described with reference to FIG.

[0018] The formal verification execution unit 111 acquires RTL data 301. The RTL data 301 describes the circuit structure of the semiconductor integrated circuit to be designed. In this embodiment, as described above, two or more FFs are connected as two or more storage elements in the semiconductor integrated circuit. The semiconductor integrated circuit operates based on a clock cycle. The formal verification execution unit 111 may acquire a netlist instead of the RTL data 301. When the formal verification execution unit 111 acquires a netlist, the RTL data 301 in the following description shall be read as a netlist.

[0019] The formal verification execution unit 111 further performs static analysis of the RTL data 301 using a property 211 (design specification) supplied from the property management unit 112. In this embodiment, the property 211 is a description that "there is always a period of two or more clock cycles in which no signal transition occurs." The formal verification execution unit 111 performs static analysis of the RTL data 301 and extracts FFs that match the property 211 as transition pause FFs. Specifically, the formal verification execution unit 111 extracts FFs whose shortest transition pause time is two or more clock cycles as transition pause FFs from two or more FFs. In other words, the formal verification execution unit 111 does not extract FFs in which a signal transition occurs in one clock cycle as transition pause FFs. The transition pause FFs are an example of transition pause memory elements.

[0020] The formal verification execution unit 111 verifies the specifications by a formal verification method using the properties 211 as static analysis. The formal verification method is a method for statically verifying the correctness of a semiconductor integrated circuit by mathematically analyzing the circuit structure of the RTL data 301 and the properties 211. The formal verification method does not require the verification patterns required in Patent Document 1. Furthermore, the formal verification method makes it possible to comprehensively verify the correctness of a semiconductor integrated circuit. Tools for the formal verification method include "Jasper Gold" by Cadence and "VC Formal" by Synopsys.

[0021] Furthermore, the formal verification execution unit 111 extracts a connection source FF of the transition pause FF as a connection source FF from two or more FFs. Specifically, the formal verification execution unit 111 extracts the connection source FF by tracing the input signal line of the transition pause FF in the RTL data 301. The connection source FF is an example of a connection source memory element. Furthermore, the formal verification execution unit 111 determines to set a multi-cycle path between the transition pause FF and the connection source FF.

[0022] The formal verification execution unit 111 corresponds to an analysis and extraction unit and a multi-cycle path determination unit. The processing performed by the formal verification execution unit 111 corresponds to an analysis and extraction process and a multi-cycle path determination process.

[0023] The property management unit 112 manages properties 211 used in static analysis of the RTL data 301 by the formal verification execution unit 111. The properties 211 are generated by a designer of a semiconductor integrated circuit. The property management unit 112 acquires the properties 211 from the designer and stores the acquired properties 211 in the auxiliary storage device 903. When the formal verification execution unit 111 performs static analysis of the RTL data 301, the property management unit 112 reads the properties 211 from the auxiliary storage device 903 and supplies the read properties 211 to the formal verification execution unit 111.

[0024] The multi-cycle path constraint generator 113 generates a multi-cycle path constraint 212 for the target multi-cycle path determined by the formal verification execution unit 111. The multi-cycle path constraint 212 describes information about the target multi-cycle path.

[0025] The timing constraint file update unit 114 acquires the timing constraint file 302. Furthermore, the timing constraint file update unit 114 adds the multi-cycle path constraint 212 generated by the multi-cycle path constraint generation unit 113 to the timing constraint file 302. The timing constraint file update unit 114 outputs the timing constraint file 302 to which the multi-cycle path constraint 212 has been added as an updated timing constraint file 303.

[0026] ***Explanation of Operation*** Next, an example of operation of the multi-cycle path setting device 100 according to this embodiment will be described with reference to FIG.

[0027] First, in step S101, the formal verification execution unit 111 acquires RTL data 301. Here, it is assumed that the RTL data 301 includes the description shown in Fig. 6 as an RTL description of the circuit structure shown in Fig. 1. Fig. 6(a) is the RTL description of FF1_reg in Fig. 1, and Fig. 6(b) is the RTL description of FF2_reg in Fig. 1.

[0028] Next, in step S102, the formal verification execution unit 111 obtains the property 211 from the property management unit 112. As described above, the property 211 is a description that "there is always a period of two or more clock cycles in which no signal transition occurs." In this embodiment, the formal verification execution unit 111 uses the property 211 shown in FIG. 7.

[0029] Next, in step S103, the formal verification execution unit 111 performs static analysis on the RTL data 301 using the property 211 to extract transition pause FFs. If there are multiple FFs that match the description of the property 211, the formal verification execution unit 111 extracts the multiple FFs as transition pause FFs. In the example of FIG. 1 , FF2_reg corresponds to the transition pause FF, so the formal verification execution unit 111 extracts FF2_reg as the transition pause FF.

[0030] Next, in step S104, the formal verification execution unit 111 extracts a source FF by tracing the input signal line of the transition pause FF in the RTL data 301. If one transition pause FF has multiple source FFs, the formal verification execution unit 111 extracts multiple source FFs. If multiple transition pause FFs are extracted in step S103, the formal verification execution unit 111 performs step S104 for each transition pause FF. In the example of FIG. 1 , the formal verification execution unit 111 extracts FF1_reg as a source FF of FF2_reg.

[0031] Next, in step S105, the formal verification execution unit 111 determines whether all connection source FFs have been extracted for all transition pause FFs. If there are any unextracted connection source FFs, the formal verification execution unit 111 repeats step S104. If all connection source FFs have been extracted for all transition pause FFs, the process proceeds to step S106.

[0032] Next, in step S106, the formal verification execution unit 111 determines, for each transition pause FF, to set a multi-cycle path between the transition pause FF and the corresponding connection source FF. More specifically, the formal verification execution unit 111 determines to set a multi-cycle path equivalent to two clock cycles between the transition pause FF and the connection source FF. Then, the formal verification execution unit 111 generates multi-cycle path information indicating a pair of the transition pause FF and the connection source FF to which the multi-cycle path is to be set, and outputs the multi-cycle path information to the multi-cycle path constraint generation unit 113. In the example of FIG. 1 , the formal verification execution unit 111 determines to set a multi-cycle path between FF1_reg and FF2_reg, and generates multi-cycle path information indicating FF1_reg and FF2_reg.

[0033] Next, in step S107, the multi-cycle path constraint generation unit 113 generates a multi-cycle path constraint 212 based on the multi-cycle path information. In the example of Fig. 1, the multi-cycle path constraint generation unit 113 generates the multi-cycle path constraint 212 shown in Fig. 8 for the multi-cycle path between FF1_reg and FF2_reg. Then, the multi-cycle path constraint generation unit 113 outputs the generated multi-cycle path constraint 212 to the timing constraint file update unit 114.

[0034] Next, in step S 108 , the timing constraint file update unit 114 adds the multi-cycle path constraint 212 to the timing constraint file 302 to generate an updated timing constraint file 303 .

[0035] Finally, in step S109, the timing constraint file update unit 114 outputs the generated updated timing constraint file 303.

[0036] ***Explanation of the Effects of the Embodiment*** As described above, according to this embodiment, it is possible to accurately set multi-cycle paths without using verification patterns and without placing a burden on the designer of the semiconductor integrated circuit.

[0037] More specifically, in this embodiment, by analyzing RTL data using a formal verification method that mathematically analyzes circuit structures, it is possible to comprehensively extract multi-cycle paths without using verification patterns. Furthermore, an updated timing constraint file that reflects the extracted multi-cycle paths is automatically generated, allowing multi-cycle paths to be accurately set without placing a burden on the designer.

[0038] If there is an error in the setting of a multi-cycle path (for example, if a multi-cycle path is mistakenly set on a path where a signal transition must occur in one clock cycle), a fatal defect occurs in which the semiconductor integrated circuit does not operate. In conventional methods, an error in the setting of a multi-cycle path can easily occur due to a mistake on the part of the designer or a lack of verification patterns. On the other hand, errors cannot occur in the method of this embodiment, which uses a formal verification method. Furthermore, because the method uses a formal verification method that mathematically analyzes the circuit structure, it is possible to extract multi-cycle paths that could not be extracted by conventional methods (that were not intended by the designer).

[0039] Second Embodiment In this embodiment, differences from the first embodiment will be mainly described. Note that matters not described below are the same as those in the first embodiment.

[0040] In the first embodiment, a property 211 is used that states that "there is always a period of two or more clock cycles in which no signal transition occurs." Also, in the first embodiment, a multi-cycle path of two clock cycles is set between the transition pause FF and the connection source FF. In the present embodiment, a property is used that also corresponds to clock cycles with a value greater than two clock cycles (for example, three clock cycles or four clock cycles). As a result, in the present embodiment, a multi-cycle path of clock cycles with a value greater than two clock cycles is set.

[0041] 9 shows an example of the functional configuration of the multi-cycle path setting device 100 according to this embodiment. Note that an example of the hardware configuration of the multi-cycle path setting device 100 according to this embodiment is as shown in FIG.

[0042] 9, compared to FIG. 1, a formal verification execution unit 121 is included instead of the formal verification execution unit 111. A property 221 is included instead of the property 211. A multi-cycle path constraint 222 is included instead of the multi-cycle path constraint 212. Elements other than the formal verification execution unit 121, the property 221, and the multi-cycle path constraint 222 are the same as those shown in FIG. 1. Therefore, only the formal verification execution unit 121, the property 221, and the multi-cycle path constraint 222 will be described here.

[0043] In this embodiment, the property 221 is described as shown in FIG. 10 . In the property 221 in FIG. 10 , compared to the property 211 in FIG. 7 , [*n] is added after "$stable(*_reg / D)." "n" is a variable value. A property set with [*1] ("n=1") is used to extract FFs whose transition pause time is two clock cycles or more. Similarly, a property set with [*2] ("n=2") is used to extract FFs whose transition pause time is three clock cycles or more. In this way, a property set with [*(j-1)] ("n=(j-1)") is used to extract FFs whose transition pause time is j clock cycles or more. In other words, in a static analysis using a property set with [*(j-1)] ("n=(j-1)"), FFs whose transition pause time is j clock cycles or more are extracted.

[0044] In this embodiment, the formal verification execution unit 121 sets "n" of the property 221 to "1" and one or more "values ​​greater than 1." In this way, the formal verification execution unit 121 designates two clock cycles and one or more clock cycles with a value greater than two clock cycles (e.g., three clock cycles, four clock cycles) as the designated clock cycles. For example, the formal verification execution unit 121 increments the value of "n" of the property 221 by 1, 2, 3, 4, and so on, to designate two clock cycles and multiple clock cycles with a value greater than two clock cycles as the designated clock cycles. Alternatively, the formal verification execution unit 121 may decrease the value of "n" of the property 221 from the predetermined upper limit value "m" toward the lower limit value "1." In this way, the formal verification execution unit 121 may designate two clock cycles and one or more clock cycles with a value greater than two clock cycles (e.g., three clock cycles, four clock cycles) as the designated clock cycles. For example, the formal verification execution unit 121 may decrement the value of "n" of the property 221 by m, (m-1), (m-2), ..., until it reaches 1, and specify as the specified clock cycles two clock cycles and multiple clock cycles with a value greater than two clock cycles. The upper limit m can be determined arbitrarily by the designer. In the following, unless otherwise noted, it is assumed that the formal verification execution unit 121 changes the value of "n" by incrementing it.

[0045] Furthermore, for each specified clock cycle, the formal verification execution unit 121 extracts, as a transition pause FF, a FF whose shortest transition pause time matches the specified clock cycle. Then, the formal verification execution unit 121 extracts, as a connection source FF, a connection source FF of the transition pause FF. That is, the formal verification execution unit 121 extracts a transition pause FF and a connection source FF for each value of n. Then, for each specified clock cycle, the formal verification execution unit 121 determines to set a multi-cycle path corresponding to the specified clock cycle between the transition pause FF extracted for the specified clock cycle and the connection source FF. That is, the formal verification execution unit 121 determines to set a multi-cycle path corresponding to the value of n between the transition pause FF and the connection source FF for each value of n. In this way, the formal verification execution unit 121 determines the setting of a multi-cycle path corresponding to the value of n for each value of n. For this reason, in this embodiment, the multi-cycle path constraint 222 generated by the multi-cycle path constraint generation unit 113 describes a multi-cycle path constraint corresponding to the value of n for each value of n.

[0046] The formal verification execution unit 121 according to this embodiment also corresponds to the analysis and extraction unit and the multi-cycle path determination unit.

[0047] The function of the formal verification execution unit 121 is also realized by a program, similar to the formal verification execution unit 111 etc. The program that realizes the function of the formal verification execution unit 121 is executed by the processor 901.

[0048] ***Explanation of Operation*** Next, an example of operation of the multi-cycle path setting device 100 according to this embodiment will be described with reference to Fig. 11. In Fig. 11, the process of step S10X is the same as the process shown in Fig. 4. The process of step S20X is a new process not included in the flow of Fig. 4.

[0049] First, in step S101 , the formal verification execution unit 121 acquires the RTL data 301 .

[0050] Next, in step S201, the formal verification execution unit 121 acquires the property 221 from the property management unit 112. As described with reference to Fig. 10, the property 221 includes [*n].

[0051] Next, in step S202, the formal verification execution unit 121 sets an initial value to "n" of the property 221. If the value of "n" is to be changed by incrementing, the formal verification execution unit 121 sets "n=1" as the initial value. On the other hand, if the value of "n" is to be changed by incrementing, the formal verification execution unit 121 sets "n=m" as the initial value.

[0052] Next, in step S103, the formal verification execution unit 121 performs static analysis on the RTL data 301 using the property 221 to extract transition pause FFs. If there are multiple FFs that match the description of the property 221, the formal verification execution unit 121 extracts the multiple FFs as transition pause FFs.

[0053] Next, in step S104, the formal verification execution unit 121 extracts a connection source FF by tracing the input signal line of the transition pause FF in the RTL data 301. If one transition pause FF has multiple connection source FFs, the formal verification execution unit 121 extracts multiple connection source FFs. If multiple transition pause FFs are extracted in step S103, the formal verification execution unit 121 performs step S104 for each transition pause FF.

[0054] Next, in step S105, the formal verification execution unit 121 determines whether all connection source FFs have been extracted for all transition pause FFs. If there are any unextracted connection source FFs, the formal verification execution unit 121 repeats step S104. If all connection source FFs have been extracted for all transition pause FFs, the process proceeds to step S203.

[0055] In step S203, the formal verification execution unit 121 generates and updates analysis result information. The analysis result information is information in which the value of n, the transition pause FF, and the connection source FF are described in association with each other.

[0056] As described above, in static analysis using the property "n=(j-1)," FFs with transition pause times of j clock cycles or more are extracted. For example, in static analysis using the property "n=1," FFs with transition pause times of two clock cycles or more are extracted. FFs with transition pause times of two clock cycles or more include FFs with transition pause times of two clock cycles and FFs with transition pause times greater than two clock cycles. Assume that the formal verification execution unit 121 performed static analysis using the property "n=1" in step S103. In this case, in the immediately following step S203, the formal verification execution unit 121 generates analysis result information that associates and describes "n=1," all FFs with transition pause times of two clock cycles or more (transition pause FFs), and their connection source FFs.

[0057] Assume that in step S203 after the static analysis using the property "n=1", the formal verification execution unit 121 generates the "n=1" analysis result information shown in (a) of FIG. 12. In the next step S103, the formal verification execution unit 121 performs static analysis using the property "n=2". Then, in the immediately following step S203, the formal verification execution unit 121 generates analysis result information in which "n=2", all FFs whose transition pause time is 3 clock cycles or more (transition pause FFs), and their connection source FFs are described in association with each other. Assume that in step S203 after the static analysis using the property "n=2", the formal verification execution unit 121 generates the "n=2" analysis result information shown in (b) of FIG. 12. The formal verification execution unit 121 compares the "n=1" analysis result information with the "n=2" analysis result information. Then, the formal verification execution unit 121 deletes lines that overlap with the "n=2" analysis result information from the "n=1" analysis result information. As a result, the formal verification execution unit 121 updates the "n=1" analysis result information to the updated "n=1" analysis result information shown in FIG. 12(c).

[0058] Next, in step S203 after static analysis using the "n=3" property, the formal verification execution unit 121 generates the "n=3" analysis result information shown in (d) of FIG. 12. The formal verification execution unit 121 compares the "n=2" analysis result information with the "n=3" analysis result information. The formal verification execution unit 121 then deletes from the "n=2" analysis result information any lines that overlap with the "n=3" analysis result information. As a result, the formal verification execution unit 121 updates the "n=2" analysis result information to the updated "n=2" analysis result information shown in (e) of FIG. 12.

[0059] In this way, the formal verification execution unit 121 increments the value of n, generates analysis result information for the incremented value of n, and uses the analysis result information for the incremented value of n to update the analysis result information generated for the pre-increment value of n. The formal verification execution unit 121 saves the analysis result information and updated analysis result information in at least one of the main memory device 902, the auxiliary memory device 903, and a cache memory not shown in FIG.

[0060] 11 , in step S204, the formal verification execution unit 121 determines whether the value of n has reached its limit. If the formal verification execution unit 121 is incrementing the value of n, the limit is the upper limit value "m". On the other hand, if the formal verification execution unit 121 is decrementing the value of n, the limit is the lower limit value "1". If the value of n has not reached the limit value, the process proceeds to step S205. On the other hand, if the value of n has reached the limit value, the process proceeds to step S206.

[0061] In step S205, the formal verification execution unit 121 increments or decrements the value of n by 1. That is, if the value of n has been incremented, the formal verification execution unit 121 increments the value of n by 1. On the other hand, if the value of n has been decremented, the formal verification execution unit 121 decrements the value of n by 1. Thereafter, the formal verification execution unit 121 executes the processes from step S103 onward with the new value of n.

[0062] In step S206, the formal verification execution unit 121 integrates the plurality of pieces of analysis result information. The analysis result information obtained by the integration in step S206 is referred to as integrated analysis result information.

[0063] Assume that the generation and updating of the analysis result information described with reference to Fig. 12 has resulted in the update "n=m" analysis result information ((e) of Fig. 13) being obtained from the update "n=1" analysis result information ((a) of Fig. 13) as shown in Fig. 13. At this time, the formal verification execution unit 121 integrates the update "n=1" analysis result information with the update "n=m" analysis result information to obtain the integrated analysis result information shown in Fig. 14. In the integrated analysis result information of Fig. 14, the update "n=1" analysis result information is integrated with the update "n=m" analysis result information.

[0064] Next, in step S207, the formal verification execution unit 121 determines, for each value of n in the integrated analysis result information, to set a multi-cycle path between the transition pause FF and the connection source FF, the number of clock cycles of which corresponds to the value of n. In the example of the integrated analysis result information in FIG. 14 , the formal verification execution unit 121 determines, for "n=1," to set a multi-cycle path of two clock cycles between FF1_reg and FF2_reg. Furthermore, for "n=2," the formal verification execution unit 121 determines, for "n=3," to set a multi-cycle path of three clock cycles between FF3_reg and FF4_reg. Furthermore, for "n=3," the formal verification execution unit 121 determines, for other values ​​of n, to set a multi-cycle path between the transition pause FF and the connection source FF, the number of clock cycles of which corresponds to the value of n, in a similar procedure. Then, the formal verification execution unit 121 generates multi-cycle path information indicating a pair of a transition pause FF and a connection source FF for each value of n, and outputs the multi-cycle path information to the multi-cycle path constraint generation unit 113.

[0065] Thereafter, steps S107 to S109 are carried out in the same manner as in the first embodiment.

[0066] In step S107, the multi-cycle path constraint generation unit 113 generates a multi-cycle path constraint 222 based on the multi-cycle path information. In this embodiment, the multi-cycle path constraint generation unit 113 generates the multi-cycle path constraint 222 shown in FIG. 15. In the multi-cycle path constraint 222 shown in FIG. 15, constraints on multi-cycle paths for (n+1) clock cycles are described for each value of n. The multi-cycle path constraint generation unit 113 outputs the generated multi-cycle path constraint 222 to the timing constraint file update unit 114.

[0067] Next, in step S 108 , the timing constraint file update section 114 adds the multi-cycle path constraint 222 to the timing constraint file 302 to generate an updated timing constraint file 303 .

[0068] Finally, in step S109, the timing constraint file update unit 114 outputs the generated updated timing constraint file 303.

[0069] ***Explanation of Effects of the Embodiment*** In this embodiment, a plurality of multi-cycle paths with different numbers of clock cycles can be set in a semiconductor integrated circuit. Therefore, compared to the first embodiment, it is possible to further simplify the layout of the semiconductor integrated circuit and reduce power consumption.

[0070] In the above description, when the value of n is changed by incrementing, the formal verification execution unit 121 increases the value of n until the value of n reaches the upper limit value m. Alternatively, even if the value of n has not reached the upper limit value m, if the formal verification execution unit 121 is unable to extract a transition pause FF in step S103, the formal verification execution unit 121 may terminate the loop from step S103 to step S205 and proceed to step S206. For example, when m = 10 and n = 4, if the formal verification execution unit 121 is unable to extract a transition pause FF in step S103, the formal verification execution unit 121 terminates the loop from step S103 to step S205 and proceeds to step S206. In this case, it is clear that the maximum number of clock cycles included in the semiconductor integrated circuit is 4 (n = 3).

[0071] Third Embodiment In this embodiment, a configuration will be described that enables clock gating during a multi-cycle path period (a period during which no signal transition occurs). Clock gating is a technique for reducing power consumption of a semiconductor integrated circuit by stopping the supply of a clock.

[0072] In this embodiment, differences from embodiment 2 will be mainly described. Note that matters not described below are the same as those in embodiment 2.

[0073] 16 shows an example of the functional configuration of a multi-cycle path setting device 100 according to this embodiment. Note that an example of the hardware configuration of the multi-cycle path setting device 100 according to this embodiment is as shown in FIG.

[0074] 16, compared to FIG. 9, a formal verification execution unit 131 is included instead of the formal verification execution unit 121. In addition, an enable signal generation unit 115, a clock gating description addition unit 116, and clock gating RTL data 304 are added. Elements other than the formal verification execution unit 131, the enable signal generation unit 115, the clock gating description addition unit 116, and the clock gating RTL data 304 are the same as those shown in FIG. 9. Therefore, only the formal verification execution unit 131, the enable signal generation unit 115, the clock gating description addition unit 116, and the clock gating RTL data 304 will be described here.

[0075] The formal verification execution unit 131, like the formal verification execution unit 121, varies the value of n in the property 221 and extracts a transition pause FF and a connection source FF for each value of n. The formal verification execution unit 131 also determines, for each value of n, to set a multi-cycle path of (n+1) clock cycles between the transition pause FF and the connection source FF. Furthermore, for each multi-cycle path, the formal verification execution unit 131 determines to add, to the semiconductor integrated circuit, a clock gating circuit that performs clock gating during the period of the multi-cycle path.

[0076] The formal verification execution unit 131 also corresponds to an analysis and extraction unit and a multi-cycle path determination unit, similar to the formal verification execution unit 121. The formal verification execution unit 131 also corresponds to a clock gating determination unit.

[0077] The enable signal generation unit 115 acquires the RTL data 301. The enable signal generation unit 115 also acquires the multi-cycle path constraint 222. The enable signal generation unit 115 then generates an enable signal using the multi-cycle path constraint 222 and adds the enable signal to the RTL data 301. The enable signal is a signal that enables clock gating during the multi-cycle path. The enable signal generation unit 115 outputs the RTL data 301 with the enable signal added to the clock gating description addition unit 116.

[0078] The clock gating description adding unit 116 generates an RTL description for adding a clock gating circuit to a semiconductor integrated circuit (hereinafter referred to as a clock gating description). Then, the clock gating description adding unit 116 adds the clock gating RTL to RTL data 301. Furthermore, the clock gating description adding unit 116 outputs the RTL data 301 to which the clock gating RTL has been added as clock gating RTL data 304. The clock gating RTL data 304 describes the circuit structure of the semiconductor integrated circuit to which the clock gating circuit has been added.

[0079] The functions of the formal verification execution unit 131, the enable signal generation unit 115, and the clock gating description addition unit 116 are also realized by a program, similar to the formal verification execution unit 111, etc. The program that realizes the functions of the formal verification execution unit 131, the enable signal generation unit 115, and the clock gating description addition unit 116 is executed by the processor 901.

[0080] ***Explanation of Operation*** Next, an example of operation of the multi-cycle path setting device 100 according to this embodiment will be described with reference to Fig. 17. In Fig. 17, the processes of steps S10X and S20X are the same as those shown in Fig. 11. The process of step S30X is a new process not included in the flow of Fig. 11.

[0081] The flow in FIG. 17 is performed after the steps up to step S207 shown in FIG. 11 are completed.

[0082] First, in step S301, the formal verification execution unit 131 determines to add a clock gating circuit to the semiconductor integrated circuit. More specifically, for each multi-cycle path determined in step S207, the formal verification execution unit 131 determines to add a clock gating circuit that performs clock gating during the period of the multi-cycle path.

[0083] Next, in step S107, the multi-cycle path constraint generation unit 113 generates multi-cycle path constraints, as in embodiment 1. In this embodiment, the multi-cycle path constraint generation unit 113 outputs the generated multi-cycle path constraints to the timing constraint file update unit 114 and the enable signal generation unit 115.

[0084] In step S108, similar to the first embodiment, the timing constraint file update unit 114 adds the multi-cycle path constraint 222 to the timing constraint file 302 to generate an updated timing constraint file 303. Also in step S109, similar to the first embodiment, the timing constraint file update unit 114 outputs the generated updated timing constraint file 303.

[0085] In step S302, the enable signal generation unit 115 generates an enable signal by referring to the multi-cycle path constraint acquired from the multi-cycle path constraint generation unit 113. The enable signal generated by the enable signal generation unit 115 is a signal for enabling clock gating during the multi-cycle path. If a corresponding enable signal already exists in the RTL data 301, the enable signal generation unit 115 does not generate an enable signal. On the other hand, if the RTL data 301 does not contain a corresponding enable signal, the enable signal generation unit 115 calculates the output timing of the enable signal and adds the enable signal to the RTL data 301. The enable signal generation unit 115 outputs the RTL data 301 with the enable signal added to the clock gating description addition unit 116.

[0086] In step S303, the clock gating description adding unit 116 generates a clock gating description based on the RTL data 301 acquired from the enable signal generating unit 115. The clock gating description adding unit 116 generates the clock gating description using, for example, the technique described in Japanese Patent No. 5143061, which is the reference document. Then, in step S304, the clock gating description adding unit 116 adds the clock gating description to the RTL data 301. Furthermore, the clock gating description adding unit 116 outputs the RTL data 301 to which the clock gating description has been added as clock gating RTL data 304.

[0087] 18 illustrates an example of the operation of the enable signal generation unit 115 and the clock gating description adding unit 116. (a) of FIG. 18 shows an example of RTL data 301. (b) of FIG. 18 is a timing waveform diagram of the circuit structure of (a) of FIG. 18. The enable signal is turned ON only at the start timing of data input. In the examples of (a) and (b) of FIG. 18, the enable signal is already included in the RTL data 301, so the enable signal generation unit 115 does not need to generate an enable signal. If the RTL data 301 does not include an enable signal, the enable signal shown in (a) and (b) of FIG. 18 is generated and added to the RTL data 301.

[0088] FIG. 18(c) shows clock gating RTL data 304 generated by the clock gating description adding unit 116. In the clock gating RTL data 304, a LATCH-AND type clock gating cell and its signal line have been added as a clock gating description by the clock gating description adding unit 116. FIG. 18(d) is a timing waveform diagram of the circuit structure of FIG. 18(c). In FIG. 18(d), the Gated Clock signal from the LATCH-AND type clock gating cell to the FF turns ON immediately after the enable signal turns ON, but the Gated Clock signal remains OFF thereafter. Based on the enable signal, the clock gating description adding unit 116 generates clock gating descriptions corresponding to the clock gating circuit and Gated Clock signal shown in FIG. 18(c) and (d). This achieves clock gating.

[0089] ***Explanation of Effects of the Embodiment*** In this embodiment, clock gating can be performed during periods when there are no signal transitions between FFs with multi-cycle paths. This makes it possible to further reduce power consumption compared to the second embodiment.

[0090] Fourth Embodiment In this embodiment, a configuration that enables power gating during a multi-cycle path period (a period during which no signal transition occurs) will be described. Power gating is a technique for reducing the power consumption of a semiconductor integrated circuit by partially stopping the power supply. Power gating stops not only the clock but also the power supply to related circuits. As a result, the power consumption of related circuits, including leakage power (power consumed even when not in operation), can be basically reduced to zero.

[0091] In this embodiment, differences from embodiment 3 will be mainly described. Note that matters not described below are the same as those in embodiment 3.

[0092] 19 shows an example of the functional configuration of a multi-cycle path setting device 100 according to this embodiment. Note that an example of the hardware configuration of the multi-cycle path setting device 100 according to this embodiment is as shown in FIG.

[0093] 19, compared to FIG. 16, a formal verification execution unit 141 is included instead of the formal verification execution unit 131. An enable signal generation unit 145 is included instead of the enable signal generation unit 115. A power gating description addition unit 117 is included instead of the clock gating description addition unit 116. Power gating RTL data 305 is included instead of the clock gating RTL data 304. Elements other than the formal verification execution unit 141, the enable signal generation unit 145, the power gating description addition unit 117, and the power gating RTL data 305 are the same as those shown in FIG. 16. Therefore, only the formal verification execution unit 141, the enable signal generation unit 145, the power gating description addition unit 117, and the power gating RTL data 305 will be described here.

[0094] The formal verification execution unit 141 specifies a clock cycle longer than the power recovery time as the specified clock cycle. That is, the formal verification execution unit 141 varies the value of n in the property 221 within a time range longer than the power recovery time, and extracts a transition pause FF and a connection source FF for each value of n. The power recovery time is the time required to resume power supply after it has been stopped by power gating. Furthermore, the formal verification execution unit 141 determines, for each value of n, to set a multi-cycle path of (n+1) clock cycles between the transition pause FF and the connection source FF. Furthermore, for each multi-cycle path, the formal verification execution unit 141 determines to add a power gating circuit to the semiconductor integrated circuit that performs power gating during the period of the multi-cycle path.

[0095] The formal verification execution unit 141 also corresponds to an analysis and extraction unit and a multi-cycle path determination unit, similar to the formal verification execution unit 121. The formal verification execution unit 141 also corresponds to a power gating determination unit.

[0096] The enable signal generation unit 145 acquires the RTL data 301. The enable signal generation unit 145 also acquires the multi-cycle path constraint 222. The enable signal generation unit 145 then generates an enable signal using the multi-cycle path constraint 222 and adds the enable signal to the RTL data 301. The enable signal is a signal that enables power gating during the multi-cycle path. The enable signal generation unit 145 outputs the RTL data 301 with the enable signal added to the power gating description addition unit 117. The operation of the enable signal generation unit 145 is substantially the same as the operation of the enable signal generation unit 115.

[0097] The power gating description adding unit 117 generates an RTL description for adding a power gating circuit to a semiconductor integrated circuit (hereinafter referred to as a power gating description). Then, the power gating description adding unit 117 adds the power gating description to RTL data 301. Furthermore, the power gating description adding unit 117 outputs the RTL data 301 to which the power gating description has been added as power gating RTL data 305. The power gating RTL data 305 describes the circuit structure of the semiconductor integrated circuit to which the power gating circuit has been added.

[0098] The functions of the formal verification execution unit 141, the enable signal generation unit 145, and the power gating description addition unit 117 are also realized by programs, similar to the formal verification execution unit 111, etc. The programs that realize the functions of the formal verification execution unit 141, the enable signal generation unit 145, and the power gating description addition unit 117 are executed by the processor 901.

[0099] ***Explanation of Operation*** Next, an example of operation of the multi-cycle path setting device 100 according to this embodiment will be described. An example of operation of the multi-cycle path setting device 100 according to this embodiment will be described with reference to FIGS. 11 and 20.

[0100] Steps S101 and S102 in FIG. 11 are the same as those described in the second embodiment, and therefore a description thereof will be omitted.

[0101] In step S202, the formal verification execution unit 141 sets an initial value for "n" of the property 221. When changing the value of n by incrementing it, the formal verification execution unit 141 sets the initial value to correspond to a clock cycle slightly longer than the power recovery time. For example, if the power recovery time is 50 clock cycles, the formal verification execution unit 141 sets "50" as the initial value of n to correspond to 51 clock cycles. On the other hand, when changing the value of n by decrementing it, the formal verification execution unit 141 sets the initial value to correspond to a clock cycle significantly longer than the power recovery time.

[0102] Steps S103 to S207 are the same as those described in the second embodiment, and therefore a description thereof will be omitted.

[0103] The flow of FIG. 20 is performed after the steps up to step S207 shown in FIG. 11 are completed.

[0104] First, in step S401, the formal verification execution unit 141 determines to add a power gating circuit to the semiconductor integrated circuit. More specifically, for each multi-cycle path determined in step S207, the formal verification execution unit 141 determines to add a power gating circuit that performs power gating during the period of the multi-cycle path.

[0105] Next, in step S107, the multi-cycle path constraint generation unit 113 generates multi-cycle path constraints, as in embodiment 1. In this embodiment, the multi-cycle path constraint generation unit 113 outputs the generated multi-cycle path constraints to the timing constraint file update unit 114 and the enable signal generation unit 145.

[0106] In step S108, similar to the first embodiment, the timing constraint file update unit 114 adds the multi-cycle path constraint 222 to the timing constraint file 302 to generate an updated timing constraint file 303. Also in step S109, similar to the first embodiment, the timing constraint file update unit 114 outputs the generated updated timing constraint file 303.

[0107] In step S402, the enable signal generation unit 145 generates an enable signal by referring to the multi-cycle path constraint acquired from the multi-cycle path constraint generation unit 113. The enable signal generated by the enable signal generation unit 145 is a signal for enabling power gating during the multi-cycle path. If a corresponding enable signal already exists in the RTL data 301, the enable signal generation unit 145 does not generate an enable signal. On the other hand, if the RTL data 301 does not include a corresponding enable signal, the enable signal generation unit 145 calculates the output timing of the enable signal and adds the enable signal to the RTL data 301. The enable signal generation unit 145 outputs the RTL data 301 with the enable signal added to the power gating description addition unit 117.

[0108] In step S403, the power gating description adding unit 117 generates a power gating description based on the RTL data 301 acquired from the enable signal generating unit 145. The power gating description adding unit 117 generates the power gating description using, for example, the method described in the aforementioned reference document (Japanese Patent No. 5143061). Then, in step S404, the power gating description adding unit 117 adds the power gating description to the RTL data 301. Furthermore, the power gating description adding unit 117 outputs the RTL data 301 to which the power gating description has been added as power gating RTL data 305.

[0109] ***Explanation of Effects of the Embodiment*** In this embodiment, power gating can be performed between FFs with a multi-cycle path during periods when there are no signal transitions. This makes it possible to further reduce power consumption compared to the third embodiment.

[0110] Recently, RAMs with a power gating function have appeared. RAMs with a power gating function have a shorter power recovery time than regular RAMs. Therefore, if a semiconductor integrated circuit includes RAM as a storage element, power gating can be achieved by replacing the RAM with a RAM with a power gating function and connecting the enable signal to a dedicated terminal such as a leakage power reduction terminal of the RAM with the power gating function. In other words, the semiconductor integrated circuit itself does not need to be power gating compatible.

[0111] Although the first to fourth embodiments have been described above, two or more of these embodiments may be combined and implemented. Alternatively, one of these embodiments may be partially implemented. Alternatively, two or more of these embodiments may be partially combined and implemented. Furthermore, the configurations and procedures described in these embodiments may be modified as necessary.

[0112] ***Supplementary Explanation of Hardware Configuration*** Finally, a supplementary explanation of the hardware configuration of the multi-cycle path setting device 100 will be provided. The processor 901 shown in FIG. 3 is an IC (Integrated Circuit) that performs processing. The processor 901 is a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or the like. The main memory device 902 shown in FIG. 3 is a RAM (Random Access Memory). The auxiliary memory device 903 shown in FIG. 3 is a ROM (Read Only Memory), a flash memory, an HDD (Hard Disk Drive), or the like. The communication device 904 shown in FIG. 3 is an electronic circuit that executes data communication processing. The communication device 904 is, for example, a communication chip or a NIC (Network Interface Card).

[0113] The auxiliary storage device 903 also stores an OS (Operating System). At least a part of the OS is executed by the processor 901. While executing at least a part of the OS, the processor 901 executes programs that realize functions of the formal verification execution unit 111 and the like. The "formal verification execution unit 111" and the like refer to the formal verification execution unit 111, property management unit 112, multi-cycle path constraint generation unit 113, timing constraint file update unit 114, enable signal generation unit 115, clock gating description addition unit 116, power gating description addition unit 117, formal verification execution unit 121, formal verification execution unit 131, formal verification execution unit 141, and enable signal generation unit 145. The processor 901 executes the OS to perform task management, memory management, file management, communication control, and the like. Furthermore, at least one of information, data, signal values, and variable values ​​indicating the results of processing by the formal verification execution unit 111 and the like is stored in at least one of the main memory device 902, the auxiliary memory device 903, and a register and cache memory in the processor 901. Furthermore, a program that realizes the functions of the formal verification execution unit 111 and the like may be stored on a portable recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a Blu-ray (registered trademark) disk, or a DVD. Then, the portable recording medium on which the program that realizes the functions of the formal verification execution unit 111 and the like is stored may be distributed.

[0114] Furthermore, at least one of the "units" such as the formal verification execution unit 111 may be interpreted as a "circuit," a "step," a "procedure," a "process," or a "circuitry." Furthermore, the multi-cycle path setting device 100 may be realized by a processing circuit. The processing circuit may be, for example, a logic IC (Integrated Circuit), a GA (Gate Array), an ASIC (Application Specific Integrated Circuit), or an FPGA (Field-Programmable Gate Array). In this case, the formal verification execution unit 111 and the like are each realized as part of the processing circuit. In this specification, the higher-level concept of a processor and a processing circuit is referred to as a "processing circuitry." In other words, a processor and a processing circuit are each specific examples of "processing circuitry."

[0115] 100 Multi-cycle path setting device, 111 Formal verification execution unit, 112 Property management unit, 113 Multi-cycle path constraint generation unit, 114 Timing constraint file update unit, 115 Enable signal generation unit, 116 Clock gating description addition unit, 117 Power gating description addition unit, 121 Formal verification execution unit, 131 Formal verification execution unit, 141 Formal verification execution unit, 145 Enable signal generation unit, 211 Properties, 212 Multi-cycle path constraints, 221 Properties, 222 Multi-cycle path constraints, 301 RTL data, 302 Timing constraint file, 303 Updated timing constraint file, 304 Clock gating RTL data, 305 Power gating RTL data, 901 Processor, 902 Main memory, 903 Auxiliary memory, 904 Communication device.

Claims

1. A data processing device having an analysis extraction unit that performs static analysis of at least one of RTL (Register Transfer Level) data and a netlist of a semiconductor integrated circuit that operates based on a clock cycle to which two or more memory elements are connected, extracts a memory element whose shortest time among times when no signal transition occurs is two or more clock cycles as a transition pause memory element from the two or more memory elements, and extracts a memory element that is the source of connection of the transition pause memory element as a source connection memory element from the two or more memory elements, and a multi-cycle path determination unit that determines to set a multi-cycle path between the transition pause memory element and the source connection memory element.

2. The analysis extraction unit designates each of two clock cycles and one or more clock cycles having a value greater than two clock cycles as a designated clock cycle, extracts, for each designated clock cycle, a memory element whose shortest time matches the designated clock cycle as the transition pause memory element, and extracts a memory element that is the source of connection of the transition pause memory element as the source connection memory element. The multi-cycle path determination unit determines to set a multi-cycle path corresponding to the designated clock cycle between the transition pause memory element and the source connection memory element extracted for the designated clock cycle. The data processing device according to claim 1.

3. The analysis extraction unit designates two clock cycles and one or more clock cycles having a value greater than two clock cycles as the designated clock cycle by either a method of sequentially increasing the value of the clock cycle starting from two clock cycles or a method of sequentially decreasing the value of the clock cycle toward two clock cycles. The data processing device according to claim 2.

4. The data processing device further has a clock gating determination unit that determines to add a clock gating circuit that performs clock gating during the period of the multi-cycle path to the semiconductor integrated circuit. The data processing device according to claim 1.

5. The data processing device further has a clock gating description addition unit that adds a description of the clock gating circuit to at least one of the RTL data and the netlist. The data processing device according to claim 4.

6. The analysis and extraction unit designates a clock cycle longer than the power-on recovery time when performing power gating of the semiconductor integrated circuit as a specified clock cycle, extracts a memory element whose shortest time matches the specified clock cycle as the transition pause memory element, and extracts the memory element from which the transition pause memory element is connected as the source memory element. The multi-cycle path determination unit determines to set a multi-cycle path corresponding to the specified clock cycle between the transition pause memory element and the source memory element extracted for the specified clock cycle. The data processing apparatus according to claim 1.

7. The data processing apparatus further includes a power gating determination unit that determines to add a power gating circuit that performs power gating of the semiconductor integrated circuit during the period of the multi-cycle path to the semiconductor integrated circuit. The data processing apparatus according to claim 1.

8. The data processing apparatus further includes a power gating description addition unit that adds a description of the power gating circuit to at least one of the RTL data and the netlist. The data processing apparatus according to claim 7.

9. The analysis and extraction unit performs analysis by a formal verification method on at least one of the RTL data and the netlist as the static analysis. The data processing apparatus according to claim 1.

10. The analysis and extraction unit performs static analysis on at least one of the RTL data and the netlist of a semiconductor integrated circuit including at least one of a FF (Flip-Flop) and a RAM (Random Access Memory) as a memory element. The data processing apparatus according to claim 1.

11. A data processing method in which a computer performs static analysis of at least one of RTL (Register Transfer Level) data and a netlist of a semiconductor integrated circuit that operates based on clock cycles and to which two or more memory elements are connected, extracts a memory element whose shortest time among times when no signal transition occurs is two or more clock cycles as a transition pause memory element from the two or more memory elements, extracts a memory element that is the source of connection of the transition pause memory element as a source connection memory element from the two or more memory elements, and determines to set a multi-cycle path between the transition pause memory element and the source connection memory element.

12. An analysis and extraction process in which a computer performs static analysis of at least one of RTL (Register Transfer Level) data and a netlist of a semiconductor integrated circuit that operates based on clock cycles and to which two or more memory elements are connected, extracts a memory element whose shortest time among times when no signal transition occurs is two or more clock cycles as a transition pause memory element from the two or more memory elements, and extracts a memory element that is the source of connection of the transition pause memory element as a source connection memory element from the two or more memory elements, and a multi-cycle path determination process that determines to set a multi-cycle path between the transition pause memory element and the source connection memory element, and a data processing program that causes the computer to execute the processes.

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