Power conversion device

Abstract

In this power conversion device, a control circuit detects overvoltage of an inverter circuit when the voltage of DC power becomes equal to or greater than a predetermined threshold. At this time, all-phase open processing is executed for turning off all semiconductor switching elements included in the inverter circuit and, after the all-phase open processing is executed, three-phase short circuit processing is executed for turning on the semiconductor switching element corresponding to one of the upper and lower arms of each phase of the inverter circuit. A drive circuit switches the switching speed of the semiconductor switching elements so that the switching speed, when the semiconductor switching element corresponding to the one arm is turned on when the control circuit executes the three-phase short circuit processing, is slower than the switching speed when said semiconductor switching element is turned on before the control circuit detects the overvoltage.

Description

Power Conversion Device

[0001] The present invention relates to a power conversion device that converts DC power into AC power.

[0002] Power conversion devices that convert DC power to AC power by switching a plurality of semiconductor switching elements at predetermined timings have been widely used. It is known that a transient voltage called a recovery surge is superimposed across the main terminals of each semiconductor switching element in such power conversion devices. The recovery surge is a surge voltage that occurs when a forward return current flows through a diode electrically connected in parallel with a semiconductor switching element in one of the upper or lower arms when the semiconductor switching element in that arm is in the off state. When a semiconductor switching element in the other arm is subsequently turned on, a reverse voltage is applied to the diode, causing a reverse recovery current to flow through the diode.

[0003] A known technique for suppressing surge voltages during switching operations of semiconductor switching elements is, for example, Patent Document 1. Patent Document 1 describes a technique in which, when the value of the DC voltage input to an inverter becomes equal to or greater than a predetermined third voltage threshold Vlsth that is lower than an overvoltage detection level, the switching speed of the semiconductor switching elements of the inverter is forcibly switched to a low speed in advance, thereby suppressing surge voltages by slowing down the switching speed when an overvoltage is detected.

[0004] Japanese Patent Application Publication No. 2016-73127

[0005] In the technology of Patent Document 1, when the DC voltage input to the inverter exceeds a third voltage threshold Vlsth, the value of the gate resistor connected to the gate terminal of the semiconductor switching element is changed to slow down the switching speed regardless of the operating state of the inverter. However, increasing the value of the gate resistor to slow down the switching speed increases the switching loss of the semiconductor switching element, resulting in a deterioration in the power conversion efficiency of the inverter. In particular, if the difference between the third voltage threshold Vlsth and the overvoltage detection level (overvoltage detection margin) is increased to avoid a delay in overvoltage detection, the voltage region in the range of the DC voltage input to the inverter where the switching speed is slowed increases accordingly, resulting in a significant deterioration in the power conversion efficiency of the inverter.

[0006] The present invention has been made in view of the above-mentioned problems, and a main object of the present invention is to suppress the occurrence of a recovery surge while avoiding a decrease in power conversion efficiency in a power conversion device that converts DC power to AC power.

[0007] A power conversion device according to the present invention converts DC power into three-phase AC power, and includes an inverter circuit having a plurality of semiconductor switching elements respectively corresponding to upper and lower arms of each phase of the three-phase AC power, a control circuit that outputs a control signal to control a drive state of the inverter circuit, and a drive circuit that applies a gate voltage to a gate terminal of the semiconductor switching element based on the control signal from the control circuit, thereby causing the semiconductor switching element to perform a switching operation and driving the inverter circuit, wherein the drive circuit is capable of switching the switching speed of the semiconductor switching element, and the control circuit detects an overvoltage of the inverter circuit when a voltage of the DC power becomes equal to or higher than a predetermined threshold. When the overvoltage is detected, an all-phase open process is executed to turn off all of the semiconductor switching elements of the inverter circuit, and after the all-phase open process is executed, a three-phase short process is executed to turn on the semiconductor switching elements corresponding to one of the upper and lower arms of each phase of the inverter circuit, and the drive circuit switches the switching speed of the semiconductor switching elements so that the switching speed at the time of turn-on of the semiconductor switching elements corresponding to the one arm when the control circuit executes the three-phase short process is slower than the switching speed at the time of turn-on of the semiconductor switching elements before the control circuit detects the overvoltage.

[0008] According to the present invention, in a power conversion device that converts DC power into AC power, it is possible to suppress the occurrence of a recovery surge while avoiding a decrease in power conversion efficiency.

[0009] 11 is a block diagram showing a schematic configuration of a motor drive system including a power conversion device according to an embodiment of the present invention.

[0023] FIG. 1 is a diagram showing an example of how a DC voltage changes over time when a motor is in a regenerative state.

[0024] FIG. 12 is an explanatory diagram of current paths in an inverter circuit during an all-phase open-circuit period and a three-phase short-circuit period.

[0025] FIG. 13 is a diagram showing example voltage waveforms of semiconductor switching elements of upper and lower arms during a transition from an all-phase open-circuit period to a three-phase short-circuit period.

[0026] FIG. 14 is an explanatory diagram showing the principle of recovery surge generation.

[0027] FIG. 15 is a diagram showing how a DC voltage changes over time when a motor is in a regenerative state and an example of a recovery surge before suppression.

[0028] FIG. 16 is a diagram showing how a DC voltage changes over time when a motor is in a regenerative state and an example of a recovery surge after suppression.

[0029] FIG. 17 is a flowchart showing the processing flow of the power conversion device when the motor is in a regenerative state.

[0029] FIG. 18 is a diagram showing a circuit configuration between each semiconductor switching element and a gate drive circuit in a power conversion device according to a first embodiment of the present invention.

[0029] FIG. 19 is a diagram showing an output circuit for a turn-on signal in the gate drive circuit of FIG. 9 and a truth table showing the correspondence between input and output signals.

[0029] FIG. 19 is a diagram showing a circuit configuration between each semiconductor switching element and a gate drive circuit in a power conversion device according to a second embodiment of the present invention.

[0029] FIG. 11 is a diagram showing an output circuit for a turn-on signal in the gate drive circuit of FIG. 11 and a truth table showing the correspondence between input and output signals. 10A and 10B are diagrams illustrating a circuit configuration between each semiconductor switching element and a gate drive circuit in a power conversion device according to a third embodiment of the present invention, and a circuit configuration between each semiconductor switching element and a gate drive circuit in a power conversion device according to a fourth embodiment of the present invention.

[0010] Fig. 1 is a block diagram showing a schematic configuration of a motor drive system including a power conversion device according to one embodiment of the present invention. In the motor drive system shown in Fig. 1, a power conversion device 100 is connected between a DC battery 200 and a motor 300, and drives the motor 300 by converting DC power supplied from the DC battery 200 into three-phase AC power and outputting the power to the motor 300. A contactor 201 is provided between the power conversion device 100 and the DC battery 200 to control the connection state between them. The motor 300 is provided with a rotational position sensor 301 to detect the rotational position of its rotor.

[0011] The power conversion device 100 includes an inverter circuit 1, a control circuit 2, a drive circuit 3, and a voltage smoothing capacitor 4. A command (e.g., a torque command or a rotation command) for driving the motor 300 is input to the power conversion device 100 from a host controller (not shown). The inverter circuit 1 is provided with a plurality of legs, each of which is configured as an upper arm and a lower arm, and each leg is configured by connecting semiconductor switching elements 11 and diodes 12 in parallel, corresponding to the number of phases of AC power to be output. These legs are connected in parallel to each other to form a bridge circuit. In the example of FIG. 1 , the motor 300 is a three-phase AC motor, and therefore the power conversion device 100 outputs three-phase AC power to the motor 300. Therefore, the inverter circuit 1 is provided with legs for the three phases.

[0012] The power conversion device 100 also includes a voltage detection circuit 5 that measures the voltage of the DC power supplied from the DC battery 200 , and current sensors 61 and 62 that measure the current of the AC power output to the motor 300 .

[0013] The control circuit 2 generates a control signal in response to a command from a higher-level controller based on the voltage value of the DC power and the current value of the AC power measured by the voltage detection circuit 5 and the current sensors 61 and 62, respectively, and outputs the generated control signal to the drive circuit 3. Specifically, the control circuit 2 calculates the AC current value of the remaining phase (e.g., W phase) from the AC current values ​​of two phases (e.g., U phase and V phase) detected by the current sensors 61 and 62, respectively, to obtain the value of the three-phase AC current output from the inverter circuit 1 to the motor 300. Then, based on the obtained three-phase AC current value, the input voltage value of the inverter circuit 1 detected by the voltage detection circuit 5, the rotational position of the motor 300 detected by the rotational position sensor 301, and a command from the higher-level controller (not shown), the control circuit 2 performs pulse width modulation using well-known feedback control to determine the timings for turning on and off each semiconductor switching element 11 of the inverter circuit 1 and generates a PWM signal indicating these timings. This allows the control circuit 2 to generate a control signal including a PWM signal for controlling the driving state of the inverter circuit 1 and output the control signal to the drive circuit 3.

[0014] The drive circuit 3 has a plurality of gate drive circuits 30 provided for each semiconductor switching element 11 of the inverter circuit 1. Based on a control signal (PWM signal) from the control circuit 2, the drive circuit 3 applies a gate voltage to the gate terminal of the semiconductor switching element 11 of the upper arm or lower arm of each phase by each gate drive circuit 30, thereby causing each semiconductor switching element 11 of the inverter circuit 1 to perform a switching operation. This drives the inverter circuit 1, and DC power supplied from the DC battery 200 is converted into three-phase AC power in the inverter circuit 1.

[0015] The voltage smoothing capacitor 4 is connected between the DC battery 200 and the inverter circuit 1, and smoothes the voltage applied to the inverter circuit 1 that fluctuates during power conversion. The voltage across the voltage smoothing capacitor 4 is measured by a voltage detection circuit 5 as the voltage applied from the DC battery 200 to the inverter circuit 1.

[0016] When the rotor of motor 300 is driven to rotate by an external force, an induced voltage is generated in the coils of each phase in motor 300, causing motor 300 to enter a regenerative state and operate as a generator. The AC power generated by motor 300 at this time is converted to DC power by power conversion device 100 and output to DC battery 200, which charges DC battery 200. As a result, the voltage of DC battery 200 increases.

[0017] 2 is a diagram showing an example of how the DC voltage changes over time when the motor 300 is in a regenerative state. In Fig. 2, the horizontal axis represents time, and the vertical axis represents the magnitude of the voltage HVDC of the DC battery 200. In the power conversion device 100, the voltage HVDC is detected by the voltage detection circuit 5, and the voltage value is notified from the voltage detection circuit 5 to the control circuit 2.

[0018] 2 , for example, when the motor 300 enters a regenerative state at time t1, the voltage HVDC continues to rise over time. Then, when the voltage HVDC reaches a predetermined threshold Vth at time t2, the control circuit 2 determines that the input voltage to the inverter circuit 1 is in an overvoltage state, detects the overvoltage of the inverter circuit 1, and activates a protection function to protect each semiconductor switching element 11 of the inverter circuit 1. The threshold Vth at which the control circuit 2 detects the overvoltage can be set according to the allowable voltage range set for each semiconductor switching element 11. Specifically, the overvoltage threshold Vth is set so that the allowable voltage range of each semiconductor switching element 11 is not exceeded even when a surge voltage generated during the switching operation of each semiconductor switching element 11 is applied.

[0019] When the control circuit 2 activates the protection function, the control circuit 2 outputs a control signal to the drive circuit 3 to turn off all of the semiconductor switching elements 11 in the inverter circuit 1. In response to this control signal, each gate drive circuit 30 of the drive circuit 3 controls the gate voltage applied to the gate terminal of each semiconductor switching element 11 so as to switch all of the semiconductor switching elements 11 in the inverter circuit 1 to the off state. As a result, at time t3, which is a predetermined detection delay period after time t2 when the voltage HVDC exceeds the threshold value Vth, an all-phase open period begins in which all of the semiconductor switching elements 11 in the inverter circuit 1 are in the off state (open state).

[0020] Thereafter, at time t4, a predetermined time after time t3 when the all-phase open period started, the control circuit 2 outputs a control signal to the drive circuit 3 to switch to the on state the semiconductor switching element 11 corresponding to one of the upper and lower arms of each phase of the inverter circuit 1. In response to this control signal, each gate drive circuit 30 of the drive circuit 3 controls the gate voltage applied to the gate terminal of each semiconductor switching element 11 so as to turn on the semiconductor switching element 11 of each phase corresponding to one arm of the inverter circuit 1 from the off state. As a result, at time t4, a three-phase short period starts in which the semiconductor switching element 11 of one arm of each phase of the inverter circuit 1 is in the on state (closed) and the semiconductor switching element 11 of the other arm is in the off state (open).

[0021] When the three-phase short-circuit period starts at time t4, the power generated by the motor 300 is consumed within each semiconductor switching element 11 and the motor 300, and the DC battery 200 is discharged. As a result, the voltage HVDC gradually decreases. That is, the voltage HVDC reaches its maximum at time t4, when the three-phase short-circuit period starts. In FIG. 2, the maximum value of the voltage HVDC at time t4 is indicated by a maximum voltage Vmax.

[0022] The power conversion device 100 performs the above-described control when the motor 300 is in a regenerative state. That is, when the voltage HVDC rises and exceeds the threshold value Vth, an overvoltage of the inverter circuit 1 is detected, and an all-phase open process is performed to turn off all of the semiconductor switching elements 11 included in the inverter circuit 1. Then, a three-phase short process is performed to turn on the semiconductor switching elements 11 corresponding to one of the upper and lower arms of each phase of the inverter circuit 1. In this way, by performing the three-phase short process after performing the all-phase open process, the DC battery 200 can be discharged to reduce the voltage HVDC while suppressing the peak current flowing through each semiconductor switching element 11 when the three-phase short process is started.

[0023] FIG. 3 is an explanatory diagram of current paths within the inverter circuit 1 during an all-phase open period and a three-phase short period.

[0024] 3A, during the all-phase open period, all of the semiconductor switching elements 11 are in the OFF state in the inverter circuit 1. Therefore, as shown by arrow 12a, a current path is formed that flows from the motor 300 to the DC battery 200 and the voltage smoothing capacitor 4 via the diode 12.

[0025] On the other hand, as shown in Fig. 3(b), during a three-phase short circuit period, the semiconductor switching elements 11 of either the upper or lower arm (the lower arm in the example of Fig. 3(b)) of all phases in the inverter circuit 1 are turned on and switched to the on state, thereby forming a closed circuit for each phase between the motor 300 and the inverter circuit 1. Therefore, as shown by arrow 12b, a current path is formed that runs from the motor 300 through the on-state semiconductor switching elements 11 of each phase, and power is consumed in this current path.

[0026] Next, a recovery surge that occurs in the semiconductor switching element 11 when the all-phase open period transitions to the three-phase short period will be described.

[0027] 4 is a diagram showing example voltage waveforms of the semiconductor switching elements 11 of the upper and lower arms during a transition from an all-phase open period to a three-phase short period. In FIG. 4, graph 41 shows an example of the gate-source voltage Vgs of the upper arm, graph 42 shows an example of the drain-source voltage Vds of the upper arm, graph 43 shows an example of the gate-source voltage Vgs of the lower arm, and graph 44 shows an example of the drain-source voltage Vds of the lower arm. Note that FIG. 4 shows an example of voltage waveforms when the semiconductor switching elements 11 of the lower arms of each phase are turned on from the off state, as shown in FIG. 3(b).

[0028] When the semiconductor switching element 11 of the lower arm is turned on during the transition from the all-phase open period to the three-phase short period, a transient voltage exceeding the voltage of the DC battery 200 is applied to the drain-source voltage Vds of the semiconductor switching element 11 of the upper arm that is in the off state, as shown in graph 42. The voltage transiently superimposed between the main terminals of the semiconductor switching element 11 of the other arm that forms a pair with the semiconductor switching element 11 that is turned on is called a recovery surge.

[0029] FIG. 5 is an explanatory diagram of the principle of recovery surge generation. In FIG. 5, during the all-phase open-circuit period shown on the left, the induced voltage generated by the motor 300 entering a regenerative state forms a current path 12a through which a reflux current flows in the upper-arm diode 12, as described in FIG. 3 . When the lower-arm semiconductor switching element 11 is turned on in this state, transitioning to the three-phase short-circuit period shown on the right, a recovery current flows in the upper-arm diode 12, through which a reflux current had been flowing, in the direction opposite to the reflux current. This reverse recovery current causes a recovery surge, as illustrated in FIG. 4 , to be superimposed on the drain-source voltage of the upper-arm semiconductor switching element 11. The magnitude of the superimposed recovery surge can be adjusted by the resistance value of the gate resistor connected to the gate terminal of the upper-arm semiconductor switching element 11.

[0030] Next, problems caused by recovery surges will be described below with reference to Figures 6 and 7. The graphs shown in Figures 6 and 7 are the same as the graph showing the time variation of DC voltage shown in Figure 2.

[0031] At time t4, when one of the semiconductor switching elements 11 in the upper or lower arm is turned on to transition from the all-phase open period to the three-phase short period, the voltage HVDC (maximum voltage Vmax) of the DC battery 200 is applied between the drain and source of the semiconductor switching element 11 in the other arm that is paired with the semiconductor switching element 11. At this time, a recovery surge is superimposed on the drain-source voltage of the semiconductor switching element 11 in the other arm, as described above. That is, the drain-source voltage Vds of the semiconductor switching element 11 in the other arm at time t4 is a value obtained by superimposing the recovery surge on the maximum voltage Vmax. If this drain-source voltage Vds exceeds the device breakdown voltage of the semiconductor switching element 11 as shown in FIG. 6, this may cause a failure of the semiconductor switching element 11.

[0032] As described above, during a transition from an all-phase open period to a three-phase short period, an excessive voltage is applied between the main terminals of the semiconductor switching element 11 due to a recovery surge. To prevent this voltage from exceeding the device breakdown voltage of the semiconductor switching element 11, it is necessary to set the resistance value of the gate resistor to a large value so as to sufficiently suppress the recovery surge. In particular, when a silicon carbide-metal oxide semiconductor field effect transistor (SiC-MOSFET), which has been increasingly put into practical use in recent years, is used as the semiconductor switching element 11, it has a shorter reverse recovery time than conventional semiconductor switching elements made from silicon, resulting in less switching loss, but a larger recovery surge. Therefore, it is necessary to set the resistance value of the gate resistor so as to suppress the recovery surge with a sufficient margin relative to the device breakdown voltage.

[0033] However, increasing the resistance value of the gate resistor slows down the switching speed of the semiconductor switching element 11, and the switching loss increases accordingly. In other words, the recovery surge and switching loss can be adjusted by adjusting the resistance value of the gate resistor, but there is a trade-off between them. Therefore, it is preferable to set the resistance value of the gate resistor so that the recovery surge does not exceed the device breakdown voltage while minimizing switching loss.

[0034] Therefore, in the power conversion device 100 of this embodiment, during normal operation in which the semiconductor switching elements 11 of the inverter circuit 1 are switched to convert DC power to three-phase AC power, the resistance value of the gate resistor in the drive circuit 3 is set to a small value to suppress switching loss, while when a three-phase short process is performed after an all-phase open process is performed, the resistance value of the gate resistor in the drive circuit 3 is switched to a large value. As a result, as shown in FIG. 7 , a recovery surge that occurs during the transition from an all-phase open period to a three-phase short period is suppressed, and the voltage applied between the main terminals of the semiconductor switching elements 11 does not exceed the device withstand voltage. Hereinafter, the function of the power conversion device 100 that suppresses the recovery surge by switching the gate resistance value in this manner will be referred to as a "soft turn-on function."

[0035] 8 is a flowchart showing the flow of processing by the power conversion device 100 when the motor 300 is in a regenerative state. In the power conversion device 100, the control circuit 2 executes the processing shown in the flowchart of FIG. 8 at predetermined intervals.

[0036] In step S10, the control circuit 2 determines whether or not the motor 300 is in a regenerative state. If the motor 300 is not in a regenerative state, the process remains in step S10, and if the motor 300 is in a regenerative state, the process proceeds to step S20.

[0037] In step S20, the control circuit 2 determines whether the input voltage of the inverter circuit 1 is an overvoltage. Here, the voltage HVDC of the DC battery 200 detected by the voltage detection circuit 5 is compared with a predetermined threshold value Vth. If the voltage HVDC is less than the threshold value Vth, it is determined that there is no overvoltage, and the process returns to step S10. On the other hand, if the voltage HVDC is equal to or greater than the threshold value Vth, it is determined that there is an overvoltage, and the process proceeds to step S30.

[0038] In step S30, the control circuit 2 executes the all-phase open process. As described above, the control circuit 2 issues an all-phase open command to the drive circuit 3 by outputting a control signal to the drive circuit 3 to turn off all of the semiconductor switching elements 11 in the inverter circuit 1. When the drive circuit 3 receives this all-phase open command, all of the semiconductor switching elements 11 in the inverter circuit 1 are turned off, and an all-phase open period begins.

[0039] In step S40, the control circuit 2 enables the soft turn-on function described above in the power conversion device 100. That is, the control circuit 2 controls the drive circuit 3 to switch the resistance value of the gate resistor to a value greater than the previous value, thereby suppressing the recovery surge. The specific operation of the drive circuit 3 at this time will be described later.

[0040] In step S50, the control circuit 2 executes three-phase short processing. As described above, a three-phase short command is issued to the drive circuit 3 by outputting a control signal to the drive circuit 3 to turn on one of the semiconductor switching elements 11 in the upper and lower arms in each phase of the inverter circuit 1 from an off state to an on state. When this three-phase short command is received by the drive circuit 3, one of the semiconductor switching elements 11 in the upper and lower arms in each phase of the inverter circuit 1 is switched from off to on, and a three-phase short period begins. Note that the processing of step S40 and the processing of step S50 may be executed simultaneously.

[0041] After executing the process of step S50, the control circuit 2 ends the process shown in the flowchart of FIG.

[0042] Next, a specific operation of the drive circuit 3 when the soft turn-on function is enabled in step S40 of FIG. 8 in the power conversion device 100 of this embodiment will be described below with reference to FIGS.

[0043] 9 is a diagram showing a circuit configuration between each semiconductor switching element 11 and a gate drive circuit 30 in a power conversion device 100 according to the first embodiment of the present invention. In the power conversion device 100 of this embodiment, each of the multiple semiconductor switching elements 11 included in the inverter circuit 1 is connected to the corresponding gate drive circuit 30 in the drive circuit 3 in a circuit configuration such as that shown in FIG.

[0044] The gate drive circuit 30 has a power supply terminal VCC1, a ground terminal GND1, input terminals for the drive signal INA, the inverted / non-inverted selection signal INB, and the enable signal ENA, and an output terminal for the fault signal FLT on its low-voltage side. It also has a power supply terminal VCC2, a ground terminal GND2, a gate output terminal OUT, an output terminal for the soft turn-off signal STOFF, and a short-circuit detection terminal OCD on its high-voltage side. The low-voltage side terminals and the high-voltage side terminals are insulated from each other within the gate drive circuit 30.

[0045] The power supply terminal VCC1 receives a low-voltage power supply voltage. The ground terminal GND1 is connected to the low-voltage ground potential. The aforementioned PWM signal, one of the control signals output from the control circuit 2, is input as the drive signal INA to the input terminal for the drive signal INA. A signal for selecting the polarity (inverted / non-inverted) of the PWM signal is input as the inverted / non-inverted selection signal INB from the control circuit 2 to the input terminal for the inverted / non-inverted selection signal INB. A signal for enabling (enabling) or disabling (disabling) the soft turn-on function is input as the enable signal ENA from the control circuit 2 to the input terminal for the enable signal ENA. When an abnormality occurs in the gate drive circuit 30, the output terminal for the abnormality signal FLT outputs an abnormality signal FLT that notifies the control circuit 2 of the occurrence of the abnormality.

[0046] A high-voltage power supply voltage is input to the power supply terminal VCC2. The ground terminal GND2 is connected to the high-voltage ground potential. The gate output terminal OUT is connected to the gate terminal of the semiconductor switching element 11, and outputs a gate signal to the gate terminal according to the drive signal INA and the inverted / non-inverted selection signal INB, thereby charging or discharging the gate terminal and turning on or off the semiconductor switching element 11. A turn-on gate resistor Ron1 and a turn-off gate resistor Roff1 are connected between the gate output terminal OUT and the gate terminal, and the switching speeds of the semiconductor switching element 11 when turned on and off are determined according to the resistance values ​​of these resistors.

[0047] The semiconductor switching element 11 is provided with a current sense terminal that shunts and outputs the current flowing between the main terminals (between the drain terminal and source terminal, or between the collector terminal and emitter terminal), and this current sense terminal is connected to the power supply terminal VCC2 of the gate drive circuit 30 via a sense resistor Rs. The short-circuit detection terminal OCD detects the current flowing through the semiconductor switching element 11 by measuring the voltage across the sense resistor Rs. The gate drive circuit 30 can detect if the semiconductor switching element 11 is short-circuited based on the current value detected at the short-circuit detection terminal OCD.

[0048] The output terminal of the soft turn-off signal STOFF is connected to the gate terminal of the semiconductor switching element 11 via a soft turn-off gate resistor Roff2 having a resistance greater than that of the aforementioned turn-off gate resistor Roff1. When the gate drive circuit 30 detects a short circuit in the semiconductor switching element 11 from the current value detected at the short-circuit detection terminal OCD, it changes the soft turn-off signal STOFF to discharge the gate terminal of the semiconductor switching element 11. This turns off the semiconductor switching element 11 at a slower switching speed than normal in the event of a short circuit, thereby protecting the semiconductor switching element 11. In other words, when the semiconductor switching element 11 is short-circuited, the soft turn-off signal STOFF is used instead of the gate signal output from the gate output terminal OUT, thereby preventing a sudden change in current and suppressing the generation of surge voltage while turning off the semiconductor switching element 11. This function is generally referred to as a "soft turn-off function."

[0049] 10A and 10B are diagrams showing an output circuit of a turn-on signal and a truth table showing the correspondence between input and output signals in the gate drive circuit 30 of Fig. 9. As shown in Fig. 10A, the gate drive circuit 30 of this embodiment includes logic circuits, an XOR circuit 31 and an AND circuit 32, switch circuits SW1 and SW2, and a soft turn-on gate resistor Ron2.

[0050] The XOR circuit 31 receives the drive signal INA and the inverted / non-inverted selection signal INB as input signals and calculates the exclusive OR of these input signals. The AND circuit 32 receives the output of the XOR circuit 31 and the inverted value of the enable signal ENA as input signals and calculates the logical product of these input signals. The switch circuit SW1 is connected between the power supply terminal VCC2 and the gate output terminal OUT and switches their connection state according to the output of the AND circuit 32. The switch circuit SW2 is connected between the power supply terminal VCC2 and the gate output terminal OUT via a soft turn-on gate resistor Ron2 and switches their connection state according to the enable signal ENA. The switch circuits SW1 and SW2 are configured using, for example, JFETs (junction field effect transistors). Note that the resistance value of the soft turn-on gate resistor Ron2 is preferably sufficiently larger (e.g., 10 times or more) than the turn-on gate resistor Ron1.

[0051] In the gate drive circuit 30 of this embodiment, with the circuit configuration described above, the voltage level (H level or L level) of the gate signal output from the gate output terminal OUT is determined as shown in the truth table of FIG. 10( b) according to the voltage levels of the drive signal INA, the inverted / non-inverted selection signal INB, and the enable signal ENA, which are respectively input as control signals from the control circuit 2. That is, when the enable signal ENA is at an L level, the state of the switch circuit SW1 switches according to the combination of the drive signal INA and the inverted / non-inverted selection signal INB, and a L level or H level gate signal is output from the gate output terminal OUT. On the other hand, when the enable signal ENA is at an H level, regardless of the combination of the drive signal INA and the inverted / non-inverted selection signal INB, the switch circuit SW1 is OFF and the switch circuit SW2 is ON, and a H level gate signal is output from the gate output terminal OUT.

[0052] Here, the gate signal output when the enable signal ENA is at H level passes through the soft turn-on gate resistor Ron2 in addition to the turn-on gate resistor Ron1. Therefore, the switching speed at the time of turning on the semiconductor switching element 11 can be made sufficiently slower than the gate signal output when the enable signal ENA is at L level. This allows the aforementioned soft turn-on function to be realized.

[0053] As described above, in the power conversion device 100 of this embodiment, by setting the enable signal ENA output from the control circuit 2 to each gate drive circuit 30 of the drive circuit 3 corresponding to either the upper or lower arm to H level, it is possible to execute three-phase short processing while activating the soft turn-on function.

[0054] According to the first embodiment of the present invention described above, the following advantageous effects are achieved.

[0055] (1) The power conversion device 100 converts DC power into three-phase AC power and includes an inverter circuit 1 having a plurality of semiconductor switching elements 11 corresponding to upper and lower arms of each phase of the three-phase AC power, a control circuit 2 that outputs a control signal for controlling the drive state of the inverter circuit 1, and a drive circuit 3 that applies a gate voltage to a gate terminal of the semiconductor switching element 11 based on the control signal from the control circuit 2, thereby causing the semiconductor switching element 11 to perform a switching operation and drive the inverter circuit 1. The drive circuit 3 is capable of switching the switching speed of the semiconductor switching element 11. When the motor 300 enters a regenerative state and the voltage HVDC of the DC power becomes equal to or higher than a predetermined threshold Vth, the control circuit 2 detects an overvoltage of the inverter circuit 1 (step S20: Yes). When an overvoltage is detected in the inverter circuit 1, an all-phase open process is executed to turn off all of the semiconductor switching elements 11 included in the inverter circuit 1 (step S30), and then a soft turn-on function is enabled (step S40) to execute a three-phase short process to turn on the semiconductor switching elements 11 corresponding to one of the upper and lower arms of each phase of the inverter circuit 1 (step S50). When the soft turn-on function is enabled, the drive circuit 3 switches the switching speed of the semiconductor switching elements 11 corresponding to one of the arms when the control circuit 2 executes the three-phase short process so that the switching speed at which the control circuit 2 turns on the semiconductor switching elements 11 is slower than the switching speed at which the control circuit 2 turns on the semiconductor switching elements before the control circuit 2 detected the overvoltage. This configuration makes it possible to suppress the occurrence of a recovery surge while avoiding a decrease in power conversion efficiency in the power conversion device 100 that converts DC power to AC power.

[0056] (2) The semiconductor switching element 11 can be a SiC-MOSFET, which can suppress recovery surges while suppressing switching losses during normal operation.

[0057] (3) The drive circuit 3 changes the switching speed of the semiconductor switching element 11 by changing the resistance value of the gate resistor connected to the gate terminal when the semiconductor switching element 11 is turned on. Specifically, a first gate resistor (turn-on gate resistor Ron1) is connected between each gate drive circuit 30 of the drive circuit 3 and the gate terminal of the semiconductor switching element 11. Each gate drive circuit 30 of the drive circuit 3 has: a power supply terminal VCC2 to which a power supply voltage is applied; a first switching circuit (switch circuit SW1) that switches the conduction state between the power supply terminal VCC2 and the turn-on gate resistor Ron1 in response to control signals (drive signal INA, inverted / non-inverted selection signal INB, and enable signal ENA) input from the control circuit 2; and a second switching circuit (switch circuit SW2) that is connected between the power supply terminal VCC2 and the turn-on gate resistor Ron1 via a second gate resistor (soft turn-on gate resistor Ron2) and switches the conduction state between the power supply terminal VCC2 and the turn-on gate resistor Ron1 in response to the enable signal ENA. Before the control circuit 2 detects an overvoltage, the enable signal ENA is set to an L level, causing the switch circuit SW1 to apply a gate voltage corresponding to the drive signal INA and the inverted / non-inverted selection signal INB to the gate terminal. On the other hand, when the control circuit 2 executes three-phase short processing, the enable signal ENA is set to an H level, causing the switch circuit SW2 to apply a gate voltage corresponding to the enable signal ENA to the gate terminal. This allows the drive circuit 3 to achieve a soft turn-on function that slows the switching speed of the semiconductor switching element 11 when three-phase short processing is executed.

[0058] Second Embodiment Next, a second embodiment of the present invention will be described below. In this embodiment, an example will be described in which a soft turn-on function is realized using a gate drive circuit 30A having a circuit configuration different from that of the gate drive circuit 30 described in the first embodiment.

[0059] Fig. 11 is a diagram showing the circuit configuration between each semiconductor switching element 11 and a gate drive circuit 30A in a power conversion device 100 according to a second embodiment of the present invention. In the power conversion device 100 of this embodiment, each gate drive circuit 30A of the drive circuit 3 provided corresponding to the plurality of semiconductor switching elements 11 included in the inverter circuit 1 has the configuration shown in Fig. 11. This gate drive circuit 30A differs from the gate drive circuit 30 of Fig. 9 described in the first embodiment in that it further has an input terminal for a soft turn-on enable signal ENB.

[0060] A signal instructing the gate drive circuit 30A to enable or disable the soft turn-on function is input from the control circuit 2 to the input terminal of the soft turn-on enable signal ENB as a soft turn-on enable signal ENB included in the control signal. That is, in this embodiment, a dedicated soft turn-on enable signal ENB can be used instead of the enable signal ENA to select whether the gate drive circuit 30A will use the soft turn-on function. Note that in this embodiment, the enable signal ENA is used not to enable the soft turn-on function, but rather to enable (enable) or disable (disable) the PWM signal output from the gate drive circuit 30A.

[0061] Fig. 12 shows an output circuit of a turn-on signal and a truth table showing the correspondence between input and output signals in the gate drive circuit 30A of Fig. 11. As shown in Fig. 12(a), the gate drive circuit 30A of this embodiment has logic circuits, an XOR circuit 31 and an AND circuit 33, switch circuits SW1 and SW2, and a soft turn-on gate resistor Ron2.

[0062] As in the first embodiment, the XOR circuit 31 receives the drive signal INA and the inverted / non-inverted selection signal INB as input signals and calculates the exclusive OR of these input signals. The AND circuit 33 is provided in the gate drive circuit 30A of this embodiment in place of the AND circuit 32 in Fig. 10, and receives the output of the XOR circuit 31, the enable signal ENA, and the inverted value of the soft turn-on enable signal ENB as input signals and calculates the logical AND of these input signals.

[0063] In the gate drive circuit 30A of this embodiment, with the circuit configuration described above, the voltage level (H level or L level) of the gate signal output from the gate output terminal OUT is determined as shown in the truth table of FIG. 12(b) according to the voltage levels of the drive signal INA, inverted / non-inverted selection signal INB, enable signal ENA, and soft turn-on enable signal ENB, which are input as control signals from the control circuit 2. That is, when the enable signal ENA is H level, the state of the switch circuit SW1 switches according to the combination of the drive signal INA and the inverted / non-inverted selection signal INB, and a L level or H level gate signal is output from the gate output terminal OUT. On the other hand, when the enable signal ENA and the soft turn-on enable signal ENB are L level, both switch circuits SW1 and SW2 are OFF, and a L level gate signal is output from the gate output terminal OUT, regardless of the combination of the drive signal INA and the inverted / non-inverted selection signal INB. On the other hand, when the soft turn-on enable signal ENB is at H level, regardless of the combination of the enable signal ENA, the drive signal INA, and the inverted / non-inverted selection signal INB, the switch circuit SW1 is turned OFF and the switch circuit SW2 is turned ON, and an H level gate signal is output from the gate output terminal OUT.

[0064] Here, the gate signal output when the soft turn-on enable signal ENB is at H level passes through the soft turn-on gate resistor Ron2 in addition to the turn-on gate resistor Ron1. Therefore, the switching speed at the time of turning on the semiconductor switching element 11 can be made sufficiently slower than the gate signal output when the soft turn-on enable signal ENB is at L level. This allows the soft turn-on function described above to be realized.

[0065] As described above, in the power conversion device 100 of this embodiment, by setting the soft turn-on enable signal ENB output from the control circuit 2 to each gate drive circuit 30A of the drive circuit 3 corresponding to either the upper or lower arm at H level, it is possible to execute three-phase short processing while activating the soft turn-on function. Furthermore, even when the enable signal ENA is set to L level, by setting the soft turn-on enable signal ENB to L level, it is possible to always set the gate signal output from the gate output terminal OUT to L level regardless of the combination of the drive signal INA and the inverted / non-inverted selection signal INB.

[0066] According to the second embodiment of the present invention described above, the same effects as those of the first embodiment are achieved.

[0067] Third Embodiment Next, a third embodiment of the present invention will be described below. In this embodiment, an example will be described in which a soft turn-on function is realized using a gate drive circuit 30B having a circuit configuration different from the gate drive circuits 30 and 30A described in the first and second embodiments, respectively.

[0068] Fig. 13 is a diagram showing the circuit configuration between each semiconductor switching element 11 and a gate drive circuit 30B in a power conversion device 100 according to a third embodiment of the present invention. In the power conversion device 100 of this embodiment, each gate drive circuit 30B of the drive circuit 3 provided corresponding to the plurality of semiconductor switching elements 11 included in the inverter circuit 1 has the configuration shown in Fig. 13. This gate drive circuit 30B differs from the gate drive circuit 30 of Fig. 9 described in the first embodiment in that it further has an output terminal for the soft turn-on signal STON.

[0069] The output terminal of the soft turn-on signal STON is connected to the gate terminal of the semiconductor switching element 11 via the soft turn-on gate resistor Ron2 described in the first and second embodiments. In the gate drive circuit 30B, when the enable signal ENA goes high and the soft turn-on function is enabled, the soft turn-on signal STON is used to turn on the semiconductor switching element 11, rather than the gate signal output from the gate output terminal OUT. That is, in the power conversion device 100 of this embodiment, the soft turn-on function can be realized in the gate drive circuit 30B by using the soft turn-on signal STON output from a dedicated terminal instead of the gate output terminal OUT.

[0070] According to the third embodiment of the present invention described above, the drive circuit 3 switches the switching speed of the semiconductor switching element 11 by changing the resistance value of the gate resistor connected to the gate terminal when the semiconductor switching element 11 is turned on. Specifically, each gate drive circuit 30B of the drive circuit 3 has a first output terminal (gate output terminal OUT) connected to the gate terminal of the semiconductor switching element 11 via a first gate resistor (turn-on gate resistor Ron1) and a second output terminal (output terminal for the soft turn-on signal STON) connected to the gate terminal via a second gate resistor (soft turn-on gate resistor Ron2) having a resistance value greater than that of the turn-on gate resistor Ron1. Before the control circuit 2 detects an overvoltage, the enable signal ENA is set to an L level, thereby applying a gate voltage corresponding to the drive signal INA and the inverted / non-inverted selection signal INB to the gate terminal using the gate output terminal OUT. On the other hand, when the control circuit 2 executes three-phase short processing, the enable signal ENA is set to an H level, and the output terminal for the soft turn-on signal STON is used to apply a gate voltage corresponding to the enable signal ENA to the gate terminal. As a result, similar to the first and second embodiments, the drive circuit 3 can achieve a soft turn-on function that slows the switching speed of the semiconductor switching element 11 when three-phase short processing is executed. Furthermore, by implementing the soft turn-on function using a terminal other than the gate output terminal OUT that is normally used, it is possible to provide redundancy in the control of the semiconductor switching element 11 and improve availability.

[0071] Fourth Embodiment Next, a fourth embodiment of the present invention will be described below. In this embodiment, an example will be described in which a soft turn-on function is realized using a gate drive circuit 30C having a circuit configuration different from the gate drive circuits 30, 30A, and 30B described in the first to third embodiments, respectively.

[0072] Fig. 14 is a diagram showing the circuit configuration between each semiconductor switching element 11 and a gate drive circuit 30C in a power conversion device 100 according to a fourth embodiment of the present invention. In the power conversion device 100 of this embodiment, each gate drive circuit 30C of the drive circuit 3 provided corresponding to the plurality of semiconductor switching elements 11 included in the inverter circuit 1 has the configuration shown in Fig. 14. This gate drive circuit 30C differs from the gate drive circuit 30 of Fig. 9 described in the first embodiment in that it has a soft output terminal STOUT instead of an output terminal for the soft turn-off signal STOFF.

[0073] The soft output terminal STOUT is a terminal used in common for the soft turn-on function and the soft turn-off function described above, and is connected to the gate terminal of the semiconductor switching element 11 via the soft turn-on gate resistor Ron2 and the soft turn-off gate resistor Roff2. That is, in the gate drive circuit 30C, when the enable signal ENA goes high to enable the soft turn-on function, an H-level signal is output from the soft output terminal STOUT via the soft turn-on gate resistor Ron2, thereby turning on the semiconductor switching element 11. Furthermore, when the semiconductor switching element 11 is short-circuited, an L-level signal is output from the soft output terminal STOUT via the soft turn-off gate resistor Roff2, thereby turning off the semiconductor switching element 11. As a result, in the power conversion device 100 of this embodiment, the soft output terminal STOUT can be used in common for both the soft turn-on function and the soft turn-off function in the gate drive circuit 30C. To achieve these functions, the gate drive circuit 30C is configured such that the connection destination of the soft output terminal STOUT can be switched between the power supply terminal VCC2 and the ground terminal GND2.

[0074] According to the fourth embodiment of the present invention described above, the drive circuit 3 has a first output terminal (gate output terminal OUT) that applies a gate voltage to the gate terminal of the semiconductor switching element 11 so that the switching speed at the time of turning off the semiconductor switching element 11 is a first switching speed corresponding to the resistance value of the turn-off gate resistor Roff1, and a second output terminal (soft output terminal STOUT) that applies a gate voltage to the gate terminal so that the switching speed at the time of turning off the semiconductor switching element 11 is a second switching speed that is slower than the first switching speed and corresponds to the resistance value of the soft turn-off gate resistor Roff2. When the control circuit 2 executes three-phase short processing, it uses the soft output terminal STOUT to apply a gate voltage corresponding to the enable signal ENA to the gate terminal, thereby turning on the semiconductor switching element 11 corresponding to one of the arms. As a result, similar to the first to third embodiments, the drive circuit 3 can achieve a soft turn-on function that slows the switching speed of the semiconductor switching element 11 when executing three-phase short processing. Furthermore, by sharing the soft output terminal STOUT to realize the soft turn-off function and the soft turn-on function, it is possible to simplify the circuit configuration.

[0075] In the third and fourth embodiments described above, the soft turn-on signal STON is output in response to the enable signal ENA, as in the first embodiment, but as in the second embodiment, an input terminal for the soft turn-on enable signal ENB may be provided and the soft turn-on signal STON may be output in response to the soft turn-on enable signal ENB input to this input terminal. This also achieves the above-described advantageous effects.

[0076] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. Furthermore, the above-described configurations, functions, processing units, processing means, etc. may be implemented in hardware, in part or in whole, by, for example, designing them as integrated circuits. Furthermore, the above-described configurations, functions, etc. may be implemented in software, by a processor interpreting and executing a program that realizes each function. Information such as programs, tables, and files that realize each function may be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card, SD card, or DVD.

[0077] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0078] 1: inverter circuit, 2: control circuit, 3: drive circuit, 4: voltage smoothing capacitor, 5: voltage detection circuit, 11: semiconductor switching element, 12: diode, 30, 30A, 30B, 30C: gate drive circuit, 61, 62: current sensor, 200: DC battery, 201: contactor, 300: motor, 301: rotational position sensor, Ron1: turn-on gate resistor, Roff1: turn-off gate resistor, Ron2: soft turn-on gate resistor, Roff2: soft turn-off gate resistor

Claims

1. A power conversion device that converts DC power into three-phase AC power, comprising: - an inverter circuit having a plurality of semiconductor switching elements respectively corresponding to upper and lower arms of each phase of the three-phase AC power; - a control circuit that outputs a control signal for controlling the driving state of the inverter circuit; - a driving circuit that drives the inverter circuit by applying a gate voltage to the gate terminals of the semiconductor switching elements based on the control signal from the control circuit to cause the semiconductor switching elements to perform a switching operation, - wherein the driving circuit can switch the switching speed of the semiconductor switching elements, - and the control circuit: - when the voltage of the DC power becomes equal to or higher than a predetermined threshold, detects an overvoltage in the inverter circuit; - when detecting the overvoltage, executes a full-phase open process of turning off all the semiconductor switching elements included in the inverter circuit; - after executing the full-phase open process, executes a three-phase short process of turning on the semiconductor switching element corresponding to one of the upper and lower arms of each phase of the inverter circuit, - and the driving circuit switches the switching speed of the semiconductor switching elements such that the switching speed at the time of turning on the semiconductor switching element corresponding to the one arm when the control circuit executes the three-phase short process is slower than the switching speed at the time of turning on the semiconductor switching element before the control circuit detects the overvoltage.

2. The power conversion device according to claim 1, wherein the semiconductor switching element is a SiC-MOSFET.

3. The power conversion device according to claim 1, wherein the driving circuit switches the switching speed of the semiconductor switching elements by changing the resistance value of a gate resistor connected to the gate terminal at the time of turning on the semiconductor switching element.

4. In the power conversion device according to claim 3, a first gate resistor is connected between the drive circuit and the gate terminal, and the drive circuit includes a power supply terminal to which a power supply voltage is applied, a first switching circuit that switches the conduction state between the power supply terminal and the first gate resistor according to the control signal, and a second switching circuit that is connected between the power supply terminal and the first gate resistor via a second gate resistor and switches the conduction state between the power supply terminal and the first gate resistor according to the control signal. Before the control circuit detects the overvoltage, the first switching circuit is used to apply the gate voltage corresponding to the control signal to the gate terminal. When the control circuit executes the three-phase short-circuit process, the second switching circuit is used to apply the gate voltage corresponding to the control signal to the gate terminal.

5. In the power conversion device according to claim 3, the drive circuit includes a first output terminal connected to the gate terminal via a first gate resistor, and a second output terminal connected to the gate terminal via a second gate resistor having a resistance value larger than that of the first gate resistor. Before the control circuit detects the overvoltage, the first output terminal is used to apply the gate voltage corresponding to the control signal to the gate terminal. When the control circuit executes the three-phase short-circuit process, the second output terminal is used to apply the gate voltage corresponding to the control signal to the gate terminal.

6. In the power conversion device according to claim 1, the drive circuit includes a first output terminal that applies the gate voltage to the gate terminal so that the switching speed at the turn-off of the semiconductor switching element becomes a first switching speed, and a second output terminal that applies the gate voltage to the gate terminal so that the switching speed at the turn-off of the semiconductor switching element becomes a second switching speed slower than the first switching speed. When the control circuit executes the three-phase short-circuit process, the second output terminal is used to apply the gate voltage corresponding to the control signal to the gate terminal, thereby turning on the semiconductor switching element corresponding to the one arm.

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