Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a first semiconductor element; a support body positioned on a first side in a first direction relative to the first semiconductor element; a first bonding sheet interposed between the first semiconductor element and the support body; and a sealing resin covering the first semiconductor element. Solid-state diffusion bonding is used to bond the first semiconductor element and the first bonding sheet, and to bond the first bonding sheet and the support body. The support body has a first main surface facing a second side in the first direction and a first recessed portion recessed from the first main surface toward the first side in the first direction. The first bonding sheet is accommodated in the first recessed portion when viewed in the first direction.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a support substrate and a semiconductor element. The semiconductor element is bonded by solid-state diffusion bonding via an intermediate metal layer.

[0003] JP 2022-63488 A

[0004] [Summary] If the bonding of a semiconductor element is insufficient, the semiconductor device may not be able to fully function.

[0005] An object of the present disclosure is to provide an improved semiconductor device and a method for manufacturing the same, particularly in view of the above circumstances, a semiconductor device and a method for manufacturing the same that can more appropriately bond semiconductor elements.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a first semiconductor element; a support member located on a first side in a first direction relative to the first semiconductor element; a first bonding sheet interposed between the first semiconductor element and the support member; and a sealing resin covering the first semiconductor element. The first semiconductor element and the first bonding sheet, and the first bonding sheet and the support member are each bonded by solid-state diffusion bonding. The support member has a first main surface facing a second side in the first direction and a first recess recessed from the first main surface toward the first side in the first direction. The first bonding sheet is housed in the first recess when viewed in the first direction.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes the steps of: pressing a main surface of a support body toward a first side in a first direction to form a first recess that is recessed from the main surface toward the first side in the first direction; placing a first bonding sheet so that the first semiconductor element is accommodated in the first recess when viewed in the first direction; placing a first semiconductor element on the first bonding sheet; and bonding the first semiconductor element and the first bonding sheet to the first bonding sheet and the support body by solid-state diffusion bonding.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a partial cross-sectional view taken along line V-V in FIG. 4. FIG. 6 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial cross-sectional view taken along line IX-IX in FIG. 8. FIG. 10 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a system configuration diagram showing a vehicle equipped with a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 13 is a partial enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a partial enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 16 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 20 is a partially enlarged cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 21 is a partially enlarged plan view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 22 is a partially enlarged cross-sectional view taken along line XXII-XXII of FIG. 21. FIG. 23 is a partially enlarged cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 25 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 26 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 27 is a perspective view showing a semiconductor device according to a third embodiment of the present disclosure.Fig. 28 is a partial perspective view showing a semiconductor device according to a third embodiment of the present disclosure. Fig. 29 is a partial perspective view showing a semiconductor device according to the third embodiment of the present disclosure. Fig. 30 is a partial plan view showing a semiconductor device according to the third embodiment of the present disclosure. Fig. 31 is a partial plan view showing a semiconductor device according to the third embodiment of the present disclosure. Fig. 32 is a partial plan view showing a semiconductor device according to the third embodiment of the present disclosure.

[0010] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0013] 1 to 10 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a support 1, one or more first semiconductor elements 5A, one or more first bonding sheets 6A, and a sealing resin 9. In this embodiment, the semiconductor device A1 may further include one or more second semiconductor elements 5B, one or more second bonding sheets 6B, a positive input terminal 7A, an output terminal 7B, a negative input terminal 7C, a plurality of control terminals 7D, a plurality of control terminals 7E, a plurality of first conductive members 8A, a plurality of second conductive members 8B, a plurality of third conductive members 8C, and a plurality of fourth conductive members 8D.

[0014] The number of one or more first semiconductor elements 5A and one or more second semiconductor elements 5B is not limited in any way. In this embodiment, the semiconductor device A1 may include a plurality of first semiconductor elements 5A and a plurality of second semiconductor elements 5B. The number of one or more first bonding sheets 6A and one or more second bonding sheets 6B is not limited in any way. In this embodiment, the semiconductor device A1 may include a plurality of first bonding sheets 6A and a plurality of second bonding sheets 6B.

[0015] In FIGS. 1 to 7 , for example, the thickness direction of the support 1 is referred to as the first direction z in the present disclosure. One side of the first direction z is referred to as the first side z1, and the other side is referred to as the second side z2. Furthermore, for example, a direction perpendicular to the first direction z is referred to as the second direction x. One side of the second direction x is referred to as the first side x1, and the other side is referred to as the second side x2. Furthermore, for example, a direction perpendicular to the first direction z and the second direction x is referred to as the third direction y. One side of the third direction y is referred to as the first side y1, and the other side is referred to as the second side y2. For ease of understanding, the positive input terminal 7A, the output terminal 7B, the negative input terminal 7C, the plurality of control terminals 7E and 7D, the plurality of first conductive members 8A, the plurality of second conductive members 8B, the plurality of third conductive members 8C, and the plurality of fourth conductive members 8D are omitted as appropriate in FIGS. 2 to 10 .

[0016] The specific use of the semiconductor device A1 is not limited in any way. In the semiconductor device A1, a half-bridge circuit may be configured by a plurality of first semiconductor elements 5A configuring an upper arm circuit and a plurality of second semiconductor elements 5B configuring a lower arm circuit. The semiconductor device A1 may, for example, configure an inverter that converts DC power to AC power and supplies power to a drive source such as a motor. Although the semiconductor device A1 of this embodiment will be described using an example in which it has one half-bridge circuit, it may also be configured to supply power to a so-called three-phase AC motor by having, for example, three half-bridge circuits.

[0017] Each of the multiple first semiconductor elements 5A and the multiple second semiconductor elements 5B is configured using a semiconductor material. The semiconductor material may be SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. In this embodiment, the first semiconductor elements 5A and the second semiconductor elements 5B may be MOSFETs (metal-oxide-semiconductor field-effect transistors). The first semiconductor elements 5A and the second semiconductor elements 5B are not limited to MOSFETs and may be field-effect transistors including MISFETs (metal-insulator-semiconductor FETs), bipolar transistors such as IGBTs (insulated gate bipolar transistors), IC chips such as LSIs, diodes, capacitors, or the like.

[0018] As shown in FIGS. 4 to 10 , the first semiconductor element 5A and the second semiconductor element 5B of this embodiment may have an element body 50, a first electrode 51, a second electrode 52, a third electrode 53, and a fourth electrode 54. The element body 50 may be made of the semiconductor material described above. The first electrode 51 may be disposed on a first side z1 of the element body 50 in the first direction z. The second electrode 52, the third electrode 53, and the fourth electrode 54 may be disposed on a second side z2 of the element body 50 in the first direction z. When the first semiconductor element 5A and the second semiconductor element 5B are MOSFETs, the first electrode 51 may be a drain electrode, the second electrode 52 may be a source electrode, the third electrode 53 may be a gate electrode, and the fourth electrode 54 may be a source sense electrode.

[0019] The first electrode 51 may have a third base material layer 510 and a fourth bonding layer 511. The third base material layer 510 may include a metal such as Cu (copper), Au (gold), or Ni (nickel). The fourth bonding layer 511 is located on a first side z1 in the first direction z of the third base material layer 510. The fourth bonding layer 511 may include a metal such as Ag (silver), Au (gold), or the like. The thickness of the fourth bonding layer 511 is thinner than that of the third base material layer 510. The thickness of the third base material layer 510 may be, for example, not less than 0.01 μm and not more than 5 μm. The thickness of the fourth bonding layer 511 may be, for example, not less than 0.1 μm and not more than 10 μm.

[0020] There is no limitation on the specific configuration of the support 1. As shown in Fig. 3, the support 1 of this embodiment can have an insulating layer 10, a back surface metal layer 11, a first main surface metal layer 2A, and a second main surface metal layer 2B.

[0021] The insulating layer 10 may be an insulating plate-like member containing, for example, ceramic. The back surface metal layer 11 may be stacked on a first side z1 in the first direction z of the insulating layer 10. The back surface metal layer 11 may contain a metal such as Cu (copper). The first main surface metal layer 2A may be stacked on a second side z2 in the first direction z of the insulating layer 10 on a first side x1 in the second direction x. The second main surface metal layer 2B may be stacked on a second side z2 in the first direction z of the insulating layer 10 on a second side x2 in the second direction x. The first main surface metal layer 2A and the second main surface metal layer 2B are separated from each other and may each contain a metal such as Cu (copper). The insulating layer 10, the back surface metal layer 11, the first main surface metal layer 2A, and the second main surface metal layer 2B may form, for example, a DBC (Direct Bonded Copper) substrate, an AMB (Active Metal Brazing) substrate, or the like.

[0022] 6 and 10 , the first main surface metal layer 2A and the second main surface metal layer 2B may have a second base material layer 20 and a third bonding layer 21, respectively. The second base material layer 20 may contain a metal such as Cu (copper). The third bonding layer 21 may contain a metal such as Ag (silver) or Au (gold). The thickness of the second base material layer 20 may be, for example, 0.5 mm or more and 5 mm or less. The thickness of the third bonding layer 21 may be, for example, 0.1 μm or more and 10 μm or less.

[0023] As shown in FIGS. 2 and 4 to 6 , the support 1 has a first main surface 1A and one or more first recesses 100A. The first main surface 1A is a surface facing a second side z2 in the first direction z. In the illustrated example, the first main surface 1A is formed by a first main surface metal layer 2A. The one or more first recesses 100A are recessed from the first main surface 1A toward a first side z1 in the first direction z. The number of the one or more first recesses 100A is not limited, and in the illustrated example, the number of the one or more first recesses 100A may be four. The shape of the first recesses 100A is not limited in any way, and in the illustrated example, it may be rectangular.

[0024] The multiple first semiconductor elements 5A are conductively bonded to the first main surface metal layer 2A via multiple first bonding sheets 6A. In this embodiment, the fourth bonding layer 511 of the first electrode 51 of the first semiconductor element 5A is conductively bonded to the first main surface metal layer 2A via the first bonding sheet 6A. The first bonding sheet 6A is used to conductively bond the first semiconductor element 5A and the first main surface metal layer 2A by solid-state diffusion bonding. The first bonding sheet 6A is housed in the first recess 100A as viewed in the first direction z. The first recess 100A may be larger than the first bonding sheet 6A as viewed in the first direction z.

[0025] The specific configuration of the first bonding sheet 6A is not limited in any way. As shown in FIG. 6 , the first bonding sheet 6A may include a first base layer 60, a first bonding layer 61, and a second bonding layer 62. The material of the first base layer 60 may be softer than the second base layer 20 of the first main surface metal layer 2A and the second main surface metal layer 2B. The first base layer 60 may include, for example, Al (aluminum). The first bonding layer 61 is located on a first side z1 in the first direction z relative to the first base layer 60. The first bonding layer 61 may include, for example, a metal such as Ag (silver) or Au (gold). The second bonding layer 62 is located on a second side z2 in the first direction z relative to the first base layer 60. The second bonding layer 62 may include, for example, a metal such as Ag (silver) or Au (gold). The thickness of the first base layer 60 may be, for example, 30 μm or more and 300 μm or less. The thickness of the first bonding layer 61 may be, for example, 0.1 μm or more and 10 μm or less. The thickness of the second bonding layer 62 may be, for example, 0.1 μm or more and 10 μm or less. In the illustrated example, the thickness ta of the first bonding sheet 6A may be greater than the depth da of the first recess 100A. In other words, the first semiconductor element 5A may be located on the second side z2 of the first main surface 1A in the first direction z. The thickness ta of the first bonding sheet 6A may be, for example, 30 μm or more and 320 μm or less. The depth da of the first recess 100A may be 20 μm or more and 300 μm or less.

[0026] 6 , in the illustrated example, the first bonding layer 61 of the first bonding sheet 6A and the third bonding layer 21 of the first main surface metal layer 2A may be bonded by solid-state diffusion bonding. The second bonding layer 62 of the first bonding sheet 6A and the fourth bonding layer 511 of the first semiconductor element 5A may be bonded by solid-state diffusion bonding. The bonding interface of the solid-state diffusion bonding may not have a clear boundary.

[0027] As shown in FIG. 6 , the first recess 100A may have a bottom surface 101 and an inner surface 102. The bottom surface 101 faces the second side z2 in the first direction z. The inner surface 102 is located between the bottom surface 101 and the first main surface 1A in the first direction z. In the illustrated example, a portion of the sealing resin 9 may be filled between the first bonding sheet 6A and the inner surface 102. As shown in FIG. 7 , the semiconductor device A1 may be configured such that the sealing resin 9 is not filled between the first bonding sheet 6A and the inner surface 102.

[0028] As shown in FIGS. 2 and 8 to 10 , the support 1 has a second main surface 1B and one or more second recesses 100B. The second main surface 1B is a surface facing a second side z2 in the first direction z. In the illustrated example, the second main surface 1B is formed by a second main surface metal layer 2B. The one or more second recesses 100B are recessed from the second main surface 1B toward a first side z1 in the first direction z. The number of the one or more second recesses 100B is not limited, and in the illustrated example, the number of the one or more second recesses 100B may be four. The shape of the second recesses 100B is not limited in any way, and in the illustrated example, it may be rectangular.

[0029] The plurality of second semiconductor elements 5B are conductively bonded to the second main surface metal layer 2B via a plurality of second bonding sheets 6B. In this embodiment, the fourth bonding layer 511 of the first electrode 51 of the second semiconductor element 5B is conductively bonded to the second main surface metal layer 2B via the second bonding sheet 6B. The second bonding sheet 6B is used to conductively bond the second semiconductor element 5B and the second main surface metal layer 2B by solid-state diffusion bonding. The second bonding sheet 6B is housed in the second recess 100B as viewed in the first direction z. The second recess 100B may be larger than the second bonding sheet 6B as viewed in the first direction z.

[0030] The specific configuration of the second bonding sheet 6B is not limited in any way. As shown in FIG. 10 , the second bonding sheet 6B may include a first base layer 60, a first bonding layer 61, and a second bonding layer 62, similar to the first bonding sheet 6A. In the illustrated example, the thickness tb of the second bonding sheet 6B may be greater than the depth db of the second recess 100B. In other words, the second semiconductor element 5B may be located on the second side z2 of the second main surface 1B in the first direction z. The thickness tb of the second bonding sheet 6B may be, for example, 30 μm or more and 320 μm or less. The depth db of the second recess 100B may be 20 μm or more and 300 μm or less.

[0031] 10 , in the illustrated example, the first bonding layer 61 of the second bonding sheet 6B and the third bonding layer 21 of the second main surface metal layer 2B may be bonded by solid-state diffusion bonding. The second bonding layer 62 of the second bonding sheet 6B and the fourth bonding layer 511 of the second semiconductor element 5B may be bonded by solid-state diffusion bonding. The bonding interface of the solid-state diffusion bonding may not have a clear boundary.

[0032] 10 , like the first recess 100A, the second recess 100B may have a bottom surface 101 and an inner surface 102. In the illustrated example, a portion of the sealing resin 9 may be filled between the second bonding sheet 6B and the inner surface 102.

[0033] The positive input terminal 7A may be a terminal connected to the positive side of a DC power supply, and may be conductively joined to the third main surface metal layer 3A.

[0034] The output terminal 7B may be a terminal connected to the load side of a motor, etc. The output terminal 7B may be conductively joined to the fourth main surface metal layer 3B.

[0035] The negative input terminal 7C may be a terminal connected to the negative side of a DC power supply. The negative input terminal 7C may be electrically connected to, for example, the second electrodes 52 of the second semiconductor elements 5B via the second conductive members 8B. The second conductive members 8B may be, for example, wires and may contain metals such as copper (Cu), aluminum (Al), and gold (Au).

[0036] For example, the second electrodes 52 of the multiple first semiconductor elements 5A can be electrically connected to the fourth main surface metal layer 3B via the multiple first conductive members 8A. The first conductive members 8A can be, for example, wires and can contain metals such as copper (Cu), aluminum (Al), and gold (Au).

[0037] The multiple control terminals 7D may be terminals for controlling the multiple first semiconductor elements 5A. The multiple control terminals 7D may be electrically connected to, for example, the third electrodes 53, the fourth electrodes 54, etc. of the multiple first semiconductor elements 5A via the multiple third conductive members 8C. The third conductive members 8C may be, for example, wires and may contain metals such as copper (Cu), aluminum (Al), and gold (Au).

[0038] The plurality of control terminals 7E may be terminals for controlling the plurality of second semiconductor elements 5B. The plurality of control terminals 7E may be electrically connected to, for example, the third electrodes 53, the fourth electrodes 54, etc. of the plurality of second semiconductor elements 5B via the plurality of fourth conductive members 8D. The fourth conductive members 8D may be, for example, wires and may contain metals such as copper (Cu), aluminum (Al), and gold (Au).

[0039] The sealing resin 9 may cover a portion of the support 1, the plurality of first semiconductor elements 5A, the plurality of second semiconductor elements 5B, etc. The positive input terminal 7A, the output terminal 7B, the negative input terminal 7C, the plurality of control terminals 7D, and the plurality of control terminals 7E each have a portion protruding from the sealing resin 9. As shown in FIG. 3 , the sealing resin 9 may have a resin main surface 91 and a resin back surface 92. The resin main surface 91 may be a surface facing the second side z2 in the first direction z. The resin back surface 92 may be a surface facing the first side z1 in the first direction z. The back surface metal layer 11 of the support 1 may be exposed from the resin back surface 92.

[0040] Next, a vehicle C1 equipped with the semiconductor device A1 will be described with reference to Fig. 11. The vehicle C1 is, for example, an electric vehicle (EV).

[0041] As shown in Fig. 11 , vehicle C1 includes an on-board charger 910, a storage battery 920, and a drive system 930. Power is supplied to the on-board charger 910 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 910 via a wired connection. The on-board charger 910 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 910 is stepped up by the converter and then supplied to the storage battery 920. The stepped-up voltage is, for example, 600 V.

[0042] The drive system 930 drives the vehicle C1. The drive system 930 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes part of the inverter 931. The power stored in the storage battery 920 is supplied to the inverter 931. The power supplied from the storage battery 920 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 11 , a step-up DC-DC converter may be further provided between the storage battery 920 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is electrically connected to the drive source 932.

[0043] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle C1. This drives the vehicle C1. To drive the vehicle C1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device A1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0044] Next, a method for manufacturing the semiconductor device A1 will be described.

[0045] 12 to 18 show an example of a method for manufacturing a semiconductor device A1. First, as shown in FIG. 12, a support 1 is prepared. Next, as shown in FIGS. 12 to 14, a tool T1 containing, for example, a metal or the like is pressed against the first main surface 1A and the second main surface 1B of the support 1. As a result, the first main surface metal layer 2A is partially pressed, forming a plurality of first recesses 100A. Furthermore, the second main surface metal layer 2B is partially pressed, forming a plurality of second recesses 100B.

[0046] 15 to 17, a plurality of first bonding sheets 6A are placed on the support body 1. At this time, the plurality of first bonding sheets 6A are placed so that the plurality of first bonding sheets 6A are individually accommodated in the plurality of first recesses 100A. Next, a plurality of first semiconductor elements 5A are placed on the plurality of first bonding sheets 6A. The plurality of first bonding sheets 6A and the plurality of first semiconductor elements 5A may be placed after the plurality of first bonding sheets 6A are placed, or the plurality of first bonding sheets 6A and the plurality of first semiconductor elements 5A may be placed simultaneously.

[0047] Furthermore, a plurality of second bonding sheets 6B are placed on the support body 1. At this time, the plurality of second bonding sheets 6B are placed so that the plurality of second bonding sheets 6B are individually accommodated in the plurality of second recesses 100B. Next, a plurality of second semiconductor elements 5B are placed on the plurality of second bonding sheets 6B. The plurality of second semiconductor elements 5B may be placed after the plurality of second bonding sheets 6B are placed, or the plurality of second bonding sheets 6B and the plurality of second semiconductor elements 5B may be placed simultaneously.

[0048] 18 , a pressing force along the first direction z and a predetermined temperature are applied to the support body 1, the plurality of first bonding sheets 6A, the plurality of second bonding sheets 6B, the plurality of first semiconductor elements 5A, and the plurality of second semiconductor elements 5B. As a result, the support body 1 and the plurality of first semiconductor elements 5A are bonded together by solid-state diffusion bonding with the plurality of first bonding sheets 6A sandwiched therebetween. The support body 1 and the plurality of second semiconductor elements 5B are bonded together by solid-state diffusion bonding with the plurality of second bonding sheets 6B sandwiched therebetween.

[0049] After this, the semiconductor device A1 is formed through processes such as attaching the positive input terminal 7A, the output terminal 7B, the negative input terminal 7C, the multiple control terminals 7D and the multiple control terminals 7E, bonding the multiple first conductive members 8A, the multiple second conductive members 8B, the multiple third conductive members 8C and the multiple fourth conductive members 8D, forming the sealing resin 9, etc.

[0050] Next, the operation of the semiconductor device A1 and the method for manufacturing the semiconductor device A1 will be described.

[0051] 4 to 6, the first bonding sheet 6A is accommodated in the first recess 100A. This makes it possible to prevent the first bonding sheet 6A from being unduly displaced relative to the support body 1 in the manufacturing process shown in FIG. 15. Therefore, the first semiconductor element 5A can be more appropriately bonded.

[0052] The first recess 100A is formed by pressing the first main surface metal layer 2A. As a result, compressive plastic strain may remain on the bottom surface 101 of the first recess 100A. When solid-phase diffusion bonding is performed on the surface where compressive plastic strain remains, the bonding condition may be improved.

[0053] 6 , a portion of the sealing resin 9 is filled between the first bonding sheet 6A and the inner surface 102. This makes it possible to more reliably insulate, for example, the element body 50 or the second electrode 52 of the first semiconductor element 5A from the support 1.

[0054] In this example, the thickness ta of the first bonding sheet 6A is greater than the depth da of the first recess 100A. For example, as shown in FIG. 7 , a configuration may occur in which the sealing resin 9 is not filled between the first bonding sheet 6A and the inner surface 102. In this case, the thickness ta being greater than the depth da prevents the void portion not filled with the sealing resin 9 from reaching the element body 50 of the first semiconductor element 5A, etc. Therefore, for example, the element body 50 or second electrode 52 of the first semiconductor element 5A can be more reliably insulated from the support 1. The configuration in which the first bonding sheet 6A is larger than the first semiconductor element 5A when viewed in the first direction z contributes to the above-mentioned improved insulation.

[0055] The above-described effects obtained by providing the first recess 100A can be similarly achieved by providing the second recess 100B.

[0056] 19 to 32 show modified examples and other embodiments of the present invention. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0057] 19 shows a first modification of the semiconductor device A1. While the figure shows a portion where a first semiconductor element 5A is bonded to a first main surface metal layer 2A via a first bonding sheet 6A, the illustrated configuration may also be applied to a portion where a second semiconductor element 5B is bonded to a second main surface metal layer 2B via a second bonding sheet 6B, and the same applies to subsequent modifications.

[0058] In the semiconductor device A11 of this modified example, the portion of the first bonding sheet 6A overlapping with the first semiconductor element 5A is thinner than the surrounding portion when viewed in the first direction z. This can occur when the first base layer 60 of the first bonding sheet 6A undergoes plastic deformation when the first semiconductor element 5A is pressed during solid-state diffusion bonding. The thickness ta2 of the portion of the first bonding sheet 6A overlapping with the first semiconductor element 5A is thinner than the thickness ta1 of the surrounding portion. In this modified example, the thickness ta2 may be greater than the depth da of the first recess 100A.

[0059] This modification allows the first semiconductor element 5A to be more appropriately bonded. Furthermore, as can be seen from this modification, the first bonding sheet 6A can be plastically deformed during the solid-state diffusion bonding process so that the portion overlapping the first semiconductor element 5A becomes locally thinner. If the thickness ta1 of the peripheral portion is greater than the depth da, the element body 50 or the second electrode 52 of the first semiconductor element 5A can be more reliably insulated from the support 1.

[0060] 20 shows a second modification of the semiconductor device A1. In the semiconductor device A12 of this modification, the thickness ta2 of the portion of the first bonding sheet 6A that overlaps with the first semiconductor element 5A as viewed in the first direction z may be smaller than the depth da of the first recess 100A.

[0061] This modification allows for more appropriate bonding of the first semiconductor element 5A. If the thickness ta1 of the peripheral portion is greater than the depth da, even if the thickness ta2 is smaller than the depth da, the element body 50 or the second electrode 52 of the first semiconductor element 5A can be more reliably insulated from the support 1.

[0062] Third Modification of First Embodiment: FIGS. 21 to 23 show a third modification of the semiconductor device A1. In a semiconductor device A13 of this modification, the support 1 may further include an insulating layer 105. The insulating layer 105 is made of an insulating material such as a resin applied to the first main surface metal layer 2A. The insulating layer 105 has a frame shape when viewed in the first direction z, and may have, for example, a rectangular frame shape. The first main surface 1A of this modification may be formed by the insulating layer 105. The bottom surface 101 of the first recess 100A may be formed by the third bonding layer 21 of the first main surface metal layer 2A, and the inner surface 102 may be formed by the insulating layer 105.

[0063] This modification allows the first semiconductor element 5A to be bonded more appropriately. As can be seen from this modification, the specific configuration for realizing the first recess 100A is not limited in any way. The same applies to the second recess 100B.

[0064] 24 to 26 show a semiconductor device according to a second embodiment of the present disclosure. In a semiconductor device A2 of this embodiment, the configuration of the support body 1 may differ from that of the above-described embodiment. The support body 1 of this embodiment may include a third main surface metal layer 3A, a fourth main surface metal layer 3B, a third bonding sheet 4A, and a fourth bonding sheet 4B.

[0065] The third main surface metal layer 3A is bonded to the first main surface metal layer 2A via a third bonding sheet 4A. The third main surface metal layer 3A may contain a metal such as Cu (copper). The third bonding sheet 4A is used to bond the first main surface metal layer 2A and the third main surface metal layer 3A by, for example, solid-state diffusion bonding. The specific configuration of the third bonding sheet 4A is not limited in any way, and it may be a configuration in which a metal layer containing, for example, Ag (silver) is formed on both sides of a base layer containing Al (aluminum).

[0066] The fourth main surface metal layer 3B is bonded to the second main surface metal layer 2B via a fourth bonding sheet 4B. The fourth main surface metal layer 3B may contain a metal such as Cu (copper). The fourth bonding sheet 4B is intended to bond the second main surface metal layer 2B and the fourth main surface metal layer 3B by, for example, solid-state diffusion bonding. The specific configuration of the fourth bonding sheet 4B is not limited in any way, and it may be configured such that, for example, a metal layer containing Ag (silver) is formed on both sides of a base layer containing Al (aluminum).

[0067] The first recess 100A of this embodiment may be formed by the third main surface metal layer 3A, and the second recess 100B of this embodiment may be formed by the fourth main surface metal layer 3B.

[0068] This embodiment allows the first semiconductor element 5A to be bonded more appropriately. As can be seen from this embodiment, there is no limitation on the specific configuration of the support 1. By providing the support 1 with the third main surface metal layer 3A, heat from the first semiconductor element 5A can be dissipated over a wider area in the second direction x and the third direction y.

[0069] 27 to 32 show a semiconductor device according to a third embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, the configuration of each part, including the configuration of the plurality of control terminals 7D and the plurality of control terminals 7E, may differ from the above-described embodiments. The semiconductor device A3 may include a first support portion 48A and a second support portion 48B.

[0070] The sealing resin 9 is omitted from Figures 28 to 32. The second conductive member 8B is omitted from Figures 29, 31 and 32. The first conductive member 8A is omitted from Figure 32.

[0071] The semiconductor device A3 may include one positive input terminal 7A, two output terminals 7B, and two negative input terminals 7C. The two negative input terminals 7C may be spaced apart from each other in the third direction y. The positive input terminal 7A may be located between the two negative input terminals 7C in the third direction y. The two output terminals 7B may be spaced apart from each other in the third direction y.

[0072] The first conductive member 8A may be formed by cutting and bending a metal plate material, for example, and the second conductive member 8B may be formed by cutting and bending a metal plate material, for example.

[0073] The multiple control terminals 7D are electrically connected to the multiple first semiconductor elements 5A via the first support portion 48A and the multiple third conductive members 8C. The first support portion 48A may be mounted on the first main surface 1A. The first support portion 48A may include, for example, an insulating layer and two conductive layers stacked in the first direction z with the insulating layer sandwiched therebetween. As shown in FIG. 31 , one of the conductive layers may be patterned into a predetermined shape. The multiple control terminals 7D are disposed on one of the conductive layers and aligned in the third direction y. Each of the multiple control terminals 7D extends in the first direction z. As shown in FIG. 27 , the multiple control terminals 7D protrude from the sealing resin 9 toward the z2 side in the first direction z.

[0074] The control terminals 7E are electrically connected to the second semiconductor elements 5B via the second support portion 48B and the fourth conductive members 8D. The second support portion 48B may be mounted on the second main surface 1B. Like the first support portion 48A, the first support portion 48A may include, for example, an insulating layer and two conductive layers stacked in the first direction z with the insulating layer sandwiched therebetween. As shown in FIG. 31 , one of the conductive layers may be patterned into a predetermined shape. The control terminals 7E are disposed on one of the conductive layers and aligned in the third direction y. Each of the control terminals 7E extends in the first direction z. As shown in FIG. 27 , the control terminals 7D protrude from the sealing resin 9 toward the z2 side in the first direction z.

[0075] According to this embodiment, the first semiconductor element 5A can be more appropriately bonded. Furthermore, as can be understood from this embodiment, the specific configurations of the plurality of control terminals 7D and the plurality of control terminals 7E are not limited in any way.

[0076] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways. The present disclosure includes the embodiments described in the following appendices.

[0077] Supplementary Note 1. A semiconductor device (A1) comprising: a first semiconductor element (5A); a support (1) located on a first side (z1) in a first direction (z) with respect to the first semiconductor element (5A); a first bonding sheet (6A) interposed between the first semiconductor element (5A) and the support (1); and a sealing resin (9) covering the first semiconductor element (5A), wherein the first semiconductor element (5A) and the first bonding sheet (6A), and the first bonding sheet (6A) and the support (1) are bonded together by solid-state diffusion bonding, and the support (1) has a first main surface (1A) facing a second side (z2) in the first direction (z) and a first recess (100A) recessed from the first main surface (1A) to the first side (z1) in the first direction (z), and the first bonding sheet (6A) is housed in the first recess (100A) when viewed in the first direction (z). Supplementary Note 2. The semiconductor device (A1) according to Supplementary Note 1, wherein the thickness (ta) of the first bonding sheet (6A) is greater than the depth (da) of the first recess (100A). Supplementary Note 3. The semiconductor device (A1) according to Supplementary Note 2, wherein the first semiconductor element (5A) is located on the second side (z2) of the first main surface (1A) in the first direction (z). Supplementary Note 4. The semiconductor device (A1) according to Supplementary Note 1, wherein the first recess (100A) has a bottom surface (101) located on the first side (z1) of the first main surface (1A), and an inner side surface (102) located between the bottom surface (101) and the first main surface (1A). Supplementary Note 5. The semiconductor device (A1) according to Supplementary Note 4, wherein a portion of the sealing resin (9) is filled between the first bonding sheet (6A) and the inner side surface (102). Supplementary Note 6. The semiconductor device (A1) according to any one of Appendices 1 to 5, wherein the first bonding sheet (6A) is larger than the first semiconductor element (5A) when viewed in the first direction (z).Appendix 7. The semiconductor device (A1) according to any one of Appendices 1 to 6, wherein the first bonding sheet (6A) has a first base material layer (60), a first bonding layer (61) located on a first side (z1) in the first direction (z) with respect to the first base material layer (60), and a second bonding layer (62) located on the second side (z2) in the first direction (z) with respect to the first base material layer (60), and the first base material layer (60) is softer than the support (1).Appendix 8. The semiconductor device (A1) according to Appendix 7, wherein the first base layer (60) is thinner than the first bonding layer (61) and the second bonding layer (62). Appendix 9. The semiconductor device (A1) according to Appendix 8, wherein the first base layer (60) contains Al. Appendix 10. The semiconductor device (A1) according to Appendix 9, wherein the first bonding layer (61) and the second bonding layer (62) contain Ag. Appendix 11. The semiconductor device (A1) according to any one of Supplementary Notes 7 to 10, wherein the support (1) includes an insulating layer (10) and a first main surface metal layer (2A) located on the second side (z2) in the first direction (z) with respect to the insulating layer (10), the first main surface (1A) and the first recess (100A) being formed by the first main surface metal layer (2A), and the first main surface metal layer (2A) includes a second base layer (20) and a third bonding layer (21) located on the second side (z2) in the first direction (z) with respect to the second base layer (20).Supplementary Note 12. The semiconductor device (A1) according to Supplementary Note 11, wherein the second base layer (20) contains Cu, and the third bonding layer (21) contains Ag.Supplementary Note 13. The semiconductor device (A1) according to Appendix 12, wherein the first semiconductor element (5A) has a first electrode (51) located on the first side (z1) in the first direction (z), and the first electrode (51) has a third base material layer (510) and a fourth bonding layer (511) located on the first side (z1) in the first direction (z) with respect to the third base material layer (510). Appendix 14. The semiconductor device (A1) according to Appendix 13, wherein the fourth bonding layer (511) contains Ag. Appendix 15. A method for manufacturing a semiconductor device, comprising the steps of: pressing a main surface (1a) of a support (1) toward a first side (z1) in a first direction (z) to form a first recess (100A) recessed from the main surface (1a) toward the first side (z1) in the first direction (z); placing a first bonding sheet (6A) so that the first recess (100A) is accommodated in the first recess (100A) when viewed in the first direction (z); placing a first semiconductor element (5A) on the first bonding sheet (6A); and bonding the first semiconductor element (5A) and the first bonding sheet (6A) to the first bonding sheet (6A) and the support (1) by solid-state diffusion bonding.Appendix 16. The semiconductor device (A1) according to any one of Appendixes 11 to 14, further comprising a second semiconductor element (5B) and a second bonding sheet (6B) interposed between the second semiconductor element (5B) and the second main surface metal layer (2B), wherein the support (1) has a second main surface metal layer (2B) positioned away from the first main surface metal layer (2A) in a second direction (x) perpendicular to the first direction (z), the second main surface metal layer (2B) having a second main surface (1B) facing the second side (z2) in the first direction (z) and a second recess (100B) recessed from the second main surface (1B) to the first side (z1) in the first direction (z), and the second bonding sheet (6B) is housed in the second recess (100B) as viewed in the first direction (z). Appendix 17. The semiconductor device (A1) according to Appendix 16, wherein the support (1) has a back surface metal layer (11) located on the first side (z1) in the first direction (z) with respect to the insulating layer (10). Appendix 18. The semiconductor device (A1) according to Appendix 17, wherein the back surface metal layer (11) is exposed from the sealing resin (9) to the first side (z1) in the first direction (z). Appendix 19. The semiconductor device (A2) according to any one of Supplementary Notes 7 to 10, wherein the support (1) includes an insulating layer (10), a first main surface metal layer (2A) located on the second side (z2) in the first direction (z) relative to the insulating layer (10), a third main surface metal layer (3A) located on the second side (z2) in the first direction (z) relative to the first main surface metal layer (2A), and a third bonding sheet (4A) interposed between the first main surface metal layer (2A) and the third main surface metal layer (3A), and the main surface (1a) and the first recess (100A) are formed by the third main surface metal layer (3A).Supplementary Note 20. The semiconductor device (A1) according to Supplementary Note 19, wherein the third main surface metal layer (3A) includes a second base layer (30) and a third bonding layer (31) located on the second side (z2) in the first direction (z) relative to the second base layer (30).Supplementary Note 21. A vehicle (C1) comprising: a drive source (932); and a semiconductor device (A1) according to any one of Supplementary Notes 1 to 14, wherein the semiconductor device (A1) is electrically connected to the drive source (932).

[0078] A1, A11, A12, A13, A2: semiconductor device 1: support 1A: first main surface 1B: second main surface 2A: first main surface metal layer 2B: second main surface metal layer 3A: third main surface metal layer 3B: fourth main surface metal layer 4A: third bonding sheet 4B: fourth bonding sheet 5A: first semiconductor element 5B: second semiconductor element 6A: first bonding sheet 6B: second bonding sheet 7A: positive electrode input terminal 7B: output terminal 7C: negative electrode input terminal 7D: control terminal 7E: control terminal 8A: first wire 8B: second wire 8C: third wire 8D: fourth wire 9: sealing resin 10: insulating layer 11: back surface metal layer 20: second base material layer 21: third bonding layer 48A: first support portion 48B: second support portion 50: Element body 51: First electrode 52: Second electrode 53: Third electrode 54: Fourth electrode 60: First base material layer 61: First bonding layer 62: Second bonding layer 91: Resin main surface 92: Resin back surface 100A: First recess 100B: Second recess 101: Bottom surface 102: Inner surface 105: Insulating layer 510: Third base material layer 511: Fourth bonding layer 910: On-board charger 920: Storage battery 930: Drive system 931: Inverter 932: Drive source C1: Vehicle T1: Tool da, db: Depth ta, ta1, ta2, tb: Thickness x: Second direction x1: First side x2: Second side y: Third direction y1: First side y2: Second side z: First direction z1: First side z2: Second side

Claims

1. A semiconductor device comprising: a first semiconductor element; a support located on a first side in a first direction with respect to the first semiconductor element; a first bonding sheet interposed between the first semiconductor element and the support; and a sealing resin covering the first semiconductor element, wherein the first semiconductor element and the first bonding sheet, and the first bonding sheet and the support are each joined by solid-phase diffusion bonding, the support has a first main surface facing a second side in the first direction and a first recess recessed from the first main surface toward the first side in the first direction, and the first bonding sheet is housed in the first recess when viewed in the first direction.

2. The semiconductor device according to claim 1, wherein a thickness of the first bonding sheet is greater than a depth of the first recess.

3. The semiconductor device according to claim 2, wherein the first semiconductor element is located on the second side of the first main surface in the first direction.

4. The semiconductor device according to claim 1, wherein the first recess has a bottom surface located on the first side with respect to the first main surface and an inner surface located between the bottom surface and the first main surface.

5. The semiconductor device according to claim 4, wherein a part of the sealing resin is filled between the first bonding sheet and the inner surface.

6. The semiconductor device according to any one of claims 1 to 5, wherein the first bonding sheet is larger than the first semiconductor element when viewed in the first direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first bonding sheet has a first base material layer, a first bonding layer located on a first side in the first direction with respect to the first base material layer, and a second bonding layer located on the second side in the first direction with respect to the first base material layer, and the first base material layer is softer than the support.

8. The semiconductor device according to claim 7, wherein the first base material layer is thinner than the first bonding layer and the second bonding layer.

9. The semiconductor device according to claim 8, wherein the first base material layer contains Al.

10. The semiconductor device according to claim 9, wherein the first bonding layer and the second bonding layer contain Ag.

11. The support includes an insulating layer and a first main surface metal layer located on the second side in the first direction with respect to the insulating layer. The first main surface and the first recess are constituted by the first main surface metal layer. The first main surface metal layer includes a second base material layer and a third bonding layer located on the second side in the first direction with respect to the second base material layer. The semiconductor device according to any one of claims 7 to 10.

12. The second base material layer contains Cu, and the third bonding layer contains Ag. The semiconductor device according to claim 11.

13. The first semiconductor element has a first electrode located on the first side in the first direction. The first electrode has a fourth bonding layer located on the first side in the first direction with respect to the third base material layer and the third base material layer. The semiconductor device according to claim 12.

14. The fourth bonding layer contains Ag. The semiconductor device according to claim 13.

15. A method for manufacturing a semiconductor device, comprising: a step of forming a first recess recessed from the main surface toward the first side in the first direction by pressing the main surface of the support toward the first side in the first direction; a step of placing a first bonding sheet so as to be accommodated in the first recess when viewed in the first direction; a step of placing a first semiconductor element on the first bonding sheet; and a step of bonding the first semiconductor element and the first bonding sheet, and the first bonding sheet and the support by solid-phase diffusion bonding.

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