Photodetection device, method for producing same, and electronic apparatus

Abstract

The present disclosure pertains to: a photodetection device in which a deterioration in dark-time characteristics can be inhibited; a method for manufacturing the photodetection device; and an electronic apparatus. This photodetection device comprises: a photoelectric conversion unit; a pixel transistor; and an element separation layer provided in the vicinity of the pixel transistor. An end surface of the gate electrode of the pixel transistor is in contact with an end surface of the element separation layer or is disposed away from the end surface of the element separation layer toward a center line connecting the gate electrode and two source / drain regions. The technology of the present disclosure is applicable to a photodetection device or the like that photoelectrically converts incoming light and outputs a pixel signal corresponding to the amount of received light.

Description

Photodetector, manufacturing method thereof, and electronic device

[0001] The present disclosure relates to a photodetector, a method for manufacturing the same, and an electronic device, and more particularly to a photodetector that can suppress deterioration of dark characteristics, a method for manufacturing the same, and an electronic device.

[0002] A pixel of a CMOS (Complementary Metal Oxide Semiconductor) image sensor has a photodiode, which is a photoelectric conversion element, and pixel transistors such as a transfer transistor, an amplification transistor, a reset transistor, a selection transistor, etc. Patent Document 1 describes a pixel arrangement in which a photodiode and a transfer transistor are arranged for each pixel, and the amplification transistor, reset transistor, and selection transistor are shared by four pixels.

[0003] Japanese Patent Application Laid-Open No. 2021-166304

[0004] The gate electrode of a pixel transistor is often laid out large enough to extend into the isolation layer of the insulating film formed around the channel portion so that it will not deviate from the channel portion under the gate electrode even if its formation position is slightly shifted due to process variations. As a result, the gate electrode and the isolation layer are partially in contact with each other above and below, and when the pixel transistor is turned on, the surface potential of the isolation layer increases, lowering the hole concentration in the semiconductor layer adjacent to the isolation layer. This makes it easier for electrons to be generated in the semiconductor layer, which then enters the nearby photodiode and causes degradation of the dark characteristics.

[0005] The present disclosure has been made in view of such circumstances, and aims to prevent a state in which the gate electrode of a pixel transistor and the element isolation layer are in contact with each other from above and below, thereby making it possible to suppress deterioration of dark characteristics.

[0006] A photodetector according to a first aspect of the present disclosure includes a photoelectric conversion unit, a pixel transistor, and an element isolation layer provided in the vicinity of the pixel transistor, wherein an end face of a gate electrode of the pixel transistor is in contact with an end face of the element isolation layer or is spaced apart from the end face of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions.

[0007] A method for manufacturing a photodetector according to a second aspect of the present disclosure includes forming a photoelectric conversion unit, a pixel transistor, and an element isolation layer in the vicinity of the pixel transistor, and forming an end face of a gate electrode of the pixel transistor so as to be in contact with an end face of the element isolation layer or to be spaced apart from the end face of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions.

[0008] An electronic device according to a third aspect of the present disclosure includes a photodetector including a photoelectric conversion unit, a pixel transistor, and an element isolation layer provided in the vicinity of the pixel transistor, wherein an end face of a gate electrode of the pixel transistor is in contact with an end face of the element isolation layer or is positioned away from the end face of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions.

[0009] In the first to third aspects of the present disclosure, a photoelectric conversion unit, a pixel transistor, and an element isolation layer are provided in the vicinity of the pixel transistor, and the gate electrode of the pixel transistor is provided so that an end face of the gate electrode of the pixel transistor is in contact with an end face of the element isolation layer or is positioned away from the end face of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions.

[0010] The photodetector and electronics may be stand-alone devices or may be modules that are incorporated into other devices.

[0011] 19 is a diagram illustrating a schematic configuration of a photodetector to which the technology of the present disclosure is applied. FIG. 19 is a plan view of a pixel region in a first embodiment of the photodetector. FIG. 2 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of FIG. 2. FIG. 19 is a diagram illustrating a manufacturing method of a pixel structure according to the first embodiment. FIG. 29 is a diagram illustrating a manufacturing method of a pixel structure according to the first embodiment. FIG. 30 is a cross-sectional view showing a modification of the first embodiment. FIG. 31 is a diagram illustrating a manufacturing method of a pixel structure according to a modification of the first embodiment. FIG. 32 is a plan view of a pixel region in a second embodiment of the photodetector. FIG. 33 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of FIG. 9. FIG. 19 is a plan view of a pixel region in a third embodiment of the photodetector. FIG. 34 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of FIG. 11. FIG. 35 is a plan view showing a modification of the third embodiment. FIG. 36 is a diagram illustrating a manufacturing method of a pixel structure according to the second and third embodiments. FIG. 37 is a diagram illustrating a manufacturing method of a pixel structure according to the second and third embodiments. FIG. 38 is a diagram illustrating a manufacturing method of a pixel structure according to the second and third embodiments. FIG. 39 is a diagram illustrating a manufacturing method of a pixel structure according to the second and third embodiments. FIG. 39 is a diagram illustrating a manufacturing method of a pixel structure according to the second and third embodiments. 25A and 25B are diagrams for explaining a method for manufacturing a pixel structure according to a fourth embodiment; FIG. 25B are diagrams for explaining a method for manufacturing a pixel structure according to a fourth embodiment; FIG. 25C are diagrams for explaining a method for manufacturing a pixel structure according to a fourth embodiment; FIG. 25D are diagrams for explaining a method for manufacturing a pixel structure according to a fourth embodiment; FIG. 25D are diagrams for explaining a method for manufacturing a pixel structure according to a fourth embodiment; FIG. 25E are diagrams for explaining a method for manufacturing a pixel structure according to a fifth embodiment; FIG. 25F ... sixth embodiment; FIG. 25C are diagrams for explaining a method for manufacturing a pixel structure according to a sixth embodiment; FIG. 25D are diagrams for explaining a method for manufacturing a pixel structure according to a sixth embodiment;46 is a diagram illustrating a manufacturing method of a pixel structure according to a sixth embodiment. FIG. 47 is a plan view of a pixel region to which a first modified example of a transfer transistor is applied. FIG. 48 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of FIG. 37. FIG. 49 is a plan view showing a variation of the first modified example of the transfer transistor. FIG. 49 is a plan view of a pixel region to which a second modified example of a transfer transistor is applied. FIG. 41 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of FIG. 40. FIG. 41 is a plan view showing a variation of the second modified example of the transfer transistor. FIG. 42 is a diagram illustrating a manufacturing method of the first modified example of the transfer transistor. FIG. 43 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of FIG. 46. FIG. 48 is a diagram illustrating a schematic configuration example of a photodetector configured with a stacked structure of three substrates. FIG. 49 is a diagram illustrating a configuration example of a sensor pixel and a readout circuit. FIG. 49 is a block diagram illustrating a configuration example of an electronic device. FIG. 49 is a diagram illustrating an example of the use of an image sensor. FIG. 50 is a diagram illustrating an example of the schematic configuration of an endoscopic surgery system. FIG. 51 is a block diagram illustrating an example of the functional configuration of a camera head and a CCU. FIG. 52 is a block diagram illustrating an example of the schematic configuration of a vehicle control system. FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0012] Modes for carrying out the technology of the present disclosure (hereinafter referred to as embodiments) will be described below with reference to the accompanying drawings. The description will be made in the following order: 1. Schematic configuration example of a photodetector 2. First embodiment 3. Manufacturing method of the first embodiment 4. Modified example of the first embodiment 5. Manufacturing method of the modified example of the first embodiment 6. Second embodiment 7. Third embodiment 8. Modified example of the third embodiment 9. Manufacturing method of the second and third embodiments 10. Fourth embodiment 11. Modified example of the fourth embodiment 12. Manufacturing method of the fourth embodiment 13. Fifth embodiment 14. Modified example of the fifth embodiment 15. Manufacturing method of the fifth embodiment 16. Sixth embodiment 17. Manufacturing method of the sixth embodiment 18. Modified example of a transfer transistor 19. Manufacturing method of the modified example of a transfer transistor 20. Combination with a pixel separator 21. Example of a stacked configuration using multiple substrates 22. Example of a configuration of an electronic device 23. Example of use of an image sensor 24. Example of application to an endoscopic surgery system 25. Example of application to a moving body

[0013] In the drawings referred to in the following description, identical or similar parts are denoted by identical or similar reference numerals to avoid repetitive explanation. The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios.

[0014] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted.

[0015] The technology disclosed herein can be applied to photodetection devices in general that have a pixel array in which pixels are arranged two-dimensionally in a matrix, perform photoelectric conversion on incident light, and output pixel signals corresponding to the amount of received light. The light detected by the photodetection device for photoelectric conversion may be light in the visible light range including wavelengths such as R (Red), G (Green), and B (Blue), or light in the non-visible light range such as infrared light. Alternatively, light in both the visible and non-visible light ranges may be used. The photodetection device can be used as a solid-state imaging device that generates and outputs an image signal corresponding to the amount of incident light, or as a light receiving device (ranging sensor) in a ranging system that receives light (reflected light) that is emitted as active light from an object and reflects infrared light off the object, thereby measuring the distance to the object using a direct ToF or indirect ToF method.

[0016] 1. Schematic Configuration Example of Photodetector> FIG. 1 is a diagram showing a schematic configuration of a photodetector to which the technology of the present disclosure is applied.

[0017] 1 is configured to include a pixel array section 3 in which pixels 2 are arranged two-dimensionally in a matrix on a semiconductor substrate 21 made of, for example, silicon (Si) as a semiconductor, and a peripheral circuit section around the pixel array section 3. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc.

[0018] The pixel 2 includes a photodiode, which is a photoelectric conversion unit, and a plurality of pixel transistors, each of which is made up of, for example, a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, each of which is made up of a MOS transistor (MOS FET).

[0019] The pixels 2 may also have a shared pixel structure. This shared pixel structure is composed of multiple photodiodes, multiple transfer transistors, one shared floating diffusion, and one other pixel transistor each. That is, in the shared pixel structure, a photodiode and a transfer transistor are disposed in each pixel 2, and the other pixel transistors are shared by multiple pixels 2.

[0020] The control circuit 8 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the photodetector 1. That is, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0021] The vertical drive circuit 4 is configured by, for example, a shift register, selects a predetermined pixel drive wiring 10, supplies a pulse for driving the pixels 2 to the selected pixel drive wiring 10, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 selects and scans each pixel 2 of the pixel array unit 3 row by row in the vertical direction, and supplies a signal based on a signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 9.

[0022] The column signal processing circuits 5 are arranged for each column of pixels 2, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 2. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to each pixel and AD conversion.

[0023] The horizontal drive circuit 6 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0024] The output circuit 7 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11. The output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0025] The photodetector 1 configured as described above has a structure known as a column AD system, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged for each column. The photodetector 1 generates a signal corresponding to the amount of light received by each pixel 2 in the pixel array section 3 and outputs the signal to the outside. The photodetector 1 can be used, for example, as a solid-state imaging device that detects the distribution of incident light amounts of infrared light or visible light and captures an image, or as a light receiving device in a distance measurement system that receives light (reflected light) that is irradiated as active light from an object and reflects it, using a direct ToF system or an indirect ToF system to measure the distance to the object.

[0026] 2. First Embodiment A first embodiment of the photodetector 1 will be described with reference to FIGS. 2 and 3. FIG.

[0027] Fig. 2 is a plan view of a pixel region (pixel array section 3) in the first embodiment of the photodetector 1, and Fig. 3 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 2. Fig. 3A is a cross-sectional view taken along line Y1-Y1' in Fig. 2, Fig. 3B is a cross-sectional view taken along line Y2-Y2' in Fig. 2, and Fig. 3C is a cross-sectional view taken along line X-X' in Fig. 2.

[0028] As shown in the plan view of Fig. 2, the pixel region of the photodetector 1 is configured by repeatedly arranging four unit pixel regions 2A in a 2x2 (two rows and two columns) array and a shared pixel region 2B in the column direction (vertical direction) and row direction (horizontal direction) of the pixel array section 3. Note that in the plan view of Fig. 2, in order to make the planar arrangement of each section easier to see and understand, the insulating film 53 and the contact interlayer film 54 shown in Fig. 3 are omitted. The same applies to the plan views of the second and subsequent embodiments described later.

[0029] The unit pixel region 2A includes a photodiode PD, which serves as a photoelectric conversion unit, and a transfer transistor TG. A floating diffusion FD is located in the center of the 2x2 unit pixel region 2A. The photodiode PD photoelectrically converts incident light and generates an electric charge (signal charge) corresponding to the amount of incident light received. The transfer transistor TG controls the transfer of the electric charge generated by the photodiode PD. When the transfer transistor TG is turned on, the transfer transistor TG transfers the electric charge generated by the photodiode PD to the floating diffusion FD. The photodiode PD is a PN junction photodiode having an N-type semiconductor region 32 formed within a P-type semiconductor region 31, which is a substrate region. The floating diffusion FD is formed of a highly doped N-type semiconductor region 33, and an N-type semiconductor region (LDD region) 34 with a lower concentration than the N-type semiconductor region 33 is formed around the N-type semiconductor region 33. The floating diffusion FD is a charge storage unit that temporarily stores the charge transferred from the photodiode PD, and is also a charge-voltage conversion unit that generates a voltage according to the amount of charge. In the plan view of Figure 2, a gate electrode 35 of the transfer transistor TG is formed between the floating diffusion FD and the photodiode PD of each unit pixel region 2A, and a sidewall (sidewall insulating film) 36 is formed around the gate electrode 35.

[0030] The shared pixel region 2B is provided with a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL. These three pixel transistors are shared by four unit pixel regions 2A arranged in a 2x2 (2 rows x 2 columns) array. Therefore, the pixel 2 of the photodetector device 1 according to the first embodiment has a shared pixel structure in which each pixel has a photodiode PD and a transfer transistor TG, and the reset transistor RST, amplifier transistor AMP, and select transistor SEL are shared by the four pixels. In the example of FIG. 2 , the reset transistor RST, amplifier transistor AMP, and select transistor SEL are arranged in this order from left to right, but the order of the shared transistors is not limited to this and can be any order. Hereinafter, when the reset transistor RST, amplifier transistor AMP, and select transistor SEL are not particularly distinguished from one another, these pixel transistors will be referred to as shared transistors.

[0031] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on by the pixel drive line supplied to its gate, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The amplifier transistor AMP generates a pixel signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD. This amplifier transistor AMP forms a source follower together with a load circuit section in the column signal processing circuit 5 connected to the vertical signal line 9. When the selection transistor SEL is turned on, the amplifier transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing circuit 5 via the vertical signal line 9. The selection transistor SEL controls the output timing of the pixel signal. The source of the selection transistor SEL is connected to the vertical signal line 9, and the gate of the selection transistor SEL is connected to the pixel drive line. When the selection transistor SEL is turned on by the pixel drive line supplied to its gate, it outputs the pixel signal from the amplifier transistor AMP to the vertical signal line 9.

[0032] As shown in FIG. 3C , the shared transistor has a gate electrode 41 and sidewalls (sidewall insulating films) 42 formed around the gate electrode 41 on an insulating film 53 that functions as a gate insulating film. A source / drain region 43 and an LDD (Lightly Doped Drain) region 44 are formed in the substrate adjacent to the gate electrode 41. The source / drain region 43 is a highly doped N-type semiconductor region that serves as the source or drain of the shared transistor, and the LDD region 44 is composed of an N-type semiconductor region with a lower concentration than the source / drain region 43. The source / drain region 43 and the LDD region 44 are formed in an N-well region 45 that is composed of an N-type semiconductor region with a lower concentration than the LDD region 44.

[0033] Shallow trench isolation (STI) 51, an element isolation layer, is formed around the three shared transistors in the shared pixel region 2B, consisting of the reset transistor RST, the amplifier transistor AMP, and the select transistor SEL, electrically isolating the shared transistors from the adjacent photodiodes PD. As shown in FIG. 3 , the STI 51 is recessed from the same height as the top surface of the gate electrode 41 of the shared transistor to a position deeper than at least the source / drain region 43, the LDD region 44, and the N-well region 45. In the cross section taken along line Y1-Y1′ in FIG. 3A, the N-well region 45 and the like are formed in the substrate inside the STI 51. The gate electrode 41 of the shared transistor is formed above the substrate surface inside the STI 51. The outer sidewall of the STI 51 protruding above the substrate surface is covered with a sidewall (sidewall insulating film) 52. The STI 51 may be provided around the entire three shared transistors, or may be provided only in the channel width W direction, not in the channel length L direction. When no STI 51 is provided around the periphery in the direction of the channel length L, only sidewalls are provided on the outside of the three shared transistors. In the cross section taken along line Y2-Y2' in FIG. 3B, the source / drain regions 43, LDD regions 44, and N-well regions 45 of the shared transistors are formed in the substrate inside the STI 51. Sidewalls 52 are formed on the outer sidewalls of the STI 51 that protrude above the substrate surface. When no gate electrode 41 is provided inside the STI 51, sidewalls 52 are also formed on the inner sidewalls of the STI 51.

[0034] A contact interlayer film 54 is formed on the upper surfaces of the STI 51, sidewall 52, gate electrode 41 and sidewall 42 of the shared transistor, gate electrode 35 and sidewall 36 of the transfer transistor TG, etc., which protrude above the substrate surface. The STI 51, sidewall 52, gate electrode 41 and sidewall 42 of the shared transistor, gate electrode 35 and sidewall 36 of the transfer transistor TG, and contact interlayer film 54 are made of an insulating material such as SiO, SiN, SiON, etc. However, the contact interlayer film 54 is formed using a material different from that of the other insulating films below it.

[0035] When an on-chip lens is formed on the light incident surface side of the semiconductor substrate 21, one on-chip lens may be arranged in four 2x2 unit pixel regions 2A, and one pixel may be composed of the four 2x2 unit pixel regions 2A, or an on-chip lens may be arranged for each unit pixel region 2A, and one pixel may be composed of the unit pixel region 2A. For example, when one pixel is composed of four 2x2 unit pixel regions 2A, a shared transistor is arranged in each of multiple rows in the plan view of FIG. 2, and a photodiode PD and a transfer transistor TG are arranged between the multiple rows in which the shared transistors are arranged. When one pixel is composed of unit pixel regions 2A, the shared transistors are arranged in multiple rows.

[0036] As described above, in the first embodiment, the gate electrode 41 of the shared transistor is surrounded by the STI 51, which is an element isolation layer formed in the shared pixel region 2B, and is formed inside the STI 51. The top surface of the gate electrode 41 of the shared transistor is located above the substrate surface of the semiconductor substrate 21, and the top surface of the gate electrode 41 of the shared transistor is located at the same level as the top surface of the STI 51. Furthermore, the gate electrode 41 of the shared transistor does not overlap with the STI 51 in the vertical direction (does not overlap in a plan view). The end surface of the gate electrode 41 of the shared transistor contacts the inner end surface of the STI 51 and shares a single surface F1. The gate electrode 41 and the N-well region 45 below the gate electrode 41, in which a channel is formed, are formed in a self-aligned manner using the STI 51. Therefore, as shown in the cross-sectional view of line Y1-Y1' in FIG. 3A, the width W1 of the gate electrode 41 in the channel width W direction and the semiconductor region width W2 of the N-well region 45 are formed to be equal.

[0037] Because the gate electrode 41 and the N-well region 45 below the gate electrode 41 are formed in a self-aligned manner using the STI 51, the gate electrode 41 does not significantly protrude from the formation position of the N-well region 45 in the direction of the channel width W, nor is it positioned at a position misaligned with respect to the formation position of the N-well region 45. Therefore, it is possible to avoid a situation in which, when a portion of the gate electrode 41 rides up onto the STI 51 and the shared transistor is turned on, the surface potential of the STI 51 increases, thereby reducing the hole concentration in the P-type semiconductor region 31 adjacent to the STI 51. In other words, it is possible to avoid a state in which the gate electrode 41 of the shared transistor and the element isolation layer are in contact with each other from above and below, thereby suppressing deterioration of dark characteristics.

[0038] If a decrease in hole concentration in the P-type semiconductor region 31 or variations in the decrease in hole concentration due to process variations occur, a conceivable method for suppressing an increase in dark current is to increase the concentration of the P-type semiconductor region 31 between the STI 51 and the N-type semiconductor region 32 in the cross-sectional view taken along line Y1-Y1' in FIG. 3A. However, if the P-type semiconductor region 31 between the STI 51 and the N-type semiconductor region 32 is increased in concentration, the high-concentration P-type semiconductor region and the N-type semiconductor region 32 of the photodiode PD will be in high-concentration contact, resulting in the generation of dark electrons due to a high electric field. According to the pixel structure of the first embodiment, the decrease in hole concentration in the P-type semiconductor region 31 can be suppressed, eliminating the need to increase the concentration of the P-type semiconductor region 31 between the STI 51 and the N-type semiconductor region 32 and avoiding the increase in dark electrons due to a high electric field.

[0039] Furthermore, since the gate electrode 41 of the shared transistor does not significantly extend beyond the formation position of the N-well region 45 or is positioned offset from the formation position of the N-well region 45, variations in the cutoff characteristics of the shared transistor can be reduced.

[0040] If the upper surface of the STI 51 is formed higher so that the upper surface position of the STI 51 is equal to the upper surface position of the gate electrode 41 of the shared transistor, there is a concern that the stress from the contact interlayer film 54 covering the upper surface will become stronger. Specifically, the stress exerted upward by the contact interlayer film 54 will become stronger, and defects may occur near a surface F2 where the outer end face of the STI 51 and the P-type semiconductor region 31 meet, for example, in the cross-sectional view taken along line Y1-Y1' in FIG. 3A. According to the pixel structure of the first embodiment, the stress from the contact interlayer film 54 can be reduced by forming sidewalls 52 on the outer side walls of the STI 51 that protrude above the substrate surface.

[0041] 3. Manufacturing Method of First Embodiment A method of manufacturing the pixel structure according to the first embodiment will be described with reference to FIGS.

[0042] 4A, an insulating film 53 is first formed on the front surface, which is the first surface of the semiconductor substrate 21 on which the P-type semiconductor region 31 is formed, and then a second insulating film 71 made of a material different from that of the insulating film 53 is formed on top of the insulating film 53. The insulating film 53 is, for example, an SiO2 film, and the second insulating film 71 is, for example, an SiN film. The insulating film 53 and the second insulating film 71 can be formed using, for example, CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like.

[0043] Next, as shown in B of FIG. 4, the second insulating film 71, the insulating film 53, and the P-type semiconductor region 31 are etched in the region where the STI 51 is to be formed, thereby forming a trench 72 dug to a predetermined depth in the semiconductor substrate 21.

[0044] 4C, an insulating film 73 is formed by, for example, CVD, ALD, or the like inside the formed trench 72 and on the entire upper surface of the second insulating film 71. The insulating film 73 is, for example, the same SiO2 film as the insulating film 53.

[0045] 4D, the insulating film 73 is polished and planarized by CMP (Chemical Mechanical Polishing) or the like until it is flush with the second insulating film 71. After planarization, the insulating film 73 embedded in the trench 72 forms the STI 51.

[0046] Next, as shown in FIG. 5A, the second insulating film 71 is removed by etching. Then, as shown in FIG. 5B, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted from the front surface side of the semiconductor substrate 21 into the regions where the photodiode PD and the N-well region 45 are to be formed, thereby forming the N-type semiconductor region 32 and the N-well region 45, respectively. The impurity concentration of the N-type semiconductor region 32 is higher than that of the N-well region 45. Note that, although the etching step shown in FIG. 5A is described with the insulating film 53 remaining, it is also possible to etch the insulating film 53 and then form another film. The ion-implantation step for forming the N-type semiconductor region 32 and the N-well region 45 is not limited to this timing and can also be performed at another timing.

[0047] 5C, a gate electrode material 76 such as polysilicon is deposited by CVD or the like to a predetermined thickness over the entire upper surfaces of the insulating film 53 and the STI 51. The gate electrode material 76 may be a metal material containing, for example, titanium (Ti), tantalum (Ta), or aluminum (Al) in addition to polysilicon.

[0048] Next, as shown in FIG. 5D, the gate electrode material 76 is planarized using CMP or the like until it is flush with the STI 51 .

[0049] 6A, the gate electrode material 76 above the photodiode PD is removed by etching, leaving a portion of it. The portion of the gate electrode material 76 remaining above the photodiode PD becomes the gate electrode 35 of the transfer transistor TG, and the portion of the gate electrode material 76 surrounded by the STI 51 becomes the gate electrode 41 of the shared transistors such as the reset transistor RST.

[0050] Although not shown in the drawings, thereafter, a step is performed in which N-type impurities are ion-implanted into a part of the N-well region 45 near the gate electrode 41 of the shared pixel region 2B to form an LDD region 44. Furthermore, together with the LDD region 44 of the shared pixel region 2B, an N-type semiconductor region (LDD region) 34 near the floating diffusion FD in the center of the 2x2 unit pixel region 2A is also formed at the same time.

[0051] 6B, an insulating material 77 is deposited by, for example, CVD, ALD, etc. on the entire upper surfaces of the gate electrode 35 of the transfer transistor TG, the gate electrode 41 of the shared transistor, the STI 51, etc. This insulating material 77 is a material that forms the sidewall 36 around the periphery of the gate electrode 35 of the transfer transistor TG and the sidewall 52 around the periphery of the STI 51, and may be, for example, SiO2 or SiN.

[0052] 6C, the insulating material 77 formed on the entire upper surface is etched back to form a sidewall 36 around the gate electrode 35 of the transfer transistor TG and a sidewall 52 around the STI 51. Note that the method for forming the sidewalls 36 and 52 is not limited to this, and other methods may also be used. The sidewalls 36 and 52 may also be made of a laminated film of SiO2, SiN, or the like.

[0053] Although not shown in the drawings, thereafter, a step is performed in which N-type impurities are further ion-implanted into a part of the LDD region 44 near the gate electrode 41 in the shared pixel region 2B to form a source / drain region 43. Furthermore, simultaneously with the source / drain region 43, a high-concentration N-type semiconductor region 33 that will become a floating diffusion FD is also formed.

[0054] Finally, as shown in Fig. 6D, an insulating film 53 is formed again above the photodiode PD, and then a contact interlayer film 54 is formed over the entire pixel region, thereby completing the structure shown in Fig. 3A. The contact interlayer film 54 can be formed of, for example, SiO2, SiN, SiON, etc., but is made of a different material from the insulating films of the underlying sidewalls 36, 52, etc. For example, if the sidewalls 36, 52, etc. are made of SiO2, the contact interlayer film 54 can be made of SiN, but vice versa.

[0055] This completes the pixel structure according to the first embodiment. In the pixel structure according to the first embodiment, the gate electrode 41 of the shared transistor and the N-well region 45 below the gate electrode 41 in which the channel is formed are formed in a self-aligned manner using STI 51, so that the width W1 of the gate electrode 41 in the channel width W direction and the semiconductor region width W2 of the N-well region 45 can be formed to be the same width.

[0056] Furthermore, the gate electrode 41 and the STI 51 of the shared transistor can be formed so that the upper surface positions of the gate electrode 41 and the STI 51 are aligned and there is no region where the gate electrode 41 and the STI 51 overlap in the vertical direction.

[0057] 4. Modification of the First Embodiment Figure 7 is a cross-sectional view showing a modification of the first embodiment described above. Figure 7A is a cross-sectional view taken along line Y1-Y1' in Figure 2, Figure 7B is a cross-sectional view taken along line Y2-Y2' in Figure 2, and Figure 7C is a cross-sectional view taken along line X-X' in Figure 2. The plan view is the same as Figure 2 and is therefore omitted. The contact interlayer film 54 is also not shown.

[0058] In the modification of the first embodiment shown in Fig. 7, the shapes of the STI 51 and the sidewall 52 formed around the STI 51 are different from those of the first embodiment shown in Fig. 3. Specifically, in the first embodiment shown in Fig. 3, the surface F3 where the sidewall 52 above the semiconductor substrate 21 and the STI 51 meet is aligned with the end surface F2 of the STI 51 below the semiconductor substrate 21 (inside the semiconductor substrate 21). In contrast, in the modification, as shown in Fig. 7A, the surface F3 where the STI 51 above the semiconductor substrate 21 and the sidewall 52 meet is formed more inward, toward the gate electrode 41, than the end surface F2 of the STI 51 below the semiconductor substrate 21 (inside the semiconductor substrate 21). 7B, when comparing the width W11 of the STI 51 above the semiconductor substrate 21 with the width W12 of the STI 51 below the semiconductor substrate 21 in the direction of the channel width W, the upper width W11 is smaller than the lower width W12. Furthermore, with regard to the width in the direction of the channel length L, as shown in FIG. 7C, the protrusion width L2 of the sidewall 52 protruding from the end face of the STI 51 below the semiconductor substrate 21 is smaller than the width L3 of the sidewall 42 of the shared transistor.

[0059] As described above, by shifting (retreating) the position of the sidewall 52 on the top of the STI 51 toward the gate electrode 41 of the shared transistor, the opening area within the rectangle surrounded by the STI 51 in plan view—more specifically, the width W13 in the channel width W direction and the width L1 in the channel length L direction—can be secured to be wider than in the first embodiment. This prevents the inside of the STI 51 from being blocked due to manufacturing variations or the like when miniaturizing pixels, and enables stable ion implantation when forming the source / drain regions 43, which are high-concentration N-type semiconductor regions. The position and width W12 of the end face F2 of the STI 51 within the semiconductor substrate 21 are the same as in the first embodiment, so there is little risk of a low hole concentration in the P-type semiconductor region 31 near the face F2.

[0060] 5. Manufacturing Method of Modified Example of First Embodiment A method of manufacturing the pixel structure according to the modified example of the first embodiment will be described with reference to FIG.

[0061] In the modified example of the first embodiment, the steps described in the manufacturing method of the first embodiment with reference to Figures 4 and 5 are the same as those described in the manufacturing method of the first embodiment, and therefore will not be described again. In the modified example of the first embodiment, the steps described in the manufacturing method of the first embodiment with reference to Figure 6 are changed to the steps described with reference to Figure 8.

[0062] The gate electrode material 76 above the photodiode PD shown in Fig. 5D is removed by etching, leaving only a portion. As a result, as shown in Fig. 8A, the portion of the gate electrode material 76 remaining above the photodiode PD becomes the gate electrode 35 of the transfer transistor TG, and the gate electrode material 76 surrounded by the STI 51 becomes the gate electrode 41 of the shared transistor such as the reset transistor RST.

[0063] 8B, the sidewall of the STI 51 above the substrate surface of the semiconductor substrate 21 is shifted (set back) by etching toward the gate electrode 41 of the shared transistor. This etching also removes some of the top surface of the STI 51, so the top surface of the STI 51 may be slightly lower than the top surface of the gate electrode 41.

[0064] Although not shown, thereafter, similarly to the first embodiment, a process of forming the LDD region 44 in the shared pixel region 2B and the N-type semiconductor region (LDD region) 34 in the vicinity of the floating diffusion FD is carried out.

[0065] 8C, an insulating material 77 is deposited by, for example, CVD, ALD, etc. on the entire upper surfaces of the gate electrode 35 of the transfer transistor TG, the gate electrode 41 of the shared transistor, the STI 51, etc. This insulating material 77 is a material that forms the sidewall 36 around the gate electrode 35 of the transfer transistor TG and the sidewall 52 around the STI 51, and may be, for example, SiO2 or SiN.

[0066] Next, as shown in FIG. 8D, the insulating material 77 formed on the entire upper surface is etched back to form sidewalls 36 around the gate electrode 35 of the transfer transistor TG and sidewalls 52 around the STI 51. The method for forming the sidewalls 36 and 52 is not limited to this, and other methods may be used. The sidewalls 36 and 52 may also be formed of a stacked film of SiO, SiN, or the like. In this modification, the step of FIG. 8B is added to shift the sidewall of the STI 51 above the substrate surface toward the gate electrode 41, thereby ensuring a wider width W14 within the unit pixel region 2A in FIG. 8D than in the first embodiment.

[0067] Although not shown in the figures, similarly, processes for forming the source / drain region 43 of the shared pixel region 2B and the high-concentration N-type semiconductor region 33 that will become the floating diffusion FD, and a process for depositing the contact interlayer film 54 are carried out, thereby completing the pixel structure according to the modified example of the first embodiment described above.

[0068] 9 and 10, a second embodiment of the photodetector 1 will be described. In the second embodiment, differences from the first embodiment will be described, and a description of common parts will be omitted.

[0069] Fig. 9 is a plan view of a pixel region in the photodetector 1 according to the second embodiment, and Fig. 10 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 9. Fig. 10A is a cross-sectional view taken along line Y1-Y1' in Fig. 9, and Fig. 10B is a cross-sectional view taken along line XX' in Fig. 9.

[0070] As shown in the cross-sectional view of A in FIG. 10 , in the second embodiment, the gate electrode 41 of the shared transistor is embedded in the semiconductor substrate 21, and the bottom surface (lower surface position) of the gate electrode 41 is located below the substrate surface of the semiconductor substrate 21. Compared to the cross-sectional view of the first embodiment shown in A in FIG. 3 , in the first embodiment, an N-well region 45 is formed below the substrate surface of the semiconductor substrate 21 in the shared pixel region 2B, and the bottom surface (lower surface) of the gate electrode 41 is either at the same level as the substrate surface of the semiconductor substrate 21 or above the substrate surface. The N-well region 45 is formed below the gate electrode 41, similarly to the first embodiment. The gate electrode 41 and the N-well region 45 are formed inside the STI 51, and the width W1 of the gate electrode 41 in the channel width W direction and the semiconductor region width W2 of the N-well region 45 are also formed to be equal. Comparing the height direction width H1 of the gate electrode 41 with the height direction width H2 of the STI 51, the height direction width H1 of the gate electrode 41 is formed to be equal to or smaller than the height direction width H2 of the STI 51. Fig. 10A shows an example in which the height direction width H1 of the gate electrode 41 is smaller than the height direction width H2 of the STI 51.

[0071] In the second embodiment, the top surfaces of the gate electrode 41 of the shared transistor and the STI 51 are formed at the same level, and there is no region where the gate electrode 41 of the shared transistor and the STI 51 overlap in the vertical direction (regions that overlap in a plan view), as in the first embodiment. Because the gate electrode 41 and the STI 51 do not have a structure that protrudes above the substrate surface, the sidewall 52 that was formed on the side wall of the STI 51 in the first embodiment is not formed. As a result, in the plan view of FIG. 9, there is no protrusion of the STI 51 toward the unit pixel region 2A, which was on line Y1-Y1' in FIG.

[0072] As shown in the cross-sectional view of FIG. 10B, the gate electrode 41 of the shared transistor is embedded in the semiconductor substrate 21. An insulating film 53 serving as a gate insulating film is formed between the gate electrode 41 and the source / drain region 43, the LDD region 44, and the N-well region 45. The cross-sectional view of FIG. 10B also shows a contact wiring 91 connected to the source / drain region 43 of the shared transistor and a contact interlayer film 92 that fills the region other than the contact wiring 91. The contact wiring 91 is made of a metal material such as titanium (Ti), tantalum (Ta), or tungsten (W). The contact interlayer film 92 can be made of, for example, SiO2, SiN, or SiON.

[0073] The source / drain region 43 of the shared transistor can be formed in a self-aligned manner using the pattern used when forming the contact wiring 91, or can be formed in a self-aligned manner using the pattern used when forming the gate electrode 41. The example in FIG. 10B shows a case where the source / drain region 43 is formed in a self-aligned manner using the pattern used when forming the contact wiring 91.

[0074] As described above, in the second embodiment, the gate electrode 41 of the shared transistor is surrounded by the STI 51, which is an element isolation layer formed in the shared pixel region 2B, and is formed inside the STI 51. Furthermore, the top surfaces of the gate electrode 41 of the shared transistor and the STI 51 are formed at the same position, and there is no area where the gate electrode 41 of the shared transistor and the STI 51 overlap vertically (in a planar view). The end surface of the gate electrode 41 of the shared transistor contacts the inner end surface of the STI 51 and shares a single surface F1. The gate electrode 41 and the N-well region 45 below the gate electrode 41, in which the channel is formed, are formed in a self-aligned manner using the STI 51, so that the width W1 of the gate electrode 41 in the channel width W direction and the semiconductor region width W2 of the N-well region 45 are formed equal. Therefore, when a portion of the gate electrode 41 rides on top of the STI 51 and the shared transistor is turned on, the surface potential of the STI 51 increases, which prevents a decrease in the hole concentration in the P-type semiconductor region 31 adjacent to the STI 51. That is, it is possible to prevent the gate electrode 41 of the shared transistor from being in contact with the element isolation layer from above and below, thereby suppressing deterioration of the dark characteristics.

[0075] 11 and 12, a third embodiment of the photodetector 1 will be described. In the third and subsequent embodiments, differences from the other embodiments described earlier will be described, and descriptions of common parts will be omitted.

[0076] Fig. 11 is a plan view of a pixel region in the photodetector 1 according to the third embodiment, and Fig. 12 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 11. Fig. 12A is a cross-sectional view taken along line Y1-Y1' in Fig. 11, Fig. 12B is a cross-sectional view taken along line XX' in Fig. 11, and Fig. 12C is a cross-sectional view taken along line X2-X2' in Fig. 11.

[0077] The third embodiment is similar to the second embodiment shown in FIGS. 9 and 10 in that the gate electrode 41 of the shared transistor is formed embedded in the semiconductor substrate 21. The third embodiment differs from the second embodiment in the shape of the N-well region 45 in which the channel is formed in the shared pixel region 2B. Specifically, in the second embodiment, as shown in the cross-sectional view along the Y1-Y1' line in FIG. 10A, the N-well region 45 is formed only below the gate electrode 41. In contrast, in the third embodiment, as shown in FIG. 12A, the N-well region 45 is formed not only below but also to the side of the gate electrode 41, forming a U-shape. In the plan view of FIG. 11, the N-well region 45 is shown to the side of the gate electrode 41, for example, along the Y1-Y1' line.

[0078] 12A, an insulating film 53 that serves as a gate insulating film is formed below and around the sides of the gate electrode 41, and an N-well region 45 is formed outside of the insulating film 53. As a result, in the direction of the channel width W, the channel width W4 of the gate electrode 41 is formed smaller than the semiconductor region width W3 of the N-well region 45. In other words, the end face F5 of the gate electrode 41 of the shared transistor is located more inward (toward the center in the direction of the channel width W) than the inner end face F4 of the STI 51.

[0079] As described above, according to the third embodiment, the channel is formed not only in the N well region 45 below the gate electrode 41 but also in the N well regions 45 on both sides of the gate electrode 41, thereby increasing the modulation degree of the shared transistor.

[0080] In the third embodiment, the gate electrode 41 of the shared transistor is also surrounded by the STI 51, which is an element isolation layer formed in the shared pixel region 2B, and is formed inside the STI 51. Furthermore, the top surfaces of the gate electrode 41 of the shared transistor and the STI 51 are formed at the same position, and there is no region where the gate electrode 41 of the shared transistor and the STI 51 overlap in the vertical direction (i.e., there is no overlapping region in a plan view). The end face F5 of the gate electrode 41 of the shared transistor is located away from the inner end face F4 of the STI 51 toward the center line connecting the gate electrode 41 and the two source / drain regions 43 of the shared transistor. Here, the side of the center line connecting the gate electrode 41 and the two source / drain regions 43 of the shared transistor from the inner end face F4 of the STI 51 is inside the end face F4 of the STI 51. Therefore, when a portion of the gate electrode 41 rides up onto the STI 51 and the shared transistor is turned on, the surface potential of the STI 51 increases, which can prevent a decrease in the hole concentration in the P-type semiconductor region 31 adjacent to the STI 51. That is, it is possible to prevent the gate electrode 41 of the shared transistor from being in contact with the element isolation layer from above and below, thereby suppressing deterioration of the dark characteristics.

[0081] Although the manufacturing method will be described later, in relation to the channel width W direction, the LDD region 44 of the shared pixel region 2B can be formed widely in a self-aligned manner using the STI 51, which can reduce variations in coverage of ion implantation when forming the source / drain regions 43. In other words, process variation errors in the ion implantation regions when forming the source / drain regions 43 can be tolerated to a certain extent.

[0082] 8. Modification of Third Embodiment Fig. 13 is a plan view showing a modification of the above-described third embodiment. The cross-sectional views taken along lines Y1-Y1', X-X', and X2-X2' in Fig. 13 are the same as those in Fig. 12, and therefore will be omitted.

[0083] In the modification of the third embodiment shown in FIG. 13 , the shape of the N-well region 45 formed in the shared pixel region 2B is different from that of the third embodiment shown in FIGS. 11 and 12 . In the third embodiment, as shown in FIG. 11 , the N-well region 45 is not provided on the side surface of the LDD region 44 of each shared transistor in the channel width W direction, but is provided only between the LDD regions 44 in the channel length L direction. In contrast, in the modification of the third embodiment, the N-well region 45 is provided adjacent to the LDD region 44 of each shared transistor in the channel width W direction, and is provided linearly on the side surface of the gate electrode 41 and the LDD region 44 of the three shared transistors in the channel width W direction. In this manner, the N-well region 45 may be provided continuously not only on the side surface of the gate electrode 41 but also on the side surface of the LDD region 44. Since the LDD region 44 can be formed as a single region by self-alignment using STI 51 in the channel length L direction, process variations in the ion implantation region during the formation of the LDD region 44 can be reduced. 13 is suitable when it is desired to reduce process variations in the direction of the channel length L, and the third embodiment in Fig. 11 is suitable when it is desired to reduce process variations in the direction of the channel width W. Similar to the third embodiment in Fig. 11, it is possible to prevent the gate electrode 41 of the shared transistor from being in contact with the element isolation layer from above and below, thereby suppressing deterioration of the dark characteristics.

[0084] 9. Manufacturing Method of Second and Third Embodiments A method of manufacturing the pixel structures according to the second and third embodiments will be described with reference to FIGS.

[0085] 14A, an insulating film 101 is formed by, for example, CVD, ALD, or the like on the front surface, which is the first surface, of the semiconductor substrate 21 on which the P-type semiconductor region 31 is formed. The insulating film 101 is, for example, a SiO2 film.

[0086] Next, as shown in FIG. 14B, the insulating film 101 and the P-type semiconductor region 31 are etched in the region where the STI 51 is to be formed, thereby forming a trench 102 dug to a predetermined depth in the semiconductor substrate 21.

[0087] 14C, an insulating film 103 is formed by, for example, CVD, ALD, or the like inside the formed trench 102 and on the entire upper surface of the insulating film 101. The insulating film 103 is, for example, the same SiO film as the insulating film 101.

[0088] 14D, the insulating film 103 is polished and planarized by CMP or the like until it is flush with the surface of the semiconductor substrate 21. After planarization, the insulating film 103 embedded inside the trench 102 forms the STI 51.

[0089] 14E, after an insulating film 104 is formed again over the entire upper surface of the planarized semiconductor substrate 21 using, for example, CVD, ALD, or the like, N-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted from the front surface side of the semiconductor substrate 21 into the regions where the photodiode PD and the N-well region 45 are to be formed, thereby forming the N-type semiconductor region 32 and the N-well region 45, respectively. The impurity concentration of the N-type semiconductor region 32 is formed to be higher than that of the N-well region 45. The ion implantation process for forming the N-type semiconductor region 32 and the N-well region 45 is not limited to this timing, and can also be performed at another timing.

[0090] 15A, after the insulating film 104 is removed by etching, a portion of the N-well region 45 formed in the region surrounded by the STI 51 is removed by etching. In the structure of the second embodiment shown in FIGS. 9 and 10, the entire N-well region 45 is etched to a uniform thickness from the substrate surface, but in the structure of the third embodiment shown in FIGS. 11 and 12, only the central portion of the N-well region 45 in the channel width W direction is etched, and the N-well region 45 is formed in a U-shape, as shown in the cross-sectional view surrounded by the dashed line.

[0091] 15B, an insulating film 53 is formed by, for example, CVD, ALD, etc. on the entire substrate surface including the N-well region 45 inside the STI 51. The insulating film 53 is, for example, an SiO2 film.

[0092] 15C, a gate electrode material 111 such as polysilicon is deposited by CVD or the like to a predetermined thickness on the entire upper surfaces of the insulating film 53 and the STI 51. The gate electrode material 111 may be a metal material containing, for example, titanium (Ti), tantalum (Ta), or aluminum (Al) in addition to polysilicon.

[0093] 15D, the gate electrode material 111 is planarized by CMP or the like until it is flush with the STI 51. The gate electrode material 111 remaining inside the STI 51 after planarization becomes the gate electrode 41 of the shared transistor such as the reset transistor RST, and the gate electrode 41 is embedded in the semiconductor substrate 21.

[0094] 16A, a hard mask 112 is formed by CVD, ALD, or the like on the entire upper surfaces of the planarized insulating film 53 and the gate electrode 41, and then a gate electrode region 113 of the transfer transistor TG is opened by etching. The material of the hard mask 112 is, for example, SiN.

[0095] 16B, a gate electrode material 114 such as polysilicon is deposited by CVD or the like to a predetermined thickness on the upper surface of the hard mask 112 and on the gate electrode region 113. The gate electrode material 114 may be a metal material containing, for example, titanium (Ti), tantalum (Ta), or aluminum (Al) in addition to polysilicon.

[0096] 16C, the gate electrode material 114 is planarized by CMP or the like until it is flush with the hard mask 112. The gate electrode material 114 buried in the gate electrode region 113 becomes the gate electrode 35 of the transfer transistor TG.

[0097] 16D, the hard mask 112 is removed by etching. Although not shown, thereafter, a step is performed in which N-type impurities are ion-implanted into a part of the N-well region 45 near the gate electrode 41 in the shared pixel region 2B to form an LDD region 44. Furthermore, together with the LDD region 44 in the shared pixel region 2B, an N-type semiconductor region (LDD region) 34 near the floating diffusion FD in the center of the 2x2 unit pixel region 2A is also formed at the same time.

[0098] 6B and 6C, an insulating material is deposited on the entire upper surface by CVD, ALD, or the like, and then etched back to form a sidewall 36 around the gate electrode 35 of the transfer transistor TG, as shown in E of Fig. 16. Note that, as with the first embodiment, the material and method for forming the sidewall 36 may be other known methods.

[0099] Next, with reference to FIGS. 17 and 18, a method for manufacturing the cross-sectional portions of the second and third embodiments taken along the line XX' in FIGS. 10 and 12 will be described.

[0100] FIG. 17A shows a state in which a contact interlayer film 92 is formed on the insulating film 53 after the step shown in FIG. 16E.

[0101] Next, as shown in FIG. 17B , the contact interlayer film 92 and the insulating film 53 are etched to form openings 121 in a portion of the upper surface of the gate electrode 41 of the shared transistor and in a portion of the upper surface of the LDD region 44. Then, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the formed openings 121 to further increase the concentration of the LDD region 44 and form source / drain regions 43. At the same time as the source / drain regions 43, a high-concentration N-type semiconductor region 33 (not shown in FIG. 17 ) that will become the floating diffusion FD is also formed. During this ion implantation, the N-type impurity is also implanted into the gate electrode 41 in which the opening 121 is formed. However, since the gate electrode 41 is already a high-concentration N-type semiconductor region, it is not shown in the drawing.

[0102] 17C, a metal material such as titanium (Ti), tantalum (Ta), or tungsten (W) is embedded in the openings 121 on the upper surfaces of the gate electrode 41 and the source / drain regions 43 to form contact wiring 91. Because the contact wiring 91 and the source / drain regions 43 are formed using the same openings 121, the contact wiring 91 can be formed robustly without being misaligned with respect to the source / drain regions 43. There is no risk of the contact wiring 91 being connected to the periphery away from the LDD region 44, causing leakage.

[0103] In this way, the pixel structures according to the second and third embodiments are completed.

[0104] According to the above-described manufacturing method, the source / drain region 43 is formed from the LDD region 44 by ion implantation of N-type impurities using the pattern (opening 121) for forming the contact wiring 91. As a result, the source / drain region 43 is formed apart from the gate electrode 41, as shown in FIG. 18A.

[0105] As another method for forming the source / drain regions 43, they may be formed by self-alignment using a pattern for forming the gate electrode 41. In this case, the source / drain regions 43 are formed up to the vicinity of the gate electrode 41, as shown in FIG. 18B.

[0106] 10. Fourth Embodiment A fourth embodiment of the photodetector 1 will be described with reference to FIGS. 19 and 20. FIG.

[0107] Fig. 19 is a plan view of a pixel region in the photodetector 1 according to the fourth embodiment, and Fig. 20 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 19. Fig. 20A is a cross-sectional view taken along line Y1-Y1' in Fig. 19, and Fig. 20B is a cross-sectional view taken along line XX' in Fig. 19. The contact interlayer film 54 is not shown in Fig. 20.

[0108] The fourth embodiment differs from the first embodiment in the shape of the gate electrode 41 of the shared transistor, but the other configurations are basically the same as those of the first embodiment. In the fourth embodiment, as shown in FIG. 20A, the end face of the gate electrode 41 embedded in the semiconductor substrate 21 contacts the inner end face of the STI 51, sharing one surface F1, similarly to the first embodiment. Meanwhile, in the first embodiment, the gate electrode 41 is formed only above the substrate surface of the semiconductor substrate 21, as shown in the cross-sectional view taken along line Y1-Y1' in FIG. 3A. In contrast, in the fourth embodiment, as shown in FIG. 20A, the gate electrode 41 is formed in an upside-down U-shape, and a portion of the gate electrode 41 is also formed below the substrate surface of the semiconductor substrate 21 (inside the semiconductor substrate 21). In other words, the lower surface of the gate electrode 41 has two different height positions: a first lower surface position on the STI 51 side and a second lower surface position on the central side, and the first lower surface positions on both sides of the gate electrode 41 are formed below the substrate surface and lower than the second lower surface position on the inside. The gate electrode 41 is shaped so that the N-well region 45 in which a channel is formed is sandwiched between the gate electrodes 41 buried in the substrate along the sidewalls on the inside of the STI 51.

[0109] According to the fourth embodiment, in addition to the same effects as those of the first embodiment described above, the modulation degree of the shared transistor can be further increased by sandwiching the N-well region 45, in which the channel portion below the gate electrode 41 is formed, between the gate electrodes 41 embedded in the substrate.

[0110] 11. Modification of the Fourth Embodiment Fig. 21 is a cross-sectional view showing a modification of the fourth embodiment described above. Fig. 21 corresponds to the cross-sectional view taken along line XX' in Fig. 19, and is a view in which a modification has been made to the cross-sectional view of B in Fig. 20.

[0111] In the modification of the fourth embodiment shown in FIG. 21 , the source / drain region 43 and the LDD region 44 formed in the shared pixel region 2B differ from those in the fourth embodiment shown in FIG. 20B. In the fourth embodiment, the drain region 43 and the LDD region 44 are formed shallower than the depth of the N-well region 45, as shown in FIG. 20B. In contrast, in the modification of the fourth embodiment, the drain region 43 and the LDD region 44 are formed to the same or approximately the same depth as the N-well region 45. When formed in this manner, as shown in FIG. 20A, the electron path at the interface between the N-well region 45 below the gate electrode 41 of the shared transistor formed below the substrate surface and the adjacent drain region 43 and LDD region 44 is widened, thereby increasing the on-current of the shared transistor and further improving the modulation degree.

[0112] 12. Manufacturing Method of Fourth Embodiment A method of manufacturing the pixel structure according to the above-described fourth embodiment will be described with reference to FIGS.

[0113] 22A, an insulating film 151 and a second insulating film 152 are formed on the front surface side of the semiconductor substrate 21, and then N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted from the front surface side of the semiconductor substrate 21 into regions where the photodiode PD and the N-well region 45 are to be formed, thereby forming the N-type semiconductor region 32 and the N-well region 45. The process of forming the insulating film 151 and the second insulating film 152 is the same as the process shown in FIG. 4A in the first embodiment, and the process of forming the N-type semiconductor region 32 and the N-well region 45 is the same as the process shown in FIG. 5B in the first embodiment.

[0114] Next, as shown in B of FIG. 22, the second insulating film 152, the insulating film 151, and the P-type semiconductor region 31 are etched in the region where the STI 51 is to be formed, thereby forming a trench 153 dug to a predetermined depth in the semiconductor substrate 21.

[0115] 22C, an insulating film 154 is formed by, for example, CVD, ALD, or the like inside the formed trench 153 and on the entire upper surface of the second insulating film 152. The insulating film 154 is, for example, the same SiO film as the insulating film 151.

[0116] 22D, the insulating film 154 is polished and planarized by CMP or the like until it is flush with the second insulating film 152. After planarization, the insulating film 154 embedded in the trench 153 forms the STI 51.

[0117] 23A, etching is performed based on a mask (not shown) patterned to match the recessed portion of the gate electrode 41 to be buried in the substrate, thereby forming a trench 161 along the sidewall inside the STI 51. Subsequently, as shown in FIG. 23B, the insulating film 151 and second insulating film 152 inside the trench 161 and the insulating film 151 and second insulating film 152 above the photodiode PD are removed by etching.

[0118] 23C, an insulating film 162 made of an SiO2 film or the like is formed on the entire front surface of the semiconductor substrate 21 by CVD, ALD, or the like, and then, as shown in Fig. 23D, a gate electrode material 163 such as polysilicon is formed by CVD or the like to a predetermined thickness on the entire upper surface of the insulating film 162. The gate electrode material 163 may be polysilicon or a metal material containing, for example, titanium (Ti), tantalum (Ta), aluminum (Al), or the like.

[0119] Next, as shown in FIG. 24A, the gate electrode material 163 is planarized by CMP or the like until it is flush with the STI 51 .

[0120] 24B, the gate electrode material 163 above the photodiode PD is removed by etching, leaving a portion thereof. The portion of the gate electrode material 163 remaining above the photodiode PD becomes the gate electrode 35 of the transfer transistor TG, and the gate electrode material 163 surrounded by the STI 51 becomes the gate electrode 41 of the shared transistors such as the reset transistor RST.

[0121] Although not shown in the drawings, thereafter, a step is performed in which N-type impurities are ion-implanted into a part of the N-well region 45 near the gate electrode 41 of the shared pixel region 2B to form an LDD region 44. Furthermore, together with the LDD region 44 of the shared pixel region 2B, an N-type semiconductor region (LDD region) 34 near the floating diffusion FD in the center of the 2x2 unit pixel region 2A is also formed at the same time.

[0122] 24C, an insulating material 164 is deposited by, for example, CVD, ALD, etc. on the entire upper surfaces of the gate electrode 35 of the transfer transistor TG, the gate electrode 41 of the shared transistor, the STI 51, etc. This insulating material 164 is a material that forms the sidewall 36 around the periphery of the gate electrode 35 of the transfer transistor TG and the sidewall 52 around the periphery of the STI 51, and may be, for example, SiO2 or SiN.

[0123] 24D, the insulating material 164 formed on the entire upper surface is etched back to form a sidewall 36 around the gate electrode 35 of the transfer transistor TG and a sidewall 52 around the STI 51. Note that the method for forming the sidewalls 36 and 52 is not limited to this, and other methods may also be used. Furthermore, the sidewalls 36 and 52 may be made of a laminated film of SiO, SiN, or the like.

[0124] Although not shown in the drawings, thereafter, a step is performed in which N-type impurities are further ion-implanted into a part of the LDD region 44 near the gate electrode 41 in the shared pixel region 2B to form a source / drain region 43. Furthermore, simultaneously with the source / drain region 43, a high-concentration N-type semiconductor region 33 that will become a floating diffusion FD is also formed.

[0125] Finally, although not shown, similar to the process shown in A of FIG. 6, the insulating film 53 is formed again above the photodiode PD, and then the contact interlayer film 54 is formed over the entire surface of the pixel region, thereby completing the structure shown in A of FIG. 20.

[0126] In this way, the pixel structure according to the fourth embodiment is completed.

[0127] 13. Fifth Embodiment A fifth embodiment of the photodetector 1 will be described with reference to FIGS. 25 and 26. FIG.

[0128] Fig. 25 is a plan view of a pixel region in the photodetector 1 according to the fifth embodiment, and Fig. 26 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 25. Fig. 26A is a cross-sectional view taken along line Y1-Y1' in Fig. 25, and Fig. 26B is a cross-sectional view taken along line XX' in Fig. 25. The contact interlayer film 54 is not shown in Fig. 25.

[0129] The fifth embodiment is similar to the fourth embodiment shown in FIGS. 19 and 20 in that the gate electrode 41 of the shared transistor protrudes downward along the inner sidewall of the STI 51 and is formed in an upside-down U-shape. The fifth embodiment differs from the fourth embodiment in that the downwardly protruding portion of the gate electrode 41 is below the substrate surface of the semiconductor substrate 21, i.e., within the substrate, in the fourth embodiment, whereas the downwardly protruding portion of the gate electrode 41 is above the substrate surface of the semiconductor substrate 21 in the fifth embodiment. In other words, the lower surface of the gate electrode 41 has two different height positions: a first lower surface position on the STI 51 side and a second lower surface position on the central side. The first lower surface positions on both sides of the gate electrode 41 are formed above the substrate surface and lower than the second lower surface position on the inside. The N-well region 45 in which a channel portion under the gate electrode 41 is formed is also formed above the substrate surface of the semiconductor substrate 21. The remaining configuration is similar to that of the fourth embodiment. For example, the edge of the gate electrode 41 embedded inside the semiconductor substrate 21 contacts the inner edge of the STI 51, sharing one surface F1, which is the same as in the fourth embodiment.

[0130] According to the fifth embodiment, in addition to the same effects as those of the first embodiment described above, the modulation degree of the shared transistor can be further increased by sandwiching the N-well region 45, in which the channel portion below the gate electrode 41 is formed, between the gate electrodes 41.

[0131] 14. Modification of Fifth Embodiment Fig. 27 is a cross-sectional view showing a modification of the fifth embodiment described above. Fig. 27 corresponds to the cross-sectional view taken along line XX' in Fig. 25, and is a view in which a modification has been made to the cross-sectional view of B in Fig. 26.

[0132] In the modification of the fourth embodiment shown in FIG. 27 , the source / drain region 43 and the LDD region 44 formed in the shared pixel region 2B differ from those in the fifth embodiment shown in FIG. 26B. In the fifth embodiment, the N-well region 45 in which the channel portion is formed is formed above the substrate surface of the semiconductor substrate 21, and the drain region 43 and the LDD region 44 are formed below the substrate surface of the semiconductor substrate 21, as shown in FIG. 26B. In contrast, in the modification of the fifth embodiment, the drain region 43 and the LDD region 44 are formed above the substrate surface in the same layer as the N-well region 45, at the same or substantially the same depth as the N-well region 45. When formed in this manner, as shown in FIG. 27 , the electron path at the interface between the N-well region 45 below the gate electrode 41 of the shared transistor formed above the substrate surface and the adjacent drain region 43 and LDD region 44 is widened, thereby increasing the on-current of the shared transistor and further improving the modulation degree.

[0133] 15. Manufacturing Method of Fifth Embodiment A method of manufacturing the pixel structure according to the fifth embodiment will be described with reference to FIGS.

[0134] 28A, an insulating film 181 and a second insulating film 182 are formed on the front surface side of the semiconductor substrate 21, and then an N-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted from the front surface side of the semiconductor substrate 21 into the formation region of the photodiode PD to form an N-type semiconductor region 32. The film formation process of the insulating film 181 and the second insulating film 182 is the same as the process shown in FIG. 4A in the first embodiment, and the process of forming the N-type semiconductor region 32 is the same as the process shown in FIG. 5B in the first embodiment. The difference from the above-described fourth embodiment is that an N-well region 45 is not formed in the shared pixel region 2B.

[0135] Next, as shown in B of FIG. 28, the second insulating film 182, the insulating film 181, and the P-type semiconductor region 31 are etched in the region where the STI 51 is to be formed, thereby forming a trench 183 dug to a predetermined depth in the semiconductor substrate 21.

[0136] 28C, an insulating film 184 is formed by, for example, CVD, ALD, or the like inside the formed trench 183 and on the entire upper surface of the second insulating film 182. The insulating film 184 is, for example, the same SiO film as the insulating film 181.

[0137] 28D, the insulating film 184 is polished and planarized by CMP or the like until it is flush with the second insulating film 182. After planarization, the insulating film 184 embedded inside the trench 183 forms the STI 51.

[0138] 29A, the second insulating film 182 and the insulating film 181 are etched based on a mask (not shown) patterned in accordance with the N-well region 45 of the shared pixel region 2B, thereby forming a trench 185. Subsequently, as shown in FIG. 29B, the N-well region 45 is formed in the trench 185 by epitaxial growth.

[0139] Next, as shown in FIG. 29C, the insulating film 181 and the second insulating film 182 inside the STI 51 and the insulating film 181 and the second insulating film 182 above the photodiode PD are removed by etching.

[0140] 29D, an insulating film 191 made of an SiO2 film or the like is formed on the entire front surface of the semiconductor substrate 21 by CVD, ALD, or the like, and then a gate electrode material 192, such as polysilicon, is formed by CVD or the like to a predetermined thickness on the entire upper surface of the insulating film 191. The gate electrode material 192 may be polysilicon or a metal material containing, for example, titanium (Ti), tantalum (Ta), aluminum (Al), or the like.

[0141] Next, as shown in FIG. 30A, the gate electrode material 192 is planarized by CMP or the like until it is flush with the STI 51 .

[0142] 30B, the gate electrode material 192 above the photodiode PD is removed by etching, leaving a portion thereof. The portion of the gate electrode material 192 remaining above the photodiode PD becomes the gate electrode 35 of the transfer transistor TG, and the gate electrode material 192 surrounded by the STI 51 becomes the gate electrode 41 of the shared transistor such as the reset transistor RST.

[0143] Although not shown in the drawings, thereafter, a step is performed in which N-type impurities are ion-implanted into a part of the N-well region 45 near the gate electrode 41 of the shared pixel region 2B to form an LDD region 44. Furthermore, together with the LDD region 44 of the shared pixel region 2B, an N-type semiconductor region (LDD region) 34 near the floating diffusion FD in the center of the 2x2 unit pixel region 2A is also formed at the same time.

[0144] 30C, an insulating material 193 is deposited by, for example, CVD, ALD, etc. on the entire upper surfaces of the gate electrode 35 of the transfer transistor TG, the gate electrode 41 of the shared transistor, the STI 51, etc. This insulating material 193 is a material that forms the sidewall 36 around the periphery of the gate electrode 35 of the transfer transistor TG and the sidewall 52 around the periphery of the STI 51, and may be, for example, SiO2 or SiN.

[0145] 30D, the insulating material 193 formed on the entire upper surface is etched back to form a sidewall 36 around the gate electrode 35 of the transfer transistor TG and a sidewall 52 around the STI 51. Note that the method for forming the sidewalls 36 and 52 is not limited to this, and other methods may also be used. Furthermore, the sidewalls 36 and 52 may be made of a laminated film of SiO, SiN, or the like.

[0146] Although not shown in the drawings, thereafter, a step is performed in which N-type impurities are further ion-implanted into a part of the LDD region 44 near the gate electrode 41 in the shared pixel region 2B to form a source / drain region 43. Furthermore, simultaneously with the source / drain region 43, a high-concentration N-type semiconductor region 33 that will become a floating diffusion FD is also formed.

[0147] Finally, although not shown, similar to the process shown in A of FIG. 6, the insulating film 53 is formed again above the photodiode PD, and then the contact interlayer film 54 is formed over the entire surface of the pixel region, thereby completing the structure shown in A of FIG. 26.

[0148] In this way, the pixel structure according to the fifth embodiment is completed.

[0149] 16. Sixth Embodiment A sixth embodiment of the photodetector 1 will be described with reference to FIGS. 31 and 32. FIG.

[0150] Fig. 31 is a plan view of a pixel region in the photodetector 1 according to the sixth embodiment, and Fig. 32 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 31. Fig. 32A is a cross-sectional view taken along line Y1-Y1' in Fig. 31, and Fig. 32B is a cross-sectional view taken along line XX' in Fig. 31.

[0151] In the sixth embodiment, as shown in FIG. 32 , the gate electrode 41 of the shared transistor formed inside the STI 51 in the shared pixel region 2B is formed above the substrate surface of the semiconductor substrate 21, as in the first embodiment. The sixth embodiment differs from the first embodiment in that, while the peripheries of the gate electrode 35, gate electrode 41, and STI 51 are covered with sidewalls 36, 42, and 52 in the first embodiment, the sidewalls 36, 42, and 52 are omitted in the sixth embodiment. Instead, an insulating film 211 of the same thickness as the gate electrodes 35 and 41 is embedded in the region between the STI 51 and the gate electrodes 35 and 41, in the same layer as the gate electrodes 35 and 41. The insulating film 211 is made of a material different from the insulating material of the STI 51. For example, if the STI 51 is made of a SiO film, the insulating film 211 can be made of a SiN film. Alternatively, the STI 51 may be made of a SiN film and the insulating film 211 may be made of a SiO film.

[0152] The contact wiring 221 and contact interlayer film 223 connected to the source / drain region 43 of the shared transistor are similar to the contact wiring 91 and contact interlayer film 92 in the second and third embodiments, respectively. The contact wiring 221 is made of a metal material such as titanium (Ti), tantalum (Ta), or tungsten (W). The contact interlayer film 223 can be made of, for example, SiO2, SiN, or SiON. The insulating film 222 formed around the contact wiring 221 may be made of the same material as the contact interlayer film 223 or a different material, but is formed in a separate process from the contact interlayer film 223.

[0153] In the sixth embodiment, the gate electrode 41 of the shared transistor is also surrounded by the STI 51, which is an element isolation layer formed in the shared pixel region 2B, and is formed inside the STI 51. The end face of the gate electrode 41 embedded in the semiconductor substrate 21 abuts the inner end face of the STI 51, sharing a single surface F1. Furthermore, the top surfaces of the gate electrode 41 of the shared transistor and the STI 51 are formed at the same height, and there is no region where the gate electrode 41 of the shared transistor and the STI 51 overlap vertically (i.e., overlapping region in plan view). Therefore, when a portion of the gate electrode 41 rides on top of the STI 51 and the shared transistor is turned on, the surface potential of the STI 51 increases, preventing a decrease in the hole concentration in the P-type semiconductor region 31 adjacent to the STI 51. In other words, this prevents the gate electrode 41 of the shared transistor from abutting the element isolation layer vertically, thereby suppressing degradation of dark characteristics.

[0154] Since the STI 51 is recessed downward from the substrate surface from the same upper surface position as the gate electrode 41, the height H1 of the gate electrode 35 of the transfer transistor TG is smaller than the height H2 of the STI 51.

[0155] 17. Manufacturing Method of Sixth Embodiment A method of manufacturing the pixel structure according to the sixth embodiment will be described with reference to FIGS.

[0156] 33A, an insulating film 53 is first formed on the front surface of the semiconductor substrate 21. Then, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted from the front surface of the semiconductor substrate 21 into the regions where the photodiode PD and the N-well region 45 are to be formed, thereby forming the N-type semiconductor region 32 and the N-well region 45, respectively. The process of forming the insulating film 53 is the same as the process shown in FIG. 4A in the first embodiment, and the process of forming the N-type semiconductor region 32 and the N-well region 45 is the same as the process shown in FIG. 5B in the first embodiment. The process of forming the N-type semiconductor region 32 and the N-well region 45 is not limited to this timing, and may be performed, for example, after the formation of the next insulating film 211.

[0157] 33B, an insulating film 211 is formed on the insulating film 53 by, for example, CVD, ALD, or the like. The insulating film 211 is made of a material different from the insulating material of the STI 51. For example, when the STI 51 is made of an SiO2 film, the insulating film 211 can be made of a SiN film.

[0158] Next, as shown in C of FIG. 33 , the insulating film 211 is patterned to open an area where the STI 51 is to be formed, and the patterned insulating film 211 is used as a mask to etch the insulating film 53 and the P-type semiconductor region 31, thereby forming a trench 252 dug to a predetermined depth in the semiconductor substrate 21.

[0159] 33D, an insulating film 253 is formed by, for example, CVD, ALD, or the like inside the formed trench 252 and on the entire upper surface of the insulating film 211. The insulating film 253 is, for example, the same SiO film as the insulating film 53.

[0160] 34A, the insulating film 253 is polished and planarized by CMP or the like until it is flush with the insulating film 211. After planarization, the insulating film 253 embedded in the trench 252 forms the STI 51.

[0161] Next, as shown in B of Fig. 34 , the insulating film 211 in the gate electrode region 254 of the transfer transistor TG and the gate electrode region 255 of the shared transistor is opened by etching using a patterned mask (not shown). In the example of B of Fig. 34 , the insulating film 53 under the insulating film 211 is left in the gate electrode regions 254 and 255, but the insulating film 53 may also be removed once along with the insulating film 211, and then the insulating film 53 may be deposited again.

[0162] 34C, a gate electrode material 256 such as polysilicon is formed by CVD or the like to a predetermined thickness on the entire upper surfaces of the gate electrode regions 254 and 255, the insulating film 211, and the STI 51. The gate electrode material 256 may be a metal material containing, for example, titanium (Ti), tantalum (Ta), aluminum (Al), or the like, in addition to polysilicon.

[0163] 34D, the gate electrode material 256 is planarized by CMP or the like until it is flush with the STI 51. The gate electrode material 256 embedded in the gate electrode region 254 becomes the gate electrode 35 of the transfer transistor TG, and the gate electrode material 256 embedded in the gate electrode region 255 becomes the gate electrode 41 of the shared transistor.

[0164] Next, a method for manufacturing the cross section taken along line XX' of the sixth embodiment will be described with reference to FIG.

[0165] After the planarization step shown in FIG. 34D, as shown in FIG. 35A, a contact interlayer film 223 is formed on the insulating film 211 by CVD, ALD, or the like.

[0166] Next, as shown in FIG. 35B , the contact interlayer film 223, the insulating film 211, and the like are etched in a portion of the upper surface of the gate electrode 41 of the shared transistor and in a portion of the upper surface of the N-well region 45, forming an opening 261. Then, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the formed opening 261 to form an LDD region 44 that further increases the concentration of the N-well region 45. At this point, the impurity concentration of the LDD region 44 is adjusted to, for example, approximately 1e+19 / cm or less. During this ion implantation, the N-type impurity is also implanted into the gate electrode 41 in which the opening 261 is formed. However, since the gate electrode 41 is already a highly-doped N-type semiconductor region, this is not shown in the drawing.

[0167] 35C, an insulating film 222 is formed inside the opening 261 and on the upper surface of the contact interlayer film 223. CVD, ALD, or the like can be used to form the insulating film 222, but in order to avoid clogging, it is preferable to use ALD, which can provide good coverage at the atomic layer level. The insulating film 222 is, for example, a SiO2 film.

[0168] 36A, N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the opening 261 to form source / drain regions 43 that further increase the concentration of the LDD region 44. In this ion implantation, the N-type impurities are also implanted into the gate electrode 41 in which the opening 261 is formed, but since the gate electrode 41 is already a highly-doped N-type semiconductor region, it is not shown in the drawing.

[0169] 36B, the insulating film 222 formed on the bottom surface of the opening 261 is removed by etching. At this time, the insulating film 222 formed on the upper surface of the contact interlayer film 223 is also removed at the same time.

[0170] Finally, as shown in FIG. 36C, a metal material such as titanium (Ti), tantalum (Ta), or tungsten (W) is filled into the openings 261 on the upper surface of the gate electrode 41 and the upper surface of the source / drain region 43, and then the metal material formed on the upper surface of the contact interlayer film 223 is removed by CMP or etching, thereby forming the contact wiring 221.

[0171] According to the above-described manufacturing method, the contact wiring 221 and the source / drain region 43 are formed using the same opening 261, so that the contact wiring 221 can be formed robustly without being misaligned with respect to the source / drain region 43. There is also no risk of the contact wiring 225 being disconnected from the LDD region 44 and connected to the periphery, causing leakage.

[0172] Furthermore, according to the above-described manufacturing method, the insulating film 211 used as a mask when forming the trench 252 for forming the STI 51 can be reused as an insulating film in the same planar region as the gate electrodes 35 and 41, thereby reducing the number of processing steps and reducing damage.

[0173] <18. Modified Examples of Transfer Transistor> <First Modified Example> Next, a modified example of the transfer transistor TG that can be applied in combination with the case where the gate electrode 41 of the shared transistor is a buried gate electrode provided below the semiconductor substrate 21 (inside the semiconductor substrate 21) will be described. Of the first to sixth embodiments described above, the second and third embodiments apply when the gate electrode 41 of the shared transistor is a buried gate electrode. Therefore, the modified example of the transfer transistor TG described below can be configured in combination with the structures of the shared transistors of the second and third embodiments described above.

[0174] Fig. 37 is a plan view of a pixel region to which a first modified example of a transfer transistor is applied, and Fig. 38 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 37. Fig. 38A is a cross-sectional view taken along line Z1-Z1' in Fig. 37, and Fig. 38B is a cross-sectional view taken along line Z2-Z2' in Fig. 37.

[0175] 38 , in accordance with the gate electrode 41 of the shared transistor formed of a buried gate electrode, the gate electrode 35 of the transfer transistor TG is also a buried gate electrode provided below the semiconductor substrate 21 (inside the semiconductor substrate 21). The depth of the gate electrode 35 from the substrate surface of the semiconductor substrate 21 to the bottom surface of the gate electrode 35 is formed to be the same as the depth of the gate electrode 41 of the shared transistor.

[0176] The transfer transistor TG with the buried gate electrode structure can modulate the potential to a deeper position in the photodiode PD compared to a planar gate electrode structure, thereby reducing transfer failures of signal charges (electrons). The manufacturing method will be described later, but the gate electrode 41 of the shared transistor and the gate electrode 35 of the transfer transistor TG are formed simultaneously, which reduces processing variations and damage.

[0177] As is clear from the plan view of FIG. 37 , the planar shape of the gate electrode 35 of the transfer transistor TG is trapezoidal, with the electrode width narrowing toward the floating diffusion FD, as in the first to sixth embodiments described above. However, the planar shape of the gate electrode 35 is not limited to a trapezoidal shape and may be, for example, circular, as shown in FIG. 39 . The plan view of FIG. 39 is a plan view showing variations in the planar shape of the gate electrode 35. By making the planar shape of the gate electrode 35 circular, it is possible to avoid forming acute angles in the substrate, thereby further reducing electric field concentration and processing damage and suppressing charge generation in the dark.

[0178] <Second Modification> Fig. 40 is a plan view of a pixel region to which a second modification of the transfer transistor is applied, and Fig. 41 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 40. Fig. 41A is a cross-sectional view taken along line Z1-Z1' in Fig. 40, and Fig. 41B is a cross-sectional view taken along line Z2-Z2' in Fig. 40.

[0179] In the second modification, as in the first modification, the gate electrode 35 of the transfer transistor TG is a buried gate electrode. The difference from the first modification described with reference to FIGS. 37 and 38 is that two gate electrodes 35 of the transfer transistor TG are provided in one unit pixel region 2A. As shown in FIG. 40 , the two gate electrodes 35 have a triangular planar shape, and are arranged so that one of the three sides of the triangle, which has the longest length, faces each other. The depth of the gate electrode 35 from the substrate surface of the semiconductor substrate 21 to the bottom surface of the gate electrode 35 is the same as the depth of the gate electrode 41 of the shared transistor.

[0180] In this way, the transfer transistor TG may be configured to have two gate electrodes 35 in one unit pixel region 2 A. Furthermore, by arranging the two gate electrodes 35 so that one side (edge) having the longest length faces each other and ensuring a wide facing surface, it is possible to increase the potential difference between the photodiode PD and the floating diffusion FD when the transfer transistor TG is turned on and off, allowing more signal charge (electrons) to be stored in the photodiode PD and widening the dynamic range.

[0181] In the second modification, the transfer transistor TG with the buried gate electrode can reduce transfer failure of signal charges (electrons) compared to a planar gate electrode. Since the gate electrode 41 of the shared transistor and the gate electrode 35 of the transfer transistor TG can be formed simultaneously, processing variations and damage can be reduced.

[0182] Also, in the second modification, as in the first modification, the planar shape of the gate electrode 35 is not limited to a trapezoidal shape, and may be a circular shape. Fig. 42 is a plan view showing an example in which the planar shape of the gate electrode 35 is a circular shape when the transfer transistor TG has two gate electrodes 35. By making the planar shape of the gate electrode 35 circular, it is possible to avoid forming acute angles in the substrate, which makes it possible to further reduce electric field concentration and processing damage, and suppress charge generation in the dark.

[0183] It should be noted that, depending on the size of the unit pixel region 2A, the transfer transistor TG may have three or more gate electrodes 35 instead of two gate electrodes 35.

[0184] 19. Manufacturing Method of Modified Transfer Transistor A manufacturing method of the first modified transfer transistor described above will be described with reference to Figures 43 to 45. The cross-sectional views shown in Figures 43 to 45 correspond to the cross-sectional view taken along line Z3-Z3' in Figure 46.

[0185] 43A, an insulating film 301 is formed by, for example, CVD, ALD, etc. on the front surface, which is the first surface, of the semiconductor substrate 21 on which the P-type semiconductor region 31 is formed. The insulating film 301 is, for example, an SiO2 film.

[0186] Next, as shown in FIG. 43B, the insulating film 301 and the P-type semiconductor region 31 are etched in the region where the STI 51 is to be formed, thereby forming a trench 302 dug to a predetermined depth in the semiconductor substrate 21.

[0187] 43C, an insulating film 303 is formed by, for example, CVD, ALD, or the like inside the formed trench 302 and over the entire upper surface of the insulating film 301. The insulating film 303 is, for example, the same SiO film as the insulating film 301.

[0188] 43D, the insulating film 303 is polished and planarized by CMP or the like until it is flush with the semiconductor substrate 21. After planarization, the insulating film 303 embedded inside the trench 302 forms the STI 51.

[0189] 44A, an insulating film 311 is formed over the entire front surface of the semiconductor substrate 21 by CVD, ALD, or the like, and then N-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted from the front surface side of the semiconductor substrate 21 into the regions where the photodiode PD and N-well region 45 are to be formed, thereby forming the N-type semiconductor region 32 and the N-well region 45, respectively. The impurity concentration of the N-type semiconductor region 32 is formed to be higher than that of the N-well region 45. The ion implantation process for forming the N-type semiconductor region 32 and the N-well region 45 is not limited to this timing and can also be performed at another timing.

[0190] Next, as shown in B of Fig. 44, after the insulating film 311 is removed by etching, a region 312 for forming the gate electrode 41 of the shared transistor and a region 313 for forming the gate electrode 35 of the transfer transistor TG are removed by etching. The regions 312 and 313 are recessed to the same depth. When the gate electrode structure of the shared transistor is the structure of the second embodiment shown in Figs. 9 and 10, the entire N-well region 45 is etched to a uniform thickness from the substrate surface, but when it is the structure of the third embodiment shown in Figs. 11 and 12, only the central portion of the N-well region 45 in the channel width W direction is etched, as shown in the cross-sectional view surrounded by a dashed line, and the N-well region 45 is formed in a U-shape.

[0191] 44C, an insulating film 53 is formed by, for example, CVD, ALD, etc. on the entire substrate surface including the regions 312 and 313. The insulating film 53 is, for example, an SiO2 film.

[0192] 45A, a gate electrode material 321 such as polysilicon is deposited by CVD or the like to a predetermined thickness on the entire upper surfaces of the insulating film 53 and the STI 51. The gate electrode material 321 may be a metal material containing, for example, titanium (Ti), tantalum (Ta), aluminum (Al), or the like, in addition to polysilicon.

[0193] Next, as shown in B of FIG. 45 , the gate electrode material 321 is planarized using CMP or the like until it is flush with the STI 51. The gate electrode material 321 remaining inside the STI 51 after planarization becomes the gate electrode 41 of the shared transistor such as the reset transistor RST, and the gate electrode 41 is embedded within the semiconductor substrate 21. The gate electrode material 321 remaining in a portion above the photodiode PD becomes the gate electrode 35 of the transfer transistor TG, and the gate electrode 35 is also embedded within the semiconductor substrate 21. In B of FIG. 45 , the insulating film 53 is left in the planarization step, but the insulating film 53 may be removed once and then re-formed.

[0194] As shown in C of Figure 45, an LDD region 34 is formed by ion-implanting N-type impurities such as phosphorus (P) and arsenic (As) into the center part inside the gate electrode 35 of the transfer transistor TG of the 2x2 unit pixel region 2A, and further, by ion-implanting N-type impurities inside the LDD region 34, a high-concentration N-type semiconductor region 33 that becomes a floating diffusion FD is formed.

[0195] In this manner, the buried gate electrode structure of the transfer transistor TG can be formed together with the buried gate electrode structure of the shared transistor of the second and third embodiments described above. Since the transfer transistor TG and the shared transistor can be formed simultaneously with the buried gate electrode structure, it is possible to reduce processing variations and damage.

[0196] 20. Combination with Pixel Separation Section In the first to sixth embodiments described above, a pixel separation section that separates the photodiodes PD into unit pixel regions 2A may be further provided.

[0197] 47 and 48 show an example of a configuration in which a pixel separating section is further provided in the first embodiment shown in FIGS.

[0198] Fig. 47 is a plan view of a pixel region of the first embodiment provided with a pixel separation portion, and Fig. 48 is a cross-sectional view taken along a predetermined cross-sectional line in the plan view of Fig. 47. Fig. 48A is a cross-sectional view taken along line Y1-Y1' in Fig. 47, Fig. 48B is a cross-sectional view taken along line Y2-Y2' in Fig. 47, and Fig. 48C is a cross-sectional view taken along line XX' in Fig. 47.

[0199] As shown in the plan view of FIG. 47 , the pixel separator 351 is disposed around the photodiode PD formed in the unit pixel region 2A and separates adjacent photodiodes PD. As shown in the cross-sectional view of FIG. 48 , the pixel separator 351 has a full trench structure penetrating the thickness direction of the semiconductor substrate 21. In the shared pixel region 2B, the pixel separator 351 is formed to include at least the same planar area as the STI 51, and the STI 51 is disposed on the front surface side of the semiconductor substrate 21, which is the tip of the pixel separator 351. The pixel separator 351 is formed, for example, by embedding an insulating film such as SiO2. The pixel separator 351 may also be configured by further embedding a metal material such as tungsten, aluminum, silver, or copper inside the insulating film. If necessary, a film of a material that improves adhesion, such as Ti or TiN, may be deposited to a thickness of several nanometers to several tens of nanometers before depositing these metal films. Embedding the metal material in the pixel separator 351 can further enhance the shielding effect against optical crosstalk. The pixel separator 351 may also have a gap inside the insulating film. In this case, crosstalk caused by light can be suppressed by interfacial reflection due to a difference in refractive index. Alternatively, the pixel separator 351 may be formed, for example, from a P-type semiconductor region and grounded. In this case, crosstalk caused by charge rolling can be suppressed. The pixel separator 351 may be formed using DTI (Deep Trench Isolation), which is a trench structure that extends to a predetermined depth in the semiconductor substrate 21, rather than a full trench structure that penetrates the semiconductor substrate 21 in the thickness direction.

[0200] 47 and 48, the configuration other than the provision of the pixel separating section is the same as that of the first embodiment shown in FIGS. 2 and 3, and therefore a description of the configuration other than the pixel separating section will be omitted.

[0201] 21. Example of a Stacked Structure Using Multiple Substrates In the above-described embodiment, an example has been described in which the photodetector 1 is configured using one substrate (semiconductor substrate 21). The photodetector 1 may be configured by stacking two or three substrates. With reference to FIG. 49 , a case in which the photodetector 1 is configured with a stacked structure of three substrates will be described.

[0202] Fig. 49 shows a schematic configuration example of the photodetector 1 when it is configured with a stacked structure of three substrates. In Fig. 49, parts corresponding to the configuration described above are given the same reference numerals, and their description will be omitted as appropriate.

[0203] 49 has a three-dimensional structure in which a first substrate 411, a second substrate 412, and a third substrate 413 are bonded together. The first substrate 411, the second substrate 412, and the third substrate 413 are stacked in this order.

[0204] The first substrate 411 has a semiconductor substrate 441 made of, for example, silicon (Si), and a pixel region 512 in which a plurality of sensor pixels 511 are two-dimensionally arranged in a matrix is ​​formed on the semiconductor substrate 441. The sensor pixel 511 includes at least the above-mentioned photodiode PD and transfer transistor TG.

[0205] The second substrate 412 has a semiconductor substrate 442 made of, for example, silicon (Si), and a readout circuit 521 is formed on the semiconductor substrate 442. The readout circuit 521 outputs pixel signals based on charges generated in the sensor pixels 511. The readout circuit 521 corresponds to, for example, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL described above, and when a shared pixel structure is adopted, one readout circuit 521 is arranged for multiple sensor pixels 511. A plurality of pixel drive wirings 522 extending in the row direction and a plurality of vertical signal lines 523 extending in the column direction are also formed on the second substrate 412.

[0206] The third substrate 413 has a semiconductor substrate 443 made of, for example, silicon (Si), and a logic circuit 541 that processes pixel signals is formed on the semiconductor substrate 443. The logic circuit 541 includes, for example, a vertical drive circuit 551, a column processing circuit 552, a horizontal drive circuit 553, and a system control circuit 554. The vertical drive circuit 551, the column processing circuit 552, the horizontal drive circuit 553, and the system control circuit 554 have functions similar to those of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the control circuit 8 in FIG. 1, respectively. The horizontal drive circuit 553 sequentially selects the column signal processing circuits in the column processing circuit 552, and pixel signals acquired from each column signal processing circuit are output from an output terminal 555.

[0207] FIG. 50 shows an example of the configuration of the sensor pixels 511 and the readout circuit 521. FIG. 50 describes a case where four sensor pixels 511 share one readout circuit 521. Here, "shared" means that the outputs of the four sensor pixels 511 are input to a common readout circuit 521. When distinguishing between the four sensor pixels 511 that share one readout circuit 521, they are referred to as sensor pixels 511A, 511B, 511C, and 511D, as shown in FIG. 50. The sensor pixels 511A, 511B, 511C, and 511D are formed on the first substrate 411, for example, and the readout circuit 521 is formed on the second substrate 412, for example.

[0208] The sensor pixels 511A, 511B, 511C, and 511D have common components. Hereinafter, when distinguishing between the components of the sensor pixels 511A, 511B, 511C, and 511D, the reference numerals of the components of the sensor pixel 511A will be suffixed with "a," the reference numerals of the components of the sensor pixel 511B will be suffixed with "b," the reference numerals of the components of the sensor pixel 511C will be suffixed with "c," and the reference numerals of the components of the sensor pixel 511D will be suffixed with "d." When it is not necessary to distinguish between the components of the sensor pixels 511A, 511B, 511C, and 511D, the identification symbols "a," "b," "c," and "d" at the end of the reference numerals of the components of the sensor pixels 511A, 511B, 511C, and 511D will be omitted.

[0209] Each sensor pixel 511 includes, for example, a photodiode PD as a photoelectric conversion unit, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TG. The cathodes of the photodiodes PD (PDa, PDb, PDc, and PDd) are electrically connected to the sources of the transfer transistors TG (TGa, TGb, TGc, and TGd), and the anodes are electrically connected to a reference potential line (e.g., ground). The photodiodes PD photoelectrically convert incident light and generate signal charges corresponding to the amount of received light. The transfer transistors TG are, for example, N-type MOS transistors. The drains of the transfer transistors TG are electrically connected to the floating diffusions FD (FDa, FDb, FDc, and FDd), and the gates are electrically connected to pixel drive wiring. The pixel drive wiring is part of multiple pixel drive wirings 522 ( FIG. 49 ) connected to a single readout circuit 521. The transfer transistors TG transfer the charges generated by the photodiodes PD to the floating diffusions FD. The floating diffusion FD is composed of, for example, an N-type semiconductor region formed in a P-type semiconductor region. The floating diffusion FD is a charge storage section that temporarily stores the signal charge transferred from the photodiode PD, and also a charge-voltage conversion section that generates a voltage according to the amount of charge.

[0210] The four floating diffusions FDa, FDb, FDc, and FDd included in one readout circuit 521 are electrically connected to each other and to the gate of the amplifier transistor AMP and the source of the reset transistor RST. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to a pixel drive line. This pixel drive line is part of the multiple pixel drive lines 522 connected to one readout circuit 521. The gate of the amplifier transistor AMP is connected to the floating diffusions FDa, FDb, FDc, and FDd, the drain of the amplifier transistor AMP is connected to a power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 523, and the gate of the selection transistor SEL is connected to the pixel drive line. This pixel drive line is part of the multiple pixel drive lines 522 connected to one readout circuit 521.

[0211] The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 521. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 523 via the selection transistor SEL. This amplification transistor AMP forms a source follower together with a load circuit section in the column processing circuit 552 connected to the vertical signal line 523. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column processing circuit 552 via the vertical signal line 523. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type MOS transistors.

[0212] The select transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the select transistor SEL is electrically connected to the pixel drive wiring 522. The source of the amplifier transistor AMP (the output terminal of the readout circuit 521) is electrically connected to the vertical signal line 523, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST.

[0213] The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL that constitute the readout circuit 521 are formed on the second substrate 412 in the pixel structures of the first to sixth embodiments described above.

[0214] Although not shown in the drawings, the number of sensor pixels 511 that share one readout circuit 521 may be other than four. For example, two or eight sensor pixels 511 may share one readout circuit 521. Alternatively, instead of a configuration in which the readout circuit 521 is shared by a plurality of sensor pixels 511, a readout circuit 521 may be provided for each pixel.

[0215] 22. Configuration Examples of Electronic Devices The above-described photodetector 1 can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0216] FIG. 51 is a block diagram showing an example of the configuration of an electronic device.

[0217] 51 , electronic device 601 includes an optical system 602, a photodetector 603, a DSP (Digital Signal Processor) 604, a display device 605, an operation system 606, a memory 607, a recording device 608, and a power supply system 609. DSP 604, display device 605, operation system 606, memory 607, recording device 608, and power supply system 609 are interconnected via a bus 610. Electronic device 601 is, for example, an imaging device capable of capturing still images and moving images.

[0218] The optical system 602 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 603 , forming an image on the light-receiving surface (sensor portion) of the photodetector 603 .

[0219] The photodetector 603 has the same configuration as the photodetector 1 described above. Electrons are accumulated as signal charges in the photodetector 603 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 602. A signal corresponding to the electrons accumulated in the photodetector 603 is then supplied to the DSP 604.

[0220] The DSP 604 performs various signal processing on the signal from the photodetector 603 to generate an image, and temporarily stores the image data in a memory 607. The image data stored in the memory 607 is recorded in a recording device 608 or supplied to a display device 605 to display the image. In addition, an operation system 606 accepts various operations by the user and supplies operation signals to each block of the electronic device 601, and a power supply system 609 supplies the power necessary to drive each block of the electronic device 601.

[0221] In the electronic device 601 configured as above, by applying the above-described photodetector 1 as the photodetector 603, it is possible to suppress deterioration of dark characteristics, and thus to generate a high-quality captured image.

[0222] 23. Example of Use of Image Sensor FIG. 52 is a diagram showing an example of use of the above-described photodetector 1 when it is an image sensor.

[0223] When the above-described photodetector 1 is an image sensor, it can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0224] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0225] 24. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0226] FIG. 53 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0227] Figure 53 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0228] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0229] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0230] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0231] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0232] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0233] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0234] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0235] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0236] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0237] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0238] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissue and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0239] Figure 54 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 53.

[0240] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0241] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0242] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0243] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0244] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0245] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0246] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0247] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0248] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0249] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0250] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0251] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0252] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0253] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0254] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0255] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0256] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 of the camera head 11102 in the above-described configuration. Specifically, the above-described light detection device 1 can be used as the imaging unit 11402. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to obtain clearer images of the surgical site while miniaturizing the camera head 11102.

[0257] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0258] 25. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0259] FIG. 55 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0260] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 55, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0261] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0262] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0263] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0264] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0265] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0266] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0267] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0268] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0269] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 55, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0270] FIG. 56 is a diagram showing an example of the installation position of the imaging unit 12031.

[0271] In FIG. 56, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0272] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0273] 56 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0274] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for detecting a phase difference.

[0275] For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which travels autonomously without relying on driver operation.

[0276] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into categories such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0277] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0278] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the image capture unit 12031 of the above-described configuration. Specifically, the above-described light detection device 1 can be applied as the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to obtain a more easily visible captured image and acquire distance information while still reducing the size of the image capture unit 12031. Furthermore, using the obtained captured image and distance information, it is possible to reduce driver fatigue and increase the safety of the driver and the vehicle.

[0279] In the above example, a photodetector in which the first conductivity type is P-type and the second conductivity type is N-type and electrons are used as signal charges has been described, but the present disclosure can also be applied to a photodetector in which holes are used as signal charges. That is, the first conductivity type can be N-type and the second conductivity type can be P-type, and the aforementioned semiconductor regions can be configured with semiconductor regions of opposite conductivity types.

[0280] Furthermore, the present disclosure is not limited to application to photodetection devices that detect the distribution of incident light amount of visible light and capture it as an image, but is also applicable to photodetection devices that capture the distribution of incident amounts of infrared rays, X-rays, particles, etc. as an image, and in a broad sense, to photodetection devices in general (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure or capacitance and capture it as an image.

[0281] The embodiments of the technology of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the technology of the present disclosure.

[0282] For example, it is possible to adopt a configuration in which some of the pixel structures of the first to sixth embodiments described above are appropriately selected and combined.

[0283] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0284] The technology disclosed herein may employ the following configurations. (1) A photodetector including a photoelectric conversion unit, a pixel transistor, and an element isolation layer provided near the pixel transistor, wherein an end face of the gate electrode of the pixel transistor is in contact with an end face of the element isolation layer or is spaced from the end face of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions. (2) The photodetector described in (1), wherein, with respect to the width in the channel width direction, the width of the gate electrode of the pixel transistor is equal to the width of a semiconductor region below the gate electrode in which a channel of the pixel transistor is formed. (3) The photodetector described in (1) or (2), wherein the gate electrode of the pixel transistor and the element isolation layer are formed so as not to overlap in the vertical direction. (4) The photodetector described in any of (1) to (3), wherein the upper surface of the gate electrode of the pixel transistor and the upper surface of the element isolation layer are formed flush with each other. (5) The photodetector described in any of (1) to (4), wherein the element isolation layer has a sidewall on a side wall above the substrate surface of a semiconductor substrate. (6) The photodetector according to (5), wherein a surface where an end face of the element isolation layer above the substrate surface and the sidewall meet is formed to coincide with an end face of the element isolation layer below the substrate surface. (7) The photodetector according to (5), wherein a surface where an end face of the element isolation layer above the substrate surface and the sidewall meet is formed closer to the center line than an end face of the element isolation layer below the substrate surface. (8) The photodetector according to (5), wherein a protrusion width of the sidewall protruding from an end face of the element isolation layer below the substrate surface is formed to be smaller than a width of the sidewall of the pixel transistor. (9) The photodetector according to (5), wherein the sidewall is formed of a material different from that of an interlayer film covering an upper surface of the element isolation layer. (10) The photodetector according to any of (1) to (9), wherein an upper surface position of the gate electrode of the pixel transistor is above the substrate surface of the semiconductor substrate.(11) The photodetector according to any one of (1) to (10), wherein the lower surface of the gate electrode of the pixel transistor has two different height positions. (12) The photodetector according to (11), wherein the lower surface position of at least a part of the gate electrode of the pixel transistor is below the substrate surface of the semiconductor substrate. (13) The photodetector according to (12), wherein the depth of the two source / drain regions of the pixel transistor is formed to be the same as or shallower than the depth of the semiconductor region below the gate electrode in which a channel is formed. (14) The photodetector according to (11), wherein the lower surface position of at least a part of the gate electrode of the pixel transistor is above the substrate surface of the semiconductor substrate. (15) The photodetector according to (14), wherein the two source / drain regions of the pixel transistor are formed in the same layer as the semiconductor region in which a channel is formed, and at the same or approximately the same depth as the semiconductor region. (16) The photodetector according to any one of (1) to (15), wherein the width in the height direction of the gate electrode of the pixel transistor is formed to be equal to or smaller than the width in the height direction of the element isolation layer. (17) The photodetector according to any one of (1) to (16), wherein, in terms of the width in the channel width direction, the width of the gate electrode of the pixel transistor is formed smaller than the width of a semiconductor region below the gate electrode in which a channel of the pixel transistor is formed. (18) The photodetector according to (17), wherein the semiconductor region in which the channel of the pixel transistor is formed is formed below and to the side of the gate electrode. (19) The photodetector according to any one of (1) to (18), wherein an insulating material different from that of the element isolation layer is buried in a region between the gate electrode of the transfer transistor and the element isolation layer, in the same layer as the gate electrode of the transfer transistor. (20) The photodetector according to any one of (1) to (19), wherein the pixel transistor is any one of an amplification transistor, a reset transistor, or a selection transistor, and the gate electrode of the pixel transistor is buried in the substrate of the semiconductor substrate. (21) The photodetector according to (20), further including a transfer transistor whose gate electrode is buried in the substrate of the semiconductor substrate.(22) The photodetector according to (21), wherein the planar shape of the transfer transistor is trapezoidal, triangular, or circular. (23) The photodetector according to (21), wherein the transfer transistor has two gate electrodes, and the two gate electrodes are arranged so that their surfaces face each other. (24) The photodetector according to any of (1) to (23), wherein the pixel transistor is any of an amplification transistor, a reset transistor, or a selection transistor, wherein the pixel transistor is arranged in each of a plurality of rows in a planar view, and the photoelectric conversion unit and the transfer transistor are arranged between the plurality of rows in which the pixel transistors are arranged. (25) The photodetector according to any of (1) to (24), further including a pixel isolation unit that isolates the photoelectric conversion unit, and wherein the element isolation layer is arranged at an end of the pixel isolation unit. (26) The photodetector according to any one of (1) to (25), wherein the pixel transistor is an amplification transistor, a reset transistor, or a selection transistor, and the element isolation layer is provided in a channel width direction of the pixel transistor. (27) The photodetector according to (26), wherein a sidewall is provided in a channel length direction of the pixel transistor. (28) The photodetector according to (26) or (27), wherein the element isolation layer is formed to a position deeper than a source / drain region of the pixel transistor. (29) A method for manufacturing a photodetector, comprising forming a photoelectric conversion unit, a pixel transistor, and an element isolation layer near the pixel transistor, and forming an end face of a gate electrode of the pixel transistor to be in contact with an end face of the element isolation layer or to be spaced from the end face of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions. (30) An electronic device comprising a photodetector including a photoelectric conversion unit, a pixel transistor, and an element isolation layer provided in the vicinity of the pixel transistor, wherein an end face of a gate electrode of the pixel transistor is in contact with an end face of the element isolation layer or is spaced apart from the end face of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions.

[0285] 1 Photodetector, 2 Pixel, 2A Unit pixel region, 2B Shared pixel region, 3 Pixel array section, 21 Semiconductor substrate, PD Photodiode, TG Transfer transistor, FD Floating diffusion, AMP Amplifying transistor, RST Reset transistor, SEL Select transistor, 31 P-type semiconductor region, 32 N-type semiconductor region, 33 N-type semiconductor region, 35 Gate electrode, 36 Sidewall, 41 Gate electrode, 42 Sidewall, 43 Source / drain region, 44 LDD region, 45 N-well region, 52 Sidewall, 53 Insulating film, 54 Contact interlayer film, 91 Contact wiring, 92 Contact interlayer film, 221 Contact wiring, 223 Contact interlayer film, 225 Contact wiring, 351 Pixel separation section, L1, W1 Width, W2 Semiconductor region width, L2 Protrusion width, L3 width, W3 semiconductor region width, W4 gate width

Claims

1. A photodetection device including a photoelectric conversion unit, a pixel transistor, and an element isolation layer provided near the pixel transistor, wherein an end surface of a gate electrode of the pixel transistor is in contact with an end surface of the element isolation layer, or is arranged away from the end surface of the element isolation layer toward a center line connecting the gate electrode and two source / drain regions.

2. The photodetection device according to claim 1, wherein a width of the gate electrode of the pixel transistor is formed to be equal to a width of a semiconductor region under the gate electrode where a channel of the pixel transistor is formed, in terms of a width in the channel width direction.

3. The photodetection device according to claim 1, wherein the gate electrode of the pixel transistor and the element isolation layer are formed so as not to overlap in the vertical direction.

4. The photodetection device according to claim 1, wherein an upper surface position of the gate electrode of the pixel transistor is formed to be equal to an upper surface position of the element isolation layer.

5. The photodetection device according to claim 1, wherein the element isolation layer has sidewalls on sidewalls above a substrate surface of a semiconductor substrate.

6. The photodetection device according to claim 5, wherein a surface where an end surface of the element isolation layer above the substrate surface and the sidewall are in contact is formed to coincide with an end surface of the element isolation layer below the substrate surface.

7. The photodetection device according to claim 5, wherein a surface where an end surface of the element isolation layer above the substrate surface and the sidewall are in contact is formed closer to the center line than an end surface of the element isolation layer below the substrate surface.

8. The photodetection device according to claim 5, wherein a protruding width of the sidewall protruding from an end surface of the element isolation layer below the substrate surface is formed to be smaller than a width of a sidewall of the pixel transistor.

9. The photodetection device according to claim 5, wherein the sidewall is formed of a material different from an interlayer film covering an upper surface of the element isolation layer.

10. The photodetection device according to claim 1, wherein an upper surface position of the gate electrode of the pixel transistor is above a substrate surface of a semiconductor substrate.

11. The photodetection device according to claim 1, wherein a lower surface of the gate electrode of the pixel transistor has two different height positions.

12. The photodetection device according to claim 11, wherein at least a part of a lower surface position of the gate electrode of the pixel transistor is below a substrate surface of a semiconductor substrate.

13. The depth of the two source-drain regions of the pixel transistor is the same as, or shallower than, the depth of the semiconductor region under the gate electrode where the channel is formed. The photodetection device according to claim 12.

14. The lower surface position of at least a part of the gate electrode of the pixel transistor is above the substrate surface of the semiconductor substrate. The photodetection device according to claim 11.

15. The two source-drain regions of the pixel transistor are formed at the same position as the semiconductor region where the channel is formed and at the same or substantially the same depth as the semiconductor region. The photodetection device according to claim 14.

16. The width of the gate electrode of the pixel transistor in the height direction is formed to be equal to or smaller than the width of the element isolation layer in the height direction. The photodetection device according to claim 1.

17. Regarding the width in the channel width direction, the width of the gate electrode of the pixel transistor is formed to be smaller than the width of the semiconductor region under the gate electrode where the channel of the pixel transistor is formed. The photodetection device according to claim 1.

18. The semiconductor region where the channel of the pixel transistor is formed is formed below and on the side of the gate electrode. The photodetection device according to claim 17.

19. An insulating material different from the element isolation layer is embedded in the region between the gate electrode of the transfer transistor and the element isolation layer in the same layer. The photodetection device according to claim 1.

20. The pixel transistor is any one of an amplification transistor, a reset transistor, or a selection transistor. The gate electrode of the pixel transistor is formed by being embedded in the semiconductor substrate. The photodetection device according to claim 1.

21. Further includes a transfer transistor in which the gate electrode is formed by being embedded in the semiconductor substrate. The photodetection device according to claim 20.

22. The planar shape of the transfer transistor is trapezoidal, triangular, or circular. The photodetection device according to claim 21.

23. The transfer transistor has two gate electrodes, and the two gate electrodes are arranged to have opposing surfaces. The photodetection device according to claim 21.

24. The pixel transistor is any one of an amplification transistor, a reset transistor, or a selection transistor, the pixel transistors are arranged in a plurality of rows in a plan view, and the photoelectric conversion unit and the transfer transistor are arranged between the plurality of rows in which the pixel transistors are arranged. The photodetection device according to claim 1.

25. The photodetection device according to claim 1, further including a pixel isolation part that isolates the photoelectric conversion part, and the element isolation layer is arranged at the tip of the pixel isolation part.

26. The pixel transistor is any one of an amplification transistor, a reset transistor, or a selection transistor, and the element isolation layer is provided in the channel width direction of the pixel transistor. The photodetection device according to claim 1.

27. A sidewall is provided in the channel length direction of the pixel transistor. The photodetection device according to claim 26.

28. The element isolation layer is formed to a position deeper than the source-drain region of the pixel transistor. The photodetection device according to claim 26.

29. A method of manufacturing a photodetection device, comprising forming a photoelectric conversion unit, a pixel transistor, and an element isolation layer in the vicinity of the pixel transistor, and forming the end face of the gate electrode of the pixel transistor to be in contact with the end face of the element isolation layer or to be separated from the end face of the element isolation layer toward the center line connecting the gate electrode and the two source-drain regions.

30. An electronic device including a photodetection device, the photodetection device including a photoelectric conversion unit, a pixel transistor, and an element isolation layer provided in the vicinity of the pixel transistor, wherein the end face of the gate electrode of the pixel transistor is in contact with the end face of the element isolation layer or is separated from the end face of the element isolation layer toward the center line connecting the gate electrode and the two source-drain regions.

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