Battery management system and battery management method

Abstract

A battery management system and a battery management method are disclosed. The battery system comprises: a battery monitoring IC (BMIC) for measuring a battery state; a processor for controlling all operations of a battery management system; a transceiver for recognizing the measured state of the battery and transmitting same to the processor; and a power source management circuit for providing a power source to the processor, wherein the processor includes a first terminal (VDDS_PowerControl) that outputs a first signal for controlling a first transistor, and uses the first signal to control the first transistor, and thus can provide a VDDS signal for determining a low power mode operation.

Description

Battery management system and battery management method

[0001] Cross-citation with related application(s)

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0002631, filed January 8, 2024, the entire contents of which are incorporated herein by reference.

[0003] The present disclosure relates to a battery management system and a battery management method.

[0004] Unlike internal combustion engine vehicles, electric vehicles are extremely difficult to extinguish if they catch fire. Furthermore, unlike smoke-powered vehicles, electric vehicles tend to burn out quickly, potentially exacerbating the damage if rescue efforts are delayed. This situation arises from a phenomenon called "thermal runaway," where the battery temperature soars to over 1,000 degrees Celsius.

[0005] Research and development are underway to detect battery thermal runaway in advance. Methods that collect battery data, such as temperature and voltage, and analyze changes in this data are widely used to predict battery thermal runaway in advance.

[0006] However, when charging a battery with an external power source, the Battery Management System (BMS) is in sleep or shutdown mode. Therefore, the BMS cannot collect battery data or predict battery thermal runaway in advance. Consequently, the phenomenon of battery thermal runaway is not detected in advance, leading to the majority of battery-related fires occurring during charging.

[0007] The task to be solved is to provide a battery management system and a battery management method that can accurately diagnose thermal runaway of a battery even when the battery is charged with power from an external charger or when the battery-mounted upper system (e.g., a car, an energy storage system, etc.) is not running and the battery management system (BMS) is in sleep mode.

[0008] According to one embodiment, a battery system includes a BMIC (Battery Monitoring IC) for measuring a state of a battery; a processor for controlling the overall operation of the battery management system; a transceiver for recognizing the measured state of the battery and transmitting it to the processor; and a power management circuit for providing power to the processor, wherein the processor includes a first terminal for outputting a first signal for controlling a first transistor, and can provide a power signal for determining operation in a low-power mode by controlling the first transistor using the first signal.

[0009] In some embodiments, the processor further includes a second terminal outputting a second signal for controlling a second transistor, and controlling the second transistor using the second signal to change a resistor value connected to a third terminal for indicating whether to use a low power mode.

[0010] In some embodiments, the signal of the third terminal can have its value detected when the voltage level of the power signal transitions.

[0011] In some embodiments, when an unintended fault occurs, a signal at the fourth terminal of the transceiver may transition from a second voltage level to a first voltage level, and the processor, the transceiver, and the BMIC may wake up.

[0012] In some embodiments, after the processor, the transceiver, and the BMIC wake up, the second signal output from the second terminal may transition from an OFF state to an ON state, and the resistance value connected to the third terminal may change to a state in which 0 kΩ is connected.

[0013] In some embodiments, while the resistance value connected to the third terminal is in a state where 0 kΩ is connected, the first signal output from the first terminal may be transitioned from an OFF state to an ON state, and no voltage may be applied to the power terminal.

[0014] In some embodiments, when the first signal output from the first terminal transitions from an ON state to an OFF state, voltage is applied to the power terminal again, and voltage is applied to the power terminal again, the value of the third terminal is captured, and the battery management system can be set not to use a low power mode based on the captured value.

[0015] In some embodiments, the second signal output from the second terminal may return from an ON state to an OFF state, and the resistance value connected to the third terminal may be changed to a state where 20 kΩ is connected.

[0016] In some embodiments, when a low power mode entry command is generated, a signal of a fifth terminal of the transceiver, which provides an output indicating whether the processor is in a normal operating state or a low power mode entry state, transitions from a first voltage level to a second voltage level, and the processor, the transceiver, and the BMIC can enter the low power mode again.

[0017] According to one embodiment, a battery method is provided for a battery management system including a BMIC (Battery Monitoring IC) for measuring a state of a battery; a processor for controlling the overall operation of the battery management system and including a first terminal for outputting a first signal for controlling a first transistor and a second terminal for outputting a second signal for controlling a second transistor; a transceiver for recognizing the measured state of the battery and transmitting it to the processor; and a power management circuit for providing power to the processor, the battery management method may include a step of providing a power signal for determining operation in a low power mode by controlling the first transistor using the first signal by the processor; and a step of changing a resistance value connected to a third terminal by controlling the second transistor using the second signal.

[0018] In some embodiments, the signal of the third terminal can have its value detected when the voltage level of the power signal transitions.

[0019] In some embodiments, the method may further include the step of transitioning a signal of a fourth terminal of the transceiver from a second voltage level to a first voltage level when an unintended fault occurs; and the step of waking up the processor, the transceiver, and the BMIC.

[0020] In some embodiments, the method may further include the step of transitioning the second signal output from the second terminal from an OFF state to an ON state after the processor, the transceiver, and the BMIC wake up; and the step of changing the resistance value connected to the third terminal to a state in which 0 kΩ is connected.

[0021] In some embodiments, the method may further include the step of transitioning the first signal output from the first terminal from an OFF state to an ON state while the resistance value connected to the third terminal is in a state where 0 kΩ is connected; and the step of changing the power terminal so that no voltage is applied.

[0022] In some embodiments, the method may further include the steps of transitioning the first signal output from the first terminal from an ON state to an OFF state; reapplying voltage to the power terminal; capturing a value of the third terminal at the time when voltage is reapplied to the power terminal; and setting the battery management system to not use a low power mode based on the captured value.

[0023] In some embodiments, the method may further include the step of returning the second signal output from the second terminal from an ON state to an OFF state; and the step of changing the resistance value connected to the third terminal to a state where 20 kΩ is connected.

[0024] In some embodiments, the method may further include the step of transitioning a signal of a fifth terminal of the transceiver, which provides an output indicating whether the processor is in a normal operating state or a low power mode entry state, from a first voltage level to a second voltage level when a low power mode entry command is generated; and the step of causing the processor, the transceiver, and the BMIC to enter the low power mode again.

[0025] According to embodiments, even when the BMS is in sleep mode, thermal runaway of the battery can be accurately diagnosed, thereby reducing casualties and property damage. Specifically, the present invention addresses the issue of not being able to return to sleep mode after waking from low-power mode due to unintended faults, such as loss of communication or connector damage, rather than changes in cell voltage or temperature. Furthermore, by addressing this issue, it is possible to prevent the vehicle's lead-acid battery from discharging due to failure to enter sleep mode.

[0026] FIG. 1 is a circuit diagram illustrating a battery management system according to one embodiment.

[0027] FIG. 2 is a timing diagram for explaining the operation of a battery management system according to one embodiment.

[0028] FIG. 3 is a timing diagram for explaining the operation of a battery management system according to one embodiment.

[0029] Figure 4 is a timing diagram for explaining a case where entry into low power mode is not possible due to an unintended fault.

[0030] FIG. 5 is a timing diagram for explaining the operation of a battery management system according to one embodiment.

[0031] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components will be given identical or similar reference numerals, and redundant descriptions thereof will be omitted. The suffixes "module" and / or "part" used for components in the following description are given or used interchangeably only for the convenience of writing the specification, and do not in themselves have distinct meanings or roles. In addition, when describing the embodiments disclosed in this specification, if it is determined that a specific description of a related known technology may obscure the gist of the embodiments disclosed in this specification, a detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the present invention.

[0032] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0033] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0034] In this application, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0035] FIG. 1 is a circuit diagram illustrating a battery management system according to one embodiment.

[0036] Referring to FIG. 1, a battery management system (BMS) (1) according to one embodiment may include a processor (10), a transceiver (11), an isolator (12), a BMIC (Battery Monitoring IC) (13a, 13b), and a power management circuit (14).

[0037] The processor (10) can control the overall operation of the battery management system (1) and perform functions necessary for battery management. For example, the processor (10) can continuously monitor the voltage, current, temperature, etc. of battery cells, perform cell balancing to adjust the voltage difference between battery cells, or detect situations that may damage the battery, such as overcharge, overdischarge, and overheating, and take protective measures. In addition, the processor (10) can predict the condition, lifespan, and charging time of the battery, and evaluate and diagnose the condition, based on data monitored for the battery, and can also process communication with other external devices. In some embodiments, the processor (10) can be implemented as a microcontroller unit (MCU).

[0038] A battery can have a discharge state, a charge state, or an idle state. The discharge state is a state in which the battery is discharged by supplying power to an external device (e.g., a load), the charge state is a state in which the battery is charged by receiving power from an external device (e.g., a charger), and the idle state is a state in which the battery and the external device are electrically connected but no power is transmitted. In the discharged state of the battery, the battery management system (1) can operate in an operating mode in which it checks the state of the battery and performs a logic set to operate it safely, and in the charged state and idle state of the battery, the battery management system (1) can operate in a sleep mode in which it does not perform a logic. However, since the state of the battery cannot be monitored while the battery management system (1) is in the sleep mode, it is difficult to prepare in advance for a battery fire. To improve these problems, in the present embodiment, the battery management system (1) can operate in a low power mode that monitors the state of the battery by periodically waking up to prevent thermal runaway, heat propagation, etc. in a charging state and an idle state.

[0039] The battery management system (1) operates in a low-power mode in a charging state and an idle state, and periodically wakes up to monitor parameters such as cell OT (Over Temperature), UV (Under Voltage), and Delta T (Temperature Differential) for the battery. Here, cell OT is a parameter indicating that a battery cell is overheated and its temperature exceeds a safe operating range, UV is a parameter indicating an over-discharge state in which the voltage of the battery cell falls below a normal operating range, and Delta T may be a parameter indicating a temperature difference between battery cells.

[0040] The battery management system (1) can enter sleep mode again when it is determined that there is no abnormality in the corresponding parameter value, and can repeat the process of waking up again and monitoring the parameter at the next cycle. Specifically, in a situation where there is no abnormality in the corresponding parameter value, the transceiver (11) and BMIC (13a, 13b) repeat waking up and sleeping periodically, and the processor (10) maintains the sleep state. If it is determined that there is an abnormality in the corresponding parameter value that may predict a fire risk of the battery, the processor (10), the transceiver (11), and the BMIC (13a, 13b) are all woken up, and the processor (10) can perform a safety reaction, such as notifying the ECU (Electronic Control Unit) of the abnormal state of the battery through CAN (Controller Area Network) communication, or opening a relay to disconnect the electrical connection with an external device.

[0041] However, in addition to the case where an abnormal state of the battery is detected, there may be a case where the processor (10), the transceiver (11), and the BMIC (13a, 13b) are all woken up due to other factors. For example, there may be a case where the processor (10), the transceiver (11), and the BMIC (13a, 13b) are all woken up due to loss of communication, connector damage, etc. In this specification, a factor that interrupts the sleep mode according to the battery state in order to prepare for a battery fire is expressed as an "intended fault", and a factor that interrupts the sleep mode due to a cause or symptom of a battery fire is expressed as an "unintended fault". If an unintended fault occurs, the battery management system (1) must enter the low power mode again, and if this fails, there is a risk of wasting the battery or, in the worst case, discharging the vehicle's lead-acid battery.

[0042] The processor (10) can control a case where the battery management system (1) that has been woken up by the unintended fault described above cannot enter a low power mode. This will be described in detail below.

[0043] The transceiver (11) can recognize the status of the BMIC (13a, 13b) and perform an operation to wake up the processor (10) or the power management circuit (14) based on the status. For example, the transceiver (12) can receive the accumulated battery status from the BMIC (13a) to the BMIC (13b). When an alarm indicating a problem with the battery status is received, the transceiver (11) can output an interrupt signal (INTR) to wake up the power management circuit (14). Then, the woken up power management circuit (14) can wake up the processor (10). In Fig. 1, the transceiver (11) outputs an interrupt signal (INTR) to the power management circuit (14), but unlike what is shown, the transceiver (11) can also directly wake up the processor (10) by outputting an interrupt signal (INTR) to the processor (10).

[0044] The separation circuit (12) can perform separation of a circuit area including a processor (10), a transceiver (11), and a power management circuit (14) in the battery management system (1), and a circuit area including a BMIC (13a, 13b). Here, the processor (10), the transceiver (11), and the power management circuit (14) may belong to a master BMS (Master BMS) or a battery pack control module (BPCM) that diagnoses the status of the battery voltage, current, temperature, etc. and communicates with the vehicle (15). The separation circuit (12) and the BMIC (13a, 13b) may belong to a slave BMS or a cell supervisory circuit. In some embodiments, the separation circuit (12) may be implemented using a transformer or a capacitor.

[0045] Each of the BMICs (13a, 13b) can measure multiple battery cell voltages for multiple electrically connected battery cells, perform cell balancing for the multiple battery cells, and measure temperature using GPIO (General Purpose Input / Output). In particular, the BMICs (13a, 13b) can independently perform low power mode operation. Specifically, the BMICs (13a, 13b) can wake up at preset intervals even in sleep mode to detect changes in cell voltage, cell temperature, and cell temperature increase rate, and can generate an alarm when the detected values ​​exceed a preset threshold. In some embodiments, BMICs (13a, 13b) are connected in a daisy chain, so that an alarm generated in BMIC (13a) can be transmitted to BMIC (13b), and can be accumulated with an alarm generated in BMIC (13b) and transmitted to the processor (10) through the transceiver (11). The processor (10) can finally detect an abnormal state of the battery based on the alarm.

[0046] In some embodiments, the BMICs (13a, 13b) can repeatedly wake up from sleep mode to detect battery voltage fluctuations. If the battery voltage fluctuations exceed a predetermined threshold, the BMICs (13a, 13b) can perform cell balancing. Cell balancing can be performed on a single cell or a specific cell, for example, using a DC (Direct Current) method or a PWM (Pulse Width Modulation) method. When cell balancing is completed after a certain period of time, cell balancing progress information from the lowest BMIC (13a) to the highest BMIC (13b) can be transmitted to the transceiver (11). If the transceiver (11) receives an alarm indicating a problem with the battery status, it can wake up the power management circuit (14) or the processor (10) through a line to which an interrupt signal (INTR) is transmitted. The processor (10) can ultimately detect an abnormal condition of the battery and notify the ECU of the vehicle (15) of the battery abnormal condition via CAN within a predetermined time or perform a safety response. If there is no abnormality in the battery, the processor can return to sleep mode.

[0047] In low power mode, the BMIC (13a, 13b) wakes up according to a preset measurement cycle (e.g., 1 second to 32 seconds) to monitor parameters such as cell OT, UV, and Delta T, and if an abnormality is determined, the processor (10) can be woken up to take safety measures before an incident such as thermal runaway or heat propagation occurs. The measurement cycle of the BMIC (13a, 13b) can be set through register settings by software, and the measurement cycle of the transceiver (11) can be set using an RTO (Resistance to Overload) resistor without using a register. In the present embodiment, the measurement cycle of the BMIC (13a, 13b) can be set in the range of 1 second to 32 seconds, and the measurement cycle of the transceiver (11) can be set to 48 seconds using an 80.6 kΩ resistor at the RTO terminal.

[0048] The transceiver (11) can be supplied with power through the VP terminal and the VDD terminal. The power provided to the VP terminal is a constant power (PWR_12V) for operation even in a low power mode, and the power provided to the VDD terminal can be a power (VAUX_5V) for communication. Meanwhile, the transceiver (11) can include an XCVRMD terminal. If the low power mode is to be used, a 20 kΩ resistor can be connected to the XCVRMD terminal, and if the low power mode is not to be used, 0 kΩ can be connected to the XCVRMD terminal. Meanwhile, the transceiver (11) can include an MSTR terminal. The MSTR terminal can be connected to a GPIO terminal of the processor (10). An output from the GPIO terminal of the processor (10) can indicate whether the processor (10) is in a normal operating state or has entered a low power mode.

[0049] The processor (10) may include a VDDS_PowerControl terminal. The VDDS_PowerControl terminal outputs a signal for controlling a transistor (T1), and by controlling the transistor (T1), power (VDDS) for determining operation in a low power mode can be selectively provided. One end of the transistor (T1) is connected to ground, and the other end of the transistor (T1) can be involved in the VDDS signal level. When the transistor (T1) is turned on, the voltage level of the VDDS signal can transition to the ground level. When the voltage level of the VDDS signal transitions, a signal of the XCVRMD of the transceiver (11) can be detected. Meanwhile, the processor (10) may include an XCVRMD_Control terminal. The XCVRMD_Control terminal outputs a signal that controls the transistor (T2), and by controlling the transistor (T2), the XCVRMD terminal can be connected to a 20 kΩ resistor or a 0 kΩ resistor.

[0050] Below, based on the circuit configuration of the battery management system as described above, a detailed method for controlling a case in which entry into a low power mode due to an unintended fault is not possible is described.

[0051] FIG. 2 is a timing diagram for explaining the operation of a battery management system according to one embodiment.

[0052] Referring to Fig. 2, the operation of the battery management system (1) when a low power mode fault does not occur is illustrated in a timing diagram.

[0053] In the first section (I), 12 V can be supplied as a constant power source to the VP terminal of the processor (10), and 5 V and 5 V can be supplied to the VDD terminal and the VDDS terminal, respectively. The XCVRMD terminal of the transceiver (11) is set to use a low power mode with a 20 kΩ resistor connected, and the RTO terminal of the transceiver (11) is set to read data in 48-second units with an 80.6 kΩ resistor connected.

[0054] The MSTR terminal of the transceiver (11) may initially have a first voltage level (e.g., a voltage level of 5 V), and the INTR terminal may initially have a second voltage level (e.g., a voltage level of 0 V). The transceiver (11) indicated by "IC_6822", the BMIC (13a, 13b) indicated by "BMIC_6830", and the processor (10) indicated by "MCU_5777C" may perform normal operation. Here, normal operation may mean operating in an operating mode that performs logic set to check the status of the battery and operate it safely.

[0055] E21 indicates the point in time when a low-power mode entry command is issued from the master BMS. At point E21, the signal at the MSTR terminal of the transceiver (11) can transition from the first voltage level to the second voltage level. Simultaneously, the signal at the INTR terminal of the transceiver (11) can transition from the second voltage level to the first voltage level.

[0056] E22 indicates the point in time when the master BMS has normally confirmed the low-power mode-related communication message received from the slave BMS. Specifically, after the low-power mode entry command is transmitted from the processor (10) to the transceiver (11), the slave BMS including the BMIC (13a, 13b) can transmit a normal confirmation message indicating that the low-power mode-related communication message has been normally confirmed to the master BMS. At point E22, the signal of the INTR terminal of the transceiver (11) can transition from a first voltage level to a second voltage level. Subsequently, the battery management system (1) can enter the low-power mode.

[0057] In the second section (II), no voltage may be applied to the VDD terminal and the VDDS terminal of the processor (10). The signal of the MSTR terminal and the signal of the INTR terminal of the transceiver (11) may maintain the second voltage level. Meanwhile, the transceiver (11) indicated as "IC_6822" may wake up at a 32-second cycle while operating in a low-power mode, and the BMIC (13a, 13b) indicated as "BMIC_6830" may wake up at a 1-second cycle while operating in a low-power mode. The processor (10) indicated as "MCU_5777C" may maintain a sleep mode state.

[0058] In the third section (III), if no abnormality is determined to be predictable that may result in a fire risk of the battery, i.e., no fault occurs in the low-power mode, the VDD terminal and the VDDS terminal of the processor (10) are maintained without voltage being applied, and the signal of the MSTR terminal and the signal of the INTR terminal of the transceiver (11) can maintain the second voltage level. In addition, the transceiver (11) can continue to wake up at a 32-second cycle while operating in the low-power mode, the BMIC (13a, 13b) can continue to wake up at a 1-second cycle while operating in the low-power mode, and the processor (10) can continue to maintain the sleep mode state.

[0059] In the fourth section (IV), E23 indicates a point in time when a wake-up occurs due to a factor or cause other than a low-power mode fault. At E23, a voltage of 5 V may be applied again to the VDD terminal and the VDDS terminal of the processor (10). The signal of the MSTR terminal of the transceiver (11) transitions from the second voltage level to the first voltage level, and since a low-power mode fault has not occurred, the signal of the INTR terminal of the transceiver (11) may maintain the second voltage level as it is. Meanwhile, the transceiver (11) indicated as "IC_6822", the BMICs (13a, 13b) indicated as "BMIC_6830", and the processor (10) indicated as "MCU_5777C" may perform normal operations again.

[0060] FIG. 3 is a timing diagram for explaining the operation of a battery management system according to one embodiment.

[0061] Referring to FIG. 3, the operation of the battery management system (1) when a low power mode fault, i.e., an intended fault, occurs is illustrated in a timing diagram.

[0062] In the first section (I), E31 may indicate the point in time when a low-power mode entry command is generated from the master BMS, and E32 may indicate the point in time when the master BMS normally confirms the low-power mode-related communication message received from the slave BMS. That is, E31 and E32 may correspond to E21 and E22 of Fig. 2. The operation of the battery management system (1) in the first section (I) may be the same as the operation of the battery management system (1) in the first section (I) of Fig. 2. The second section (II) may also be the same as the second section (II) of Fig. 2, and therefore, any duplicate description will be omitted.

[0063] In the third section (III), E33 indicates the time at which a wake-up due to a low-power mode fault occurs. A low-power mode fault may indicate a case in which it is determined that action is necessary before a battery fire occurs due to an abnormality in parameter values ​​such as cell OT, UV, and Delta T. Since a low-power mode fault occurs at E33, the signal at the INTR terminal of the transceiver (11) may transition from a second voltage level to a first voltage level. The processor (10), the transceiver (11), and the BMIC (13a, 13b) may wake up due to the interrupt signal generated in this way.

[0064] That is, the transceiver (11) indicated as "IC_6822", the BMIC (13a, 13b) indicated as "BMIC_6830", and the processor (10) indicated as "MCU_5777C" can perform normal operation again, and a voltage of 5 V is again applied to the VDD terminal and the VDDS terminal of the processor (10), and the signal of the MSTR terminal of the transceiver (11) can be transitioned from the second voltage level to the first voltage level. And the signal of the INTR terminal of the transceiver (11) can be transitioned from the first voltage level to the second voltage level again.

[0065] Figure 4 is a timing diagram for explaining a case where entry into low power mode is not possible due to an unintended fault.

[0066] Referring to FIG. 4, the operation of the battery management system (1) in the event of a fault other than a low power mode fault, i.e., an unintended fault, is illustrated in a timing diagram.

[0067] In the first section (I), E41 may indicate the point in time when a low-power mode entry command is generated from the master BMS, and E42 may indicate the point in time when the master BMS normally confirms the low-power mode-related communication message received from the slave BMS. That is, E41 and E42 may correspond to E31 and E32 of FIG. 3. The operation of the battery management system (1) in the first section (I) may be the same as the operation of the battery management system (1) in the first section (I) of FIG. 3. The second section (II) may also be the same as the second section (II) of FIG. 3, and therefore, any duplicate description will be omitted.

[0068] In the third section (III), E43 indicates the point in time at which a wake-up occurs due to an unintended fault. An unintended fault may indicate an abnormality in parameter values, such as communication failure or connector damage. Since an unintended fault occurs at E43, the signal at the INTR terminal of the transceiver (11) may transition from a second voltage level to a first voltage level. The processor (10), the transceiver (11), and the BMIC (13a, 13b) may wake up due to the interrupt signal generated in this manner.

[0069] That is, the transceiver (11) indicated as "IC_6822", the BMIC (13a, 13b) indicated as "BMIC_6830", and the processor (10) indicated as "MCU_5777C" can perform normal operation again, and a voltage of 5 V is again applied to the VDD terminal and the VDDS terminal of the processor (10), and the signal of the MSTR terminal of the transceiver (11) can be transitioned from the second voltage level to the first voltage level. And the signal of the INTR terminal of the transceiver (11) can be transitioned from the first voltage level to the second voltage level again.

[0070] E44 indicates the point in time when a low-power mode entry command is generated from the master BMS. At point E44, the signal at the MSTR terminal of the transceiver (11) may transition from the first voltage level to the second voltage level. Since this is not a low-power mode fault, a low-power mode entry command from the master BMS is generated, and accordingly, the battery management system (1) must enter the low-power mode again. However, in a situation where the unintended fault is not resolved, the signal at the INTR terminal of the transceiver (11) may transition from the second voltage level to the first voltage level again.

[0071] Accordingly, in the fourth section (IV), as indicated by E45, the transceiver (11) indicated by "IC_6822", the BMIC (13a, 13b) indicated by "BMIC_6830", and the processor (10) indicated by "MCU_5777C" may fail to enter the low power mode. Even if a low power mode entry command is issued again from the master BMS in E46, as indicated by E47 in the fifth section (V), the transceiver (11) indicated by "IC_6822", the BMIC (13a, 13b) indicated by "BMIC_6830", and the processor (10) indicated by "MCU_5777C" may still fail to enter the low power mode. A method for improving this problem will be described below with reference to FIG. 5.

[0072] FIG. 5 is a timing diagram for explaining the operation of a battery management system according to one embodiment.

[0073] Referring to FIG. 5, the operation of the battery management system (1) in the event of a fault other than a low power mode fault, i.e., an unintended fault, is illustrated in a timing diagram.

[0074] A difference from the timing diagram of FIG. 4 is that a VDDS_PowerControl signal and an XCVRMD_Control signal are additionally illustrated. Referring to FIG. 1 together, the VDDS_PowerControl terminal is a terminal of the processor (10) that outputs a signal for controlling a transistor (T1), and the XCVRMD_Control terminal is a terminal of the processor (10) that outputs a signal for controlling a transistor (T2). By controlling the transistor (T1) through the VDDS_PowerControl signal, the power (VDDS) for determining the operation of the low power mode can be selectively provided, and by controlling the transistor (T2) through the XCVRMD_Control signal, the XCVRMD terminal can be made to be connected to a 20 kΩ resistor or to be connected to a 0 kΩ resistor.

[0075] In the first section (I) and the second section (II), except that both the VDDS_PowerControl signal and the XCVRMD_Control signal are set to the OFF state, the remaining signals can operate in the same manner as in the first section (I) and the second section (II) of Fig. 4. Therefore, any duplicate description will be omitted.

[0076] In the third section (III), E51 indicates the point in time when a wake-up occurs due to an unintended fault. An unintended fault may indicate an abnormality in parameter values, such as communication failure or connector damage. Since an unintended fault occurs at E51, the signal at the INTR terminal of the transceiver (11) may transition from a second voltage level to a first voltage level. The processor (10), the transceiver (11), and the BMIC (13a, 13b) may wake up due to the interrupt signal generated in this manner.

[0077] Next, E52 indicates the point at which the low power mode function starts to turn OFF to resolve abnormal low power mode behavior. Specifically, at E52, the XCVRMD_Control signal can transition from OFF to ON. Accordingly, the XCVRMD terminal can change to a state where 0 kΩ is connected.

[0078] Next, in the fourth section (IV), while the XCVRMD terminal indicates that the low power mode is in the OFF state, the VDDS_PowerControl signal may transition from the OFF state to the ON state. Accordingly, no voltage may be applied to the VDDS terminal. Next, voltage may be applied to the VDDS terminal again as the VDDS_PowerControl signal transitions from the ON state to the OFF state. At the point when voltage is applied to the VDDS signal, the value of the XCVRMD terminal may be captured, and the battery management system (1) may be set not to use the low power mode based on the captured value. Thereafter, the XCVRMD_Control signal may return from the ON state to the OFF state again, and accordingly, the XCVRMD terminal may be changed to a state where 20 kΩ is connected.

[0079] Now, in the fifth section, a low power mode entry command is generated from the master BMS, and accordingly, the signal of the MSTR terminal of the transceiver (11) can transition from the first voltage level to the second voltage level. Then, the transceiver (11) indicated by "IC_6822", the BMIC (13a, 13b) indicated by "BMIC_6830", and the processor (10) indicated by "MCU_5777C" can enter the low power mode again.

[0080] According to embodiments, even when the BMS is in sleep mode, thermal runaway of the battery can be accurately diagnosed, thereby reducing casualties and property damage. Specifically, the system can address the issue of not being able to return to sleep mode after waking from low-power mode due to unintended faults, such as communication interruptions or connector damage, rather than changes in cell voltage or temperature. Furthermore, by addressing this issue, it is possible to prevent the vehicle's lead-acid battery from discharging due to failure to enter sleep mode.

[0081] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by a person of ordinary skill in the art to which the present invention pertains also fall within the scope of the present invention.

Claims

1. As a battery management system, BMIC (Battery Monitoring IC) that measures the status of the battery; A processor controlling the overall operation of the battery management system; A transceiver that recognizes the state of the measured battery and transmits it to the processor; and A power management circuit for providing power to the processor, The above processor, A first terminal for outputting a first signal for controlling a first transistor is included, and a power signal for determining operation in a low power mode is provided by controlling the first transistor using the first signal. Battery management system.

2. In paragraph 1, The above processor, A battery management system further comprising a second terminal outputting a second signal for controlling a second transistor, and changing a resistance value connected to a third terminal for indicating whether to use a low power mode by controlling the second transistor using the second signal.

3. In paragraph 2, A battery management system, wherein the signal of the third terminal is detected when the voltage level of the power signal transitions.

4. In paragraph 2, When an unintended fault occurs, the signal of the fourth terminal of the transceiver transitions from the second voltage level to the first voltage level, A battery management system wherein the processor, the transceiver and the BMIC are woken up.

5. In paragraph 4, After the above processor, the above transceiver and the above BMIC wake up, the second signal output from the second terminal transitions from an OFF state to an ON state, A battery management system, wherein the resistance value connected to the third terminal is changed to a state where 0 kΩ is connected.

6. In paragraph 5, While the resistance value connected to the third terminal is in a state where 0 kΩ is connected, the first signal output from the first terminal transitions from the OFF state to the ON state, A battery management system that changes the voltage to no longer be applied to the power terminals.

7. In paragraph 6, The first signal output from the first terminal transitions from the ON state to the OFF state, Voltage is again applied to the above power terminals, At the point when voltage is applied again to the above power terminal, the value of the third terminal is captured, A battery management system, wherein the battery management system is set to not use a low power mode based on the captured value.

8. In paragraph 7, The second signal output from the second terminal returns from the ON state to the OFF state, A battery management system, wherein the resistance value connected to the third terminal is changed to a state where 20 kΩ is connected.

9. In paragraph 8, When a low power mode entry command occurs, a signal of the fifth terminal of the transceiver, which provides an output indicating whether the processor is in a normal operating state or a low power mode entry state, transitions from a first voltage level to a second voltage level, A battery management system wherein the processor, the transceiver and the BMIC enter a low power mode again.

10. BMIC (Battery Monitoring IC) that measures the battery status; A processor controlling the overall operation of the battery management system, comprising a first terminal outputting a first signal controlling a first transistor and a second terminal outputting a second signal controlling a second transistor; A transceiver that recognizes the state of the measured battery and transmits it to the processor; and A battery management method for a battery management system including a power management circuit providing power to the above processor, A step of providing a power signal for determining operation in a low power mode by controlling the first transistor using the first signal by the processor; and A step of changing the resistance value connected to the third terminal to indicate whether to use the low power mode by controlling the second transistor using the second signal. How to care for your battery.

11. In paragraph 10, A battery management method, wherein the signal of the third terminal is detected when the voltage level of the power signal transitions.

12. In paragraph 10, When an unintended fault occurs, a step of transitioning a signal of the fourth terminal of the transceiver from a second voltage level to a first voltage level; and A battery management method further comprising the step of waking up the processor, the transceiver and the BMIC.

13. In paragraph 12, A step of transitioning the second signal output from the second terminal from an OFF state to an ON state after the processor, the transceiver and the BMIC wake up; and A battery management method further comprising the step of changing the resistance value connected to the third terminal to a state where 0 kΩ is connected.

14. In paragraph 13, A step of transitioning the first signal output from the first terminal from an OFF state to an ON state while the resistance value connected to the third terminal is in a state where 0 kΩ is connected; and A battery management method further comprising the step of changing the power terminal so that no voltage is applied.

15. In paragraph 14, A step of transitioning the first signal output from the first terminal from an ON state to an OFF state; A step of re-applying voltage to the above power terminal; A step of capturing the value of the third terminal at the point when voltage is applied again to the power terminal; and A battery management method further comprising a step of disabling the low power mode of the battery management system by the captured value.

16. In paragraph 15, A step of returning the second signal output from the second terminal from the ON state to the OFF state again; and A battery management method further comprising the step of changing the resistance value connected to the third terminal to a state where 20 kΩ is connected.

17. In paragraph 16, When a low power mode entry command occurs, a step of transitioning a signal of a fifth terminal of the transceiver, which provides an output indicating whether the processor is in a normal operating state or a low power mode entry state, from a first voltage level to a second voltage level; and A battery management method further comprising the step of causing the processor, the transceiver and the BMIC to enter a low power mode again.

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