Multi-level reverse current blocking systems and methods

Abstract

Circuits and methods are provided that more effectively and efficiently implement multi-level converter circuits. In some embodiments an integrated circuit comprises a switching network that when connected to one or more capacitors causes said switching network to form a capacitor arrangement dependent on a state of the switching network. A controller may be configured to control the state of the switching network to cycle between a set of states maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage. The controller may be further configured to maintain a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current flow to a source of the first voltage may occur.

Description

Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2 MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS Gregory Szczeszynski CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of and priority to in their entirety the following United States Provisional Patent Applications filed on January 12, 2024, which are all incorporated by reference in their entirety:

[0002] Application No.63 / 620,507 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0003] Application No.63 / 620,623 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0004] Application No.63 / 620,613 entitled “INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTER;”

[0005] Application No.63 / 620,465 entitled “STARTUP INTERLOCK FOR POWER CONVERTER CIRCUITS;”

[0006] Application No.63 / 620,331 entitled “FULLY DIFFERENTIAL LEVEL SHIFT IN A NOISY ENVIRONMENT;”

[0007] Application No.63 / 620,450 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0008] Application No.63 / 620,469 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0009] Application No.63 / 620,678 entitled “RECONFIGURABLE MULTI-LEVEL POWER CONVERTER TO CHARGE PUMP MODE AND FRACTIONAL CHARGE PUMP MODE;”

[0010] Application No.63 / 620,417 entitled “INPUT CURRENT SLEW FOR A MULTI- LEVEL CONVERTER;”Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0011] Application No.63 / 620,726 entitled “ADJUSTING OVERVOLTAGE PROTECTION BASED ON MODE OF OPERATION SYSTEMS AND METHODS;”

[0012] Application No.63 / 620,737 entitled “HYBRID PEAK AVERAGE CURRENT MODE CONTROL;”

[0013] Application No.63 / 620,741 entitled “CURRENT LIMITED VOLTAGE MODE CONTROL OF MULTIPLE INPUTS;”

[0014] Application No.63 / 620,527 entitled “MULTI-FUNCTION COMP PIN SYSTEMS AND METHODS;”

[0015] Application No.63 / 620,488 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0016] Application No.63 / 620,553 entitled “MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS;”

[0017] Application No.63 / 620,638 entitled “GENERAL STARTUP FOR MULTI- LEVEL POWER CONVERTER CIRCUITS;”

[0018] Application No.63 / 620,733 entitled “PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER;”

[0019] Application No.63 / 620,738 entitled “PREDICTIVE CONTROL LOOP PRE- CHARGING DURING A MULTI-LEVEL ZONE CHANGE;”

[0020] Application No.63 / 620,764 entitled “DETECTOR CIRCUIT FOR DETECTING ONE OF MULTI-INPUT CONTROLLING SIGNALS THAT CONTROLS A CONTROL LOOP CIRCUIT;”

[0021] Application No.63 / 620,607 entitled “STARTUP VOLTAGE SELECTION FOR MULTI-LEVEL POWER CONVERTER CIRCUITS;”

[0022] Application No.63 / 620,575 entitled “MULTI-LEVEL CAPACITOR FAULT DETECTION SYSTEMS AND METHODS;”

[0023] Application No.63 / 620,582 entitled “PARELLEL OPERATION OF MULTI- LEVEL POWER CONVERTERS;” andDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0024] Application No.63 / 620,763 entitled “AVERAGE AND PEAK CURRENT SENSE SYSTEMS AND METHODS.” BACKGROUND

[0025] This disclosure relates to electronic circuits, and more particularly for example to multi-level power converters.

[0026] Many electronic products, including mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD, LED displays, and the like) use multiple voltage levels for operation. For example, radio frequency (RF) transmitter power amplifiers may operate at relatively high voltages (e.g., 12V or more), whereas logic circuitry may operate at a relatively low voltage level (e.g., 1-3V) and other circuitry may operate at an intermediate voltage level (e.g., 5-10V).

[0027] Direct current power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, solar cells, and rectified AC sources. Power converters which generate a lower output voltage level from a higher input voltage power source are commonly known as buck converters, so-called because the output voltage VOUT is less than the input voltage VIN, and hence the converter is “bucking” the input voltage. Power converters which generate a higher output voltage level from a lower input voltage power source are commonly known as boost converters, because VOUTis greater than VIN. Some power converters may be either a buck converter or a boost converter depending on which terminals are used for input and output. Some power converters may provide an inverted output.

[0028] One type of direct current power converter known as a multi-level power converter includes charge transfer capacitors as energy storage elements coupled by controlled switches to transfer charge from VIN to VOUT. Such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors”. When a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge

[0029] There is a continued need for improved circuits and methods for more effectively and efficiently operating and implementing various type of electrical circuits and devices, including for example multi-level converter circuits.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2 SUMMARY

[0030] Embodiments of the present disclosure include systems, circuits, and methods for operating and implementing multi-level converter circuits.

[0031] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.

[0032] In some embodiments, an integrated circuit comprises a switching network that when connected to one or more capacitors causes said switching network to form a capacitor arrangement dependent on a state of the switching network. A controller may be configured to control the state of the switching network to cycle between a set of states maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage. The controller may be further configured to maintain a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current flow to a source of the first voltage may occur.

[0033] In some embodiments, a method comprises controlling a state of a switching net- work coupled to one or more capacitors to cycle between a set of states associated with different capacitor arrangements of the one or more capacitors, maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage. The method may further comprise maintaining a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current to a source of the first voltage may occur.

[0034] In some embodiments, a circuit comprises one or more capacitors, an inductor, a switching network couplable to the one or more capacitors and configured to form a capacitor arrangement dependent on a state of the switching network, and a controller. The controller may be configured to control the state of the switching network to cycle between a set of states maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage coupled to the inductor. The controller may be further con- figured to maintain a particular state of the switching network for longer than the predefinedDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 amount of time in response to a determination that a current to a source of the first voltage may occur. DESCRIPTION OF THE DRAWINGS

[0035] FIG.1A is an example power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0036] FIG.1B is an example power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0037] FIG. 2A is an example dual integrated circuit (IC) power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0038] FIG. 2B is an example dual IC power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0039] FIG. 3A is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0040] FIG. 3B is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0041] FIG. 4 is a diagram illustrating an example charging function in step down regulation mode of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0042] FIG. 5 is a diagram illustrating an example charging function in step down divide by 3 charge pump mode, in accordance with one or more embodiments of the present disclosure.

[0043] FIG. 6 is a functional block diagram illustrating aspects of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0044] FIG. 7 is a block diagram illustrating an example system implementing a power converter circuit, in accordance with one or more embodiments of the present disclosure.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0045] FIG. 8A is a circuit diagram illustrating an example 3-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0046] FIG. 8B is a circuit diagram illustrating an example 4-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0047] FIG. 8C is a circuit diagram illustrating an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0048] FIG. 9 is an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0049] FIG.10 is a block diagram of an example embodiment of control circuitry for an M-level converter cell, in accordance with one or more embodiments of the present disclo- sure.

[0050] FIGs.11A-11C illustrate simplified diagrams of a multi-level converter circuit, according to some aspects of the present disclosure.

[0051] FIG. 12 is a diagram illustrating an example power converter system that may include a power converter, in accordance with embodiments of the present disclosure.

[0052] FIG.13 is a diagram illustrating a power converter system that includes multiple power converters coupled in parallel, in accordance with embodiments of the present disclo- sure.

[0053] FIG.14 is a diagram illustrating a power converter that includes multiple power converters coupled in parallel, in accordance with embodiments of the present disclosure.

[0054] FIG.15 is a diagram illustrating an exemplary fault handling circuit, in accord- ance with embodiments of the present disclosure.

[0055] FIG.16 is a diagram illustrating a logic circuit of an example power converter system that may include a power converter, in accordance with embodiments of the present disclosure.

[0056] FIG.17 is a diagram illustrating voltage levels for fault handling of power con- verters, in accordance with embodiments for the present disclosure.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0057] FIGs.18A-18C illustrate example waveforms representing the reverse current blocking, according to some aspects of the disclosure.

[0058] FIG.19 is a timing diagram of a reverse current blocking method, according to some aspects of the disclosure.

[0059] FIG.20 is a flowchart illustrating an exemplary method of reverse current block- ing, in accordance with embodiments of the present disclosure.

[0060] FIG.21 is a flowchart illustrating an exemplary method of reverse current block- ing, in accordance with embodiments of the present disclosure.

[0061] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various compo- nents and distances between these components are not drawn to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. DETAILED DESCRIPTION

[0062] The present disclosure encompasses novel circuits, architectures, systems, and methods that more effectively and efficiently address the configuration and operation of multi- level converter circuits. It will be appreciated that various improvements disclosed herein encompass innovative circuits, hardware components, architectures, and related logic that are applicable to applications beyond multi-level converter circuits.

[0063] FIGs.1-6 illustrate various embodiments of a high efficiency 4-level step-down and step-up power converter for battery charging applications, such as single cell Li-ion and Li- polymer battery applications. In the illustrated embodiments, the power converter is configured to deliver up to 5 amperes (A) of charging current in regulation mode and in a divide-by-3 charge pump mode, though other configurations are within the scope of the present disclosure. The power converter can be configured, for example, into dual ICs operation for 9A charging current in regulation mode and in divide-by-3 charge pump mode. Although a 4-level power converter is illustrated, it will be appreciated that the embodiments described herein may be applicable to various M-level implementations, where M >= 3.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0064] In some implementations, for example, the power converter may supply an input range of approximately 4.5 V to 18 V input to support both universal serial bus (USB) and wireless inputs, and in a reverse step-up mode, the output may be programmable from 4.8 V to 16 V in 100 mV step with a programmable output current limit up to 1.7 A. This input voltage range may be used, for example, to support fast charging of single Li-Ion cells from USB and wireless input. It will be appreciated that other voltage and current ranges and limits may be implemented depending on the application. It will also be appreciated that while compatibility with USB is described herein, other wired interfaces and protocols may be implemented with the power converter of the present disclosure.

[0065] In various embodiments, the power converter may be implemented as a single integrated circuit (IC) (see, e.g., Figs.1A-B), dual-integrated circuits (see, e.g., Figs.2A-B), or in other configurations depending on the implementation. In various embodiments, the power converter may operate as a parallel charger along with a main charger, as shown in Fig.3B, to provide the desired functionality noted herein and, for example, as illustrated in Figs. 4 and 5 for the desired charging functionality for various applications, as would be understood by one skilled in the art. Fig. 3B may represent a system level point of view of a mobile architecture having a parallel charger and a main charger that accepts power from a wired port (e.g., a wired USB) or from a wireless interface. The parallel charger for one or more embodiments may represent an IC as illustrated in Figs.1-3A, for example, and may function to charge a battery for some portion of the charging profile (e.g., as shown in Figs.4 and 5), while the main charger charges the battery for other portions of the charging profile. In various embodiments, the parallel charger may also be configured to function as the main charger as well, depending upon the desired application. The novel architecture disclosed herein may be implemented to enable (i) improved efficiency (e.g., at 9A charging current) in a low-profile solution; (ii) low electromagnetic interference (EMI) fixed-frequency operation under heavy load conditions; (iii) input and output current and voltage, IC temperature monitoring and telemetry via inter- integrated circuit (I2C) technology; and / or (iv) full protection including input and output under voltage lockout (UVLO), input and output over voltage protection (OVP), input and output over current protection (OCP), and IC over-temperature with fault and warning status. In some implementations, the power converter supports divide-by-3, step-down and step-up regulating modes, dual external disconnect switch control, and / or paralleled operation.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0066] In the illustrated embodiments, the power converter is implemented as a multi-level charge pump incorporating power switches and control circuitry. The power converter’s internal bias may be provided by the system battery through a VOUT connection (e.g., pin). The charging input can be USB (or other wired input) or wireless input by an external FET register control. In some implementations, the power converter may be programmed to different operating modes, which may include a step-down regulation mode, a step-down divide-by-3 charge pump mode, and a reverse step-up mode.

[0067] In a step-down regulation mode, the power converter operates as a multi-level step- down regulator to support USB power delivery (USB-PD) (or other wired protocol) or fixed input charging. During a constant-current (CC) phase, the maximum charging current may be limited for example, by configuring registers. When the input current does not reach a predetermined maximum input setting, the charge current is set to a predetermined maximum output setting. If the input current reaches the input maximum setting, then the charge current throttles and maintains input current at the input maximum setting. This allows maximum charging current while ensuring that the charge current does not go above a battery maximum current rating and the input current does not trip adapter over-current protection.

[0068] During a constant-voltage (CV) phase, the CV regulation may be limited, for example, by configuring registers. In operation, a single-wire sense pin or other sensor is configured to sense the output voltage VOUT, which is compared to a predetermined value stored in a register, VOUT_REG. The voltage differential between the battery’s positive terminal and negative terminal is sensed and compared to a predetermined value stored in a register, VBATT_REG. In some implementations, a single-wire sense pin or other sensor senses VBATTP (battery voltage at positive terminal) and a single-wire sense pin or other sensor senses VBATTN (battery volage at negative terminal). The CV regulates to the lower of the two settings. If the VOUT sensed voltage reaches VOUT_REG first, then CV is regulated to VOUT_REG. If the VBATTP sensed voltage reaches VBATT_REG first, then CV is regulated to VBATT_REG. This provides a fast battery top off while preventing voltage above safety limit.

[0069] In a step-down divide-by-3 charge pump mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a divide- by-3 step-down charge divider to support USB-Programmable Power Supply (USB-PPS) or other charging protocol or programmable input charging. In some embodiments, the powerDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 converter allows the USB-PPS adapter to control voltage and current and ignores conflicting settings (e.g., settings stored in registers for IOUT_MAX, VOUT_REG and VBATT_REG). In this mode, the power converter monitors an IIN_MAX setting, shuts down the power train (which includes switches to configure, enable and disable various modes of operation) and disconnects external FET when IIN current exceeds IIN_MAX setting. In the illustrated embodiment, the output current is up to 10A in dual IC operation and 5A in single IC operation.

[0070] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register) the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired protocol or standard) or wireless input. The power converter draws power from the system battery and regulates VIN to the VOUT_REG programmable setting of 4.8V to 16V. The VIN output current limit may be set, for example, by an IIN_MAX register.

[0071] In some embodiments, to enable the IC, both an EN pin and an IC_EN bit are set to logic high (1). When either the EN pin or IC_EN bit is set to logic low (0), the IC is disa- bled. After the IC is enabled, the POR status bit sets to 1 to indicate the IC has a fresh power up.

[0072] In some embodiments, the power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs may be controlled by registers (e.g., 1-bit registers V_EXTG, EXTG_EN and EXTGX). The V_EXTG bit sets the gate drive voltage and can be set to 9V or 5V, in the illustrated embodiment. The EXTGX bits select which FET(s) to turn on. The EXTG_EN bit enables the gate driver to turn on the selected FET(s). In various embodiments, the external FET can be turned on or off independently from other IC operations except when the IC is disabled. The EXT_EN_IND status bit set to 1 when external FET is enabled. When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respected FET would not turn on from the off mode.

[0073] In various embodiments, the power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path may be configured between the external FET on time and the power train on time to minimize in-rush current. Next, both PT_EN pin and PT_EN bit are set to logic high (1) to turn on the power train. When either PT_EN pin or PT_EN pin is logic low, the powerDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 train is off. In dual IC operation, the slave IC power train may be configured to turn on first before the master IC. The COMP, SYNC and SYNCH pins from two ICs gate the power train and synchronize the operation. The SYNC_SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down the power train operation when fault is detected.

[0074] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired port) or wireless input. The power converter draws power from the system battery and regulates VIN pin to a VOUT_REG programmable setting of 4.8V to 16V. The VIN output current limit is set by IIN_MAX register.

[0075] To enable the IC, both the EN pin and IC_EN bit are set to logic high (1). When either EN pin or IC_EN bit is set to logic low (0), the IC is disabled. After the IC enables, the POR status bit sets to 1 to indicate the IC has a fresh power up. The power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs are controlled by register bits, such as V_EXTG, EXTG_EN and EXTGX. The V_EXTG bit sets the gate drive voltage and can be set to 9V or 5V, for example. The EXTGX bits select which FET(s) to turn on. The EXTG_EN bit enables the gate driver to turn on the selected FET(s). The external FET can be turned on or off independently from other IC operation except when the IC is disabled. The EXT_EN_IND status bit set to 1 when external FET is enabled.

[0076] When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respective FET would not turn on from off mode. The power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path should be given between external FET on time to power train on time to minimize in-rush current. Next, both PT_EN pin and PT_EN bit are set to logic high (1) to turn on the power train. When either PT_EN pin or PT_EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train is turned on before the master IC. The COMP, SYNC and SYNCH pins from the two ICs gate the power train and synchronize the operation. SYNC_SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down power train operation when a fault is detected.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0077] In accordance with various embodiments, an example power converter initialization, an example power up sequence, and an example fault handling will now be described for the three different operating modes. In an example step-down regulation mode, the initialization and power up sequence uses EXT1 as an example. The same sequence may apply to EXT2 with the only change in EXTGX bit and related EXT2 register settings. First, pull EN to logic high and then set IC_EN bit=1 at 100us(TBD) after EN is logic high to enable IC. IC startup from POR stage, POR bit reports 1 indicating fresh IC startup. Next, the POR bit is read to confirm the IC is enabled. The FREQUENCY register is then set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT_REG register is set to the target regulation voltage on the VOUT sense pin in CV operation. The VBATT_REG register is set to the target regulation voltage on the VBATTP sense pin in CV operation. The IOUT_MAX register is set to the target maximum charger current in CC operation, and the IIN_MAX register is set to a value below the adapter current limit. Next, the FAULT and WARNING registers was set to a desired setting. Each Fault and Warning enables at a different time based on IC status and operating mode. The WATCHDOG register is then set to a desired setting.

[0078] The MODE register and other related registers are set for step-down regulation mode, including power train setup and enablement of an external FET, while checking for faults. In a dual IC operation, the external FETs are controlled by the master IC. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the external FET after the shutdown fault is initiated. Next, the power train is enabled. In a dual IC operation, the slave IC power train is turned on before the master IC. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation.

[0079] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0080] An example step-down divide-by-3 power converter mode initialization and power up sequence will now be described. The initialization and power up sequence uses EXT1 as anDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 example, but it will be appreciated that the same sequence applies to EXT2 with a change in EXTGX bit and related EXT2 register settings. The EN is pulled to logic high and then IC_EN bit=1 at 100us(TBD) after EN is logic high to enable IC. The IC starts up from POR stage, POR bit reports 1 indicating fresh IC startup. The POR bit is read to confirm the IC is enabled. The FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The IIN_MAX register is set to a value below the adapter current limit. VOUT_REG, VBATT_REG and IOUT_MAX registers are not used in step-down divide-by-3 charge pump mode. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. The FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at different time based on IC status and operating mode.

[0081] The MODE register and other registers are set for step-down divide-by-three mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter.

[0082] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0083] An example reverse step-up mode initialization and power up sequence will now be described. This initialization and power up sequence uses EXT2 as an example, but the same sequence applies to EXT1 with the change in EXTGX bit and related EXT1 register setting. The value EN is pulled to logic high and then IC_EN bit is set to 1 at 100us(TBD) after EN is logic high to enable IC. The IC starts up from the POR stage, and the POR bit reports 1 indicating a fresh IC startup. The POR bit is read to confirm the IC is enabled. Next, the FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to theDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 same frequency setting. The VOUT_REG register is set to the target regulation voltage at VIN. Next, the IIN_MAX register is set to the target current limit. VBATT_REG and IOUT_MAX registers are not used in reverse step-up mode. FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at a different time based on IC status and operating mode.

[0084] The MODE register and other registers are set for reverse step-up mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. In dual IC operation, the slave IC power train is turned on before the master IC and is controlled by the master IC.

[0085] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault. The EXT2 or VIN pins are not configured to detect OVP as it is set as the output in reverse step-up mode. But if EXT2 or VIN pin detects an OVP event, then IC_STATUS1 and IC_STATUS2 would report the fault event.

[0086] In an example system 700 illustrated in FIG. 7, a power converter 720 is implemented in a host 710 (e.g., a device or system) that includes a battery 730 and various system components 740. The host 710 may be any system or device that implements a power converter as described herein, including but not limited to a smart phone, tablet, portable electronics, a mobile device, low power electronics, and other electronic systems. The battery 730 may include one or more batteries that store electricity for use by the host 710, such as single cell Li-ion and Li-polymer batteries.

[0087] The power converter 720 may be configured to convert electricity stored in the battery 730 to a desired system voltage, VSYS, for powering various system components 740,Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2 which may include one or more logic devices 742, memories 744, communications components 746, input / output (I / O) components 748, circuitry 750, and other components 752. The power converter 720 may also supply power to one or more external devices 760, such as a component connected to the host 710 through a wired or wireless connection, such as a USB compatible device. The power converter 720 may also be configured to receive power from an external power source 712 and convert the received power to the battery 730 for storage, or to the system components 740 and / or external device 760, as applicable.

[0088] In various embodiments, the one or more logic devices 742 and memories 744 may be configured to perform operations of the host 710. A logic device 742 may be imple- mented as a general-purpose processor, a digital signal processor (DSP), an application-spe- cific integrated circuit (ASIC), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), or other programmable logic device(s). The logic de- vice 742 and other components may be configured through hardwiring, software execution, or a combination of both. In various embodiments, the host 710 includes one or more memory devices designed to retain data, such as software instructions for execution by the logic device. The memory may include volatile and non-volatile memories, such as random- access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile random- access memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically-erasable pro- grammable read-only memory (EEPROM), flash memory, hard disk drives, or other memory types. The logic device may be configured to execute software instructions residing in the memory, thereby accomplishing method steps and operations.

[0089] Referring to FIGs. 8A-8C, the converter circuit may be configured to switch between two or more switch states. One or more PWM duty cycle controllers may be provided to set the time in each switch state based on the voltage at VOUT. For example, FIG. 8A is a schematic diagram of a 3-level DC-to-DC buck converter circuit 800 that may be used as the converter circuit 920 of FIG. 9. A set of four switches, S1-S4, is series-coupled between VIN and circuit ground. A fly capacitor C1 is coupled in series with switches S3 and S4, and in parallel with switches S1 and S2. An inductor L1 is coupled to an output capacitor COUT and to a node Lx between switches S1 and S2, and the voltage across the output capacitor COUT is VOUT.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0090] In the illustrated example, the presence of the single fly capacitor C1 in the converter circuit 800 enables four switch states that each generate one of three voltage levels at node Lx. In a first switch state, S2 and S4 are closed and S1 and S3 are open, effectively bypassing C1 and connecting Lx to circuit ground (voltage level at Lx = GND). In a second switch state, S2 and S4 are open and S1 and S3 are closed, effectively bypassing C1 and connecting Lx to VIN (voltage level at Lx = VIN). In a third switch state S1 and S4 are open and S2 and S3 are closed, connecting C1 from VIN to LX, and thus charging C1 with inductor L1 current flowing into a load. The voltage across C1 will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2. In a fourth switch state, S1 and S4 are closed and S2 and S3 are open, connecting C1 from Lx to GND and thus discharging C1 with inductor L1 current flowing to a load. The voltage across C1 will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2 (e.g., this may assume that C1 was previously charged in state three). Accordingly, the illustrated converter circuit 800 has two switch states that generate a voltage level of VIN / 2 at the Lx node.

[0091] If the converter circuit 800 is toggled between switch states three and four (avoiding switch state two that bypasses the fly capacitor C1), the inductor L1 sees small jumps in the voltage level at Lx, going from GND to only VIN / 2 and back to GND, which results in reduced voltage ripple across the inductor L1 and less filtering to smooth VOUT than a converter circuit with only S1 and S2 switches.

[0092] Adding additional series switches Sx and fly capacitors Cx to the 2-level converter circuit 800 increases the number of switch states and resulting voltage levels between VIN and circuit ground that can be applied to the Lx node, thus generating an even smaller voltage ripple across the inductor L. This reduces the filtering requirements to get a smooth output voltage. For example, a 4-level DC-to-DC buck converter circuit (see, e.g., FIG.8B) includes 6 series- coupled switches S1-S6 and two fly capacitors Cx (X = 2). Consequently, a 4-level converter circuit can define 4 voltage levels (VIN, GND, VIN, and VIN) at node LX from 8 switch states (3 switch states result in the VIN level at Lx, and 3 other switch states result in the VIN level at Lx). For some applications, VOUT is set low enough that the voltage level at node Lx alternates between GND and the next higher voltage level available. For higher output voltages, the switching pattern may never use GND. For example, in a 4-level converter circuit,an output VOUT set to 0.5 VIN can be achieved by alternating the Lx node between VINand V.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0093] A different interpretation of a multi-level converter circuit is that the fly capacitors Cx create a charge-pump for the buck converter circuit. Unlike a standard charge-pump where the output is restricted to one output, a multi-level converter circuit allows the fly capacitors Cx to be coupled to create multiple intermediate voltages. For the 4-level example, the two fly capacitors each act as a charge-pump with the additional benefit that any input voltage that is a sum of ratios can be created, including VIN and GND.

[0094] A multi-level converter circuit couples the fly capacitors Cx in different combinations in order to bring the voltage level at the Lx node down or up. As noted above, when a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it, which creates a control problem in maintaining an average voltage.

[0095] Resolving the charge-balance problem so as to maintain an average voltage across the single capacitor in a 3-level converter circuit will now be described. For example, in a 3- level converter circuit, one way to generate the Level-1 (GND) and Level-3 (VIN) voltage levels at the Lx node is to not use the fly capacitors C1 for these Lx voltage levels. However, for the Level 2 (VIN / 2) voltage level at Lx, two separate switch states can be used: one switch state charges the capacitor (S3 and S2 closed, S1 and S4 open) and the other switch state discharges the capacitor (S3 and S2 open, S1 and S4 closed). The control of a 3-level converter circuit may operate such that each time the converter circuit switches states to Level-2, a controller can alternate between charging and discharging the single capacitor to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help decide on a charging state or a discharging state. For instance, if the capacitor voltage is below VIN / 2, then a controller would select charge (the third switch state), and if the capacitor voltage is above VIN / 2, then the controller would select discharge (the fourth switch state).

[0096] Referring to FIGs.8B, a 4-level converter circuit 830 (X = 2) illustrates the charge- balance difficulty when more capacitors are present. A Level-1 voltage level (GND) and a Level-4 voltage level (VIN) at the Lx node are each determined by a single switch state.However, the Level-2 voltage level ( VIN) and Level-3 voltage level ( VIN) at Lx each canbe achieved by any of three different switch states. At higher orders of a multi-level converter circuit (X > 2), more switch states are possible for generating the intermediate levels between VIN and GND. The problem gets more complicated with a 5-level converter circuit (X= 3). A Level-1 voltage level (GND) and a Level-5 voltage level (VIN) at the Lx node are eachDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 determined by a single switch state. However, the Level-2 voltage level (¼VIN) and Level-4 voltage level (¾ VIN) at Lx each can be achieved by any of four different switch states, the Level-3 voltage level (2 / 4 VIN) at Lx can be achieved by any of six different switch states.

[0097] As should be clear from these examples, determining a suitable charge-balance method can become exceedingly difficult as the complexity of a multi-level converter circuit increases. As previously noted, most conventional control methods rely on establishing a sequence of linked state-changes to try to achieve charge balance. Control systems based on long sequences of switch states generally assume that all system variables - such as input voltage and output current - are constant during the sequence. This is unrealistic for a real- world environment, where all system variables tend to be dynamic.

[0098] In a 2-Level example, the converter circuit switches between two switch states: S1 closed and S2 open (voltage level at LX = VIN), or S1 open and S2 closed (voltage level at LX = GND). A PWM duty cycle controller sets the time in each switch state based on the voltage at VOUT, which determines the amplitude of the average voltage at LX (noting that, the average LX voltage in theory is equal to the VOUT average voltage, but that, due to parasitics, the LX average voltage is higher and / or lower (for negative currents) than the VOUT average). As can be appreciated, the inductor L sees large jumps in the voltage level at LX, from GND to VIN and back to GND. The resulting voltage ripple across the inductor L necessitates a significant amount of filtering to smooth VOUT.

[0099] An alternative way of reducing the voltage ripple across the inductor L is to add more series switches as well as charge transfer capacitors as energy storage elements to transfer charge from VINto VOUT. As noted above, such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be external components coupled to an integrated circuit embodiment of a converter circuit. The presence of X fly capacitors Cx defines a multi-level capacitive converter circuit capable of generating M = X + 2 voltage levels at node LX from 2(X+1)switch states.

[0100] FIG. 8C is schematic diagram of a generalized M-level multi-level converter cell 870 that may be used as the converter circuit 920 of FIG.9. A set of switches, S1-S[2*(M 1)], is series-coupled between VIN and circuit ground. The set of switches are organized in switch pairs: S1 & S2, S3 & S4, … S[2*(M 2)+1] & S[2*(M 1)]. A set of M 2 fly capacitor Cx is coupled in series with certain respective switches, and in parallel with switches in betweenDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 those switches. In terms of switch pairs, there are M 1 pairs of switches, or one more than the number of fly capacitors. An optional inductor L is coupled to an output capacitor COUT and to a node LX between switches S1 and S2, and again the voltage across the output capacitor COUT is VOUT. The inductor L doubles as a virtual current source that facilitates movement of charge between the fly capacitors Cx. This creates a very efficient form of charge transfer, but introduces the problem of charge-balancing the fly capacitors Cx.

[0101] In various embodiments, each fly capacitor Cx has a first terminal coupled betweenan outer high-side switch S[2*x + 1] and an inner high-side switch S[2*x 1], where “high-side” refers to the VINside of the converter circuit. Each fly capacitor Cx has a second terminal coupled between an outer low-side switch S[2*x + 2] and an inner low-side switch S[2*x], where “low-side” refers to the circuit ground (GND) side of the converter circuit. Thus, for an M = 3 multi-level converter cell, a first terminal of the single (X = 1) fly capacitor C1 would be coupled between outer high-side switch S3 and inner high-side switch S1, and a second terminal of the capacitor C1 would be coupled between inner low-side switch S2 and outer low-side switch S4. Accordingly, each fly capacitor Cx within the multi-level converter cell 870 has four switches that can affect current flow through that fly capacitor Cx.

[0102] In some embodiments, a voltage detector, which may be a simple comparator-type circuit, is provided to sense the voltage across a corresponding fly capacitor Cx with respect to a reference voltage, VREF, which represents a desired target voltage for the fly capacitor Cx. Every fly capacitor Cx may have a target average voltage in order to maintain proper output level. For an M-level converter and capacitor Cx, where x = 1, 2, … [M 2], its target voltage Vtarget[Cx] = VIN *

[0103] The voltage detector may be configured to output a HIGH / LOW status signal, CFx_H / L, indicating with the voltage across the corresponding fly capacitor Cx is greater than VREF or less than VREF. The CFx_H / L status signal is coupled to control circuitry for the switches associated with the fly capacitor Cx.

[0104] The control circuitry for the four switches that can affect current flow through a fly capacitor Cx set states for those switches in part as a function of the voltage across the fly capacitor Cx as measured by the associated voltage detector and conveyed by the CFx_H / Lx statusDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 signal. Accordingly, for ease of understanding, it can be said that each fly capacitor Cx “controls” its own pairs of high-side and low-side switches. If it is assumed that current flow in the inductor is charging the output VOUT, there are four possible states that can be defined for the pairs of high-side and low-side switches for each fly capacitor Cx.

[0105] In a switch state in which the outer high-side and inner low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a charging configuration (whether or not charging actually occurs may depend on the switch states for other fly capacitors Cx). In a switch state in which the inner high-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a discharging configuration (whether or not discharging actually occurs may depend on the switch states for other fly capacitors Cx). In a switching state in which the inner low-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be bypassed. In a switching state in which the outer high-side and inner high-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would again be bypassed.

[0106] While each fly capacitor Cx can control both of its own pairs of high-side and low- side switches, in general, methods of control disclosed herein may utilize either the outer switches or the inner switches controllable by each corresponding capacitor. For example, referring to FIG.8B, in “outer-switch” methods, fly capacitor C1 will control its outer switches S3 and S4, fly capacitor C2 will control its outer switches S5 and S6, etc. Conversely, for example, in “inner-switch” methods, fly capacitor C1 will control its inner switches S1 and S2, fly capacitor C2 will control its inner switches S3 and S4, etc. The switch states of either pair (inner or outer) of switches controlled by a fly capacitor Cx may be complementary – that is, no fly capacitor Cx closes or opens both of its high-side and low-side controlled switches at the same time. If each fly capacitor Cx controls its outer-switches, then no fly capacitor controls the left-over innermost switches S1 and S2. If instead each fly capacitor Cx controls its inner- switches, then no fly capacitor controls the left-over outermost switches S[2*(M-1)] and S[2*(M-2)+1]. Switch states for the left-over switches are also complementary.

[0107] FIG. 9 is a high-level block diagram of an example circuit that includes a power converter 900, in accordance with one or more embodiments of the present disclosure. In the illustrated example, the power converter 900 includes a converter circuit 920 and a controllerDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 910. The converter circuit 920 and controller 910 may be configured to implement, for example, any of the multi-level power converter circuits as previously described with reference to FIGs. 1A-8C, and as described further herein. In the illustrated embodiment, the converter circuit 920 is configured to receive an input voltage VIN from a voltage source and transform the input voltage VIN into an output voltage VOUT. In some embodiments of the power converter 900, auxiliary circuitry (not shown), such as a bias voltage generator(s), a clock generator, a voltage control circuit, etc., may also be present and coupled to the converter circuit 920 and the controller 910.

[0108] The controller 910 receives a set of input signals and produces a set of output signals. Some of these input signals arrive along a signal path connected to the converter circuit 920. These input signals carry information that is indicative of the operational state of the converter circuit 920. The controller 910 may also receive a clock signal CLK (for synchronous converter circuits 920) and one or more external input / output signals I / O that may be analog, digital (encoded or direct signal lines), or a combination of both. Based upon the received input signals, the controller 910 produces a set of control signals back to the converter circuit 920 that control the internal components of the converter circuit 920 (e.g., internal switches, such as low voltage FETs / MOSFETs) to cause the converter circuit 920 to boost or buck VIN to VOUT. In some embodiments, an auxiliary circuit (not shown) may provide various signals to the controller 910 (and optionally directly to the converter circuit 920), such as the clock signal CLK, the input / output signals I / O, as well as various voltages, such as a general supply voltage VDD and a transistor bias voltage VBIAS.

[0109] FIG. 10 is a block diagram of one embodiment of advanced control circuitry 1000 for an M-level converter cell 1000 such as the generalized version depicted in FIG.8B. The M- level converter cell 1020 is shown coupled to an output block 1001 comprising an inductor L and an output capacitor COUT (conceptually, the inductor L also may be considered as being included within the M-level converter cell 1020). The advanced control circuitry 1000 functions as a control loop coupled to the output of the M-level converter cell 1020 and to switch control inputs of the M-level converter cell 1020. In general, the advanced control circuitry 1000 is configured to monitor the output (e.g., voltage and / or current) of the M-level converter cell 1020 and dynamically generate a set of switch control inputs to the M-level converter cell 1020 that attempt to stabilize the output voltage and / or current at specified values, taking into account variations of VIN and output load. In alternative embodiments, theDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 advanced control circuitry 1000 may be configured to monitor the input of the M-level converter cell 1020 (e.g., voltage and / or current) and / or an internal node of the M-level converter cell 1020 (e.g., the voltage across one or more fly capacitors or the current through one or more power switches). Accordingly, most generally, the advanced control circuitry 1000 may be configured to monitor the voltage and / or current of a node (e.g., input terminal, internal node, or output terminal) of the M-level converter cell 1020. The advanced control circuitry 1000 may be incorporated into, or separate from, the overall controller for a power converter 100 embodying the M-level converter cell 1020.

[0110] A first block comprises a feedback controller 1002, which may be a traditional controller such as a fixed frequency voltage mode or current mode controller, a constant-ON- time controller, a hysteretic controller, or any other variant. The feedback controller 1002 is shown as being coupled to VOUT from the M-level converter cell 1020. In alternative embodiments, the feedback controller 1002 may be configured to monitor the input of the M- level converter cell 1020 and / or an internal node of the M-level converter cell 1020. The feedback controller 1002 produces a signal directly or indirectly indicative of the voltage at VOUT that determines in general terms what needs to be done in the multi-level converter cell 1020 to maintain desired values for VOUT: charge, discharge, or tri-state (i.e., open, with no current flow).

[0111] In the illustrated example, the feedback controller 1002 includes a feedback circuit 1004, a compensation circuit 1006, and a PWM generator 1008. The feedback circuit 1004 may include, for example, a feedback-loop voltage detector which compares VOUT(or an attenuated version of VOUT) to a reference voltage which represents a desired VOUTtarget voltage (which may be dynamic) and outputs a control signal to indicate whether VOUTis above or below the target voltage. The feedback-loop voltage detector may be implemented with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier).

[0112] The compensation circuit 1006 is configured to stabilize the closed-loop response of the feedback controller 1002 by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response of the feedback controller 1002. The compensation circuit 1006 may be implemented in known manner, and may include LC and / or RC circuits.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0113] The PWM generator 1008 generates the actual PWM control signal which ultimately sets the duty cycle of the switches of the multi-level converter cell 1020. In addition, in some embodiments, the PWM generator 1008 may pass on additional optional control signals CTRL indicating, for example, the magnitude of the difference between VOUTand the reference voltage (thus indicating that some levels of the M-level converter cell 1020 should be bypassed to get to higher or lower levels), and the direction of that difference (e.g., whether VOUTis greater than or less than the reference voltage). In other embodiments, the optional control signals CTRL can be derived from the output of the compensation circuit 1006, or from the output of the feedback circuit 1004, or from a separate comparator (not shown) coupled to, for example, VOUT. One purpose of the optional control signals CTRL is for advanced control algorithms, when it may be beneficial to know how far away VOUT is from a target output voltage, thus allowing faster charging of the inductor L if the VOUT is severely under regulated.

[0114] A second block comprises a multi-level controller 1010, the primary function of which is to select the switch states that generate a desired VOUT while maintaining a charge- balance state on the fly capacitors within the M-level converter cell 1020 every time an output voltage level is selected, regardless of what switch state or states were used in the past.

[0115] The multi-level controller 1010 includes a Voltage Level Selector 1012 which receives the PWM control signal and the additional control signals CTRL if available. In addition, the Voltage Level Selector 1012 may be coupled to VOUTand / or VIN, and, in some embodiments, to the HIGH / LOW status signals, CFx_H / L, from the voltage detectors coupled to corresponding fly capacitors Cx within the M-level converter cell 1020. A function of the Voltage Level Selector 1012 is to translate the received signals to an output voltage Target Level (e.g., on a cycle-by-cycle basis). The Voltage Level Selector 1012 typically will consider at least VOUT and VIN to determine which Target Level should charge or discharge the output of the M-level converter cell 1020 with a desired rate. For example, in a 6-level converter circuit, the available Target Levels are Level-1 (GND), Level-2 (1 / 5VIN), Level-3 (2 / 5VIN), Level-4 (3 / 5VIN), Level-5 (4 / 5VIN), and Level-6 (VIN), which may be represented as a count value from 1-6 (or 0-5).

[0116] As an example, in a 4-Level converter circuit, if VIN = 12V and VOUT nominally should be 3V, then the Voltage Level Selector 1012 may indicate that a Target Level of “2” can be selected, which results in a 1 / 3VIN voltage level at LX (i.e., 4V). The PWM control signalDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 sets a duty cycle between that Target Level and another Target Level (e.g., GND) so that the average voltage level at LX will be about 3V.

[0117] In general, for steady-state operations, the Target Level voltage closest to VOUTthat either charges or discharges the inductor L may be selected for simplicity of the selection algorithm. In general, for transient response, a Target Level that is higher (for charging) or lower (for discharging) than the closest Target Level may be selected to quickly charge or discharge the inductor L. The Voltage Level Selector 1012 may be implemented, for example, as a look-up table (LUT) or as comparison circuitry and combinatorial logic or more generalized processor circuitry. In some embodiments, the Voltage Level Selector 1012 can implement advanced methods (described below) that try to speed up charging or discharging based on additional factors, such as inductor voltage drop, load transients, the magnitude of output deviations, and / or external input signals from external sources. The output of the Voltage Level Selector 1012 may include duty cycle information (e.g., derived from the input PWM control signal) as well as switch state.

[0118] The output of the Voltage Level Selector 1012 is coupled to a Multi-Level Switch State Selector 1014, which generally would be coupled to the status signals, CFx_H / L, from the voltage detectors for the fly capacitors Cx. Taking into account the Target Level generated by the Voltage Level Selector 1012, the Multi-Level Switch State Selector 1014 determines a pattern of switch states for the desired output level that generally achieves charge-balancing the fly capacitors Cx. The Multi-Level Switch State Selector 1014 may be implemented, for example, as comparison circuitry and combinatorial logic, as a look-up table (LUT), or as more generalized processor circuitry. The output of the Multi-Level Switch State Selector 1014 is coupled to the switches of the multi-level converter cell 1020 (through appropriate level-shifter circuits and drivers circuits, as may be needed for a particular converter cell) and includes a pattern of switch state settings determined by the Multi-Level Switch State Selector 1014. The pattern of switch state settings selects the configuration of the switches within the multi-level converter cell 1020.

[0119] In general (but not always), for PWM-based control systems, the Voltage Level Selector 1012 and the M-level Switch State Selector 1014 only change their states when the PWM signal changes. For example, when the PWM signal goes high, the Voltage Level Selector 1012 selects which level results in charging of the inductor L and the M-level Switch State Selector 1014 sets which version to use of that level. Then when the PWM signal goesDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 low, the Voltage Level Selector 1012 selects which level can discharge the inductor L and the M-level Switch State Selector 1014 sets which version of that level to use. Thus, the Voltage Level Selector 1012 and the M-level Switch State Selector 1014 generally only change states when the PWM signal changes (the PWM signal is in effect their clock signal). However, there may be situations or events where it is desirable for the CTRL signal to change the state of the Voltage Level Selector 1012. Further, there may be situations or events where it is desirable for the CFx_H / Lstatus signal(s) to cause the M-level Switch State Selector 1014 to select a particular configuration of power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the M- level Switch State Selector 1014 to re-evaluate the optimal version of the state periodically, for example, in order to avoid being “stuck” at one level for a very long time, potentially causing charge imbalances.

[0120] One notable benefit of the control circuitry shown in FIG. 10 is that it enables generation of voltages in boundary zones between voltage levels, which represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits.

[0121] In alternative unregulated charge-pumps embodiments, the feedback controller 1002 and the Voltage Level Selector 1012 may be omitted, and instead a clock signal CLK may be applied to the M-level Switch State Selector 1014. The M-level Switch State Selector 1014 would generate a pattern of switch state settings that periodically charge balances the fly capacitors Cx regardless of what switch state or states were used in the past (as opposed to cycling through a pre-defined sequency of states). This ensures that if VINchanges or anomalous evens occur, the system generally always seeks charge balance for the fly capacitors Cx.

[0122] In some embodiments, the M-level Switch State Selector 1014 may take into account the current IL flowing through the inductor L by way of an optional current- measurement input 1016, which may be implemented in conventional fashion.

[0123] In an M-level multi-level converter circuit, the configuration of switches that achieves Level-1 (e.g., GND) or Level-M (e.g., VIN) effectively bypasses the fly capacitors Cx. Conversely, for all intermediate voltage levels, at least one fly capacitor Cx is coupled to VOUT and there are always at least two configurations of switches that can achieve any intermediate voltage level. For any particular intermediate voltage level, at least one configuration ofDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 switches results in charging the associated fly capacitor and at least one other configuration of switches results in discharging the associated fly capacitor. One aspect of the present disclosure is the realization that any achievable output voltage VOUT requiring intermediate voltage levels can be attained by dynamically selecting patterns of switch configurations – that is, by selecting switch configurations without regard to or memory of the switch configurations of any previous switching cycle – to select appropriate Levels, and doing so in a way that purposefully selects either charging or discharging switch configurations that also balance charge across the fly capacitors Cx.

[0124] Embodiments of the disclosure use the following approach for positive inductor L current (charging VOUT): (1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer high-side switch in outer-switch control methods, or the inner low-side switch for inner-switch control methods); and (2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer low-side switch for outer-switch control methods, or the inner high-side switch for inner-switch control methods).

[0125] For negative inductor L current (discharging VOUT), the selection of switches inverts. Accordingly: (1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer low-side switch in outer-switch control methods, or the inner high-side switch for inner-switch control methods); and (2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer high-side switch for outer-switch control methods, or the inner low-side switch for inner-switch control methods).

[0126] Note again that whether or not charging actually occurs for a particular fly capacitor Cx generally depends on the switch states for all other fly capacitors. For a fly capacitor C(x)to actually charge or discharge, the next inward (if one exists) fly capacitor C(x 1) (for outer-switch control methods) or the previous outward (if one exists) fly capacitor C(x+1) (for inner- switch control methods) must be set to the opposite state (i.e., discharge or charge) so that a bypass situation does not occur.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0127] For any multi-level converter circuit of order M that can create M voltage levels – i.e., Level-1 (e.g., GND) through Level-M (e.g., VIN) – then the following switch count rules apply for any Level-m: (1) M m low-side switches must be set to be closed (ON); (2) m 1 high-side switches must be set to be closed (ON); and (3) switches that are not required to be ON must be set to be OFF (open).

[0128] With these switch count rules in mind, the following generalized capacitor control method applies for each state change of the Multi-Level Switch State Selector 1014: Step 1) Select a fly capacitor that has not previously been selected; Step 2) If the voltage of the selected fly capacitor is above its Vtarget and there are remaining (i.e., not been set by this method in this cycle) low-side or high-side switches that can be set to be closed to enable a discharge path for the selected fly capacitor, then set those switches that enable a discharge path for the selected fly capacitor to be closed, decrement one or more appropriate counters (e.g., for the number of low-side switches set to be closed and the number of high-side switches set to be closed), and flag the current fly capacitor as “done” (i.e., as having been selected); otherwise (since the voltage of the selected fly capacitor is below its Vtarget) set the switches that enable a charging path for the selected fly capacitor to be closed and flag the current fly capacitor as “done”; Step 3) Loop to Step 1 until all fly capacitors have been selected; Step 4) For the remaining pair of left-over switches, set the high-side switch or the low-side switch to be closed based on the switch count rules and the counter values.

[0129] With the above generalized capacitor control method, more specific multi-level charge-balancing control methods can be created. Examples can be found, for example, in U.S. Patent Publication No.20230148059, which is incorporated by reference herein in its entirety.

[0130] FIGs.11A-11C illustrate exemplary embodiments of capacitor voltage sensing cir- cuits. In some embodiments, the sensing circuits sample voltage across a capacitor after a spec- ified delay and compare the sample voltage to a reference target voltage. The reference target voltage a predetermined fraction of an input voltage, or a voltage supplied to an associated power converter, such as a multi-level power converter.

[0131] A simplified diagram of an embodiment of a multi-level converter circuit 1100 is illustrated in FIG.11A, according to some aspects of the disclosure. As shown, the circuit 1100Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2 includes six switches, labeled as S1-S6, connected in series between an input voltage Vin and ground. The circuit 1100 may be referred to as a four-level multi-level converter because the voltage supplied to node Lx can be one of four levels, depending on the states of the switches S1-S6. The switches S1-S6 may be implemented using field-effect transistors (FETs), as un- derstood in the art. For example, the switches S1-S6 may be implemented as FETs Q1-Q6, as shown in FIG.3, where the on / off (closed / open) state of each FET is controlled by a gate volt- age. The circuit 1100 may be coupled to a clock (not shown), and the switches may be con- trolled such that the state of each switch is set as open or closed and may be changed each clock cycle or some multiple of clock cycles. Each switch S1-S6 may include associated circuitry for controlling the state of the switch. For example, if each switch is implemented using a FET, a level shifter and gate driver may be connected to the gate of the FET to control the on / off state. The level shifter and gate driver may receive an input signal that controls the state of the FET. In some embodiments, the series-connected switches S1-S6 may utilized in a power con- verter, and an operating state of the power converter may be referred to as a power state. For example, a power state corresponds to a particular combination of states of switches S1-S6 that may occur during operation of the power converter. The power states may be switched at a specified frequency, such as one megahertz (MHz) or more. The multi-level power converter circuit 1100 includes capacitor C1 and C2 that are charged to a target voltage range during steady-state operation. The voltage across C1 is typically maintained at around Vin / 3, and the voltage across C2 is typically maintained at around 2Vin / 3.

[0132] FIGS.11B and 11C illustrate multi-level converter circuit 1100 operating in differ- ent power states during different regularly occurring time periods, such as during different clock cycles, and for an exemplary input voltage of 5V. In all the power states, the voltage across C2 is maintained at about 2Vin / 3, or about 3.3V in this example, and the voltage across C1 is maintained at about Vin / 3, or about 1.6V in this example. FIG. 11B illustrates power states labeled as State 1, State 2, and State 3, and all three states yield about the same voltage (of 1.6V) at the node labeled as Lx, where one terminal of the inductor L connects to the series of switches. The state of charging and discharging the capacitors C1 and C2 are also illustrated, using the abbreviations “Dis” for discharge and “Ch” for charge. For example, for the state of the switches shown as State 1, C1 is charging and C2 is discharging (switches S1, S4, and S5 are open and the remaining switches are closed). In State 2, C1 is discharging (Dis); and in State 3, C2 is charging (Ch).Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0133] FIG. 11C illustrates power states labeled as State 4, State 5, and State 6, and all three states yield about the same voltage (of 3.3V) at the node labeled as Lx. The charging and discharging states of C1 and C2 are illustrated in FIG.11C.

[0134] During operation of multi-level converter circuits, such as circuit 1100, it can be important to carefully maintain the voltage of each fly capacitor within a specified range. For example, during a normal or steady-state operation of a multi-level power converter circuit, the voltage across C2 is typically maintained within a range around a fraction of Vin, such as 2Vin / 3, and the voltage across C1 is typically maintained within a range around a fraction of Vin, such as Vin / 3. The voltage fraction may be maintained, even though the input voltage Vin may “float,” or vary. The states of switches S1-S6 may be changed periodically to maintain an appropriate charge on fly capacitors C1 and C2, while at the same time delivering the desired power at the output denoted by Vout in FIG. 11A. For example, a load (not shown) may be connected in parallel with capacitor Cout, and the circuit 1100 may deliver power to this load according to the needs of the load, which may vary with time.

[0135] Balancing the competing needs of maintaining charge across fly capacitors in multi-level converters, such as the circuit 1100, while at the same time delivering power to a load according to potentially time-varying needs of the load is challenging, particularly where the input voltage Vin may also be floating. Therefore, there is a need to accurately sense voltage across fly capacitors in a “noisy” environment due to frequent changes of states of switches in multi-level converters to be able to control the level of charge on the capacitors.

[0136] There is also a need to develop techniques to maintain a desired level of charge on fly capacitors, which can be particularly challenging where a time-varying load may enter a “low load” condition, in which output current becomes small or relatively close to zero. For example, in one use case, a multi-level converter may supply power to a processor or other complex integrated circuit as a load, and such a load may enter a dormant or sleep state where little power may be needed.

[0137] By carefully switching among States 1-6, target voltages can be maintained across capacitors C1 and C2 while delivering power to a load (not shown) connected in parallel with Cout, according to the needs of the load.

[0138] FIG. 12 is a diagram illustrating an example power converter system 1200 (e.g., power converter systems 600, 720, 800, 830, 870, 900, 1000, 1300, 1400, 1500) that may haveDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 a power converter (e.g., devices 1302, 1304, 1306). As shown in FIG. 12, power converter system 1200 may include a power converter shown as device 1240. Device 1240 may include a buck converter, a boost converter, a charge pump circuit, or any other types of converter circuits. In various embodiments, power converter system 1200 may have different operating ranges for different applications, such as an energy management system in large-scale data centers, a vehicle electrical system in automotive applications, etc.

[0139] Power converter system 1200 may have a voltage source that provides a voltage VIN 1241 to device 1240. Device 1240 may include a high side switch HS 1242 and a low side switch LS 1244. In some embodiments, device 1240 may provide a voltage to an inductance (e.g., inductor) 1246. In some embodiments, power converter system 1200 may include a capacitance 1243 across a load 1248. Inductance 1246 and capacitance 1243 may together define an LC filter that may output or regulate a voltage that may be provided to load 1248.

[0140] In some embodiments, device 1240 may include switches that need to be opened and closed at certain times. Thus, power converter system 1200 may implicitly require one or more controllers 1250 to provide control signals that open and close these switches. Controller 1250 may include an input / output (I / O) node 1254, an input voltage VIN 1252, and a compensation / control node COMP 1256. Controller 1250 may provide a control signal to control switches (e.g., high side switch HS 1242 or low side switch LS 1244) in device 1240. In other embodiments, for example at input / output node 1254, the controller may receive other inputs such as input current / output current sensing, output voltage, digital / analog communications, etc. Controller 1250 may control switches S1-S6 as illustrated in FIG. 11A using a sequence of states (e.g., as described in FIGs.11A-11C) to maintain a particular output voltage or current. Based on a current or voltage measurement, the sequence of states may be temporarily paused to maintain a particular state. For example, if a reverse current is measured to Vin 1241, A state causing one or more of the fly capacitors to discharge through inductor 1246 to load 1248 may be maintained such that the capacitors absorb the reverse current rather than Vin 1241.

[0141] Controller 1250 may receive a current measurement for the input voltage Vin 1241 and / or measurements of voltages across fly capacitors (e.g., capacitors C1 and C2 in FIGs. 11A-11C). The current measurement may be performed, for example, by measuring a voltage drop across a series resistance associated with Vin 1241 (not shown), or any other appropriate location that provides information about the current associated with Vin 1241. In someDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 embodiments, controller 1250 may further perform, or cause to be performed, the actions described herein for controlling aspects of power converters (e.g., actions described in FIGs. 18A-21).

[0142] FIG. 13 is a diagram illustrating a power converter system 1300 (e.g., power con- verter systems 600, 720, 800, 830, 870, 900, 1000, 1100, 1400, 1500) that may have a plurality of power converters (e.g., devices 1302, 1304, 1306) connected in parallel. As shown in FIG. 13, the power converter system 1300 may include power converters shown as device 1302, device 1304, and device 1306, each of which may be configured to convert an input voltage Vin from their respective input terminals 1301, 1307, 1313 that are coupled together via a common input node 1320, to an output voltage Vout at their respective second terminals 1303, 1309, and 1315 that are coupled together via a common output node 1323. Devices 1302, 1304, and 1306 may include a power conversion circuit 1318, 1320, and 1322 respectively, regulation circuits (e.g., shown by op-amps or transconductance amplifiers OP_11312, OP_21314, and OP_31316) respectively, electrically coupled to control / compensation terminals / nodes (pins) comp 1305, 1311, and 1317 (e.g., analog signal pins, op-amp pins, etc.). In some embodiments, op-amps, which output a voltage, may be used while in some embodiments transconductance amplifiers, which output a current, may be used. In some embodiments, a transconductance amplifier outputs a current which may be converted to a voltage, for example by charging a capacitor. Also shown in FIG.13 are an output capacitor Cout 1321 coupled between common output node (regulation node) 1323 and ground 1319 (GND). Devices 1302, 1304, and 1306 may include a buck converter, a boost converter, a charge pump circuit, or any other types of converter circuits. In various embodiments, power converter system 1300 may have different operating ranges for different applications, such as an energy management system in large- scale data centers, a vehicle electrical system in automotive applications, etc. Although FIG. 13 shows three devices coupled in parallel, in other embodiments there can be as many devices coupled in parallel as required and suitable per practical design considerations.

[0143] Devices 1302, 1304, and 1306 also include parallel control / compensation termi- nals / nodes (COMP) 1305, 1311, and 1317, respectively which are coupled together at a com- mon terminal / node 1325 and to ground (GND) 1319 (e.g., AC ground) via a circuit comprising a resistor Rcomp 1308 and a capacitor Ccomp 1310. In the existing systems, control / compen- sation terminals / nodes 1305, 1311, and 1317 may be the output of op-amps 1312, 1314, and 1316, respectively. In some embodiments, any of devices 1302, 1304, or 1306 may include aDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 compensation circuit, where the compensation circuit may include a resistor having a first ter- minal and a second terminal coupled in series with a capacitor having a first terminal and a second terminal. In some embodiments, the first terminal of the resistor may be coupled to the compensation / control terminal / node of the device, the second terminal of the resistor may be coupled to the first terminal of the capacitor, and the second terminal of the capacitor may be coupled to ground.

[0144] Common terminal / node 1325 may be used for regulation purposes in various ways. For example, it may be appreciated that system 1300 can be operated in a voltage mode control scheme or a current mode control scheme. Common terminal / node 1325 can be used for con- trolling duty ratio when the system 1100 is being operated in the voltage mode control scheme or for controlling peak current when the system is being operated in the current mode control scheme.

[0145] For example, in some embodiments, a voltage at the compensation / control termi- nal / node (e.g., compensation / control terminals / nodes 1305, 1311, or 1317) may control the power conversion blocks at power conversion circuits 1318, 1320, or 1322, which may adjust the output current at second terminals 1303, 1309, or 1315. In some embodiments, at an op- amp of a device (e.g., op-amp OP_11312, OP_21314, OP_31316), a difference between a reference voltage of its respective device (e.g., device 1302, device 1304, device 1306) and an output voltage of system 1300 may be calculated and adjusted by a feedback circuit imple- mented in system 1100 and the adjusted output voltage of the op-amp may be used to control power conversion circuits 1318, 1320, or 1322 of a device. Furthermore, resistor Rcomp 1308 and Ccomp 1310 may be specifically included to provide a compensation circuit for the output signal of the op amp OP_11312, OP_21314, OP_31316). In some embodiments, during a normal operation mode of the system, an op-amp (e.g., OP_1 1312, OP_2 1314, and OP_3 1316) of any of devices 1302, 1304, or 1306 may provide its respective device with regulated output current at its respective compensation / control terminal / node.

[0146] FIG.14 is a diagram illustrating a power converter 1400 (e.g., power converter sys- tems 600, 720, 800, 830, 870, 900, 1000, 1100, 1300, 1500) comprising a plurality of power converters (e.g., devices 1302, 1305, 1306) coupled in parallel and including a multi-purpose (e.g., dual, third, fourth, etc.) regulation and fault handling terminal, in accordance with some embodiments of the present disclosure. System 1400 is similar to system 1300 of FIG. 13 in many aspects and similarly named and numbered elements are coupled in a similar manner inDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 both systems. According to embodiments of this disclosure, system 1400 provides a novel method to use common regulation terminal / node 1325 to operate as a multi-purpose terminal, as a regulation (compensation) terminal / node and also as a fault handing terminal. More spe- cifically, in system 1400, during the normal operation common terminal / node 1325 can be used for providing the control for the regulation (e.g., as explained previously with respect to FIG. 13) and in the event of a fault detected by any of devices 1302, 1304, and 1306, common terminal / node 1325 can be used to take a fault protection measure such as shutting down system 1400. For example, a compensation / control terminal / node (e.g., compensation / control termi- nals / nodes 1305, 1311, or 1317) may be used for regulating its respective device and for fault handling communication between one or more devices.

[0147] As those skilled in the art may appreciate, a fault can occur in a power converter system for various reasons. One common reason can be a thermal failure (e.g., failure due to overheating) or an electrical failure (e.g., overcurrent due to overloading or overvoltage due to high voltage transients).

[0148] Although not shown in FIG. 14, system 1400 may have a controller which may control the operation of various devices in various operating regions. For example, a controller (e.g., controller 1250 of FIG. 12) may control any device (e.g., devices 1302, 1304, 1306) to operate in a normal operating region (e.g., normal operation region 1706 of FIG. 17), a fault region (e.g., fault region 1702 of FIG.17), or a wait region (e.g., wait region 1704 of FIG.17).

[0149] System 1400 may include additional circuitry in order to achieve the fault handing and communication feature, which will explained in more detail below. In some embodiments, each device of devices 1302, 1304, and 1306 may include a voltage level detection circuit (not shown), a pull-down switch (e.g., a transistor), and a supplemental regulation circuit for fault handling and communication. For example, device 1302 is shown to include a transistorized pull-down switch M11402 and a DC voltage source 1408 with a resistor R11406 in series with it configured to work as a supplemental regulation circuit.

[0150] The supplemental regulation circuit (DC voltage source 1408 with a resistor R1 1406) may generate a voltage to regulate one or more devices when other forces (e.g., a pull- down switch or op-amp voltage outputs) are absent. For example, a supplemental regulation circuit may maintain a very low voltage upon receiving an indication that some other device has detected a fault. As such, the device that has detected an actual fault may generate a voltageDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 that may be substantially zero (e.g., owing to pull-down switch M11402), whereas the other devices (which are not at fault) can maintain a low voltage at their respective compensa- tion / control terminals. In some embodiments, when a fault associated with a device is detected, an op-amp of any of devices 1302, 1304, or 1306 may be shut down via a pull-down switch (e.g., MA 1402, M2 1412, M3 1422) to make the regulated output current of one or more devices (without fault) substantially zero. It should be understood that a “low” voltage is not equivalent to a “weak voltage.” For example, 0 V may be a “low” voltage that has a “strong” (i.e., not weak) signal.

[0151] Pull-down switch M11402 may be coupled between regulation terminal / node 1305 and ground 1319. By virtue of its coupling, when activated pull-down switch M11402 may couple regulation terminal / node 1305 to ground 1319. It may be appreciated that in other em- bodiments, pull-down switch M11402 may be coupled differently instead of as a direct pull- down switch to ground. Any common methods in the art including various transistorized cir- cuits may be used to implement a configuration equivalent to pull-down switch M11402. Pull- down switch M11402 may be internal or external to device 1302. In other embodiments, one or more devices may include pull-down switches for other devices. In general, the pulldown switches can be configured in any arrangement as suitable per system design considerations.

[0152] Device 1302 may also include a voltage detection circuit and other circuitry (not shown) to work in conjunction with pull-down switch M11402 and the supplemental regula- tion circuit (e.g., DC voltage source 1408 and resistor R11406). Devices 1304 and 1306 may include similar circuitry. Particularly, device 1304 may include a pull-down switch M21412, comparator 1414, and a supplemental regulation circuit (e.g., DC power source 1418 and re- sistor R21416). Similarly, device 1306 is shown to include a pull-down switch M31422, a comparator 1424, and a supplemental regulation circuit (e.g., DC power source 1428 and re- sistor R31426).

[0153] System 1400 may be configured to work in various modes of operation in response to the voltage (Vcomp) at common terminal / node 1325. In a normal mode (e.g., without any fault), system 1400 may operate to provide a regulated DC voltage at regulation node 1323. At this time, the output may be provided by all devices (e.g., power converters) 1302, 1304, and 1306 that are coupled in parallel and common terminal / node 1325 may provide control for regulating regulation node 1323 as explained with respect to FIG.13.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0154] If any device is at fault, then system 1400 may operate in a fault communication and handling mode. In some embodiments, each device is configured in such a way that if there is a fault condition, then the op-amp (e.g., op-amp OP_11312, op-amp OP_21314, op-amp OP_31316) may stop driving the compensation / control node such that the compensation / con- trol node of that device may drop below a regulation threshold, which may be sensed by the voltage level detection circuit of that corresponding device. The voltage level detection circuit may then turn on the corresponding pull-down switch. When the pulldown switch is turned on, the corresponding comp terminal is coupled to ground, bringing the compensation / control ter- minal / node voltage Vcomp below a predefined threshold value Vfault. By virtue of the parallel configuration of the all the devices, when the compensation / control terminal / node voltage of one device falls below predefined threshold value Vfault, it may indicate to the other devices that one of the devices is at fault. The other devices may also then enter fault-protection mode. In other words, if one device is at fault then the fault may be communicated to the other devices.

[0155] When any other device receives an indication from the voltage level at the compen- sation / control node that there is a fault in the system, device(s) may stop driving the compen- sation / control node voltage and stop regulating the output current of the device(s). The supple- mental regulation circuit (DC voltage source and the resistor R11406, R21416, or R31426) may generate a voltage to regulate one or more devices when other forces (e.g., a pull-down switch or op-amp voltage outputs) are absent. For example, a supplemental regulation circuit may maintain a very low voltage. As such, the compensation / control terminal / node voltage of the device that has detected an actual fault may be substantially zero (owing to pull-down switch M1), whereas the other devices (which are not at fault) can maintain the low voltage at their respective compensation / control terminals / nodes. In some embodiments, a typical value for the weak voltage can be 0.5 V.

[0156] It may be appreciated that during normal operation, as explained with respect to FIG.13, the compensation / control terminal / node voltage (Vcomp) of a device may be substan- tially equal to the voltage generated by the circuit (resistor Rcomp 1308 and capacitor Ccomp 1310) to provide regulation of output voltage Vout. However, when the device detects a fault, the compensation / control terminal / node voltage of that device may be substantially equal to zero due to its coupling to ground 1319 caused by the turning on of pull-down switch M1.

[0157] FIG.15 is a diagram 1500 illustrating an exemplary fault handling circuit included in device 1304 of systems 1300 and 1400 of FIGs.13-14, in accordance with embodiments ofDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 the present disclosure. As explained earlier, if device 1304 is at fault, then the voltage detection circuit included in device 1304 may activate or turn on pull-down switch M21412 to make the compensation / control terminal / node voltage Vcomp lower than a predefined voltage Vfault. Comparator 1414 may detect the compensation / control terminal / node voltage Vcomp is lower than predefined voltage Vfault (e.g., Vcomp < Vfault), which may signal to the other devices that one or more devices are at fault. In other words, the fault is broadcast to the other devices. The other devices may then proceed to taking fault protection measures, such as not providing voltage regulation. When device 104 is not in a voltage regulation mode, it may use the sup- plemental regulation circuit to maintain the value of compensation / control terminal / node volt- age Vcomp to be higher than a fault threshold voltage Vfault and lower than a minimum normal operating voltage V_op(min). The force of the supplemental regulation circuit is weaker than any fault signaling a pull-down of the compensation / control terminal / node.

[0158] In other words, a fault condition generally has a higher priority over any other con- dition. When the fault disappears, the compensation / control terminal / node voltage Vcomp can gradually begin to rise, thereby indicating that the fault has disappeared. Once the fault disap- pears, the compensation / control terminal / node voltage Vcomp may gradually rise above pre- defined threshold value Vfault and eventually above minimum normal operating voltage V_op(min) after a predefined wait time. Once the compensation / control terminal / node voltage rises above minimum normal operating voltage V_op(min), the normal operation of the devices can resume. It may be appreciated that the predefined wait time is chosen per practical design considerations. In some embodiments a typical value for the predefined wait time can be 1 millisecond (ms). In some embodiments, the value for predefined threshold value Vfault may be 0.25 V. In some embodiments, the value for minimum normal operating voltage V_op(min) may be 1 V. For example, compensation / control terminal / node voltage Vcomp may be less than 0.25 V, where weak voltage Vweak may pull compensation / control terminal / node Vcomp to above 0.25 V (e.g., to 0.5 V) and normal operation may begin around 1 V

[0159] FIG.16 is a diagram illustrating a logic circuit 1600 of an example power converter system (e.g., power converter systems 600, 720, 800, 830, 870, 900, 1000, 1100, 1300, 1400, 1500) that may have a power converter (e.g., devices 1302, 1304, 1306, 1240). FIG.16 shows an exemplary fault detection logic circuit 1600, similar to embodiments disclosed in U.S. Pa- tent No.8,619,445 B1, which is incorporated by reference in its entirety for all purposes. Fault detection circuit 1600 may be used in connection with the fault handling circuit 1500 such thatDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 if there is no fault, Vcomp is not allowed to be driven into fault region 1702 by the power converter.

[0160] For example, when a device corresponding to logic circuit has a fault, fault detec- tion unit 1616 of logic circuit 1600 may trigger pull-down switch M11622 (e.g., pull-down switches 1402, 1412, 1422) such that the compensation / control node voltage Vcomp1624 of the device may decrease to below a threshold voltage VTHR1614 (e.g., minimum normal operating V_op(min) 2410). Other devices may see, via a comparator 1610, that some device has pulled down its compensation / control node voltage Vcomp1612 to below threshold voltage VTHR1614. In some embodiments, other devices, which may not be at fault, may activate their respective pull-down switches to decrease their respective compensation / control node voltages to below a threshold voltage. When the pull-down switch of a device is activated, regulation of the cor- responding integrated circuit may stop and the shut-down of circuits (e.g., compensation com- parator) may commence.

[0161] In some embodiments, when the devices, including the faulted device, have acti- vated their respective pull-down switch such that their respective compensation / control node voltage decreases below the threshold voltage, timer 1632 may be activated. When the time of timer 1632 has elapsed, the device may determine whether a fault in the device still exists. If the device does not have a fault, then the device may raise the compensation / control node volt- age Vcomp1624 (e.g., raise the voltage to wait region). In some embodiments, timer 1632 may reset latch 1650.

[0162] In some embodiments, timer 1634 may be activated when the compensation / control node voltage Vcomp1612 of the device decreases to below the threshold voltage VTHR1614. When the time of timer 1634 has elapsed, the system (e.g., power converter systems 600, 720, 800, 830, 870, 900, 1000, 1100, 1300, 1400, 1500) may determine whether any faults exist in any of the devices and restart the circuitry (e.g., control circuitry 1636) of the system to enable regulation of the system. In some embodiments, the enable signal UEN 1638 may refer to a voltage, a current, etc. In one example, the enable signal UEN 1638 may be a part of the circuitry that enables / disables the supply to transconductance amplifier 1314 in Fig.5.

[0163] FIG. 17 is a diagram illustrating COMP terminal voltage levels related to various operating regions for devices included in systems described in FIGs. 1-16 and 18-21 for fault handling of power converters, in accordance with embodiments for the present disclosure. AsDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 shown, the devices described herein can operate in three different regions with regard to COMP / Fault voltage: a fault region 1702, a wait region 1704, and a normal operation region 1706. Fault region 1702 may have an upper boundary predefined threshold value Vfault 1708. Wait region 1704 may have a lower boundary predefined threshold value Vfault 1708 and an upper boundary minimum normal operating voltage V_op(min) 1710. Normal operation region 1706 may have a lower boundary minimum normal operating V_op(min) 1710.

[0164] Referring back to FIG.14 and FIG.15, comparator 1414 (and corresponding com- parators in other devices) may be used to detect various operating regions of device 1304 based on the voltage of second terminal 1309. Comparator 1413 may further provide a digital signal to the controller (not shown) to perform operation related tasks for device 1304.

[0165] The boundary values may represent compensation / control terminal / node voltage values which may signal a fault condition, a wait condition, or a normal operation condition. It may be appreciated from FIG. 17 that for any device, when the compensation / control termi- nal / node voltage Vcomp falls below predefined threshold value Vfault 1708, the device enters the fault region and a fault may be signaled to other devices. Once the fault has subsided, the device can enter wait region 1704. At this time all the other devices can also stay in the wait region for a predefined time, after which the device can enter back to normal operation region 1706. In some embodiments, the faulting device(s) may maintain the compensation / control terminal / node voltage Vcomp in fault region 1702 for a predetermined duration of time. The faulting device(s) may release the fault, allowing the compensation / control terminal / node volt- age Vcomp to rise to wait region 1704, signaling that the compensation / control terminal / node voltage Vcomp may rise to normal operation region 1706 without any additional waiting pe- riod.

[0166] It may be appreciated that wait region 1704 is used for hand-shaking among various devices. During the predefined wait time, the controller (e.g., control circuit, control circuitry, etc.) (not shown) can confirm that the fault has disappeared from all the devices. Additionally, it can be used for synchronizing the start-up operation of all the devices. In other embodiments, the devices can come out of wait region 1704 sequentially based on a predefined priority scheme. In one such priority scheme, the master device can come out of the wait region first and the other devices can follow the master device. In some embodiments, one or more devices (e.g., devices 1302 or 1306) may control the compensation / control terminal / node voltage Vcomp of one or more other devices (e.g., device 1304) such that the compensation / controlDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 terminal / node voltage Vcomp of the one or more other devices rise into normal operation re- gion 1706. Devices may be configured such that Vcomp is held at a voltage above the fault region 1702 even when regulation would normally cause Vcomp to fall below that level to avoid inadvertently triggering a fault state.

[0167] Various types of detecting circuits or sensors may be applied for fault detection, consistent with this disclosure. For example, a temperature sensor may be used to monitor the temperature of the power converter. In some embodiments, the detecting circuits may further be configured to detect the fault level and whether the fault is cleared. The detecting circuit may output a signal corresponding to the fault state to trigger operations. For example, the detecting circuit may provide a signal that limits the fault condition while maintaining opera- tion and regulation of the second terminal (e.g., second terminals 1303, 1309, or 1315). In some embodiments, the detecting circuits may output corresponding signal(s) to automatically disa- ble the regulation of the second terminal and latch-off, to perform auto restart / reset, etc. For example, these operations may be set in response to the fault conditions by one or more digital bits in the fault signals. As described herein.

[0168] FIGs. 18A-18C illustrate example waveforms representing the reverse current blocking, according to some aspects of the disclosure. The top chart of FIG. 18A illustrates voltage on the Y axis in some units, and time on the X axis in some units. Input voltage 1802a may be an input voltage to a power converter (e.g., Vin 1320) and capacitor voltage may be the voltage across a fly capacitor (e.g., capacitor C1 in FIG. 11A). The bottom chart of FIG. 18A illustrates current on the Y axis and time on the X axis aligned with the time of the top chart. Input current 1806a may be the current from a voltage source of an input voltage (e.g., the current from Vin 1320). Zero current 1806 illustrates where no current is flowing from Vin. Positive current represents current from Vin to Vout, and negative current represents current from Vout to Vin. As illustrated in the bottom chart, input current 1806a may be relatively steady, until some event causes the input current 1806a to drop below zero current 1806, mean- ing a reverse current event occurs. As illustrated, this reverse current event may correct as the capacitor continues switching states (e.g., as described in FIGs.11A-11C).

[0169] One event which may cause input current to 1806a to go below zero current 1806 is a sudden drop in input voltage 1802a as illustrated. This reverse current may correct itself through the normal operation of switching the fly capacitor(s) through the different charg- ing / discharging states, and capacitor voltage 1804a may discharge to a new voltage and theDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 input current 1806a may rise back to some positive level. Capacitor voltage may be set to a ratio of input voltage 1802a (e.g., one third of input voltage 1802a), and a drop in input voltage 1802a will cause capacitor voltage 1804a to correct to one third of the new lower input voltage 1802a level. Another even which may cause input current 1806a to go below zero current is a sudden rise in output voltage due to some change in a load (e.g., load 1248). For example, a load may be a charging battery, and that battery may also be connected to a device that is actively in use causing a drain on the battery. If the device suddenly stops pulling current from the battery (e.g., it goes into a low power mode or stops performing some function), the voltage at the battery (Vout) may rise above input voltage 1802a (not shown).

[0170] FIG. 18B illustrates voltage and current similar to FIG. 18A with input voltage 1802b, fly capacitor voltage 1804b, and input current 1806b. As illustrated in FIG. 18B, cor- rective action may be taken by a system to block the reverse current. FIG.18B illustrates input current 1806b dropping in response to a drop in input voltage 1802b but reaching a minimum of zero current 1806. This may be accomplished by stopping the normal cycling between ca- pacitor states and maintaining a capacitor discharge state, which also effectively disconnects input voltage from the load. Capacitor voltage 1804b may discharge more slowly to its new corresponding level (e.g., one third of input voltage 1802b) since the reverse current is blocked (e.g., by keeping switch S5 as shown in FIG.11A open). The current necessary for the load on Vout is supplied temporarily only by the discharging capacitor(s), until the capacitor(s) dis- charges to the appropriate level, and the charging / discharging states resume causing input cur- rent 1806b to return to a positive level.

[0171] FIG.18C illustrates voltage and current similar to FIGs.18A-18B, with the addition of a second capacitor voltage. Specifically, FIG.18C illustrates input voltage 1802c, capacitor voltage 1804c (e.g., the voltage across C1 in FIG. 11A), capacitor voltage 1805c (e.g., the voltage across C2 in FIG.11A) and input current 1806c. Input current 1806c is again illustrated as remaining non-negative despite a drop in input voltage 1802c which may cause a reverse current to occur if not corrected. First, a capacitor state is maintained that discharges capacitor voltage 1804c (i.e., input voltage is disconnected form the load, and all current for the load is provided by the discharging of the first capacitor until capacitor voltage 1804c reaches the appropriate level with respect to input voltage 1802c). Once capacitor voltage 1804c reaches the appropriate level, rather than maintaining a single state, the first capacitor may cycle be- tween charging / discharging states to maintain the correct voltage level but keep the secondDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 capacitor discharging until capacitor voltage 1805c reaches its appropriate level (e.g., two thirds input voltage 1802c). Once both capacitors (or more for higher order multi-level power converters) have discharged to their respective desired levels, normal operation may return, cycling through the states as described in FIGs.11A-11C, causing input current 1806c to return to some positive level as illustrated.

[0172] FIG. 19 is a timing diagram 1900 of a reverse current blocking method, according to some aspects of the disclosure. The timing diagram is for an exemplary power converter with a single fly capacitor, but similar methods may be performed with multiple capacitors as described in FIG. 18C. A power converter may have two states for a fly capacitor determined by switch states, a charge state 1902, and a discharge state 1904, generally as described in FIGs. 11A-11C. In some embodiments, each state is maintained, during normal operation, for a predetermined time 1906. By cycling between charging and discharging states, the voltage across the fly capacitor is maintained at some ratio of the input voltage.

[0173] As illustrated, the state may alternate back and forth between charge state 1902 and discharge state 1904 until some event occurs. The illustrated event is Vin drop 1908, which may be determined by a controller (e.g., controller 1250) by measuring Vin. In some embodi- ments, a measured reverse current may also trigger the change, which may be measured by a controller (e.g., controller 1250). Based on event 1908, the system stops alternating between states, and maintains the discharge state 1904. After some time (e.g., until the capacitor has discharged to the predetermined ratio of input voltage), the normal cycle of states may resume. In some embodiments, a second fly capacitor may be present. In that case, the first capacitor may be maintained in a discharging state in response to event 1908 until the first capacitor has discharged sufficiently (e.g., state 2 in FIG. 11B). Then the first capacitor may cycle between charging and discharging while the second capacitor discharges (e.g., states 1 and 2 in FIG. 11B). Once the second capacitor has discharged to the predetermined level, normal operation may resume. In some embodiments, while the first capacitor is maintained in a discharge state, the second capacitor is disconnected such that it is neither charging nor discharging (e.g., state 2 in FIG.11B).

[0174] FIG. 20 is a flowchart illustrating an exemplary method 2000 of reverse current blocking, in accordance with embodiments of the present disclosure. It is understood that ad- ditional operations may be performed before, during, and / or after method 2000 depicted in FIG.20, and that some other processes may only be briefly described herein. Method 2000 canDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 be performed by a system including circuits and components in the power converter, e.g., de- vices 1302, 1304, or 1306 illustrated in any of FIGs.13-15, but method 2000 is not limited to being performed using those specific systems.

[0175] In some embodiments, the system may include an integrated circuit and / or discrete components. In some embodiments, the system may be a DC-DC power converter (e.g., a buck converter, a boost converter, or a charge pump converter). A single power converter may per- form the steps of method 2000 alone. A single power converter may perform the steps of method 2000 while connected in parallel with one or more additional multiple power convert- ers (e.g., by connecting Vout and COMP of each parallel device).

[0176] In step 2001, a system may control a state of a switching network (e.g., switches S1-S6 in FIG.11A) coupled to one or more capacitors (e.g., capacitors C1 and C2 in FIG.11A) to cycle between a set of states associated with different capacitor arrangements of the one or more capacitors, maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage.

[0177] Different methods may be used by the system to determine a current to a source of the first voltage may occur. In some embodiments, the determination may be based on the first voltage decreasing more than a threshold amount. As discussed in FIGs. 18A-18C, a drop in the first voltage (e.g., an input voltage) may result in a reverse current to the source of the input current. If the capacitor switching network state is such that the input voltage is not connected to the output (e.g., in a capacitor discharge state), no reverse current may actually occur, but based on the input voltage dropping, the system may preemptively maintain a particular state as described in step 2001. the state switching procedure to maintain the discharge state until the capacitor reaches the correct level, since the current going to the source of the first voltage may otherwise occur. In some embodiments, the determination may be based on a current measurement of current into the source of the input voltage. In some embodiments, the deter- mination is based on the current exceeding a predetermined threshold (e.g., any current towards the source of the first voltage, or some minimum amount i.e., a reverse current threshold). Reverse current to the source of the first voltage may occur, for example, in response to the first voltage decreasing suddenly, and the system may respond by changing to the discharge state and maintaining that state until the capacitor reaches the correct voltage. In some embod- iments, as described in FIG.21, the method used by the system to make the determination may be dependent on the current state of the switching network.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0178] In step 2002, the system may maintain a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current to a source of the first voltage may occur. In some embodiments, the particular state forms a capac- itor arrangement that disconnects the one or more capacitors from the source of the first volt- age. In some embodiments, the particular state forms a capacitor arrangement that discharges one or more of the one or more capacitors to an output load via an inductor (e.g., inductor L in FIGs.11A-11C). For example, the method 2000 may further comprise measuring a third volt- age across a first capacitor of the one or more capacitors, and maintaining the particular state until the third voltage reaches a first threshold value.

[0179] When more than one capacitor is in the one or more capacitors, a sequence of states may be maintained while discharging the capacitors in sequence as described in FIG. 18C. In some embodiments, after the first capacitor has discharged sufficiently (e.g., it has reached one third of the first voltage), the particular state may be a set of states that alternate charging and discharging the first capacitor but always discharging the second capacitor until the second capacitor has reached its target voltage (e.g., two thirds of the first voltage). For example, method 2000 may further comprise measuring a fourth voltage across a second capacitor of the one or more capacitors, and controlling the state of the switching network to cycle between a subset of the set of states until the fourth voltage reaches a second threshold value.

[0180] FIG. 21 is a flowchart illustrating an exemplary method 2100 of reverse current blocking, in accordance with embodiments of the present disclosure. It is understood that ad- ditional operations may be performed before, during, and / or after method 2100 depicted in FIG.21, and that some other processes may only be briefly described herein. Method 2100 can be performed by a system including circuits and components in the power converter, e.g., de- vices 1302, 1304, or 1306 illustrated in any of FIGs.13-15, but method 2100 is not limited to being performed using those specific systems.

[0181] In some embodiments, the system may include an integrated circuit and / or discrete components. In some embodiments, the system may be a DC-DC power converter (e.g., a buck converter, a boost converter, or a charge pump converter). A single power converter may per- form the steps of method 2100 alone. A single power converter may perform the steps of method 2100 while connected in parallel with one or more additional multiple power convert- ers (e.g., by connecting Vout and COMP of each parallel device).Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0182] In step 2101, a system may control a state of a switching network (e.g., switches S1-S6 in FIG.11A) coupled to one or more capacitors (e.g., capacitors C1 and C2 in FIG.11A) to cycle between a set of states associated with different capacitor arrangements of the one or more capacitors, maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage. In some embodiments, the determination may be based on the first voltage decreasing more than a threshold amount. As discussed in FIGs.18A-18C, a drop in the first voltage (e.g., an input voltage) may result in a reverse current to the source of the input current. If the capacitor switching network state is such that the input voltage is not connected to the output (e.g., in a capacitor discharge state), no reverse current may actually occur, but based on the input voltage dropping, the system may preemptively modify the state switching procedure to maintain the discharge state until the capacitor reaches the correct level, since the current going to the source of the first voltage may otherwise occur. In some embodiments, the determination may be based on a current measurement of current into the source of the input voltage. In some embodiments, the determination is based on the current exceeding a predetermined threshold (e.g., any current towards the source of the first voltage, or some minimum amount i.e., a reverse current threshold). Reverse current to the source of the first voltage may occur, for example, in response to the first voltage decreasing suddenly, and the system may respond by changing to the discharge state and maintaining that state until the capacitor reaches the correct voltage.

[0183] In decision 2102, the system may determine if the one or more capacitors are in a charging state (i.e., the capacitor is connected to the first voltage). If the one or more capacitors is in a charging state, method 2103 proceeds to step 2103, otherwise method 2104 proceeds to step 2104.

[0184] In step 2103, the system may maintain a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current measurement exceeds a reverse current threshold.

[0185] In step 2104, the system may maintain a particular state of the switching network for longer than the predefined amount of time in response to a determination that the first volt- age decreased more than a threshold amount. In other words, the system may use a different method to determine to maintain the particular state depending on the state of the switching network causing the one or more capacitors to be charging or discharging. If a capacitor is in a charging state, then it may be connected to the first voltage source, and a condition that wouldDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 cause a reverse current to the first voltage may be measured directly by measuring the current. If a capacitor is in a discharging state, it is not connected to the input voltage, so a condition that would cause a reverse current to the first voltage may not occur but may be anticipated by monitoring the first voltage.

[0186] Further aspects of the present disclosure include the following:

[0187] Aspect 1 includes an integrated circuit comprising: a switching network that when connected to one or more capacitors causes said switching network to form a capacitor arrange- ment dependent on a state of the switching network; and a controller configured to: control the state of the switching network to cycle between a set of states maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage; and maintain a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current flow to a source of the first voltage may occur.

[0188] Aspect 2 includes the integrated circuit of aspect 1, wherein the determination is based on at least one of: the first voltage decreasing more than a threshold amount; or a current measurement exceeding a reverse current threshold.

[0189] Aspect 3 includes the integrated circuit of any of aspects 1-2, wherein the determi- nation is based on the first voltage decreasing more than a threshold amount when the one or more capacitors are in a discharging state; and / or wherein the determination is based on a cur- rent measurement exceeding a reverse current threshold when the one or more capacitors are in a charging state.

[0190] Aspect 4 includes the integrated circuit of any of aspects 1-3, wherein the particular state forms a capacitor arrangement that disconnects the one or more capacitors from a source of the first voltage.

[0191] Aspect 5 includes a system comprising the integrated circuit of any of aspects 1-4, wherein the system further comprises: the one or more capacitors; an inductor; and wherein the particular state forms a capacitor arrangement that discharges one or more of the one or more capacitors to an output load via the inductor.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0192] Aspect 6 includes the integrated circuit of any of aspects 1-5, wherein the controller is further configured to: measure a third voltage across a first capacitor of the one or more capacitors; and maintain the particular state until the third voltage reaches a first threshold value.

[0193] Aspect 7 includes the integrated circuit of aspect 6, wherein the controller is further configured to: measure a fourth voltage across a second capacitor of the one or more capacitors; and control the state of the switching network to cycle between a subset of the set of states until the fourth voltage reaches a second threshold value.

[0194] Aspect 8 includes a method, comprising: controlling a state of a switching network coupled to one or more capacitors to cycle between a set of states associated with different capacitor arrangements of the one or more capacitors, maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage; and maintaining a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current to a source of the first voltage may occur.

[0195] Aspect 9 includes the method of aspect 8, wherein the determination is based on at least one of: the first voltage decreasing more than a threshold amount; or a current measure- ment exceeding a reverse current threshold.

[0196] Aspect 10 includes the method of any of aspects 8-9, wherein the determination is based on the first voltage decreasing more than a threshold amount when the one or more ca- pacitors are in a discharging state; and wherein the determination is based on a current meas- urement exceeding a reverse current threshold when the one or more capacitors are in a charg- ing state.

[0197] Aspect 11 includes the method of any of aspects 8-10, wherein the particular state forms a capacitor arrangement that disconnects the one or more capacitors from a source of the first voltage.

[0198] Aspect 12 includes the method of any of aspects 8-11, wherein the particular state forms a capacitor arrangement that discharges one or more of the one or more capacitors to an output load via an inductor.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0199] Aspect 13 includes the method of any of aspects 8-12, further comprising: measur- ing a third voltage across a first capacitor of the one or more capacitors; and maintaining the particular state until the third voltage reaches a first threshold value.

[0200] Aspect 14 includes the method of aspect 13, further comprising: measuring a fourth voltage across a second capacitor of the one or more capacitors; and controlling the state of the switching network to cycle between a subset of the set of states until the fourth voltage reaches a second threshold value.

[0201] Aspect 15 includes a circuit for converting a first voltage to a second voltage, com- prising: one or more capacitors; an inductor; a switching network couplable to the one or more capacitors and configured to form a capacitor arrangement dependent on a state of the switch- ing network; and a controller configured to: control the state of the switching network to cycle between a set of states maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage coupled to the inductor; and main- tain a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current to a source of the first voltage may occur.

[0202] Aspect 16 includes the circuit of aspect 15, wherein the determination is based on at least one of: the first voltage decreasing more than a threshold amount; or a current meas- urement exceeding a reverse current threshold.

[0203] Aspect 17 includes the circuit of any of aspects 15-16, wherein the particular state forms a capacitor arrangement that disconnects the one or more capacitors from a source of the first voltage.

[0204] Aspect 18 includes the circuit of any of aspects 15-17, wherein the particular state forms a capacitor arrangement that discharges one or more of the one or more capacitors to an output load.

[0205] Aspect 19 includes the circuit of any of aspects 15-18, wherein the controller is further configured to: measure a third voltage across a first capacitor of the one or more capac- itors; and maintain the particular state until the third voltage reaches a first threshold value.

[0206] Aspect 20 includes the circuit of aspect 19, wherein the controller is further config- ured to: measure a fourth voltage across a second capacitor of the one or more capacitors; andDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 control the state of the switching network to cycle between a subset of the set of states until the fourth voltage reaches a second threshold value.

[0207] General Benefits and Advantages of Multi-Level Power Converters

[0208] Embodiments of the current invention improve the power density and / or power efficiency of incorporating circuits and circuit modules or blocks. As a person of ordinary skill in the art should understand, a system architecture is beneficially impacted utilizing em- bodiments of the current invention in critical ways, including lower power and / or longer bat- tery life. The current invention therefore specifically encompasses system-level embodiments that are creatively enabled by inclusion in a large system design and application.

[0209] More particularly, multi-level power converters provide or enable numerous bene- fits and advantages, including:

[0210] – adaptability to applications in which input and / or output voltages may have a wide dynamic-range (e.g., varying battery input voltage levels, varying output voltages);

[0211] – efficiency improvements on the run-time of devices operating on portable elec- trical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0212] – efficiency improvements where efficiency is important for thermal management, particularly to protect other components (e.g., displays, nearby ICs) from excessive heat;

[0213] – enabling design optimizations for power efficiency, power density, and form- factor of the power converter – for example, smaller-size multi-level power converters may allow placing power converters in close proximity to loads, thus increasing efficiency, and / or to lower an overall bill of materials;

[0214] – the ability to take advantage of the performance of smaller, low voltage transis- tors;

[0215] – adaptability to applications in which power sources can vary widely, such as batteries, other power converters, generators or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, power-over Ethernet, etc.);Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0216] – adaptability to applications in which loads may vary widely, such as ICs in gen- eral (including microprocessors and memory ICs), electrical motors and actuators, transduc- ers, sensors, and displays (e.g., LCDs and LEDs of all types);

[0217] – the ability to be implemented in a number of IC technologies (e.g., MOSFETs, GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

[0218] The advantages and benefits of multi-level power converters enable usage in a wide array of applications. For example, applications of multi-level power converters include portable and mobile computing and / or communication products and components (e.g., note- book computers, ultra-book computers, tablet devices, and cell phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z- Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for battery-backup systems and / or power conversion for processing systems and / or electronic / op- tical networking systems), internet-of-things (IOT) devices (e.g., smart switches and lights, safety sensors, and security cameras), household appliances and electronics (e.g., set-top boxes, battery-operated vacuum cleaners, appliances with built-in radio transceivers such as washers, dryers, and refrigerators), AC / DC power converters, electric vehicles of all types (e.g., for drive trains, control systems, and / or infotainment systems), and other devices and systems that utilize portable electricity generating sources and / or require power conversion.

[0219] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature ampli- tude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Mul- tiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.11a, b, g, ac, ax), as well as other radio communication standards and protocols.

[0220] Programmable Embodiments

[0221] Some or all aspects of the invention, particularly the Multi-Level Switch State Se- lector 1014 of FIG.10, may be implemented in hardware or software, or a combination of both (e.g., programmable logic arrays). Unless otherwise specified, the algorithms includedDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 as part of the invention are not inherently related to any particular computer or other appa- ratus. In particular, various general purpose computing machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to use a special purpose computer or special-purpose hardware (such as integrated circuits) to perform partic- ular functions. Thus, embodiments of the invention may be implemented in one or more com- puter programs (i.e., a set of instructions or codes) executing on one or more programmed or programmable computer systems (which may be of various architectures, such as distributed, client / server, or grid) each comprising at least one processor, at least one data storage system (which may include volatile and non-volatile memory and / or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code may be applied to input data to perform the functions described in this disclosure and generate output information. The output information may be applied to one or more output devices in known fashion.

[0222] Each such computer program may be implemented in any desired computer lan- guage (including machine, assembly, or high-level procedural, logical, or object-oriented pro- gramming languages) to communicate with a computer system, and may be implemented in a distributed manner in which different parts of the computation specified by the software are performed by different computers or processors. In any case, the computer language may be a compiled or interpreted language. Computer programs implementing some or all of the in- vention may form one or more modules of a larger program or system of programs. Some or all of the elements of the computer program can be implemented as data structures stored in a computer readable medium or other organized data conforming to a data model stored in a data repository.

[0223] Each such computer program may be stored on or downloaded to (for example, by being encoded in a propagated signal and delivered over a communication medium such as a network) a tangible, non-transitory storage media or device (e.g., solid state memory media or devices, or magnetic or optical media) for a period of time (e.g., the time between refresh periods of a dynamic memory device, such as a dynamic RAM, or semi-permanently or per- manently), the storage media or device being readable by a general or special purpose pro- grammable computer or processor for configuring and operating the computer or processor when the storage media or device is read by the computer or processor to perform the proce- dures described above. The inventive system may also be considered to be implemented as aDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer or processor to operate in a spe- cific or predefined manner to perform the functions described in this disclosure.

[0224] Fabrication Technologies & Options

[0225] In various embodiments of multi-level power converters, it may be beneficial to use specific types of capacitors, particularly for the fly capacitors. For example, it is generally useful for such capacitors to have low equivalent series resistance (ESR), low DC bias degra- dation, high capacitance, and small volume. Low ESR is especially important for multi-level power converters that incorporate additional switches and fly capacitors to increase the num- ber of voltage levels. Selection of a particular capacitor should be made after consideration of specifications for power level, efficiency, size, etc. Various types of capacitor technologies may be used, including ceramic (including multi-layer ceramic capacitors), electrolytic ca- pacitors, film capacitors (including power film capacitors), and IC-based capacitors. Capaci- tor dielectrics may vary as needed for particular applications, and may include dielectrics that are paraelectric, such as silicon dioxide (SiO2), hafnium dioxide (HFO2), or aluminum oxide Al2O3. In addition, multi-level power converter designs may beneficially utilize intrinsic par- asitic capacitances (e.g., intrinsic to the power FETs) in conjunction with or in lieu of de- signed capacitors to reduce circuit size and / or increase circuit performance. Selection of ca- pacitors for multi-level power converters may also take into account such factors as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitor temperature coefficients (minimum and maximum temperature operating limits, and capaci- tance variation with temperature).

[0226] Similarly, in various embodiments of multi-level power converters, it may be ben- eficial to use specific types of inductors. For example, it is generally useful for the inductors to have low DC equivalent resistance, high inductance, and small volume.

[0227] The controller(s) used to control startup and operation of a multi-level power con- verter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register-transfer level (RTL) circuitry, and / or combinatorial logic.

[0228] The term “MOSFET”, as used in this disclosure, includes any field effect transis- tor (FET) having an insulated gate whose voltage determines the conductivity of the transis-Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2 tor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semicon- ductor structure. The terms “metal” or “metal-like” include at least one electrically conduc- tive material (such as aluminum, copper, or other metal, or highly doped polysilicon, gra- phene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0229] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of os- cillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequen- cies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0230] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and direc- tions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are rel- ative to the example drawings, and not necessarily absolute orientations or directions.

[0231] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particu- larly useful when fabricated using an SOI or SOS based process, or when fabricated with pro- cesses having similar characteristics. Fabrication in CMOS using SOI or SOS processes ena- bles circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio fre- quencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2

[0232] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities re- versed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the dis- closed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0233] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC pack- ages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive compo- nents, and possibly additional ICs) into one package. The ICs and / or modules are then typi- cally combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0234] A number of embodiments of the disclosure have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0235] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the disclosure, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the disclosure includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that theDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2 CLAIMS WHAT IS CLAIMED IS:

1. An integrated circuit comprising: a switching network that when connected to one or more capacitors causes said switching network to form a capacitor arrangement dependent on a state of the switching net- work; and a controller configured to: control the state of the switching network to cycle between a set of states maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage; and maintain a particular state of the switching network for longer than the prede- fined amount of time in response to a determination that a current flow to a source of the first voltage may occur.

2. The integrated circuit of claim 1, wherein the determination is based on at least one of: the first voltage decreasing more than a threshold amount; or a current measurement exceeding a reverse current threshold.

3. The integrated circuit of claim 1, wherein the determination is based on the first voltage decreasing more than a thresh- old amount when the one or more capacitors are in a discharging state; and / or wherein the determination is based on a current measurement exceeding a reverse cur- rent threshold when the one or more capacitors are in a charging state.

4. The integrated circuit of claim 1, wherein the particular state forms a capacitor ar- rangement that disconnects the one or more capacitors from a source of the first voltage.

5. A system comprising the integrated circuit of claim 1, wherein the system further comprises: the one or more capacitors; an inductor; andDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 wherein the particular state forms a capacitor arrangement that discharges one or more of the one or more capacitors to an output load via the inductor.

6. The integrated circuit of claim 1, wherein the controller is further configured to: measure a third voltage across a first capacitor of the one or more capacitors; and maintain the particular state until the third voltage reaches a first threshold value.

7. The integrated circuit of claim 6, wherein the controller is further configured to: measure a fourth voltage across a second capacitor of the one or more capacitors; and control the state of the switching network to cycle between a subset of the set of states until the fourth voltage reaches a second threshold value.

8. A method, comprising: controlling a state of a switching network coupled to one or more capacitors to cycle between a set of states associated with different capacitor arrangements of the one or more capacitors, maintaining each state for a predefined amount of time according to a timing pat- tern to convert a first voltage to a second voltage; and maintaining a particular state of the switching network for longer than the predefined amount of time in response to a determination that a current to a source of the first voltage may occur.

9. The method of claim 8, wherein the determination is based on at least one of: the first voltage decreasing more than a threshold amount; or a current measurement exceeding a reverse current threshold.

10. The method of claim 8, wherein the determination is based on the first voltage decreasing more than a thresh- old amount when the one or more capacitors are in a discharging state; and wherein the determination is based on a current measurement exceeding a reverse cur- rent threshold when the one or more capacitors are in a charging state.Docket No.61658.42WO01 Client Ref. No. PER-533-PCT2 11. The method of claim 8, wherein the particular state forms a capacitor arrangement that disconnects the one or more capacitors from a source of the first voltage.

12. The method of claim 8, wherein the particular state forms a capacitor arrangement that discharges one or more of the one or more capacitors to an output load via an inductor.

13. The method of claim 8, further comprising: measuring a third voltage across a first capacitor of the one or more capacitors; and maintaining the particular state until the third voltage reaches a first threshold value.

14. The method of claim 13, further comprising: measuring a fourth voltage across a second capacitor of the one or more capacitors; and controlling the state of the switching network to cycle between a subset of the set of states until the fourth voltage reaches a second threshold value.

15. A circuit for converting a first voltage to a second voltage, comprising: one or more capacitors; an inductor; a switching network couplable to the one or more capacitors and configured to form a capacitor arrangement dependent on a state of the switching network; and a controller configured to: control the state of the switching network to cycle between a set of states maintaining each state for a predefined amount of time according to a timing pattern to convert a first voltage to a second voltage coupled to the inductor; and maintain a particular state of the switching network for longer than the prede- fined amount of time in response to a determination that a current to a source of the first voltage may occur.

16. The circuit of claim 15, wherein the determination is based on at least one of: the first voltage decreasing more than a threshold amount; orDocket No.61658.42WO01 Client Ref. No. PER-533-PCT2 a current measurement exceeding a reverse current threshold.

17. The circuit of claim 15, wherein the particular state forms a capacitor arrangement that disconnects the one or more capacitors from a source of the first voltage.

18. The circuit of claim 15, wherein the particular state forms a capacitor arrangement that discharges one or more of the one or more capacitors to an output load.

19. The circuit of claim 15, wherein the controller is further configured to: measure a third voltage across a first capacitor of the one or more capacitors; and maintain the particular state until the third voltage reaches a first threshold value.

20. The circuit of claim 19, wherein the controller is further configured to: measure a fourth voltage across a second capacitor of the one or more capacitors; and control the state of the switching network to cycle between a subset of the set of states until the fourth voltage reaches a second threshold value.

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