Display panel, display device and driving method

Abstract

Provided are a display panel, a display device and a driving method. A pixel circuit comprises: a light-emitting device (L); a drive transistor (M0) which is configured to generate, on the basis of a data voltage signal, a drive current for driving the light-emitting device (L) to emit light; a first control circuit (10) which is configured to provide, in response to a signal on a first control signal line (CS1), a signal on a first reference voltage signal line (Vref1) to a first electrode of the drive transistor (M0), and which is configured to connect, in response to signals on a second control signal line (CS2) and a third control signal line (CS3), a gate and a second electrode of the drive transistor (M0); a second control circuit (20) which is configured to provide, in response to a signal on a fourth control signal line (CS4), a signal on a second reference voltage signal line (Vref2) to a first node (N1); a data writing circuit (30) for providing a data voltage signal on a data signal line (DA) to the first node (N1); and a light emission control circuit (50) for providing a signal on a first power signal line (EM1) to the first electrode of the drive transistor (M0), and connecting the second electrode of the drive transistor to the light-emitting device (L) so as to drive the light-emitting device (L) to emit light.

Description

Display panel, display device, and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a driving method. Background Art

[0002] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) offer advantages such as self-luminescence and low energy consumption, making them a hot topic in current display device application research. Display devices typically use pixel circuits to drive the light-emitting devices.

[0003] Summary of the Invention

[0004] The display panel provided by the embodiment of the present disclosure includes a base substrate, comprising a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel circuit;

[0005] The pixel circuit comprises:

[0006] Light-emitting devices;

[0007] a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

[0008] a first control circuit coupled to the driving transistor and configured to provide a signal on a first reference voltage signal line to a first electrode of the driving transistor in response to a signal on a first control signal line, and to conduct electricity between a gate electrode of the driving transistor and a second electrode in response to signals on a second control signal line and a third control signal line;

[0009] a second control circuit coupled to the first node and configured to provide a signal on a second reference voltage signal line to the first node in response to a signal on a fourth control signal line;

[0010] a data writing circuit coupled to the first node and configured to provide a data voltage signal on the data signal line to the first node in response to a signal on the scan signal line;

[0011] a coupling control circuit coupled to the gate of the driving transistor and the first node, configured to couple the data voltage signal of the first node to the gate of the driving transistor and stabilize the voltage of the first node;

[0012] The light-emitting control circuit is coupled to the driving transistor and the light-emitting device, and is configured to provide a signal on the first power signal line to the first electrode of the driving transistor in response to a signal on the first light-emitting control signal line, and to connect the second electrode of the driving transistor to the light-emitting device in response to a signal on the second light-emitting control signal line, thereby driving the light-emitting device to emit light.

[0013] Optionally, in some embodiments of the present disclosure, the further comprising: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the base substrate;

[0014] The first semiconductor layer and the second semiconductor layer are made of different materials.

[0015] Optionally, in some embodiments of the present disclosure, the first control circuit includes: a first transistor, a second transistor, and a third transistor;

[0016] The gate of the first transistor is coupled to the first control signal line, the first electrode of the first transistor is coupled to the first electrode of the driving transistor, and the second electrode of the first transistor is coupled to the first reference voltage signal line;

[0017] The gate of the second transistor is coupled to the second control signal line, the first electrode of the second transistor is coupled to the second electrode of the third transistor, and the second electrode of the second transistor is coupled to the second electrode of the driving transistor;

[0018] A gate of the third transistor is coupled to the third control signal line, and a first electrode of the third transistor is coupled to the gate of the driving transistor.

[0019] Optionally, in some embodiments of the present disclosure, the first semiconductor layer includes the active layer of the driving transistor, the active layer of the first transistor, and the active layer of the second transistor; the second semiconductor layer includes the active layer of the third transistor;

[0020] The first conductive layer includes a gate of the driving transistor, a gate of the first transistor, and a gate of the second transistor; the second conductive layer and the third conductive layer include a gate of the third transistor.

[0021] Optionally, in some embodiments of the present disclosure, the second control circuit includes: a fourth transistor;

[0022] A gate of the fourth transistor is coupled to the fourth control signal line, a first electrode of the fourth transistor is coupled to the first node, and a second electrode of the fourth transistor is coupled to the second reference voltage signal line.

[0023] Optionally, in some embodiments of the present disclosure, the second semiconductor layer includes an active layer of the fourth transistor; and the second conductive layer and the third conductive layer include a gate of the fourth transistor.

[0024] Optionally, in some embodiments of the present disclosure, the data writing circuit includes: a fifth transistor;

[0025] A gate of the fifth transistor is coupled to the scan signal line, a first electrode of the fifth transistor is coupled to the data signal line, and a second electrode of the fifth transistor is coupled to the first node.

[0026] Optionally, in some embodiments of the present disclosure, the second semiconductor layer includes an active layer of a fifth transistor; and the second conductive layer and the third conductive layer include a gate of the fifth transistor.

[0027] Optionally, in some embodiments of the present disclosure, the coupling control circuit includes: a first capacitor and a second capacitor;

[0028] A first plate of the first capacitor is coupled to the gate of the driving transistor, and a second plate of the first capacitor is coupled to the first node;

[0029] The first plate of the second capacitor is coupled to the first power signal line, and the second plate of the second capacitor is coupled to the first node.

[0030] Optionally, in some embodiments of the present disclosure, the first conductive layer includes the first plate of the first capacitor and the first plate of the second capacitor; the second conductive layer includes the second plate of the first capacitor and the second plate of the second capacitor; the third conductive layer includes the first plate of the second capacitor;

[0031] The first electrode plate of the first capacitor and the first electrode plate of the second capacitor located on the first conductive layer are spaced apart from each other; the second electrode plate of the first capacitor and the second electrode plate of the second capacitor located on the second conductive layer are integrated;

[0032] The orthographic projection of the first plate of the first capacitor on the first conductive layer on the substrate overlaps with the orthographic projection of the second plate of the first capacitor on the second conductive layer on the substrate;

[0033] The orthographic projection of the first plate of the second capacitor on the first conductive layer on the substrate overlaps with the orthographic projection of the second plate of the second capacitor on the second conductive layer on the substrate;

[0034] The orthographic projection of the first plate of the second capacitor on the third conductive layer on the substrate completely overlaps with the orthographic projection of the second plate of the second capacitor on the second conductive layer on the substrate;

[0035] The orthographic projection of the first plate of the second capacitor on the third conductive layer on the base substrate partially overlaps with the orthographic projection of the first plate of the first capacitor on the first conductive layer on the base substrate.

[0036] Optionally, in some embodiments of the present disclosure, the light emitting control circuit includes: a sixth transistor and a seventh transistor;

[0037] The gate of the sixth transistor is coupled to the first light emitting control signal line, the first electrode of the sixth transistor is coupled to the first power signal line, and the second electrode of the sixth transistor is coupled to the first electrode of the driving transistor;

[0038] A gate of the seventh transistor is coupled to the second light emitting control signal line, a first electrode of the seventh transistor is coupled to the second electrode of the driving transistor, and a second electrode of the seventh transistor is coupled to the light emitting device.

[0039] Optionally, in some embodiments of the present disclosure, the first semiconductor layer includes an active layer of the sixth transistor and an active layer of the seventh transistor; and the first conductive layer includes a gate of the sixth transistor and a gate of the seventh transistor.

[0040] Optionally, in some embodiments of the present disclosure, the pixel circuit further includes: a first reset circuit, coupled to the first control circuit, and configured to provide a signal on the first initialization signal line to the first control circuit in response to a signal on the fifth control signal line;

[0041] A second reset circuit is coupled to the light emitting device and configured to provide a signal on the first initialization signal line or the second initialization signal line to the light emitting device in response to a signal on the first control signal line.

[0042] Optionally, the first reset circuit includes: an eighth transistor;

[0043] The gate of the eighth transistor is coupled to the fifth control signal line, the first electrode of the eighth transistor is coupled to the second electrode of the third transistor, and the second electrode of the eighth transistor is coupled to the first initialization signal line;

[0044] The second reset circuit includes: a ninth transistor;

[0045] A gate of the ninth transistor is coupled to the first control signal line, a first electrode of the ninth transistor is coupled to the light emitting device, and a second electrode of the ninth transistor is coupled to the first initialization signal line or the second initialization signal line.

[0046] Optionally, in some embodiments of the present disclosure, the first semiconductor layer includes an active layer of the eighth transistor; the first conductive layer includes a gate of the eighth transistor;

[0047] The first semiconductor layer includes an active layer of the ninth transistor; and the first conductive layer includes a gate of the ninth transistor.

[0048] Optionally, in some embodiments of the present disclosure, the signal lines in the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer extend along the first direction; and the signal lines in the fifth conductive layer extend along the second direction.

[0049] Optionally, in some embodiments of the present disclosure, the first conductive layer includes the first control signal line and a fifth control signal line;

[0050] The second conductive layer includes a first initialization signal line, the second light emitting control signal line, and at least two of the first reference voltage signal lines;

[0051] The third conductive layer includes a first light emitting control signal line;

[0052] The fourth conductive layer includes the scan signal line, the fourth control signal line, the second reference voltage signal line, the first power signal line, the third control signal line, the second control signal line, and a second initialization signal line;

[0053] The fifth conductive layer includes the data signal line, the first power signal line, and the second reference voltage signal line. The first power signal line is located between the data signal line and the second reference voltage signal line.

[0054] Optionally, in some embodiments of the present disclosure, the fourth conductive layer further includes a second power signal line; the second power signal line provides a second power signal to the light emitting device;

[0055] The fifth conductive layer further includes the first initialization signal line, the second initialization signal line, a first reference voltage signal line, and the second power signal line.

[0056] Optionally, in some embodiments of the present disclosure, the substrate further comprises: a plurality of pixel units; the pixel unit comprises three sub-pixels;

[0057] The orthographic projections of the first sub-pixel and the second sub-pixel in the pixel unit on the substrate are symmetrical with respect to the orthographic projection of the second reference voltage signal line on the substrate, and the first sub-pixel and the second sub-pixel in the pixel unit share the second reference voltage signal line;

[0058] The orthographic projections of the data signal line and the second reference voltage signal line on the substrate are located between the orthographic projections of the second sub-pixel and the third sub-pixel in the pixel unit on the substrate;

[0059] The first initialization signal line or the second initialization signal line or the first reference voltage signal line or the second power supply signal line is located between two adjacent pixel units along the first direction.

[0060] Optionally, in some embodiments of the present disclosure, the first initialization signal line, the second initialization signal line, the first reference voltage signal line, and the second power signal line are alternately arranged in sequence along the first direction.

[0061] The driving method of the display panel provided in the embodiment of the present disclosure includes:

[0062] When the first frequency display is used, it includes:

[0063] In the reset phase, the first control circuit provides the signal on the first reference voltage signal line to the first electrode of the driving transistor in response to the signal on the first control signal line; the first reset circuit provides the signal on the first initialization signal line to the first control circuit in response to the signal on the fifth control signal line; and the second reset circuit provides the signal on the second initialization signal line to the light-emitting device in response to the signal on the first control signal line.

[0064] In the threshold voltage compensation stage, the first control circuit connects the gate of the driving transistor to the second electrode in response to the signals on the second control signal line and the third control signal line; the second control circuit provides the signal on the second reference voltage signal line to the first node in response to the signal on the fourth control signal line; and the light emission control circuit provides the signal on the first power supply signal line to the first electrode of the driving transistor in response to the signal on the first light emission control signal line.

[0065] In the data writing stage, the data writing circuit responds to the signal on the scanning signal line and provides the data voltage signal on the data signal line to the first node; the second reset circuit responds to the signal on the first control signal line and provides the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line and provides the signal on the first reference voltage signal line to the first electrode of the driving transistor;

[0066] In the bias phase, the second reset circuit provides the signal on the second initialization signal line to the light-emitting device in response to the signal on the first control signal line; the first control circuit provides the signal on the first reference voltage signal line to the first electrode of the driving transistor in response to the signal on the first control signal line;

[0067] In the light-emitting stage, the light-emitting control circuit responds to the signal on the first light-emitting control signal line, provides the signal on the first power signal line to the first electrode of the driving transistor, and responds to the signal on the second light-emitting control signal line, connects the second electrode of the driving transistor to the light-emitting device, and drives the light-emitting device to emit light.

[0068] Optionally, in some embodiments of the present disclosure, the method further includes:

[0069] When the second frequency display is used, it includes:

[0070] In the bias phase, the second reset circuit provides the signal on the second initialization signal line to the light-emitting device in response to the signal on the first control signal line; the first control circuit provides the signal on the first reference voltage signal line to the first electrode of the driving transistor in response to the signal on the first control signal line;

[0071] In the light emitting stage, the light emitting control circuit provides the signal on the first power supply signal line to the first electrode of the driving transistor in response to the signal on the first light emitting control signal line, and connects the second electrode of the driving transistor to the light emitting device in response to the signal on the second light emitting control signal line, thereby driving the light emitting device to emit light;

[0072] The second frequency is lower than the first frequency.

[0073] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] FIG1 is a schematic diagram of some structures of pixel circuits provided by an embodiment of the present disclosure;

[0075] FIG2 is another schematic diagram of the structure of the pixel circuit provided by the embodiment of the present disclosure;

[0076] FIG3 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0077] FIG4 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0078] FIG5 is a schematic diagram of some structures of a display panel provided by an embodiment of the present disclosure;

[0079] FIG6 is a schematic diagram of some other structures of a display panel provided by an embodiment of the present disclosure;

[0080] FIG7 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0081] FIG8 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0082] FIG9 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0083] FIG10 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0084] FIG11 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0085] FIG12 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0086] FIG13 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0087] FIG14 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0088] FIG15 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0089] FIG16 is a flowchart of some driving methods provided by embodiments of the present disclosure;

[0090] FIG17 is a flowchart of other driving methods provided by embodiments of the present disclosure;

[0091] FIG18 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0092] FIG19 is another signal timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0094] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0095] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0096] The display device provided by the embodiment of the present disclosure includes: a display panel, and the display area of ​​the display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0097] In the disclosed embodiments, each sub-pixel includes a pixel circuit, which includes a driving transistor and a light-emitting device to drive the light-emitting device to emit light, thereby enabling the display panel to display images. Due to factors such as process technology and device aging, the threshold voltage Vth of the driving transistor may be non-uniform. This causes the current flowing through different light-emitting devices to vary, resulting in uneven display brightness, thereby affecting the overall image display effect.

[0098] Furthermore, due to the current market's high demand for display quality, high frame rate display has become a trend in the future display industry. However, high frame rate display consumes a lot of power, resulting in a decrease in the battery life of the display device. The introduction of high and low frame rate switching technology (Variable Refresh Rate, VRR) can improve power consumption and increase the battery life of the display device. However, under low frame rate display, the hysteresis effect of the driving transistor will cause the display to have an afterimage problem, affecting the display effect; and flickering will occur when switching between each frame, further affecting the display effect.

[0099] The display panel provided by the embodiment of the present disclosure, as shown in FIG1 , includes: a base substrate 100 including a plurality of sub-pixels spx, each of the plurality of sub-pixels spx including a pixel circuit 200;

[0100] The pixel circuit 200 includes:

[0101] Light emitting device L;

[0102] a driving transistor M0 coupled to the light emitting device L and configured to generate a driving current for driving the light emitting device L to emit light according to the data voltage signal;

[0103] The first control circuit 10 is coupled to the driving transistor M0 and is configured to provide a signal on the first reference voltage signal line Vref1 to the first electrode of the driving transistor M0 in response to a signal on the first control signal line CS1, and to conduct the gate electrode of the driving transistor M0 to the second electrode in response to signals on the second control signal line CS2 and the third control signal line CS3;

[0104] The second control circuit 20 is coupled to the first node N1 and configured to provide a signal on the second reference voltage signal line Vref2 to the first node N1 in response to a signal on the fourth control signal line CS4;

[0105] The data writing circuit 30 is coupled to the first node N1 and is configured to provide a data voltage signal on the data signal line DA to the first node N1 in response to a signal on the scan signal line SS;

[0106] a coupling control circuit 40 coupled to the gate of the driving transistor M0 and the first node N1, configured to couple the data voltage signal of the first node N1 to the gate of the driving transistor M0 and stabilize the voltage of the first node N1;

[0107] The light-emitting control circuit 50 is coupled to the driving transistor M0 and the light-emitting device L, and is configured to provide the signal on the first power signal line VDD to the first electrode of the driving transistor M0 in response to the signal on the first light-emitting control signal line EM1, and to connect the second electrode of the driving transistor M0 to the light-emitting device L in response to the signal on the second light-emitting control signal line EM2, thereby driving the light-emitting device L to emit light.

[0108] In the embodiment of the present disclosure, through the cooperation of the first control circuit, the second control circuit, the data writing circuit, the coupling control circuit, and the light emitting control circuit, the threshold voltage compensation of the driving transistor is performed separately from the writing of the data voltage signal. As a result, the threshold voltage compensation duration of the driving transistor is not limited by the writing of the data voltage signal. The threshold voltage compensation process can be performed for a longer period of time, which is beneficial to the stability of the threshold voltage of the driving transistor. In turn, high frame rate display can be achieved and the influence of the threshold voltage drift of the driving transistor on the light emission of the light emitting device can be avoided, thereby improving the image quality of high frame rate display.

[0109] Moreover, by cooperating with each other, the first control circuit, the second control circuit, the data writing circuit, the coupling control circuit and the light emitting control circuit, the driving transistor is strongly biased, which can improve the hysteresis effect of the driving transistor, thereby avoiding the afterimage problem and the flicker problem and improving the display effect.

[0110] For example, as shown in FIG1 , the driving transistor M0 can be configured as a P-type transistor, wherein the first electrode of the driving transistor M0 can be its source electrode, and the second electrode of the driving transistor M0 can be its drain electrode. Of course, the driving transistor M0 can also be configured as an N-type transistor, which is not limited here.

[0111] Exemplarily, as shown in FIG1 , the second electrode of the driving transistor M0 is coupled to the anode of the light-emitting device L, and the cathode of the light-emitting device L is coupled to the second power signal line VSS. Exemplarily, the light-emitting device L may include at least one of: a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED) and a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED). Exemplarily, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In actual applications, the specific structure of the light-emitting device can be designed and determined according to the actual application environment, and is not limited here.

[0112] In some embodiments of the present disclosure, as shown in Figure 2, the first control circuit 10 includes: a first transistor M1, a second transistor M2 and a third transistor M3; wherein, the gate of the first transistor M1 is coupled to the first control signal line CS1, the first electrode of the first transistor M1 is coupled to the first electrode of the driving transistor M0, and the second electrode of the first transistor M1 is coupled to the first reference voltage signal line Vref1; the gate of the second transistor M2 is coupled to the second control signal line CS2, the first electrode of the second transistor M2 is coupled to the second electrode of the third transistor M3, and the second electrode of the second transistor M2 is coupled to the second electrode of the driving transistor M0; the gate of the third transistor M3 is coupled to the third control signal line CS3, and the first electrode of the third transistor M3 is coupled to the gate of the driving transistor M0.

[0113] For example, the first transistor M1 can be turned on under the control of the active level of the first control signal transmitted by the first control signal line CS1, and can be turned off under the control of the inactive level of the first control signal. For example, if the first transistor M1 is configured as a P-type transistor, the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level. Alternatively, if the first transistor M1 is configured as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level.

[0114] For example, the second transistor M2 can be turned on under the control of the active level of the second control signal transmitted by the second control signal line CS2, and can be turned off under the control of the inactive level of the second control signal. For example, if the second transistor M2 is configured as a P-type transistor, the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level. Alternatively, if the second transistor M2 is configured as an N-type transistor, the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level.

[0115] For example, the third transistor M3 can be turned on under the control of the active level of the third control signal transmitted by the third control signal line CS3, and can be turned off under the control of the inactive level of the third control signal. For example, if the third transistor M3 is configured as a P-type transistor, the active level of the third control signal is a low level, and the inactive level of the third control signal is a high level. Alternatively, if the third transistor M3 is configured as an N-type transistor, the active level of the third control signal is a high level, and the inactive level of the third control signal is a low level.

[0116] In some embodiments of the present disclosure, as shown in Figure 2, the second control circuit 20 includes: a fourth transistor M4; wherein the gate of the fourth transistor M4 is coupled to the fourth control signal line CS4, the first electrode of the fourth transistor M4 is coupled to the first node N1, and the second electrode of the fourth transistor M4 is coupled to the second reference voltage signal line Vref2.

[0117] For example, the fourth transistor M4 can be turned on under the control of the active level of the fourth control signal transmitted by the fourth control signal line CS4, and can be turned off under the control of the inactive level of the fourth control signal. For example, if the fourth transistor M4 is configured as a P-type transistor, the active level of the fourth control signal is a low level, and the inactive level of the fourth control signal is a high level. Alternatively, if the fourth transistor M4 is configured as an N-type transistor, the active level of the fourth control signal is a high level, and the inactive level of the fourth control signal is a low level.

[0118] In some embodiments of the present disclosure, as shown in Figure 2, the data write circuit 30 includes: a fifth transistor M5; the gate of the fifth transistor M5 is coupled to the scan signal line SS, the first electrode of the fifth transistor M5 is coupled to the data signal line DA, and the second electrode of the fifth transistor M5 is coupled to the first node N1.

[0119] Exemplarily, the fifth transistor M5 can be turned on under the control of the active level of the scan signal transmitted by the scan signal line SS, and can be turned off under the control of the inactive level of the scan signal. Exemplarily, the fifth transistor M5 is configured as a P-type transistor, then the active level of the scan signal is a low level, and the inactive level of the scan signal is a high level. Alternatively, the fifth transistor M5 is configured as an N-type transistor, then the active level of the scan signal is a high level, and the inactive level of the scan signal is a low level.

[0120] In some embodiments of the present disclosure, as shown in Figure 2, the coupling control circuit 40 includes: a first capacitor C1 and a second capacitor C2; wherein, the first plate of the first capacitor C1 is coupled to the gate of the driving transistor M0, and the second plate of the first capacitor C1 is coupled to the first node N1; the first plate of the second capacitor C2 is coupled to the first power signal line, and the second plate of the second capacitor C2 is coupled to the first node N1.

[0121] In some embodiments of the present disclosure, as shown in Figure 2, the light-emitting control circuit 50 includes: a sixth transistor M6 and a seventh transistor M7; wherein, the gate of the sixth transistor M6 is coupled to the first light-emitting control signal line EM1, the first electrode of the sixth transistor M6 is coupled to the first power signal line, and the second electrode of the sixth transistor M6 is coupled to the first electrode of the driving transistor M0; the gate of the seventh transistor M7 is coupled to the second light-emitting control signal line EM2, the first electrode of the seventh transistor M7 is coupled to the second electrode of the driving transistor M0, and the second electrode of the seventh transistor M7 is coupled to the light-emitting device L.

[0122] Exemplarily, the sixth transistor M6 can be turned on under the control of the active level of the first light-emitting control signal transmitted by the first light-emitting control signal line EM1, and can be turned off under the control of the inactive level of the first light-emitting control signal. Exemplarily, if the sixth transistor M6 is configured as a P-type transistor, the active level of the first light-emitting control signal is a low level, and the inactive level of the first light-emitting control signal is a high level. Alternatively, if the sixth transistor M6 is configured as an N-type transistor, the active level of the first light-emitting control signal is a high level, and the inactive level of the first light-emitting control signal is a low level.

[0123] Exemplarily, the seventh transistor M7 can be turned on under the control of the active level of the second light-emitting control signal transmitted by the second light-emitting control signal line EM2, and can be turned off under the control of the inactive level of the second light-emitting control signal. Exemplarily, if the seventh transistor M7 is configured as a P-type transistor, the active level of the second light-emitting control signal is a low level, and the inactive level of the second light-emitting control signal is a high level. Alternatively, if the seventh transistor M7 is configured as an N-type transistor, the active level of the second light-emitting control signal is a high level, and the inactive level of the second light-emitting control signal is a low level.

[0124] In some embodiments of the present disclosure, as shown in Figure 1, the pixel circuit 200 also includes: a first reset circuit 60, coupled to the first control circuit 10, and configured to provide the signal on the first initialization signal line Vinit1 to the first control circuit 10 in response to the signal on the fifth control signal line CS5.

[0125] In some embodiments of the present disclosure, as shown in Figure 2, the first reset circuit 60 includes: an eighth transistor M8; wherein the gate of the eighth transistor M8 is coupled to the fifth control signal line CS5, the first electrode of the eighth transistor M8 is coupled to the second electrode of the third transistor M3, and the second electrode of the eighth transistor M8 is coupled to the first initialization signal line Vinit1.

[0126] For example, the eighth transistor M8 can be turned on under the control of the active level of the fifth control signal transmitted by the fifth control signal line CS5, and can be turned off under the control of the inactive level of the fifth control signal. For example, if the eighth transistor M8 is configured as a P-type transistor, the active level of the fifth control signal is a low level, and the inactive level of the fifth control signal is a high level. Alternatively, if the eighth transistor M8 is configured as an N-type transistor, the active level of the fifth control signal is a high level, and the inactive level of the fifth control signal is a low level.

[0127] In some embodiments of the present disclosure, as shown in FIG1 , the pixel circuit 200 further includes: a second reset circuit 70 coupled to the light-emitting device L and configured to provide a signal on the second initialization signal line Vinit2 to the light-emitting device L in response to a signal on the first control signal line CS1 .

[0128] In some embodiments of the present disclosure, as shown in Figure 2, the second reset circuit 70 includes: a ninth transistor M9; wherein the gate of the ninth transistor M9 is coupled to the first control signal line CS1, the first electrode of the ninth transistor M9 is coupled to the light-emitting device L, and the second electrode of the ninth transistor M9 is coupled to the second initialization signal line Vinit2.

[0129] The present disclosure couples the first reset circuit 60 to the first initialization signal line Vinit1 and the second reset circuit 70 to the second initialization signal line Vinit2, thereby resetting the gate of the driving transistor M0 and the anode of the light emitting device L respectively, thereby further improving image quality.

[0130] For example, the ninth transistor M9 can be turned on under the control of the active level of the first control signal transmitted by the first control signal line CS1, and can be turned off under the control of the inactive level of the first control signal. For example, if the ninth transistor M9 is configured as a P-type transistor, the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level. Alternatively, if the ninth transistor M9 is configured as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level.

[0131] The present disclosure provides other schematic diagrams of pixel circuits, as shown in Figures 3 and 4, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0132] In other embodiments of the present disclosure, as shown in FIG3 , the pixel circuit 200 further includes: a second reset circuit 70 coupled to the light-emitting device L and configured to provide the signal on the first initialization signal line Vinit1 to the light-emitting device L in response to the signal on the first control signal line CS1 .

[0133] In other embodiments of the present disclosure, as shown in Figure 4, the second reset circuit 70 includes: a ninth transistor M9; wherein the gate of the ninth transistor M9 is coupled to the first control signal line CS1, the first electrode of the ninth transistor M9 is coupled to the light-emitting device L, and the second electrode of the ninth transistor M9 is coupled to the first initialization signal line Vinit1.

[0134] In the present disclosure, the first reset circuit 60 and the second reset circuit 70 are coupled to the first initialization signal line Vinit1 , which can reduce the number of signal lines, lower the wiring difficulty, and further simplify the circuit layout.

[0135] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0136] For example, the first power signal line VDD can be configured to carry a constant first power voltage VDD, which is generally a positive value. Furthermore, the second power signal line VSS can be configured to carry a constant second power voltage VSS, which is generally a ground voltage or a negative value. In actual applications, the specific values ​​of the first power voltage VDD and the second power voltage VSS can be designed and determined based on the actual application environment and are not limited here.

[0137] In some embodiments of the present disclosure, as shown in Figures 5 to 13, it also includes: a first semiconductor layer 110, a first conductive layer 120, a second conductive layer 130, a second semiconductor layer 140, a third conductive layer 150, a fourth conductive layer 160 and a fifth conductive layer 170 stacked in sequence on the base substrate 100; wherein the materials of the first semiconductor layer 110 and the second semiconductor layer 140 are different.

[0138] It should be noted that the first semiconductor layer and the second semiconductor layer are used to form the active layer of each transistor in the pixel circuit. The active layer includes a channel region, and source and drain regions located on either side of the channel region. By configuring the first semiconductor layer and the second semiconductor layer to be made of different materials, the present disclosure reduces leakage current in the pixel circuit and improves the display effect and quality of the display panel.

[0139] Exemplarily, as shown in FIG. 6 , an auxiliary conductive layer 101 is further included, located between the base substrate 100 and the first semiconductor layer 110 .

[0140] In some embodiments of the present disclosure, the material of the first semiconductor layer 110 is a low-temperature polysilicon material, and the material of the second semiconductor layer 140 is an oxide material.

[0141] Transistors using low-temperature polysilicon (LTPS) as active layers generally have high mobility and can be made thinner and smaller, with lower power consumption. In specific implementations, the active layer of the transistor can also be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, enabling the pixel circuit to achieve high mobility, be thinner and smaller, and have lower power consumption.

[0142] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of the transistor may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. This allows the transistor to be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0143] For example, some of the transistors in the pixel circuit of the present disclosure can be set as oxide-type transistors, and other transistors can be set as LTPS-type transistors. For example, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are set as oxide-type transistors, and the driving transistor M0, the first transistor M1, the second transistor M2, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are set as LTPS-type transistors; thereby reducing the leakage current of the pixel circuit and improving the display quality. The embodiment of the present disclosure utilizes the low leakage characteristics of the oxide-type transistor to ensure that the gate voltage value of the driving transistor M0 is maintained under low frame rate display, thereby avoiding flickering of the display panel.

[0144] For example, the materials of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be conductive materials. For example, the conductive material can include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of the present disclosure do not specifically limit the materials of the conductive layers, and can be set as required.

[0145] By way of example, the various structures in the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be formed using a patterning process. It should be noted that the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes such as printing and inkjet printing for forming a predetermined pattern. A photolithography process refers to a process that uses photoresist, a mask, an exposure machine, and the like to form a pattern, including film formation, exposure, and development processes. In specific implementations, a corresponding patterning process can be selected based on the structure formed in the present disclosure.

[0146] In some embodiments of the present disclosure, as shown in Figures 7 to 13, the first semiconductor layer 110 includes an active layer of the driving transistor M0, an active layer of the first transistor M1, and an active layer of the second transistor M2; the second semiconductor layer 140 includes an active layer of the third transistor M3; the first conductive layer 120 includes a gate of the driving transistor M0, a gate of the first transistor M1, and a gate of the second transistor M2; the second conductive layer 130 and the third conductive layer 150 include a gate of the third transistor M3.

[0147] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 13 , the second semiconductor layer 140 further includes an active layer of the fourth transistor M4 ; the second conductive layer 130 and the third conductive layer 150 further include a gate of the fourth transistor.

[0148] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 13 , the second semiconductor layer 140 further includes an active layer of the fifth transistor M5 ; the second conductive layer 130 and the third conductive layer 150 further include a gate of the fifth transistor.

[0149] In some embodiments of the present disclosure, as shown in Figures 7 to 13, the first semiconductor layer 110 further includes an active layer of the sixth transistor M6 and an active layer of the seventh transistor M7; the first conductive layer 120 further includes a gate of the sixth transistor M6 and a gate of the seventh transistor M7.

[0150] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 13 , the first semiconductor layer 110 further includes an active layer of the eighth transistor M8 ; and the first conductive layer 120 further includes a gate of the eighth transistor M8 .

[0151] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 13 , the first semiconductor layer 110 further includes an active layer of the ninth transistor M9 ; and the first conductive layer 120 further includes a gate of the ninth transistor M9 .

[0152] In some embodiments of the present disclosure, as shown in FIG7 to FIG13, the first conductive layer 120 further includes a first plate of the first capacitor C1 and a first plate of the second capacitor C2; the second conductive layer 130 further includes a second plate of the first capacitor C1 and a second plate of the second capacitor C2; the third conductive layer 150 further includes a first plate of the second capacitor C2;

[0153] The first electrode plate of the first capacitor C1 and the first electrode plate of the second capacitor C2 located on the first conductive layer 120 are spaced apart from each other; the second electrode plate of the first capacitor C1 and the second electrode plate of the second capacitor C2 located on the second conductive layer 130 are integrated;

[0154] The orthographic projection of the first plate of the first capacitor C1 on the first conductive layer 120 on the substrate overlaps with the orthographic projection of the second plate of the first capacitor C1 on the second conductive layer 130 on the substrate;

[0155] The orthographic projection of the first electrode plate of the second capacitor C2 on the first conductive layer 120 on the substrate overlaps with the orthographic projection of the second electrode plate of the second capacitor C2 on the second conductive layer 130 on the substrate;

[0156] The orthographic projection of the first electrode plate of the second capacitor C2 on the third conductive layer 150 on the substrate completely overlaps with the orthographic projection of the second electrode plate of the second capacitor C2 on the second conductive layer 130 on the substrate;

[0157] The orthographic projection of the first plate of the second capacitor C2 on the third conductive layer 150 on the substrate partially overlaps with the orthographic projection of the first plate of the first capacitor C1 on the first conductive layer 120 on the substrate.

[0158] Exemplarily, as shown in FIG8 , the first electrode plate of the first capacitor C1 on the first conductive layer 120 extends along the first direction X, and the second capacitors C2 on the first conductive layer 120 are spaced apart from each other in the first direction X.

[0159] Exemplarily, as shown in FIG9 , the second plate of the first capacitor C1 and the second plate of the second capacitor C2 in each sub-pixel (e.g., spx1, spx2, spx3 in FIG9 ) are a whole, that is, the second plate of the first capacitor C1 and the second plate of the second capacitor C2 in each sub-pixel (e.g., spx1, spx2, spx3 in FIG9 ) are connected to each other.

[0160] Exemplarily, as shown in Figure 11, the first plates of the second capacitor C2 on the third conductive layer 150 are connected to each other in the first direction X, that is, the first plate of the second capacitor C2 in the sub-pixel spx1 is connected to the first plate of the second capacitor C2 in the sub-pixel spx2, and the first plate of the second capacitor C2 in the sub-pixel spx2 is connected to the first plate of the second capacitor C2 in the sub-pixel spx3.

[0161] Exemplarily, the orthographic projection of the first plate of the first capacitor C1 located on the first conductive layer 120 on the base substrate 100 overlaps with the orthographic projection of the second plate of the first capacitor C1 located on the second conductive layer 130 on the base substrate 100, that is, the first plate of the first capacitor C1 located on the first conductive layer 120 and the second plate of the first capacitor C1 located on the second conductive layer 130 have a facing area, thereby forming the first capacitor C1.

[0162] Exemplarily, the orthographic projection of the first plate of the second capacitor C2 located on the first conductive layer 120 on the substrate 100 overlaps with the orthographic projection of the second plate of the second capacitor C2 located on the second conductive layer 130 on the substrate 100, that is, the first plate of the second capacitor C2 located on the first conductive layer 120 and the second plate of the second capacitor C2 located on the second conductive layer 130 have a facing area to form a sub-capacitor of the second capacitor; the orthographic projection of the first plate of the second capacitor C2 located on the third conductive layer 150 on the substrate 100 overlaps with the orthographic projection of the second plate of the second capacitor C2 located on the second conductive layer 130 on the substrate 100, that is, the first plate of the second capacitor C2 located on the third conductive layer 150 and the second plate of the second capacitor C2 located on the second conductive layer 130 have a facing area to form another sub-capacitor of the second capacitor C2; the second capacitor C2 is formed by connecting these two sub-capacitors in series to increase the capacitance value of the second capacitor C2. While ensuring the capacitance value of the second capacitor C2 , the area occupied by the second capacitor C2 can also be reduced, thereby saving the space occupied by the second capacitor C2 and improving the space utilization of the display panel.

[0163] It should be noted that, as shown in FIG8 , the first plate of the first capacitor C1 located on the first conductive layer 120 can be reused as the gate of the driving transistor M0 , thereby saving space and improving space utilization of the display panel.

[0164] Exemplarily, the third conductive layer 130 may serve as a shielding layer to shield the parasitic capacitance between the data signal line DA and the gate node of the driving transistor M0 and the first node N1, thereby avoiding adverse effects caused by signal crosstalk and improving display quality.

[0165] In some embodiments of the present disclosure, as shown in Figures 7 to 13, the signal lines in the first conductive layer 120, the second conductive layer 130, the third conductive layer 150, and the fourth conductive layer 160 extend along the first direction X; the signal lines in the fifth conductive layer 170 extend along the second direction Y.

[0166] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 13 , the first conductive layer 120 includes a first control signal line CS1 and a fifth control signal line CS5 ;

[0167] The second conductive layer 130 includes a first initialization signal line Vinit1, a second light emitting control signal line EM2, and at least two first reference voltage signal lines Vref1;

[0168] The third conductive layer 150 includes a first light emitting control signal line EM1;

[0169] The fourth conductive layer 160 includes a scan signal line SS, a fourth control signal line CS4, a second reference voltage signal line Vref2, a first power signal line VDD, a third control signal line CS3, a second control signal line CS2, and a second initialization signal line Vinit2;

[0170] The fifth conductive layer 170 includes a data signal line DA, a first power signal line VDD, and a second reference voltage signal line Vref2. The first power signal line VDD is located between the data signal line DA and the second reference voltage signal line Vref2.

[0171] Exemplarily, as shown in Figure 2, the fourth conductive layer 160 also includes: a first connecting portion Z1, a second connecting portion Z2, a third connecting portion Z3, a fourth connecting portion Z4, a fifth connecting portion Z5, a sixth connecting portion Z6, a seventh connecting portion Z7, an eighth connecting portion Z8, a ninth connecting portion Z9, a tenth connecting portion Z10 and an eleventh connecting portion Z11; wherein the first connecting portion Z1 is used to electrically connect the fifth transistor M5 to the data signal line DA; the second connecting portion Z2 is used to electrically connect the fourth transistor M4 and the fifth transistor M5 to the second plate of the first capacitor C1 and the second plate of the second capacitor C2 on the second conductive layer 130 (it should be noted that the second connecting portion Z2 is equivalent to the first node N1); the third connecting portion Z3 is used to electrically connect the first plate of the second capacitor C2 in the first conductive layer 120 to the first plate of the second capacitor C2 in the third conductive layer 150; the fourth connecting portion Z4 is used to electrically connect the gate of the driving transistor M0, the third transistor M3 and the first gate of the driving transistor M0 in the second conductive layer 130. The second plate of a capacitor C1 is electrically connected (it should be noted that the fourth connection part Z4 is equivalent to the second node N2); the fifth connection part Z5 is used to electrically connect the second transistor M2, the eighth transistor M8 and the third transistor M3 (it should be noted that the fifth connection part Z5 is equivalent to the third node N3); the sixth connection part Z6 is used to electrically connect the eighth transistor M8 to the first initialization signal line Vinit1; the seventh connection part Z7 is used to electrically connect the sixth transistor M6 to the first power supply signal line VDD in the fifth conductive layer 170; the eighth connection part Z8 is used to electrically connect the sixth transistor M6 to the first light-emitting control signal line EM1 in the third conductive layer 150; the ninth connection part Z9 is used to electrically connect the seventh transistor M7 to the second light-emitting control signal line EM2 in the second conductive layer 130; the tenth connection part Z10 is used to electrically connect the seventh transistor M7 and the ninth transistor M9 to the anode of the light-emitting device; the eleventh connection part Z11 is used to electrically connect the first transistor M1 to the first reference voltage signal line Vref1 in the second conductive layer 130.

[0172] Among them, the third connection part Z3 and the first power signal line VDD in the fourth conductive layer 160 are an integrated structure. Since the third connection part Z3 is connected to the first plate of the second capacitor C2 in the first conductive layer 120 and the first plate of the second capacitor C2 in the third conductive layer 150, the signal on the first power signal line VDD can be provided to the first plate of the second capacitor C2 in the first conductive layer 120 and the first plate of the second capacitor C2 in the third conductive layer 150. This arrangement can increase the capacitance of the second capacitor C2, and the orthographic projection of the first plate of the second capacitor C2 in the third conductive layer 150 on the substrate partially overlaps with the orthographic projection of the first plate of the first capacitor C1 on the first conductive layer 120 on the substrate, which can stabilize the voltage on the first node N1, and thus the data signal provided to the first node N1 through the fifth transistor M5 will be more stable. Furthermore, the orthographic projection of the first power signal line VDD in the fifth conductive layer 170 on the substrate overlaps with the orthographic projections of the second connecting portion Z2, the fourth connecting portion Z4, and the fifth connecting portion Z5 on the substrate, thereby stabilizing the voltages of the signals at the first node N1, the second node N2, and the third node N3, further stabilizing the voltages of the signals at the first node N1, the second node N2, and the third node N3. Furthermore, the first power signal line VDD in the fourth conductive layer 160 extends along the first direction X, while the first power signal line VDD in the fifth conductive layer 170 extends along the second direction Y. As a result, the orthographic projection of the first power signal line VDD on the substrate forms a grid. The signal lines extending along the first direction X in the first conductive layer 120, the third conductive layer 150, and the fourth conductive layer 160 are connected to the signal lines extending along the second direction Y in the fifth conductive layer 170, further reducing voltage drop.

[0173] For example, as shown in Figure 8, the first control signal line CS1 is an integrated structure with the gate of the first transistor M1 and the gate of the ninth transistor M9; the fifth control signal line CS5 is an integrated structure with the gate of the eighth transistor M8; then, the first control signal line CS1 in the first conductive layer 120 is multiplexed as the gate of the first transistor M1 and the ninth transistor M9, and the fifth control signal line CS5 in the first conductive layer 120 is multiplexed as the gate of the eighth transistor M8, thereby saving space and improving the space utilization of the display panel.

[0174] Exemplarily, as shown in FIG. 8 and FIG. 9 , the second light emitting control signal line EM2 in the second conductive layer 130 is connected to the gate of the seventh transistor M7 in the first conductive layer 120 .

[0175] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 13 , the fourth conductive layer 160 further includes a second power signal line VSS; the second power signal line VSS provides a second power signal to the light emitting device L;

[0176] The fifth conductive layer 170 further includes a first initialization signal line Vinit1 , a second initialization signal line Vinit2 , a first reference voltage signal line Vref1 , and a second power signal line VSS.

[0177] For example, the second initialization signal line Vinit2 in the fifth conductive layer 170 is electrically connected to the second initialization signal line Vinit2 in the fourth conductive layer 160; the second power signal line VSS in the fifth conductive layer 170 is electrically connected to the second power signal line VSS in the fourth conductive layer 160; the first initialization signal line Vinit1 in the fifth conductive layer 170 is electrically connected to the first initialization signal line Vinit1 in the second conductive layer 130; and the first reference voltage signal line Vref1 in the fifth conductive layer 170 is electrically connected to the first reference voltage signal line Vref1 in the second conductive layer 130. Thus, the orthographic projections of the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference voltage signal line Vref1, and the second power signal line VSS on the substrate are all arranged in a grid pattern.

[0178] In some embodiments of the present disclosure, as shown in FIG5 to FIG15 , the substrate 100 further includes: a plurality of pixel units SPX; the pixel unit SPX includes three sub-pixels (eg, spx1, spx2, spx3 in FIG5 );

[0179] The orthographic projections of the first sub-pixel spx1 and the second sub-pixel spx2 in the pixel unit on the base substrate 100 are symmetrical with respect to the orthographic projection of the second reference voltage signal line Vref2 on the base substrate 100, and the first sub-pixel spx1 and the second sub-pixel spx2 in the pixel unit share the second reference voltage signal line Vref2;

[0180] The orthographic projections of the data signal line DA and the second reference voltage signal line Vref2 on the base substrate 100 are located between the orthographic projections of the second sub-pixel spx2 and the third sub-pixel spx3 in the pixel unit on the base substrate 100;

[0181] Between two adjacent pixel units along the first direction X, there is a first initialization signal line Vinit1 or a second initialization signal line Vinit2 or a first reference voltage signal line Vref1 or a second power signal line VSS.

[0182] In some embodiments of the present disclosure, as shown in FIG14 and FIG15 , the first initialization signal line Vinit1 , the second initialization signal line Vinit2 , the first reference voltage signal line Vref1 , and the second power signal line VSS are alternately arranged along the first direction X.

[0183] Illustratively, the present disclosure can further reduce the power consumption of the pixel circuit and improve the stability of the current and voltage of the pixel circuit by setting the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference voltage signal line Vref1 and the second power signal line VSS as a grid wiring, thereby improving the display effect of the display panel.

[0184] The driving method of the display panel provided by the embodiment of the present disclosure, as shown in FIG16 , includes the following steps when displaying at a first frequency:

[0185] S100, reset stage, the first control circuit responds to the signal on the first control signal line and provides the signal on the first reference voltage signal line to the first electrode of the driving transistor; the first reset circuit responds to the signal on the fifth control signal line and provides the signal on the first initialization signal line to the first control circuit; the second reset circuit responds to the signal on the first control signal line and provides the signal on the second initialization signal line to the light-emitting device;

[0186] S200, threshold voltage compensation stage: the first control circuit connects the gate of the driving transistor to the second electrode in response to the signal on the second control signal line and the third control signal line; the second control circuit provides the signal on the second reference voltage signal line to the first node in response to the signal on the fourth control signal line; the light emitting control circuit provides the signal on the first power supply signal line to the first electrode of the driving transistor in response to the signal on the first light emitting control signal line;

[0187] S300, data writing stage, the data writing circuit responds to the signal on the scan signal line and provides the data voltage signal on the data signal line to the first node; the second reset circuit responds to the signal on the first control signal line and provides the signal on the second initialization signal line to the light emitting device; the first control circuit responds to the signal on the first control signal line and provides the signal on the first reference voltage signal line to the first electrode of the driving transistor;

[0188] S400, in a biasing stage, the second reset circuit provides a signal on the second initialization signal line to the light-emitting device in response to a signal on the first control signal line; the first control circuit provides a signal on the first reference voltage signal line to the first electrode of the driving transistor in response to a signal on the first control signal line;

[0189] S500, in the light-emitting stage, the light-emitting control circuit responds to the signal on the first light-emitting control signal line, provides the signal on the first power signal line to the first electrode of the driving transistor, responds to the signal on the second light-emitting control signal line, connects the second electrode of the driving transistor to the light-emitting device, and drives the light-emitting device to emit light.

[0190] For example, the first frequency may be 120 Hz, 180 Hz, or 240 Hz, etc., which are not limited herein.

[0191] In some embodiments of the present disclosure, as shown in FIG17 , when a second frequency is used for display, where the second frequency is less than the first frequency, the following steps are included:

[0192] S600, in a biasing stage, the second reset circuit provides a signal on the second initialization signal line to the light-emitting device in response to a signal on the first control signal line; the first control circuit provides a signal on the first reference voltage signal line to the first electrode of the driving transistor in response to a signal on the first control signal line;

[0193] S700, in the light-emitting stage, the second control circuit responds to the signal on the fourth control signal line and provides the signal on the second reference voltage signal line to the first node; the light-emitting control circuit responds to the signal on the first light-emitting control signal line and provides the signal on the first power supply signal line to the first electrode of the driving transistor, and responds to the signal on the second light-emitting control signal line to connect the second electrode of the driving transistor to the light-emitting device, thereby driving the light-emitting device to emit light.

[0194] For example, the second frequency may be 1 Hz, etc., which is not limited here.

[0195] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG4 as an example and combining it with the signal timing diagram shown in FIG18 .

[0196] In some embodiments of the present disclosure, as shown in Figure 18, ss represents the scan signal on the scan signal line SS, cs1 represents the first control signal on the first control signal line CS1, cs2 represents the second control signal on the second control signal line CS2, cs3 represents the third control signal on the third control signal line CS3, cs4 represents the fourth control signal on the fourth control signal line CS4, cs5 represents the fifth control signal on the fifth control signal line CS5, em1 represents the first light-emitting control signal on the first light-emitting control signal line EM1, and em2 represents the second light-emitting control signal on the second light-emitting control signal line EM2.

[0197] Furthermore, a reset phase F1 , a threshold voltage compensation phase F2 , a data writing phase F3 , a bias phase F4 and a light emitting phase F5 in a display frame 1H are selected.

[0198] During the reset phase F1, the first transistor M1 is turned on by the low level of the first control signal cs1. The second transistor M2 is turned off by the high level of the second control signal cs2. The third transistor M3 is turned on by the high level of the third control signal cs3. The fourth transistor M4 is turned off by the low level of the fourth control signal cs4. The fifth transistor M5 is turned off by the low level of the scan signal ss. The sixth transistor M6 is turned off by the high level of the first emission control signal em1. The seventh transistor M7 is turned off by the high level of the second emission control signal em2. The eighth transistor M8 is turned on by the low level of the fifth control signal cs5. The ninth transistor M9 is turned on by the low level of the first control signal cs1. The first transistor M1 is turned on and provides the signal on the first reference voltage signal line Vref1 to the first electrode of the driving transistor M0; the eighth transistor M8 is turned on and provides the signal on the first initialization signal line Vinit1 to the second electrode of the third transistor M3 in the first control circuit 10; the third transistor M3 is turned on and connects the second electrode with the gate of the driving transistor M0, thereby providing the signal on the first initialization signal line Vinit1 to the gate of the driving transistor M0, resetting the gate of the driving transistor M0, and V g =V init1 , where V g Represents the gate voltage of the driving transistor M0, V init1 Represents the voltage on the first initialization signal line Vinit1; the turned-on ninth transistor M9 provides the signal on the second initialization signal line Vinit2 to the anode of the light-emitting device L, and resets the anode of the light-emitting device L. Then, V L =V init2 , where V L Represents the voltage of the anode of the light emitting device L, V init2 Represents the voltage on the second initialization signal line Vinit2.

[0199] In the first stage F21 of the threshold voltage compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1. The second transistor M2 is turned on under the control of the low level of the second control signal cs2. The third transistor M3 is turned on under the control of the high level of the third control signal cs3. The fourth transistor M4 is turned on under the control of the high level of the fourth control signal cs4. The fifth transistor M5 is turned off under the control of the low level of the scan signal ss. The sixth transistor M6 is turned on under the control of the low level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the second light-emitting control signal em2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal cs5. The ninth transistor M9 is turned off under the control of the high level of the first control signal cs1. The turned-on sixth transistor M6 provides the signal on the first power supply signal line VDD to the first electrode of the driving transistor M0; the turned-on second transistor M2 and the turned-on third transistor M3 turn the gate of the driving transistor M0 on to the second electrode to compensate for the threshold voltage Vth of the driving transistor. Then, V g =Vdd+Vth, where Vdd represents the voltage on the first power signal line VDD, and Vth represents the threshold voltage of the driving transistor; the turned-on fourth transistor M4 provides the signal on the second reference voltage signal line Vref2 to the first node N1, then, V N1 =V ref2 , where V N1 represents the voltage on the first node N1, V ref2 Represents the voltage on the second reference voltage signal line Vref2.

[0200] During the second stage F22 of the threshold voltage compensation stage F2, the first transistor M1 is turned off under the control of a high level of the first control signal cs1. The second transistor M2 is turned off under the control of a high level of the second control signal cs2. The third transistor M3 is turned on under the control of a high level of the third control signal cs3. The fourth transistor M4 is turned off under the control of a low level of the fourth control signal cs4. The fifth transistor M5 is turned off under the control of a low level of the scan signal ss. The sixth transistor M6 is turned on under the control of a low level of the first emission control signal em1. The seventh transistor M7 is turned off under the control of a high level of the second emission control signal em2. The eighth transistor M8 is turned on under the control of a low level of the fifth control signal cs5. The ninth transistor M9 is turned off under the control of a high level of the first control signal cs1. The conductive sixth transistor M6 provides the signal on the first power signal line VDD to the first electrode of the driving transistor M0; the conductive eighth transistor M8 provides the signal on the first initialization signal line Vinit1 to the second electrode of the third transistor M3 in the first control circuit 10; the conductive third transistor M3 connects the second electrode with the gate of the driving transistor M0, thereby providing the signal on the first initialization signal line Vinit1 to the gate of the driving transistor M0.

[0201] In the data writing phase F3, the first transistor M1 is turned on under the control of the low level of the first control signal cs1. The second transistor M2 is turned off under the control of the high level of the second control signal cs2. The third transistor M3 is turned off under the control of the low level of the third control signal cs3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal cs4. The fifth transistor M5 is turned on under the control of the high level of the scan signal ss. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the second light-emitting control signal em2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal cs5. The ninth transistor M9 is turned on under the control of the low level of the first control signal cs1. The turned-on first transistor M1 provides the signal on the first reference voltage signal line Vref1 to the first electrode of the driving transistor M0; the turned-on fifth transistor M5 provides the data voltage signal Vda on the data signal line DA to the first node N1, then V N1 =V da , where V da ; The first capacitor C1 couples the data voltage signal Vda of the first node N1 to the gate of the driving transistor M0, and the second capacitor C2 stabilizes the voltage on the first node N1 and the gate of the driving transistor M0; the turned-on ninth transistor M9 provides the signal on the second initialization signal line Vref2 to the light-emitting device L.

[0202] In the bias phase F4, the first transistor M1 is turned on under the control of the low level of the first control signal cs1. The second transistor M2 is turned off under the control of the high level of the second control signal cs2. The third transistor M3 is turned off under the control of the low level of the third control signal cs3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal cs4. The fifth transistor M5 is turned off under the control of the low level of the scan signal ss. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the second light-emitting control signal em2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal cs5. The ninth transistor M9 is turned on under the control of the low level of the first control signal cs1. The turned-on first transistor M1 provides the signal on the first reference voltage signal line Vref1 to the first electrode of the driving transistor M0, then V g =Vdd+Vth+V da -V ref1 , where V ref1 represents the voltage on the first reference voltage signal line Vref1; the turned-on ninth transistor M9 provides the signal on the second initialization signal line Vref2 to the light emitting device L.

[0203] During the light-emitting phase F5, the first transistor M1 is turned off by the high level of the first control signal cs1. The second transistor M2 is turned off by the high level of the second control signal cs2. The third transistor M3 is turned off by the low level of the third control signal cs3. The fourth transistor M4 is turned off by the low level of the fourth control signal cs4. The fifth transistor M5 is turned off by the low level of the scan signal ss. The sixth transistor M6 is turned on by the low level of the first light-emitting control signal em1. The seventh transistor M7 is turned on by the low level of the second light-emitting control signal em2. The eighth transistor M8 is turned off by the high level of the fifth control signal cs5. The ninth transistor M9 is turned off by the high level of the first control signal cs1. The turned-on sixth transistor M6 supplies the signal on the first power supply signal line VDD to the first electrode of the driving transistor M0. The turned-on seventh transistor M7 connects the second electrode of the driving transistor M0 to the light-emitting device L, supplying the drive current generated by the driving transistor M0 to the anode of the light-emitting device L. This drive current charges the anode of the light-emitting device L until the light-emitting device L emits stable light. The driving transistor M0 is in saturation working state, then V g =Vdd+Vth+V da -V ref1 , V gs =Vth+V da -V ref1 , where V gsRepresents the voltage difference between the gate and source of the driving transistor M0. The driving current I oled =β*(Vgs-Vth) 2 =β*(V da -V ref1 ) 2 , Where, l represents the length of the channel of the driving transistor M0, w represents the width of the channel of the driving transistor M0, C ox represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor M0 , and μ represents the mobility of the driving transistor M0 .

[0204] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG4 as an example in combination with the signal timing diagram shown in FIG19 .

[0205] In some embodiments of the present disclosure, as shown in Figure 19, ss represents the scan signal on the scan signal line SS, cs1 represents the first control signal on the first control signal line CS1, cs2 represents the second control signal on the second control signal line CS2, cs3 represents the third control signal on the third control signal line CS3, cs4 represents the fourth control signal on the fourth control signal line CS4, cs5 represents the fifth control signal on the fifth control signal line CS5, em1 represents the first light-emitting control signal on the first light-emitting control signal line EM1, and em2 represents the second light-emitting control signal on the second light-emitting control signal line EM2.

[0206] Furthermore, a reset phase F1 , a threshold voltage compensation phase F2 , a data writing phase F3 , a bias phase F4 and a light emitting phase F5 in a display frame 1H are selected.

[0207] In the bias phase F4, the first transistor M1 is turned on under the control of the low level of the first control signal cs1. The second transistor M2 is turned off under the control of the high level of the second control signal cs2. The third transistor M3 is turned off under the control of the low level of the third control signal cs3. The fourth transistor M4 is turned off under the control of the low level of the fourth control signal cs4. The fifth transistor M5 is turned off under the control of the low level of the scan signal ss. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the second light-emitting control signal em2. The eighth transistor M8 is turned off under the control of the high level of the fifth control signal cs5. The ninth transistor M9 is turned on under the control of the low level of the first control signal cs1. The turned-on first transistor M1 provides the signal on the first reference voltage signal line Vref1 to the first electrode of the driving transistor M0, then V g =Vdd+Vth+V da -V ref1The turned-on ninth transistor M9 provides the signal on the second initialization signal line Vref2 to the light emitting device L.

[0208] During the light-emitting phase F5, the first transistor M1 is turned off by the high level of the first control signal cs1. The second transistor M2 is turned off by the high level of the second control signal cs2. The third transistor M3 is turned off by the low level of the third control signal cs3. The fourth transistor M4 is turned off by the low level of the fourth control signal cs4. The fifth transistor M5 is turned off by the low level of the scan signal ss. The sixth transistor M6 is turned on by the low level of the first light-emitting control signal em1. The seventh transistor M7 is turned on by the low level of the second light-emitting control signal em2. The eighth transistor M8 is turned off by the high level of the fifth control signal cs5. The ninth transistor M9 is turned off by the high level of the first control signal cs1. The turned-on sixth transistor M6 supplies the signal on the first power supply signal line VDD to the first electrode of the driving transistor M0. The turned-on seventh transistor M7 connects the second electrode of the driving transistor M0 to the light-emitting device L, supplying the drive current generated by the driving transistor M0 to the anode of the light-emitting device L. This drive current charges the anode of the light-emitting device L until the light-emitting device L emits stable light. The driving transistor M0 is in saturation working state, then V g =Vdd+Vth+V da -V ref1 , V gs =Vth+V da -V ref1 The driving current I oled =β*(Vgs-Vth) 2 =β*(V da -V ref1 ) 2 ,

[0209] The present disclosure also provides a display device including the display panel provided in the present disclosure. The display device solves the problem in a similar manner to the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts are not repeated here.

[0210] In specific implementations, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, an electronic watch, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0211] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0212] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, wherein, Comprising: A substrate substrate including a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel circuit; The pixel circuit includes: A light-emitting device; A driving transistor coupled to the light-emitting device and configured to generate a driving current for driving the light-emitting device to emit light according to a data voltage signal; A first control circuit coupled to the driving transistor and configured to, in response to a signal on a first control signal line, provide a signal on a first reference voltage signal line to a first pole of the driving transistor, and in response to signals on a second control signal line and a third control signal line, conduct the gate and a second pole of the driving transistor; A second control circuit coupled to a first node and configured to, in response to a signal on a fourth control signal line, provide a signal on a second reference voltage signal line to the first node; A data writing circuit coupled to the first node and configured to, in response to a signal on a scan signal line, provide a data voltage signal on a data signal line to the first node; A coupling control circuit coupled to the gate of the driving transistor and the first node and configured to couple the data voltage signal of the first node to the gate of the driving transistor and stabilize the voltage of the first node; A light-emitting control circuit coupled to the driving transistor and the light-emitting device and configured to, in response to a signal on a first light-emitting control signal line, provide a signal on a first power supply signal line to a first pole of the driving transistor, and in response to a signal on a second light-emitting control signal line, conduct the second pole of the driving transistor and the light-emitting device to drive the light-emitting device to emit light.

2. The display panel according to claim 1, wherein, Further comprising: A first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate substrate; Wherein, the materials of the first semiconductor layer and the second semiconductor layer are different.

3. The display panel according to claim 2, wherein, The first control circuit includes: a first transistor, a second transistor, and a third transistor; The gate of the first transistor is coupled to the first control signal line, the first pole of the first transistor is coupled to the first pole of the driving transistor, and the second pole of the first transistor is coupled to the first reference voltage signal line; The gate of the second transistor is coupled to the second control signal line, the first pole of the second transistor is coupled to the second pole of the third transistor, and the second pole of the second transistor is coupled to the second pole of the driving transistor; The gate of the third transistor is coupled to the third control signal line, and the first pole of the third transistor is coupled to the gate of the driving transistor.

4. The display panel according to claim 3, wherein, The first semiconductor layer includes the active layer of the driving transistor, the active layer of the first transistor, and the active layer of the second transistor; the second semiconductor layer includes the active layer of the third transistor; The first conductive layer includes the gate of the driving transistor, the gate of the first transistor, and the gate of the second transistor; the second conductive layer and the third conductive layer include the gate of the third transistor.

5. The display panel according to any one of claims 2-4, wherein, The second control circuit includes: a fourth transistor; The gate of the fourth transistor is coupled to the fourth control signal line, a first pole of the fourth transistor is coupled to the first node, and a second pole of the fourth transistor is coupled to the second reference voltage signal line.

6. The display panel according to claim 5, wherein, The second semiconductor layer includes the active layer of the fourth transistor; the second conductive layer and the third conductive layer include the gate of the fourth transistor.

7. The display panel according to any one of claims 2-6, wherein, The data writing circuit includes: a fifth transistor; The gate of the fifth transistor is coupled to the scan signal line, a first pole of the fifth transistor is coupled to the data signal line, and a second pole of the fifth transistor is coupled to the first node.

8. The display panel according to claim 7, wherein, The second semiconductor layer includes the active layer of the fifth transistor; the second conductive layer and the third conductive layer include the gate of the fifth transistor.

9. The display panel according to any one of claims 2-8, wherein, The coupling control circuit includes: a first capacitor and a second capacitor; A first electrode plate of the first capacitor is coupled to the gate of the driving transistor, and a second electrode plate of the first capacitor is coupled to the first node; A first electrode plate of the second capacitor is coupled to the first power supply signal line, and a second electrode plate of the second capacitor is coupled to the first node.

10. The display panel according to claim 9, wherein, The first conductive layer includes the first electrode plate of the first capacitor and the first electrode plate of the second capacitor; the second conductive layer includes the second electrode plate of the first capacitor and the second electrode plate of the second capacitor; the third conductive layer includes the first electrode plate of the second capacitor; The first electrode plate of the first capacitor and the first electrode plate of the second capacitor located on the first conductive layer are spaced apart from each other; The second electrode plate of the first capacitor and the second electrode plate of the second capacitor located on the second conductive layer are an integral body; The orthographic projection of the first electrode plate of the first capacitor on the first conductive layer on the substrate overlaps with the orthographic projection of the second electrode plate of the first capacitor on the second conductive layer on the substrate; The orthographic projection of the first electrode plate of the second capacitor on the first conductive layer on the substrate overlaps with the orthographic projection of the second electrode plate of the second capacitor on the second conductive layer on the substrate; The orthographic projection of the first electrode plate of the second capacitor on the third conductive layer on the substrate completely overlaps with the orthographic projection of the second electrode plate of the second capacitor on the second conductive layer on the substrate; The orthographic projection of the first electrode plate of the second capacitor on the third conductive layer on the substrate partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the first conductive layer on the substrate.

11. The display panel according to any one of claims 2-10, wherein, The light emitting control circuit includes: a sixth transistor and a seventh transistor; The gate of the sixth transistor is coupled to the first light emitting control signal line, a first pole of the sixth transistor is coupled to the first power supply signal line, and a second pole of the sixth transistor is coupled to the first pole of the driving transistor; The gate of the seventh transistor is coupled to the second light emitting control signal line, a first pole of the seventh transistor is coupled to the second pole of the driving transistor, and a second pole of the seventh transistor is coupled to the light emitting device.

12. The display panel according to claim 11, wherein, The first semiconductor layer includes the active layers of the sixth transistor and the seventh transistor; the first conductive layer includes the gates of the sixth transistor and the seventh transistor.

13. The display panel according to any one of claims 2-12, wherein, The pixel circuit further includes: a first reset circuit, coupled to the first control circuit, configured to provide a signal on a first initialization signal line to the first control circuit in response to a signal on a fifth control signal line; a second reset circuit, coupled to the light-emitting device, configured to provide a signal on the first initialization signal line or a second initialization signal line to the light-emitting device in response to a signal on the first control signal line.

14. The display panel according to claim 13, wherein, The first reset circuit includes: an eighth transistor; The gate of the eighth transistor is coupled to the fifth control signal line, the first pole of the eighth transistor is coupled to the second pole of the third transistor, and the second pole of the eighth transistor is coupled to the first initialization signal line; The second reset circuit includes: a ninth transistor; The gate of the ninth transistor is coupled to the first control signal line, the first pole of the ninth transistor is coupled to the light-emitting device, and the second pole of the ninth transistor is coupled to the first initialization signal line or the second initialization signal line.

15. The display panel according to claim 14, wherein, The first semiconductor layer includes the active layer of the eighth transistor; the first conductive layer includes the gate of the eighth transistor; The first semiconductor layer includes the active layer of the ninth transistor; the first conductive layer includes the gate of the ninth transistor.

16. The display panel according to any one of claims 2-15, wherein, The signal lines in the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer extend in a first direction; the signal lines in the fifth conductive layer extend in a second direction.

17. The display panel according to claim 16, wherein, The first conductive layer includes the first control signal line and the fifth control signal line; The second conductive layer includes a first initialization signal line, the second light-emitting control signal line, and at least two of the first reference voltage signal lines; The third conductive layer includes a first light-emitting control signal line; The fourth conductive layer includes the scan signal line, the fourth control signal line, the second reference voltage signal line, the first power supply signal line, the third control signal line, the second control signal line, and the second initialization signal line; The fifth conductive layer includes the data signal line, the first power supply signal line, and the second reference voltage signal line, and the first power supply signal line is located between the data signal line and the second reference voltage signal line.

18. The display panel according to claim 17, wherein, The fourth conductive layer further includes a second power supply signal line; the second power supply signal line provides a second power supply signal to the light-emitting device; The fifth conductive layer further includes the first initialization signal line, the second initialization signal line, the first reference voltage signal line, and the second power supply signal line.

19. The display panel according to claim 18, wherein, The substrate further includes: a plurality of pixel units; each pixel unit includes three sub-pixels. The orthographic projections of the first sub-pixel and the second sub-pixel in the pixel unit on the substrate are symmetric about the orthographic projection of the second reference voltage signal line on the substrate, and the first sub-pixel and the second sub-pixel in the pixel unit share the second reference voltage signal line; The orthographic projections of the data signal line and the second reference voltage signal line on the substrate are located between the orthographic projections of the second sub-pixel and the third sub-pixel in the pixel unit on the substrate; There is the first initialization signal line or the second initialization signal line or the first reference voltage signal line or the second power supply signal line between two adjacent pixel units along the first direction.

20. The display panel according to claim 18, wherein, The first initialization signal line, the second initialization signal line, the first reference voltage signal line, and the second power supply signal line are alternately arranged in sequence along the first direction.

21. A driving method of a display panel according to any one of claims 1-20, wherein, Including: When displaying at the first frequency, including: Reset stage: The first control circuit responds to the signal on the first control signal line and provides the signal on the first reference voltage signal line to the first pole of the driving transistor; the first reset circuit responds to the signal on the fifth control signal line and provides the signal on the first initialization signal line to the first control circuit; the second reset circuit responds to the signal on the first control signal line and provides the signal on the second initialization signal line to the light-emitting device; Threshold voltage compensation stage: The first control circuit responds to the signals on the second control signal line and the third control signal line and conducts the gate and the second pole of the driving transistor; the second control circuit responds to the signal on the fourth control signal line and provides the signal on the second reference voltage signal line to the first node; the light-emitting control circuit responds to the signal on the first light-emitting control signal line and provides the signal on the first power supply signal line to the first pole of the driving transistor; Data writing stage: The data writing circuit responds to the signal on the scan signal line and provides the data voltage signal on the data signal line to the first node; the second reset circuit responds to the signal on the first control signal line and provides the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line and provides the signal on the first reference voltage signal line to the first pole of the driving transistor; Bias stage: The second reset circuit responds to the signal on the first control signal line and provides the signal on the second initialization signal line to the light-emitting device; the first control circuit responds to the signal on the first control signal line and provides the signal on the first reference voltage signal line to the first pole of the driving transistor; Light-emitting stage: The light-emitting control circuit responds to the signal on the first light-emitting control signal line and provides the signal on the first power supply signal line to the first pole of the driving transistor, and responds to the signal on the second light-emitting control signal line to conduct the second pole of the driving transistor and the light-emitting device, driving the light-emitting device to emit light.

22. The driving method of the display panel according to claim 21, wherein, Also including: When displaying at the second frequency, including: During the offset stage, the second reset circuit provides the signal on the second initialization signal line to the light-emitting device in response to the signal on the first control signal line; the first control circuit provides the signal on the first reference voltage signal line to the first pole of the driving transistor in response to the signal on the first control signal line. During the light-emitting stage, the light-emitting control circuit provides the signal on the first power supply signal line to the first pole of the driving transistor in response to the signal on the first light-emitting control signal line, and conducts the second pole of the driving transistor and the light-emitting device in response to the signal on the second light-emitting control signal line to drive the light-emitting device to emit light. Wherein, the second frequency is less than the first frequency.

23. A display device, wherein, The display panel according to any one of claims 1-20.

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