Pixel driving circuit and display panel

Abstract

A pixel driving circuit and a display panel. On the basis of a first scanning signal (Scan1) and a light-emission control signal (EM), an inverting control unit (201) controls the electric potential of a second node (N2) to be a voltage corresponding to a first voltage signal (VGH) or a second voltage signal (VGL), such that on the basis of the electric potential of the second node (N2), a pulse width control unit (202) increases a control speed for a signal transmission state between a first power source end (VDD_PWM) and a first node (N1), and on the basis of the electric potential of the first node (N1), a pulse amplitude modulation module (10) increases a control speed for a light-emission state of a light-emitting device (Di).

Description

Pixel driving circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] Using pulse amplitude modulation (PAM) to change the drive current to switch between grayscales can cause pitting in low-grayscale displays, affecting display uniformity. To improve display uniformity, Pulse Width Modulation (PWM) and Pulse Amplitude Modulation (PAM) technologies are used. PWM adjusts the drive current to switch grayscales when displaying high-grayscale images, and PWM adjusts the light-emission duration of the light-emitting device to switch grayscales when displaying low-grayscale images. However, PWM adjusts the light-emission duration by comparing the swept frequency signal with the PWM voltage to control the control terminal potential of the drive transistor in the PWM circuit. Consequently, the duration of the light-emitting device switching from bright to dark state is relatively long, taking up the actual light-emission time. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide a pixel driving circuit and a display panel, which can improve the problem that the time taken to control the switching of the light-emitting device from the bright state to the dark state is long, occupying the actual light-emitting time.

[0004] An embodiment of the present application provides a pixel driving circuit, comprising a light-emitting device, a pulse amplitude modulation module, and a pulse width modulation module. The pulse amplitude modulation module is electrically connected to the light-emitting device and a first node, and is configured to control the light-emitting state of the light-emitting device based on the potential of the first node. The pulse width modulation module includes an inverting control unit electrically connected to a second node, and a pulse width control unit electrically connected between the first node and the second node. The inverting control unit is configured to control the transmission of one of a first voltage signal and a second voltage signal to the second node based on a first scanning signal and a light-emitting control signal. The pulse width control unit is configured to control the transmission of a signal between a first power supply terminal and the first node based on the potential of the second node.

[0005] The present application also provides a display panel, comprising a plurality of sub-pixels, at least one of which comprises any of the above-mentioned pixel driving circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a working efficiency curve of a micro light emitting diode;

[0007] 2A to 2C are structural block diagrams of pixel driving circuits provided in embodiments of the present application;

[0008] 3A to 3D are schematic structural diagrams of a pixel driving circuit provided in an embodiment of the present application;

[0009] 4A and 4B are timing diagrams corresponding to the pixel driving circuit provided in an embodiment of the present application;

[0010] 5A to 5D are simulation timing diagrams provided in an embodiment of the present application;

[0011] FIG6 is a schematic structural diagram of a display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0012] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0013] The present application provides a pixel driving circuit and a display panel. A pulse width modulation module includes an inverting control unit and a pulse width control unit, so that the inverting control unit can control one of a first voltage signal and a second voltage signal to be transmitted to a second node based on a first scanning signal and a light-emitting control signal, thereby controlling the potential of the second node to be the voltage corresponding to the first voltage signal or the voltage corresponding to the second voltage signal. This eliminates the need for the potential of the second node to undergo a gradual change process. Furthermore, the pulse width control unit can increase the speed of controlling the signal transmission state between the first power supply terminal and the first node based on the potential of the second node, thereby increasing the speed of controlling the light-emitting state of the light-emitting device based on the potential of the first node. This improves the problem that the light-emitting device takes a long time to switch from a bright state to a dark state, occupying the actual light-emitting time.

[0014] Specifically, Figure 1 shows the operating efficiency curve of a micro-LED. The efficiency of a chip containing a micro-LED varies significantly across operating current ranges, especially in the low current range, where the efficiency fluctuation is particularly significant, leading to poor display uniformity on the display.

[0015] To improve the problem of poor display uniformity, the pixel drive circuit uses a pulse amplitude modulation method for driving. By changing the amplitude of the driving current that drives the light-emitting device to emit light, the display screen is controlled to switch between different display grayscales. However, the actual display screen at low current and low grayscale has a serious display pitting problem and poor display uniformity. Therefore, in addition to the pulse amplitude modulation method used for driving in the pixel drive circuit, a pulse width modulation method is further used for driving. When displaying high grayscales, the pulse amplitude modulation method is used to adjust the driving current to achieve switching between different grayscales of the display screen. When displaying low grayscales, the pulse width modulation method is used to adjust the pulse width of the driving current to achieve switching between different grayscales of the display screen.

[0016] However, when the pixel drive circuit uses a pulse amplitude modulation method combined with a pulse width modulation method for driving, the control terminal potential of the driving transistor included in the pulse width modulation module of the pixel drive circuit is gradually lowered by comparing the frequency sweep signal with the pulse width modulation voltage to adjust the pulse width of the driving current. As a result, when the light-emitting device switches from the bright state to the dark state, the falling edge of the control terminal potential of the driving transistor included in the pulse amplitude modulation module of the pixel drive circuit is larger, which in turn makes the switching time from the bright state to the dark state longer, which reduces the actual light emission time.

[0017] The following describes the problem of long switching time of light-emitting devices from bright state to dark state and improvement measures in combination with a specific pixel circuit structure.

[0018] Figures 2A through 2C are block diagrams of a pixel driver circuit according to an embodiment of the present application. The pixel driver circuit according to an embodiment of the present application includes a light-emitting device Di, a pulse amplitude modulation module 10, and a pulse width modulation module 20. The pulse amplitude modulation module 10 is electrically connected to the light-emitting device Di and is configured to receive a pulse amplitude modulation voltage signal D_PAM to control the pulse amplitude of the drive current that drives the light-emitting device Di to emit light. The pulse width modulation module 20 is electrically connected to the pulse amplitude modulation module 10 and is configured to receive a pulse width modulation voltage signal D_PWM and a sweep signal Sweep to control the pulse width of the drive current.

[0019] Figures 3A to 3D are schematic diagrams of the structure of the pixel driving circuit provided in an embodiment of the present application, Figures 4A to 4B are timing diagrams corresponding to the pixel driving circuit provided in an embodiment of the present application, and Figures 5A to 5D are simulation timing diagrams provided in an embodiment of the present application. Among them, Figure 4A is a timing diagram corresponding to the pixel driving circuit shown in Figure 3A, and Figure 4B is a timing diagram corresponding to the gate driving circuit shown in Figures 3B to 3D. Figure 5A is a simulation timing diagram corresponding to the pixel driving circuit shown in Figure 3A, Figures 5B to 5C are simulation timing diagrams corresponding to the pixel driving circuit shown in Figures 3B to 3C, and Figure 5D is a simulation timing diagram corresponding to the pixel driving circuit shown in Figure 3D.

[0020] Please refer to FIG. 2A . The pulse amplitude modulation module 10 includes first to sixth transistors T1 to T6 and a first storage capacitor Cs1 . The pulse width modulation module 20 includes first to twelfth transistors T1 to T12 and a second storage capacitor Cs2 .

[0021] The control terminal of the first transistor T1 is electrically connected to the output terminal of the second transistor T2, the output terminal of the third transistor T3, and the first terminal of the first storage capacitor Cs1. The input terminal of the first transistor T1 is electrically connected to the output terminal of the fourth transistor T4 and the output terminal of the fifth transistor T5. The output terminal of the first transistor T1 is electrically connected to the input terminal of the third transistor T3 and the input terminal of the sixth transistor T6. The input terminal of the second transistor T2 is configured to receive the reset signal Vi. The input terminal of the fourth transistor T4 is configured to receive the pulse amplitude modulated voltage signal D_PAM. The input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal VDD_PAM. The output terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting device Di. The cathode of the light-emitting device Di is electrically connected to the third power supply terminal VSS. The control terminal of the seventh transistor T7 is electrically connected to the output terminal of the eighth transistor T8, the output terminal of the ninth transistor T9, and the first terminal of the second storage capacitor Cs2. The input terminal of the seventh transistor T7 is electrically connected to the output terminal of the tenth transistor T10 and the output terminal of the eleventh transistor T11. The output terminal of the seventh transistor T7 is electrically connected to the input terminal of the ninth transistor T9 and the input terminal of the twelfth transistor T12. The input terminal of the eighth transistor T8 is configured to receive the reset signal Vi. The input terminal of the tenth transistor T10 is configured to receive the pulse width modulation voltage signal D_PWM. The input terminal of the eleventh transistor T11 and the second terminal of the first storage capacitor Cs1 are electrically connected to the first power supply terminal VDD_PWM. The output terminal of the twelfth transistor T12 is electrically connected to the control terminal of the first transistor T1. The control end of the second transistor T2 is configured to receive the first control signal PAM(n-1), the control end of the eighth transistor T8 is configured to receive the second control signal PWM(n-1), the control end of the third transistor T3 and the control end of the fourth transistor T4 are configured to receive the third control signal PAM(n), the control end of the ninth transistor T9 and the control end of the tenth transistor T10 are configured to receive the fourth control signal PWM(n), the control end of the fifth transistor T5 and the control end of the sixth transistor T6 are configured to receive the first light-emitting control signal EM_PAM, the control end of the eleventh transistor T11 and the control end of the twelfth transistor T12 are configured to receive the second light-emitting control signal EM_PWM, and the second end of the second storage capacitor Cs2 is configured to receive the sweep signal Sweep.

[0022] Taking the pixel driving circuit shown in FIG3A as an example in which the first transistor T1 to the twelfth transistor T12 are all P-type transistors, the working principle of the pixel driving circuit shown in FIG3A is explained in combination with the timing diagram shown in FIG4A. The working process of the pixel driving circuit includes a first stage t1 to a third stage t3.

[0023] In the first phase t1, the first control signal PAM(n-1) and the second control signal PWM(n-1) are in a low state, and the third control signal PAM(n), the fourth control signal PWM(n), the first light-emitting control signal EM_PAM, and the second light-emitting control signal EM_PWM are in a high state. The second transistor T2 and the eighth transistor T8 are turned on, and the reset signal Vi resets the potential of the control terminal of the first transistor T1 and the potential of the control terminal of the seventh transistor T7.

[0024] During the second phase t2, the third control signal PAM(n) and the fourth control signal PWM(n) are low, while the first control signal PAM(n-1), the second control signal PWM(n-1), the first emission control signal EM_PAM, and the second emission control signal EM_PWM are high. The first transistor T1, the third transistor T3, and the fourth transistor T4 are turned on, and the pulse-amplitude modulation voltage signal D_PAM compensates for the threshold voltage of the first transistor T1. The seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned on, and the pulse-width modulation voltage signal D_PWM compensates for the threshold voltage of the seventh transistor T7.

[0025] During the third phase t3, the first light-emission control signal EM_PAM and the second light-emission control signal EM_PWM are in a low state, while the first control signal PAM(n-1), the second control signal PWM(n-1), the third control signal PAM(n), and the fourth control signal PWM(n) are in a high state. The first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on to generate a driving current that drives the light-emitting device Di to emit light, thereby controlling the light-emitting device Di to emit light. Because the gate-source voltage difference of the seventh transistor T7 is greater than or equal to the threshold voltage of the seventh transistor T7, the seventh transistor T7 remains off. However, as the voltage of the sweep signal Sweep decreases, the potential of the control terminal of the seventh transistor T7 fluctuates through coupling with the second capacitor C2 until the gate-source voltage difference of the seventh transistor T7 is less than the threshold voltage of the seventh transistor T7. The seventh transistor T7 then turns on, and the first power supply terminal VDD_PWM is electrically connected to the control terminal of the first transistor T1. This causes the gate-source voltage difference of the first transistor T1 to be greater than or equal to the threshold voltage of the first transistor T1, turning off the first transistor T1 and stopping the light-emitting device Di from emitting light.

[0026] Therefore, according to the operating principle of the pixel driver circuit, when the sweep signal Sweep pulls down the potential of the control terminal of the seventh transistor T7, the voltage corresponding to the control terminal of the seventh transistor T7 is gradually reduced by coupling with the second storage capacitor Cs2, mainly based on the comparison between the sweep signal Sweep and the pulse-width modulation voltage signal D_PWM. As a result, the conduction speed of the seventh transistor T7 is relatively slow, resulting in a longer duration for the light-emitting device Di to switch from the bright state to the dark state. As shown in Figure 5A, a simulation analysis of the pixel driver circuit shown in Figure 2A shows that the duration corresponding to the light-emitting device Di switching from the bright state to the dark state is approximately 1ms, which greatly affects the actual light-emitting time ratio.

[0027] To improve the problem of a long duration corresponding to the switching of the light-emitting device Di from the bright state to the dark state, the present application further proposes a pixel driving circuit, as shown in Figures 2B to 2C. By making the pulse width modulation module 20 of the pixel driving circuit include an inverting control unit 201 and a pulse width control unit 202, the inverting control unit 201 is used to control one of the first voltage signal VGH and the second voltage signal VGL to be transmitted to the second node N2, thereby increasing the speed of change of the potential of the second node N2. Subsequently, the pulse width control unit 202 can increase the speed of controlling the signal transmission state between the first power supply terminal VDD_PWM and the first node N1 according to the potential of the second node N2, so that the pulse amplitude modulation module 10 can increase the speed of controlling the light-emitting state of the light-emitting device Di according to the potential of the first node N1, thereby improving the problem of the long duration corresponding to the switching of the light-emitting device Di from the bright state to the dark state, which occupies the actual light-emitting time.

[0028] Specifically, referring to Figures 2B-2C and 3B-3D, this application discloses a pixel driving circuit. The pulse amplitude modulation module 10 of the pixel driving circuit is electrically connected to the light-emitting device Di and a first node N1. The pulse amplitude modulation module 10 is configured to control the light-emitting state of the light-emitting device Di based on the potential of the first node N1. The pulse width modulation module 20 of the pixel driving circuit includes an inverting control unit 201 and a pulse width control unit 202. The inverting control unit 201 is electrically connected to a second node N2, and the pulse width control unit 202 is electrically connected between the first node N1 and the second node N2.

[0029] The inverting control unit 201 is configured to control one of the first voltage signal VGH and the second voltage signal VGL to be transmitted to the second node N2 based on the first scan signal Scan1 and the light-emission control signal EM. The pulse width control unit 202 is configured to control signal transmission between the first power supply terminal VDD_PWM and the first node N1 based on the potential of the second node N2. By configuring the inverting control unit 201 so that the voltage at the second node N2 corresponds to the voltage of the first voltage signal VGH or the voltage of the second voltage signal VGL, the pulse width control unit 202 can control the switching speed between the first node N1 and the first power supply terminal VDD_PWM to enable or disable signal transmission, thereby improving the speed at which the pulse amplitude modulation module 10 can control the light-emitting device Di to emit light or not, thereby alleviating the problem that the switching time from the bright state to the dark state of the light-emitting device Di is long, which takes up the actual light-emitting time.

[0030] Optionally, in some embodiments, the inverting control unit 201 can control one of the first voltage signal VGH and the second voltage signal VGL to be transmitted to the second node N2 based on the pulse-width modulation voltage signal D_PWM and the sweep signal Sweep. This reduces control complexity by continuing to use the pulse-width modulation voltage signal D_PWM and the sweep signal Sweep. Furthermore, by setting the pulse-width modulation voltage signal D_PWM to different voltages, switching between different light-emitting times can be achieved.

[0031] Continuing to refer to FIG. 2B to FIG. 2C , the inversion control unit 201 includes a first control unit 2011 and a second control unit 2012 .

[0032] The first control unit 2011 is electrically connected to the third node N3 and is configured to control one of the pulse width modulation voltage signal D_PWM and the sweep signal Sweep to couple the potential of the third node N3 according to the first scan signal Scan1 and the light emitting control signal EM.

[0033] The second control unit 2012 is electrically connected between the second node N2 and the third node N3, and is configured to control one of the first voltage signal VGH and the second voltage signal VGL to be transmitted to the second node N2 according to the potential of the third node N3.

[0034] Optionally, referring to FIG. 3B to FIG. 3D , the first control unit 2011 includes a first control transistor Tc1 , a second control transistor Tc2 , and a first capacitor C1 , and the second control unit 2012 includes a third control transistor Tc3 and a fourth control transistor Tc4 .

[0035] The control terminal of the first control transistor Tc1 is configured to receive the first scan signal Scan1 , and the input terminal of the first control transistor Tc1 is configured to receive a pulse width modulation voltage signal D_PWM.

[0036] The control end of the second control transistor Tc2 is configured to receive the light emitting control signal EM, the input end of the second control transistor Tc2 is configured to receive the sweep signal Sweep, and the output end of the second control transistor Tc2 is electrically connected to the output end of the first control transistor Tc1.

[0037] A first end of the first capacitor C1 is electrically connected to the output end of the first control transistor Tc1 , and a second end of the first capacitor C1 is electrically connected to the third node N3 .

[0038] The control end of the third control transistor Tc3 is electrically connected to the third node N3 , the input end of the third control transistor Tc3 is configured to receive the first voltage signal VGH, and the output end of the third control transistor Tc3 is electrically connected to the second node N2 .

[0039] The control terminal of the fourth control transistor Tc4 is electrically connected to the third node N3 , the input terminal of the fourth control transistor Tc4 is configured to receive the second voltage signal VGL, and the output terminal of the fourth control transistor Tc4 is electrically connected to the second node N2 .

[0040] Optionally, the third control transistor Tc3 is one of a P-type transistor and an N-type transistor, and the fourth control transistor Tc4 is the other of a P-type transistor and an N-type transistor.

[0041] Optionally, in some embodiments, the third control transistor Tc3 is a P-type transistor, and the fourth control transistor Tc4 is an N-type transistor. When the first control transistor Tc1 is turned on according to the first scan signal Scan1, the voltage corresponding to the pulse-width modulation voltage signal D_PWM is less than or equal to the sum of the voltage corresponding to the second voltage signal VGL and the threshold voltage of the fourth control transistor Tc4. Therefore, when the first control transistor Tc1 is turned on according to the first scan signal Scan1, the fourth control transistor Tc4 is turned off, so that the second voltage signal VGL is not transmitted to the second node N2, thereby causing the pulse-width control unit 202 to control the first power supply terminal VDD_PWM to be electrically disconnected from the first node N1.

[0042] Similarly, in some embodiments, the third control transistor Tc3 is an N-type transistor, and the fourth control transistor Tc4 is a P-type transistor. When the first control transistor Tc1 is turned on in response to the first scan signal Scan1, the voltage corresponding to the pulse-width modulation voltage signal D_PWM is greater than or equal to the sum of the voltage corresponding to the second voltage signal VGL and the threshold voltage of the fourth control transistor Tc4. This causes the fourth control transistor Tc4 to be turned off when the first control transistor Tc1 is turned on in response to the first scan signal Scan1, and causes the pulse-width control unit 202 to control the first power supply terminal VDD_PWM to be electrically disconnected from the first node N1.

[0043] Optionally, please continue to refer to Figures 3B to 3D. The pulse width control unit 202 includes a first driving transistor Tdr1, the control end of the first driving transistor Tdr1 is electrically connected to the second node N2, the input end of the first driving transistor Tdr1 is electrically connected to the first power supply end VDD_PWM, and the output end of the first driving transistor Tdr1 is electrically connected to the first node N1.

[0044] Optionally, the first driving transistor Tdr1 is a P-type transistor or an N-type transistor.

[0045] Optionally, in some embodiments, the first driving transistor Tdr1 is a P-type transistor, and the voltage corresponding to the first voltage signal VGH is greater than the voltage corresponding to the second voltage signal VGL, so that the first driving transistor Tdr1 is turned on when the fourth control transistor Tc4 is turned on.

[0046] Similarly, in some embodiments, the first driving transistor Tdr1 is an N-type transistor, and the voltage corresponding to the first voltage signal VGH is less than the voltage corresponding to the second voltage signal VGL, so that when the fourth control transistor Tc4 is turned on, the first driving transistor Tdr1 is turned on.

[0047] 3B to 3D , the pulse amplitude modulation module includes a driving unit configured to receive a pulse amplitude modulation voltage signal D_PAM to generate a driving current for driving the light emitting device Di to emit light.

[0048] Optionally, the driving unit includes a second driving transistor Tdr2 and a second capacitor C2.

[0049] The control end of the second driving transistor Tdr2 is electrically connected to the first node N1, the input end of the second driving transistor Tdr2 is electrically connected to the second power supply end VDD_PAM, and the output end of the second driving transistor Tdr2 is electrically connected to the light emitting device Di.

[0050] A first end of the second capacitor C2 is electrically connected to the control end of the second driving transistor Tdr2 , and a second end of the second capacitor C2 is electrically connected to the second power end VDD_PAM or the first power end VDD_PWM.

[0051] 3B to 3D , the pulse amplitude modulation module includes a data writing unit electrically connected to the driving unit. The data writing unit is configured to transmit the pulse amplitude modulation voltage signal D_PAM to the driving unit according to a second scan signal Scan2 .

[0052] Optionally, the data writing unit includes a data transistor Tda, the control end of the data transistor Tda is configured to receive the second scan signal Scan2, the input end of the data transistor Tda is configured to receive the pulse amplitude modulation voltage signal D_PAM, and the output end of the data transistor Tda is electrically connected to the input end of the second driving transistor Tdr2.

[0053] Continuing to refer to FIG. 3B to FIG. 3D , the pulse amplitude modulation module includes a compensation unit electrically connected to the driving unit. The compensation unit is configured to compensate for the threshold voltage of the second driving transistor Tdr2 according to the second scan signal Scan2 .

[0054] Optionally, the compensation unit includes a first compensation transistor Tc, the control end of the first compensation transistor Tc is configured to receive the second scan signal Scan2, the input end of the first compensation transistor Tc is electrically connected to the output end of the second driving transistor Tdr2, and the output end of the first compensation transistor Tc is electrically connected to the control end of the second driving transistor Tdr2.

[0055] 3B to 3D , the pulse amplitude modulation module includes a light emitting control unit electrically connected to the driving unit. The light emitting control unit is configured to control the generation of the driving current flow path according to a light emitting control signal EM.

[0056] Optionally, the light emitting control unit includes a first light emitting control transistor Te1 and a second light emitting control transistor Te2.

[0057] The control end of the first light-emitting control transistor Te1 is configured to receive the light-emitting control signal EM, the input end of the first light-emitting control transistor Te1 is electrically connected to the second power supply end VDD_PAM, and the output end of the first light-emitting control transistor Te1 is electrically connected to the input end of the second driving transistor Tdr2.

[0058] The control end of the second light emitting control transistor Te2 is configured to receive the light emitting control signal EM, the input end of the second light emitting control transistor Te2 is electrically connected to the control end of the second driving transistor Tdr2, and the output end of the second light emitting control transistor Te2 is electrically connected to the light emitting device Di.

[0059] 3B to 3D , the pulse amplitude modulation module includes a reset unit electrically connected to the driving unit. The reset unit is configured to reset the potential of the control terminal of the second driving transistor Tdr2 according to the first scanning signal Scan1 .

[0060] Optionally, the reset unit includes a reset transistor Ti, the control end of the reset transistor Ti is configured to receive the first scan signal Scan1, the input end of the reset transistor Ti is configured to receive the reset signal Vi, and the output end of the reset transistor Ti is electrically connected to the control end of the second drive transistor Tdr2.

[0061] Optionally, in some embodiments, when only the first driving transistor Tdr1 is provided between the first power terminal VDD_PWM and the first node N1, a leakage path may exist between the first node N1 and the first power terminal VDD_PWM when the first driving transistor Tdr1 is turned off, affecting the potential of the first node N1 and thus the brightness of the light-emitting device Di. Therefore, to improve the problem of leakage between the first node N1 and the first power terminal VDD_PWM affecting the potential of the first node N1, the pulse width control unit 202 includes a switching transistor. The switching transistor is configured to control the electrical connection between the first power terminal VDD_PWM and the first driving transistor Tdr1 according to the light-emitting control signal EM.

[0062] Optionally, please continue to refer to Figures 3C to 3D. The switching transistor includes a first switching transistor Ts1, the control end of the first switching transistor Ts1 is configured to receive the light-emitting control signal EM, the input end of the first switching transistor Ts1 is electrically connected to the first power supply end VDD_PWM, and the output end of the first switching transistor Ts1 is electrically connected to the input end of the first driving transistor Tdr1.

[0063] Optionally, the switch transistor is configured to control the electrical connection between the first driving transistor Tdr1 and the first node N1 according to the light emitting control signal EM.

[0064] Optionally, please continue to refer to Figures 3C to 3D. The switching transistor includes a second switching transistor Ts2, the control end of the second switching transistor Ts2 is configured to receive the light-emitting control signal EM, the input end of the second switching transistor Ts2 is electrically connected to the output end of the first driving transistor Tdr1, and the output end of the second switching transistor Ts2 is electrically connected to the first node N1.

[0065] Optionally, the first driver transistor, the reset transistor, and the compensation transistor may be silicon transistors or oxide transistors. Optionally, in some embodiments, the first driver transistor, the reset transistor, and the compensation transistor are oxide transistors, so as to utilize the low leakage current characteristics of oxide transistors to reduce leakage current between the first power supply terminal and the first node, reduce leakage current between the reset signal and the first node, and reduce leakage current between the output terminal and the control terminal of the second driver transistor.

[0066] Optionally, the first voltage signal VGH may be provided by a third power supply terminal, and the second voltage signal VGL may be provided by a fourth power supply terminal.

[0067] Taking the fourth control transistor Tc4 as an N-type transistor, the first control transistor Tc1 to the third control transistor Tc3, the first driving transistor Tdr1, the second driving transistor Tdr2, the first switching transistor Ts1, the second switching transistor Ts2, the data transistor Tda, the reset transistor Ti, the compensation transistor Tc, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 as P-type transistors as an example, the working principle of the pixel driving circuit shown in Figures 3B to 3C is explained using the timing shown in Figure 4B.

[0068] Phase 1 t1: The first scan signal Scan1 is in a low-level state, the second scan signal Scan2 and the emission control signal EM are in a high-level state. The first control transistor Tc1 and the reset transistor Ti are turned on. The pulse-width modulated voltage signal D_PWM is coupled to the potential of the third node N3 via the first capacitor C1, turning on the third control transistor Tc3. The first voltage signal VGH is transmitted to the second node N2, and the first drive transistor Tdr1 is turned off. The reset signal Vi is transmitted to the first node N1 to reset the potential of the first node N1.

[0069] Second stage t2: The second scan signal Scan2 is at a low level, the first scan signal Scan1 and the light-emitting control signal EM are at a high level, the data transistor Tda and the compensation transistor Tc are turned on, and the pulse amplitude modulation voltage signal D_PAM compensates the threshold voltage of the second driving transistor Tdr2.

[0070] In the third phase t3, the light-emission control signal EM is at a low level, and the first scan signal Scan1 and the second scan signal Scan2 are at a high level. The first and second light-emission control transistors Te1 and Te2 are turned on, and the second drive transistor Tdr2 generates a drive current to drive the light-emitting device Di to emit light. The second control transistor Tc2 is turned on, and the sweep signal Sweep is coupled to the potential of the third node N3 via the first capacitor C1. As the voltage corresponding to the sweep signal Sweep gradually increases, the potential of the third node N3 is also gradually coupled and increased until, when the voltage of the third node N3 and the voltage of the first voltage signal VGH are greater than the threshold voltage of the third control transistor Tc3, and the voltage of the third node N3 and the voltage of the first voltage signal VGH are greater than the threshold voltage of the fourth control transistor Tc4, the third control transistor Tc3 is turned off, the fourth control transistor Tc4 is turned on, and the second voltage signal VGL is transmitted to the second node N2, turning on the first drive transistor Tdr1, electrically connecting the first power supply terminal VDD_PWM to the first node N1, turning off the second drive transistor Tdr2, and the light-emitting device Di stops emitting light. In the pixel driving circuit shown in FIG3C , the first switching transistor Ts1 and the second switching transistor Ts2 are also turned on.

[0071] Therefore, according to the operating principles of the pixel driving circuit shown in Figures 3B to 3C, the voltage of the second node N2 corresponds to either the voltage of the first voltage signal VGH or the voltage of the second voltage signal VGL. Therefore, the potential of the control terminal of the first driving transistor Tdr1 changes faster, which can improve the problem of the long switching time of the light-emitting device Di from the bright state to the dark state.

[0072] Continuing with FIG5B , the inventors conducted simulations and verification of the pixel drive circuits shown in FIG3B through FIG3C . The simulation results demonstrate that the pixel drive circuit designs shown in FIG3B through FIG3C can optimize the duration of the light-emitting device Di switching from a bright state to a dark state to less than 0.1 ms. Compared to the pixel drive circuit design shown in FIG3A , where the duration of the light-emitting device Di switching from a bright state to a dark state is greater than 1 ms, the present application utilizes a pulse width modulation module 20 including an inverting control unit 201 and a pulse width control unit 202, thereby shortening the duration of the light-emitting device Di switching from a bright state to a dark state, achieving an optimization effect exceeding 90%.

[0073] When the pixel driving circuit is applied to a display panel, due to factors such as process technology, the switching performance of the transistors may vary, which may affect the display quality of the display panel. For example, if the switching performance of the fourth control transistor Tc4 varies, the timing at which different sub-pixels switch from receiving the first voltage signal VGH to receiving the second voltage signal VGL at the second node N2 may be inconsistent. As shown in FIG5C , when the threshold voltage of the fourth control transistor Tc4 drifts by ±0.5V, the emission time of different sub-pixels varies significantly, ultimately leading to poor brightness uniformity and affecting the display quality. L1 corresponds to a threshold voltage drift of +0.5V for the fourth control transistor Tc4, L2 corresponds to a threshold voltage drift of 0V for the fourth control transistor Tc4, and L3 corresponds to a threshold voltage drift of -0.5V for the fourth control transistor Tc4.

[0074] Therefore, to improve the problem of uneven light emission time caused by the threshold voltage drift of the fourth control transistor Tc4, the pulse width modulation module 20 of the pixel driving circuit further includes an inverting compensation unit 203, as shown in FIG2C . The inverting compensation unit 203 is electrically connected between the second node N2 and the third node N3, and is configured to control signal transmission between the second node N2 and the third node N3 according to the first scan signal Scan1.

[0075] Optionally, please continue to refer to Figure 3D. In some embodiments, the inverting compensation unit 203 includes an inverting compensation transistor Tc5, the control end of the inverting compensation transistor Tc5 is configured to receive the first scan signal Scan1, the input end of the inverting compensation transistor Tc5 is electrically connected to the third node N3, and the output end of the inverting compensation transistor Tc5 is electrically connected to the second node N2.

[0076] By controlling the inverting compensation transistor Tc5 to be turned on according to the first scanning signal Scan1 before the second control unit 2012 operates, the second node N2 and the third node N3 are short-circuited, so that the potentials of the third nodes N3 of the pixel driving circuits corresponding to different sub-pixels in the display panel tend to be consistent, so that when the scanning signal Sweep is coupled to the potential of the third node N3 through the first capacitor C1, the turn-on rates of the fourth control transistors Tc4 of the pixel driving circuits corresponding to different sub-pixels in the display panel tend to be consistent, thereby compensating for the problem of poor brightness uniformity caused by the different degrees of threshold voltage drift of the fourth control transistors Tc4 corresponding to different sub-pixels in the display panel.

[0077] Please continue to refer to Figure 5D. The inventors conducted simulation verification on the pixel driving circuit shown in Figure 3D. The simulation results show that when the threshold voltage of the fourth control transistor Tc4 drifts by ±0.5V, the light-emitting time of the light-emitting device Di of the pixel driving circuit corresponding to different sub-pixels remains almost unchanged, thereby improving the problem of poor brightness uniformity caused by the different threshold voltage drifts of the fourth control transistor Tc4 corresponding to different sub-pixels.

[0078] It can be understood that, based on the pixel driving circuit shown in FIG3B , the pixel driving circuit may still include the inverting compensation unit 203 , and the connection method of the inverting compensation transistor Tc5 included in the inverting compensation unit 203 may refer to the design in the pixel driving circuit shown in FIG3C .

[0079] Optionally, the pixel driving circuit further includes an initialization transistor, wherein a control terminal of the initialization transistor is configured to receive an initial control signal, an input terminal of the initialization transistor is configured to receive an initialization signal, and an output terminal of the initialization transistor is electrically connected to the anode of the light-emitting device Di. The initialization transistor is turned on in at least one of the first phase t1 and the second phase t2 to reset the anode potential of the light-emitting device Di.

[0080] FIG6 is a schematic structural diagram of a display panel provided in an embodiment of the present application. The present application further provides a display panel comprising a plurality of sub-pixels Pi, at least one of the sub-pixels Pi comprising any of the above-mentioned pixel driving circuits.

[0081] Optionally, the display panel includes a self-luminous display panel.

[0082] Optionally, the light emitting device Di includes at least one of an organic light emitting diode, a sub-millimeter light emitting diode and a micro light emitting diode.

[0083] The display panel includes a plurality of scan lines SL, a plurality of data lines DL, and a plurality of emission lines EML. The plurality of scan lines SL are configured to transmit a plurality of scan signals, the plurality of data lines DL are configured to transmit a plurality of modulation voltage signals, and the plurality of emission lines EML are configured to transmit a plurality of emission control signals EM. The plurality of scan signals include the first scan signal Scan1 and the second scan signal Scan2, and the plurality of modulation voltage signals include the pulse amplitude modulation voltage signal D_PAM and the pulse width modulation voltage signal D_PWM.

[0084] Optionally, the plurality of scan lines SL include a plurality of first scan lines SL1 and a plurality of second scan lines SL2 , the plurality of first scan lines SL1 are configured to transmit a plurality of first scan signals Scan1 , and the plurality of second scan lines SL2 are configured to transmit a plurality of second scan signals Scan2 .

[0085] Optionally, the display panel includes a gate driving unit, the gate driving unit includes a plurality of cascaded gate driving circuits, and the plurality of gate driving circuits are configured to generate a plurality of the scanning signals.

[0086] Optionally, the sub-pixel Pi located in the nth row is electrically connected to the n-1th-stage gate driving circuit and the nth-stage gate driving circuit, so that the first scanning signal Scan1 received by the first control transistor Tc1 of the sub-pixel Pi located in the nth row corresponds to the n-1th-stage scanning signal output by the n-1th-stage gate driving circuit, and the second scanning signal Scan2 received by the data transistor Tda of the sub-pixel Pi located in the nth row corresponds to the nth-stage scanning signal output by the nth-stage gate driving circuit, where n>1.

[0087] Optionally, the display panel further includes at least one sweep line SWL, and the sweep line SWL is configured to transmit the sweep signal Sweep.

[0088] Optionally, the plurality of sub-pixels Pi share a sweep signal Sweep and a light control signal EM, and the plurality of sub-pixels Pi each undergoes the first stage t1 and the second stage t2 shown in FIG4B , and then jointly undergoes the third stage t3 shown in FIG4B .

[0089] Optionally, when the display panel displays at a high grayscale, the display brightness is primarily determined by the magnitude of the driving current, i.e., it is controlled solely by the pulse amplitude modulation module 10 (the magnitude of the current flowing through the light-emitting device Di can be varied by writing different pulse amplitude modulation voltage signals D_PAM). Therefore, when the display panel displays at a high grayscale, to ensure a constant light-emitting duration, the first driving transistor Tdr1 is turned off, and signal transmission between the first power supply terminal VDD_PWM and the first node N1 is disconnected.

[0090] Accordingly, the third control transistor Tc3 is a P-type transistor, and the fourth control transistor Tc4 is an N-type transistor. When the display panel displays at a high grayscale, the voltage corresponding to the pulse-width modulation voltage signal D_PWM is less than or equal to the sum of the voltage corresponding to the second voltage signal VGL and the threshold voltage of the fourth control transistor Tc4, so that the fourth control transistor Tc4 is turned off when the display panel displays at a high grayscale, thereby turning off the first drive transistor Tdr1.

[0091] Similarly, in some embodiments, the third control transistor Tc3 is an N-type transistor, and the fourth control transistor Tc4 is a P-type transistor. When the display panel displays at a high grayscale, the voltage corresponding to the pulse-width modulation voltage signal D_PWM is greater than or equal to the sum of the voltage corresponding to the second voltage signal VGL and the threshold voltage of the fourth control transistor Tc4, so that the fourth control transistor Tc4 and the first driving transistor Tdr1 are turned off when the display panel displays at a high grayscale.

[0092] Optionally, when the display panel is displaying at a low grayscale, to ensure stable luminous efficiency of the light-emitting device Di, the light-emitting duration is adjusted while maintaining a constant current, thereby varying the brightness. Specifically, the pulse amplitude modulation module 10 is used to maintain a constant driving current, while the pulse width modulation module 20 acts on the pulse amplitude modulation module 10 (i.e., controls the first drive transistor Tdr1 to be on or off, thereby enabling or disabling signal transmission between the first node N1 and the first power supply terminal VDD_PWM) to control the pulse amplitude modulation module 10 to prematurely shut down the light-emitting device Di, thereby varying the light-emitting duration of the light-emitting device Di.

[0093] The pixel drive circuit and display panel provided in the embodiments of the present application, by including an inverting control unit 201 and a pulse width control unit 202 in the pulse width modulation module 20, improve the speed of change of the potential of the second node N2 and the actual light-emitting duty cycle. This improves the problem of the light-emitting device Di taking a long time to switch from a bright state to a dark state, which takes up the actual light-emitting time, thereby improving display uniformity. By including an inverting compensation unit 203 in the pulse width modulation module 20, the problem of poor display uniformity caused by different threshold voltage drifts of the fourth control transistor Tc4 in different sub-pixels Pi is improved.

[0094] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A pixel driving circuit, wherein, Comprising: A light-emitting device; A pulse amplitude modulation module, electrically connected to the light-emitting device and a first node, and configured to control the light-emitting state of the light-emitting device according to the potential of the first node; A pulse width modulation module, including an inverting control unit electrically connected to a second node and a pulse width control unit electrically connected between the first node and the second node, where the inverting control unit is configured to control one of a first voltage signal and a second voltage signal to be transmitted to the second node according to a first scan signal and a light-emitting control signal, and the pulse width control unit is configured to control the signal transmission between a first power supply terminal and the first node according to the potential of the second node.

2. The pixel driving circuit according to claim 1, wherein, The inverting control unit includes: A first control unit, electrically connected to a third node, and configured to control one of a pulse width modulation voltage signal and a frequency sweep signal to couple the potential of the third node according to the first scan signal and the light-emitting control signal; A second control unit, electrically connected between the second node and the third node, and configured to control one of the first voltage signal and the second voltage signal to be transmitted to the second node according to the potential of the third node.

3. The pixel driving circuit according to claim 2, wherein, The first control unit includes a first control transistor, a second control transistor, and a first capacitor; a control terminal of the first control transistor is configured to receive the first scan signal, and an input terminal of the first control transistor is configured to receive the pulse width modulation voltage signal; A control terminal of the second control transistor is configured to receive the light-emitting control signal, an input terminal of the second control transistor is configured to receive the frequency sweep signal, an output terminal of the second control transistor, a first end of the first capacitor are electrically connected to an output terminal of the first control transistor, and a second end of the first capacitor is electrically connected to the third node; The second control unit includes a third control transistor and a fourth control transistor, a control terminal of the third control transistor is electrically connected to the third node, an input terminal of the third control transistor is configured to receive the first voltage signal, and an output terminal of the third control transistor is electrically connected to the second node; a control terminal of the fourth control transistor is electrically connected to the third node, an input terminal of the fourth control transistor is configured to receive the second voltage signal, and an output terminal of the fourth control transistor is electrically connected to the second node.

4. The pixel driving circuit according to claim 3, wherein, The third control transistor is a P-type transistor, and the fourth control transistor is an N-type transistor; Wherein, when the first control transistor is turned on according to the first scan signal, the voltage corresponding to the pulse width modulation voltage signal is less than or equal to the sum of the voltage corresponding to the second voltage signal and the threshold voltage of the fourth control transistor.

5. The pixel driving circuit according to claim 2, wherein, The pulse width modulation module further includes: An inverting compensation unit, electrically connected between the second node and the third node, and configured to control the signal transmission between the second node and the third node according to the first scan signal.

6. The pixel driving circuit according to claim 5, wherein The inverting compensation unit includes: An inverting compensation transistor, wherein a control terminal of the inverting compensation transistor is configured to receive the first scan signal, an input terminal of the inverting compensation transistor is electrically connected to the third node, and an output terminal of the inverting compensation transistor is electrically connected to the second node.

7. The pixel driving circuit according to claim 1, wherein the pulse width control unit includes a first driving transistor, a control terminal of the first driving transistor is electrically connected to the second node, an input terminal of the first driving transistor is electrically connected to the first power supply terminal, and an output terminal of the first driving transistor is electrically connected to the first node.

8. The pixel driving circuit according to claim 7, wherein, The pulse width control unit includes: a first switching transistor, a control terminal of the first switching transistor is configured to receive the light emission control signal, an input terminal of the first switching transistor is electrically connected to the first power supply terminal, and an output terminal of the first switching transistor is electrically connected to the input terminal of the first driving transistor; and a second switching transistor, a control terminal of the second switching transistor is configured to receive the light emission control signal, an input terminal of the second switching transistor is electrically connected to the output terminal of the first driving transistor, and an output terminal of the second switching transistor is electrically connected to the first node.

9. The pixel driving circuit according to claim 7, wherein, The pulse amplitude modulation module includes: a second driving transistor, a control terminal of the second driving transistor is electrically connected to the first node; a data transistor, a control terminal of the data transistor is configured to receive a second scan signal, an input terminal of the data transistor is configured to receive a pulse amplitude modulation voltage signal, and an output terminal of the data transistor is electrically connected to the input terminal of the second driving transistor; a reset transistor, a control terminal of the reset transistor is configured to receive the first scan signal, an input terminal of the reset transistor is configured to receive a reset signal, and an output terminal of the reset transistor is electrically connected to the control terminal of the second driving transistor; a first compensation transistor, a control terminal of the first compensation transistor is configured to receive the second scan signal, an input terminal of the first compensation transistor is electrically connected to the output terminal of the second driving transistor, and an output terminal of the first compensation transistor is electrically connected to the control terminal of the second driving transistor; a first light emission control transistor, a control terminal of the first light emission control transistor is configured to receive the light emission control signal, an input terminal of the first light emission control transistor is electrically connected to a second power supply terminal, and an output terminal of the first light emission control transistor is electrically connected to the input terminal of the second driving transistor; a second light emission control transistor, a control terminal of the second light emission control transistor is configured to receive the light emission control signal, an input terminal of the second light emission control transistor is electrically connected to the control terminal of the second driving transistor, and an output terminal of the second light emission control transistor is electrically connected to the light emitting device; and a second capacitor, a first end of the second capacitor is electrically connected to the control terminal of the second driving transistor, and a second end of the second capacitor is electrically connected to the second power supply terminal.

10. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit includes: Initialize a transistor. The control terminal of the initialization transistor is configured to receive an initial control signal, the input terminal of the initialization transistor is configured to receive an initialization signal, and the output terminal of the initialization transistor is electrically connected to the anode of the light-emitting device.

11. A display panel, wherein, It includes a plurality of sub-pixels, and at least one of the sub-pixels includes a pixel driving circuit including: A light-emitting device; A pulse amplitude modulation module, electrically connected to the light-emitting device and a first node, and configured to control the light-emitting state of the light-emitting device according to the potential of the first node; A pulse width modulation module, including an inverting control unit electrically connected to a second node and a pulse width control unit electrically connected between the first node and the second node. The inverting control unit is configured to control one of a first voltage signal and a second voltage signal to be transmitted to the second node according to a first scan signal and a light-emitting control signal, and the pulse width control unit is configured to control the signal transmission between a first power supply terminal and the first node according to the potential of the second node.

12. The display panel according to claim 11, wherein, The inverting control unit includes: A first control transistor, the control terminal of the first control transistor is configured to receive the first scan signal, and the input terminal of the first control transistor is configured to receive a pulse width modulation voltage signal; A second control transistor, the control terminal of the second control transistor is configured to receive the light-emitting control signal, and the input terminal of the second control transistor is configured to receive a frequency sweep signal; A third control transistor, the control terminal of the third control transistor is electrically connected to a third node, the input terminal of the third control transistor is configured to receive the first voltage signal, and the output terminal of the third control transistor is electrically connected to the second node; A fourth control transistor, the control terminal of the fourth control transistor is electrically connected to the third node, the input terminal of the fourth control transistor is configured to receive the second voltage signal, and the output terminal of the fourth control transistor is electrically connected to the second node; and A first capacitor, the first end of the first capacitor is electrically connected to the output terminal of the first control transistor and the output terminal of the second control transistor, and the second end of the first capacitor is electrically connected to the third node.

13. The display panel according to claim 12, wherein, The third control transistor is a P-type transistor, and the fourth control transistor is an N-type transistor; Wherein, when the first control transistor is turned on according to the first scan signal, the voltage corresponding to the pulse width modulation voltage signal is less than or equal to the sum of the voltage corresponding to the second voltage signal and the threshold voltage of the fourth control transistor.

14. The display panel according to claim 12, wherein, The pulse width modulation module further includes: An inverting compensation transistor, the control terminal of the inverting compensation transistor is configured to receive the first scan signal, the input terminal of the inverting compensation transistor is electrically connected to the third node, and the output terminal of the inverting compensation transistor is electrically connected to the second node.

15. The display panel according to claim 11, wherein, The pulse width control unit includes: A first driving transistor, a control terminal of the first driving transistor is electrically connected to the second node, an input terminal of the first driving transistor is electrically connected to the first power supply terminal, and an output terminal of the first driving transistor is electrically connected to the first node; A first switching transistor, a control terminal of the first switching transistor is configured to receive the light emission control signal, an input terminal of the first switching transistor is electrically connected to the first power supply terminal, and an output terminal of the first switching transistor is electrically connected to the input terminal of the first driving transistor; and A second switching transistor, a control terminal of the second switching transistor is configured to receive the light emission control signal, an input terminal of the second switching transistor is electrically connected to the output terminal of the first driving transistor, and an output terminal of the second switching transistor is electrically connected to the first node.

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