Prefetching method and apparatus, electronic device, and readable storage medium

Abstract

Embodiments of the present application relate to the technical field of computers, and provide a prefetching method and apparatus, an electronic device, and a readable storage medium. The method comprises: when a first cache block corresponding to a memory access address exists in a cache, determining whether a target pointer exists in the first cache block, wherein said target pointer points to an address space in which a cache miss occurs in a historical period; if the target pointer pointing to the address space in which a cache miss occurs in the historical period exists in the first cache block, increasing the value of a first parameter of the first cache block by n; and performing continuous prefetching by taking the target pointer in the first cache block as a trigger starting point for prefetching, and stopping the prefetching operation until a prefetching termination condition is met.

Description

Prefetching method, device, electronic device and readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 15, 2024, with application number 202410057634.4 and titled “A Prefetching Method, Device, Electronic Device and Readable Storage Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a prefetching method, device, electronic device, and readable storage medium. Background Art

[0004] As processor speeds continue to increase, the gap between processor speed and data access speed continues to widen, creating a memory wall problem that has become a bottleneck restricting further processor performance. To address this problem, it is necessary to identify patterns in memory access sequences based on application memory access behavior and predict future data reads and writes. This allows the processor to pre-load data into the cache before it is used, thereby reducing memory access latency when the processor accesses this data in the future.

[0005] Pointer is a common addressing method in applications. It is commonly found in data structures such as linked lists and graphs that are commonly used in applications. Specifically, the virtual address of the target object (such as a node in a linked list or graph) can be stored in the memory as data, which serves as a pointer to the target object. When the target object needs to be accessed, the pointer is first retrieved, and then the target object is accessed based on the pointer.

[0006] However, the address of the pointer itself and the address it points to are usually unrelated. For example, in a graph data structure, pointers are used to link different nodes in the graph. The relationship between these nodes depends on the topological characteristics of the graph itself, and it is impossible to directly observe the exploitable patterns from spatial changes. The indirect nature of pointer addressing leads to a low cache hit rate and long data access latency for the data pointed to by the pointer, hindering the improvement of processor performance.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a prefetching method, device, electronic device and readable storage medium, which can solve the problems of cache hit rate and long data access delay in the pointer-based prefetching process in related technologies, which hinder the improvement of processor performance.

[0009] The present application discloses a prefetching method, which is applied to a cache. The method includes:

[0010] Receive a memory access request sent by a processor, and obtain a memory access address carried in the memory access request;

[0011] If a first cache block corresponding to the memory access address exists in the cache, scanning the first cache block to determine whether there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period;

[0012] If the first cache block contains a target pointer pointing to an address space in which a cache miss has occurred in a historical period, the value of a first parameter of the first cache block is increased by n; the first parameter is used to indicate a prefetch depth corresponding to the cache block, and a starts at a value a; n is a positive integer, and a is a natural number;

[0013] Taking the target pointer in the first cache block as the triggering starting point of prefetching, continuous prefetching is performed until a prefetching termination condition is satisfied, and then the prefetching operation is stopped; each time a prefetch is triggered, the value of the first parameter is increased by n;

[0014] The pre-fetch termination condition includes at least one of the following:

[0015] The value of the first parameter is greater than a first threshold;

[0016] There is no target pointer in the prefetched data block pointing to the address space where a cache miss occurred in the historical cycle.

[0017] On the other hand, an embodiment of the present application discloses a prefetching device, which is applied to a cache, and the device includes:

[0018] A receiving module, configured to receive a memory access request sent by a processor and obtain a memory access address carried in the memory access request;

[0019] a determining module configured to, if a first cache block corresponding to the memory access address exists in the cache, scan the first cache block to determine whether there is a target pointer in the first cache block pointing to an address space in which a cache miss has occurred in a historical period;

[0020] a calculation module configured to, if the first cache block contains a target pointer pointing to an address space in which a cache miss has occurred in a historical period, add n to the value of a first parameter of the first cache block; the first parameter is used to indicate a prefetch depth corresponding to the cache block, and a starts at a value a; n is a positive integer, and a is a natural number;

[0021] a prefetch module, configured to perform continuous prefetching with the target pointer in the first cache block as a triggering starting point for prefetching, and to stop the prefetching operation when a prefetching termination condition is satisfied; and each time a prefetch is triggered, the value of the first parameter is increased by n;

[0022] The pre-fetch termination condition includes at least one of the following:

[0023] The value of the first parameter is greater than a first threshold;

[0024] There is no target pointer in the prefetched data block pointing to the address space where a cache miss occurred in the historical cycle.

[0025] On the other hand, an embodiment of the present application further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned prefetching method.

[0026] An embodiment of the present application further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the aforementioned pre-fetching method.

[0027] The embodiment of the present application further discloses a pre-fetching apparatus / device, including the apparatus / device (configured to) be used to execute steps to implement the aforementioned pre-fetching method.

[0028] The embodiments of the present application include the following advantages:

[0029] An embodiment of the present application provides a prefetching method. When a first cache block corresponding to a memory access address carried in a memory access request exists in a cache, and a target pointer pointing to an address space where a cache miss has occurred in a historical period exists in the first cache block, continuous prefetching is performed using the target pointer in the first cache block as a triggering starting point for prefetching. According to the principle of program locality, an address space that has recently experienced a cache miss is more likely to experience a cache miss again. The pointer in the first cache block pointing to the address space where a cache miss has occurred in a historical period is determined as a target pointer, and continuous prefetching is performed using the target pointer as a triggering starting point for prefetching. This can improve the cache hit rate of data blocks prefetched into the cache. In addition, when the value of a first parameter of the prefetched data block is greater than a first threshold and / or when the prefetched data block does not contain a target pointer pointing to an address space where a cache miss has occurred in a historical period, the prefetching operation is stopped. This can avoid the problem of continuing to issue multiple erroneous prefetches in the event of a prefetch error, which would cause cache storage space pollution and memory bandwidth occupation. This improves the speed of data access and reduces the impact of the gap between the processor's operating speed and data access speed on computer system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] FIG1 is a flowchart of a prefetching method embodiment of the present application;

[0032] FIG2 is a logical diagram of a continuous prefetching of the present application;

[0033] FIG3 is a logical diagram of another continuous prefetching of the present application;

[0034] FIG4 is a schematic diagram of a process for determining a target pointer according to the present application;

[0035] FIG5 is a logic block diagram of a prefetching method of the present application;

[0036] FIG6 is a structural block diagram of a prefetching device of the present application;

[0037] FIG7 is a structural block diagram of an electronic device for prefetching provided by an example of this application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0040] Method Example

[0041] 1 , a flowchart of a prefetching method embodiment of the present application is shown. The method may specifically include the following steps:

[0042] Step 101: Receive a memory access request sent by a processor, and obtain a memory access address carried in the memory access request.

[0043] Step 102: If a first cache block corresponding to the memory access address exists in the cache, scan the first cache block to determine whether there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period.

[0044] Step 103: If there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period, add n to the value of a first parameter of the first cache block; the first parameter is used to indicate a prefetch depth corresponding to the cache block, and the starting value of the first parameter is a.

[0045] Step 104 : Using the target pointer in the first cache block as the triggering starting point for prefetching, perform continuous prefetching until a prefetching termination condition is met, then stop the prefetching operation; each time a prefetch is triggered, the value of the first parameter is increased by n.

[0046] The pre-fetch termination condition includes at least one of the following:

[0047] The value of the first parameter is greater than a first threshold;

[0048] There is no target pointer in the prefetched data block pointing to the address space where a cache miss occurred in the historical cycle.

[0049] The prefetching method provided in the embodiments of the present application can be applied to a cache. A cache is a cache area that exists between the memory and the processor. Because the processor's computing speed is very fast, but the memory access speed is relatively slow, a storage wall problem exists between the processor and the memory. If the processor has to read data from the memory every time, it will cause a lot of waiting time, reducing the overall performance of the processor. By introducing a cache between the processor and the memory, a data cache layer can be established between the processor and the memory, and the processor's most frequently used data can be prefetched into the cache for fast access by the processor.

[0050] In the process of prefetching data from memory into the cache, it is generally necessary to identify the hidden patterns in the memory access sequence and predict the data that will be read and written in the future based on the patterns of the application's memory access behavior, and pre-fetch the data into the cache before the data is used by the processor. However, the indirect nature of pointer addressing leads to a low cache hit rate for the data pointed to by the pointer, resulting in frequent long-latency data access, which in turn hinders the improvement of processor performance. In order to solve this problem, in an embodiment of the present application, when the memory access address hits the first cache block in the cache, the target pointer in the first cache block pointing to the address space where the cache miss occurred in the historical period is used as the trigger starting point for prefetching, and continuous prefetching is performed, which can improve the cache hit rate of the prefetched data block; when the first parameter of the prefetched data block is greater than the first threshold or there is no target pointer pointing to the address space where the cache miss occurred in the historical period in the prefetched data block, the prefetch operation is stopped, and it can also avoid continuing to issue multiple erroneous prefetches in the case of prefetch errors, causing cache storage space pollution and memory bandwidth occupation, which is beneficial to improving the data access speed of the processor, improving the performance of the processor, and reducing the impact of the gap between the processor's computing speed and data access speed on the performance of the computer system.

[0051] Specifically, when the cache receives a memory access request sent by the processor, it can first determine whether there is a first cache block corresponding to the memory access address carried in the memory access request in the cache block currently stored in the cache, and when the first cache block exists in the cache, further determine whether there is a target pointer in the first cache block pointing to the address space where a cache miss has occurred in the historical cycle. Only when the target pointer exists in the first cache block, the cache will use the target pointer as the trigger starting point for prefetching and perform continuous prefetching. That is, only when the first cache block in the cache is hit and there is a target pointer in the first cache block pointing to the address space where a cache miss has occurred in the historical cycle, the cache will perform continuous prefetching based on the target pointer. It can be understood that if the cache block in the cache is not hit or the target pointer does not exist in the first cache that is hit, continuous prefetching will not be triggered. During the continuous prefetching process, if the value of the first parameter of the prefetched data block is greater than the first threshold or there is no target pointer in the prefetched data block pointing to the address space where a cache miss has occurred in the historical period, the prefetching operation is stopped. According to the locality principle of the program, the target pointer is determined and continuous prefetching is performed based on the target pointer, which can improve the cache hit rate of the prefetched data block in the cache. If the cache block in the cache is not hit, or the prefetch termination condition is met during the continuous prefetching process, the prefetching operation is stopped. This can avoid continuing to issue multiple erroneous prefetches in the event of a prefetch error, resulting in erroneous prefetching operations occupying memory bandwidth and erroneous prefetched data blocks being stored in the cache, causing cache storage space pollution, thereby reducing the probability of erroneous prefetching, improving the cache hit rate of the cache, and further improving the speed of data access, and reducing the impact of the gap between the processor's computing speed and data access speed on the performance of the computer system.

[0052] In the embodiments of the present application, the processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a field programmable gate array (FPGA), and a processing module or processing unit in an application specific integrated circuit (ASIC).

[0053] In the embodiment of the present application, the data blocks pre-fetched and backfilled into the cache are cache blocks in the cache, wherein the first cache block may be any cache block in the cache.

[0054] When the cache obtains the memory access address carried in the memory access request, it can search the cache for a cache block that matches the memory access address. If a first cache block that matches the memory access address exists in the cache, before returning the first cache block to the processor, the first cache block can be scanned in step 102 to determine whether there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical cycle, and the first cache block can be returned to the processor after step 102. If the first cache block that matches the memory access address does not exist in the cache, it is necessary to search for a data block that matches the memory access address in a downstream node, read the found data block from the downstream node, and backfill it into the cache.

[0055] Among them, when the cache is specifically a first-level cache, the downstream node is a second-level cache; when the cache is specifically a second-level cache, the downstream node is a third-level cache; when the cache is specifically a third-level cache, the downstream node is a system-level cache or memory.

[0056] The historical period can be a time period (for example, the recent 1024 clock cycles can be used as a historical period), or a memory access count period (for example, the recent 256 memory accesses can be used as a historical period). This embodiment of the present application does not limit this.

[0057] A cache miss refers to the absence of the first cache block corresponding to the memory access address in the cache. Specifically, the cache may scan and obtain a virtual address in the first cache block when the memory access address hits the first cache block; if the virtual address exists in the first cache block, it is determined that a pointer exists in the first cache block, and the virtual address is the pointer; if the virtual address does not exist in the first cache block, it is determined that the pointer does not exist in the first cache block, and it is determined that the target pointer does not exist in the first cache block; if the pointer exists in the first cache block, the virtual address is matched with the memory access address corresponding to the address space where a cache miss occurred in the historical cycle; if the virtual address in the first cache block matches the memory access address corresponding to any address space where a cache miss occurred in the historical cycle, the virtual address is determined as the target pointer, and the operations corresponding to steps 103 and 104 are continued; if the virtual address in the first cache block does not match the memory access address corresponding to the address space where a cache miss occurred in the historical cycle, it is determined that the target pointer does not exist in the first cache block, and the operations corresponding to steps 103 and 104 are not performed.

[0058] For example, when the processor is a RISC-V processor, the virtual address of the data structure in the processor is an Sv39 virtual address structure, in which a virtual address has 39 bits. In the process of scanning the first cache block to determine whether there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical cycle, the cache can scan and obtain all data in the first cache block with valid bits of 39 bits, determine the obtained data with valid bits of 39 bits as a virtual address, and match the virtual address with a memory access address corresponding to the address space where a cache miss has occurred in a historical cycle to determine whether there is a target pointer in the first cache block.

[0059] As an example, a cache includes a memory access log for recording memory access information within a historical period. The memory access information includes, but is not limited to, the memory access address in the memory access request received by the cache within the historical period and the memory access hit flag corresponding to the memory access address. If, within the historical period, the memory access address hits the first cache block in the cache, the cache records the memory access address in the memory access log and sets the memory access hit flag corresponding to the memory access address to "1." If, in the case of a cache miss, the cache records the memory access address in the memory access log and sets the memory access hit flag corresponding to the memory access address to "0." When the cache obtains a virtual address in the first cache block, it can match the virtual address with the memory access addresses in the memory access log whose memory access hit flag is "0." If the virtual address matches any memory access address whose memory access hit flag is "0," the virtual address is determined to be a target pointer. If the virtual address does not match any memory access address whose memory access hit flag is "0," it is determined that the target pointer does not exist in the first cache block.

[0060] In an embodiment of the present application, the cache includes a first parameter corresponding to a cache block, which is used to indicate the prefetch depth corresponding to the cache block. The prefetch depth is the number of consecutive prefetches starting from the target pointer in the first cache block that has a cache hit; the first parameter can be set in the cache block or outside the cache block, and this embodiment of the present application does not limit this. The starting value of the first parameter can be any natural number a. If there is a target pointer in the first cache block that points to an address space that has experienced a cache miss in a historical period, the value of the first parameter of the first cache block can be increased by n, and n can be any positive integer.

[0061] For example, with the first cache block as the starting point, the starting value of the first parameter a=1, if there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period, the value of the first parameter of the first cache block is increased by 2, and the value of the first parameter of the first cache block is 3; a prefetch is performed based on the target pointer in the first cache block, the prefetch depth is 1, and the value of the first parameter of the first data block prefetched once is the same as the value of the first parameter of the first cache block, which is 3; if there is a target pointer in the first data block, the value of the first parameter of the first data block is increased by 2, and the value of the first parameter of the first data block is 5; a second prefetch is performed based on the target pointer in the first data block, the prefetch depth is 2, and the value of the first parameter of the second prefetched data block is the same as the value of the first parameter of the first data block, which is 5, and so on. It should be noted that the starting value a of the first parameter can also be a natural number other than 1; if there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period, the value of the first parameter of the first cache block plus n can also be a positive integer other than 2, and this embodiment of the application is not limited to this.

[0062] It can be understood that the value of the first parameter of the data block prefetched and backfilled into the cache is initialized to the starting value a by default; when the data block is hit and there is a target pointer in the data block pointing to the address space where a cache miss has occurred in the historical period, the value of the first parameter of the cache block is increased by n, and step 104 is executed to perform continuous prefetching with the target pointer in the cache block as the trigger starting point for prefetching.

[0063] Specifically, starting from the first cache block, a pre-fetch is performed based on the target pointer in the first cache block to obtain the first data block; before backfilling the first data block into the cache, it is first determined whether there is a target pointer in the first data block; after determining whether there is a target pointer in the first data block, the first data block is backfilled into the cache, at which time the cache will initialize the value of the first parameter of the first data block to a.

[0064] In an embodiment of the present application, if a target pointer exists in the first cache block that results in a cache hit, and after adding n to the value of the first parameter of the first cache block, the cache may perform continuous prefetching using the target pointer in the first cache block as the triggering starting point for prefetching, and stop prefetching if the value of the first parameter of the prefetched data block is greater than a first threshold or if the prefetched data block does not contain a target pointer pointing to an address space that has experienced a cache miss within a historical period. The first threshold is an integer greater than 1, and the first threshold may be determined based on a prefetch delay requirement. When the prefetch delay requirement is high, the first threshold may be relatively small, and when the delay requirement is relatively low, the first threshold may be relatively large. This embodiment of the present application does not specifically limit this.

[0065] Specifically, the cache can generate a prefetch request based on the target pointer in the first cache block and the first parameter of the first cache block and send it to the prefetcher in the cache. The prefetcher prefetches the first data block pointed to by the target pointer from the downstream node based on the prefetch request and adds the value of the first parameter in the prefetch request to the first data block and returns it to the cache; before backfilling the first data block into the cache, the cache scans the first data block to determine whether there is a target pointer in the first data block pointing to an address space where a cache miss has occurred in a historical period, and if there is a target pointer in the first data block, adds n to the value of the first parameter of the first data block to further determine whether the value of the first parameter of the first data block is greater than a first threshold; if there is a target pointer in the first data block and the value of the first parameter of the first data block is less than or equal to the first threshold, the prefetch request continues to be generated based on the target pointer in the first data block and the first parameter of the first data block and is continuously prefetched through the prefetcher; otherwise, if there is no target pointer in the first data block or the value of the first parameter of the first data block is greater than the first threshold, the prefetch is stopped.

[0066] Optionally, the cache may also include a first parameter record table for recording the values ​​of the first parameters of each data block prefetched during continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching. The cache determines whether the value of the first parameter of the prefetched data block is greater than a first threshold based on the first parameter record table.

[0067] It can be understood that when the continuous prefetching process satisfies any of the prefetching termination conditions, the prefetching operation can be stopped.

[0068] As an example, referring to FIG2 , a logical diagram of a continuous prefetching process provided by an embodiment of the present application is shown. As shown in FIG2 , a is 0, n is 1, and the first threshold is 3; after step 103 , the value of the first parameter of the first cache block is 1. The cache uses the target pointer in the first cache block as the triggering point for prefetching, and performs continuous prefetching until a prefetch termination condition is met. Specifically, the prefetching process is terminated as follows:

[0069] First, when the memory access address hits the first cache block in the cache and there is a target pointer in the first cache block pointing to the address space where a cache miss has occurred in a historical period, the value of the first parameter of the first cache block is increased by 1, and the first data block pointed to by the target pointer in the first cache block is prefetched. The value of the first parameter of the prefetched first data block is the same as the value of the first parameter of the first cache block by default, and the prefetch depth of this prefetch is 1.

[0070] Then, before backfilling the first data block into the cache, the first data block is scanned to determine whether there is a target pointer in the first data block pointing to an address space where a cache miss has occurred in a historical period, and if there is no target pointer in the first data block, prefetching is stopped; if there is a target pointer in the first data block, the value of the first parameter of the first data block is increased by 1, and at this time, the value of the first parameter of the first data block is 2; it is determined that the value of the first parameter of the first data block is less than a first threshold; the second data block pointed to by the target pointer in the first data block is prefetched, and the value of the first parameter of the prefetched second data block is the same as the value of the first parameter of the first data block by default, and the prefetch depth of this prefetch is 2.

[0071] Then, before backfilling the second data block into the cache, the second data block is scanned to determine whether there is a target pointer in the second data block pointing to an address space where a cache miss has occurred in a historical period; if there is no target pointer in the second data block, prefetching is stopped; if there is a target pointer in the second data block, the value of the first parameter of the second data block is increased by 1, and at this time, the value of the first parameter of the second data block is 3; it is determined that the value of the first parameter of the second data block is equal to the first threshold; the third data block pointed to by the target pointer in the second data block is prefetched, and the value of the first parameter of the prefetched third data block is the same as the value of the first parameter of the second data block by default, and the prefetch depth of this prefetch is 3.

[0072] Finally, before backfilling the third data block into the cache, the third data block is scanned to determine whether there is a target pointer in the third data block pointing to an address space where a cache miss has occurred in a historical period; if there is no target pointer in the third data block, prefetching is stopped; if there is a target pointer in the third data block, the value of the first parameter of the third data block is increased by 1, and at this time, the value of the first parameter of the third data block is 4; it is determined that the value of the first parameter of the third data block is greater than the first threshold, and prefetching is stopped.

[0073] The prefetching method provided in the embodiment of the present application, based on the principle of program locality, is more likely to cause a cache miss again in an address space that has experienced a cache miss in the recent period. The pointer in the first cache block pointing to the address space that has experienced a cache miss in the historical period is determined as the target pointer, and the target pointer is used as the trigger starting point for prefetching to perform continuous prefetching, which can improve the cache hit rate of the data blocks prefetched into the cache; when the prefetch termination condition is met during the continuous prefetching process, the prefetching operation is stopped, which can avoid continuing to issue multiple erroneous prefetches in the case of prefetch errors, causing problems such as cache storage space pollution and memory bandwidth occupation, thereby improving the speed of data access and reducing the impact of the gap between the processor's computing speed and data access speed on the performance of the computer system.

[0074] In an optional embodiment of the present application, if a first cache block corresponding to the memory access address exists in the cache, scanning the first cache block to determine whether a target pointer pointing to an address space in which a cache miss has occurred in a historical period in the first cache block in step 102 includes:

[0075] Step 1021: If a first cache block corresponding to the memory access address exists in the cache, obtain a prefetch flag of the first cache block.

[0076] Step 1022: When the prefetch flag is the first flag, scan the first cache block to determine whether there is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period.

[0077] Step 1023: Set the prefetch flag of the first cache block to the second flag.

[0078] The prefetch flag is used to indicate whether to trigger continuous prefetch, and the prefetch flag includes a first flag and a second flag; the first flag is used to indicate triggering continuous prefetch, and the second flag is used to indicate not triggering continuous prefetch. The prefetch flag of the cache block in the cache can be the first flag or the second flag. For example, the first flag can be represented as "1" and the second flag can be represented as "0".

[0079] In an embodiment of the present application, when there is a first cache block corresponding to the memory access address in the cache, it is also possible to first confirm whether the prefetch flag of the first cache block is the first flag. Only when the prefetch flag of the first cache block is the first flag, the operations corresponding to steps 1022 and 1023 will be executed.

[0080] Specifically, the prefetch flag of a cache block that has not been hit in the cache and has been scanned to determine whether there is a target pointer pointing to an address space where a cache miss has occurred in a historical period can be set to the second flag. When the cache block with the prefetch flag set to the second flag is subsequently hit by a memory access address, the cache can directly return the cache block to the processor without executing the operations corresponding to steps 1022 and 1023, thereby avoiding repeated scanning of the cache blocks in the cache and triggering continuous prefetch operations. While improving the cache hit rate of the cache, it also reduces unnecessary scanning and prefetching operations, reduces the resource overhead of the cache for data prefetching, and improves the efficiency of data prefetching.

[0081] Among them, when the prefetch flag of the first cache block is the first flag, the first cache block is scanned to determine whether there is a target pointer pointing to the address space where a cache miss has occurred in the historical period. The process can refer to the detailed description of step 102, and will not be repeated here to avoid repetition.

[0082] It is understandable that after step 102 , the prefetch flag of the first cache block may be modified from the first flag to the second flag to prevent subsequent repeated scanning of the first cache block.

[0083] The prefetch method provided in an embodiment of the present application determines whether to perform an operation of scanning the first cache block based on a prefetch flag of the first cache block when there is a first cache block corresponding to a memory access address in the cache, and after performing an operation of scanning the first cache block to determine whether there is a target pointer pointing to an address space in which a cache miss has occurred in a historical period, sets the prefetch flag of the first cache block to a second flag for indicating that continuous prefetching is not triggered, thereby avoiding repeated scanning of the cache blocks in the cache and triggering continuous prefetching. While improving the cache hit rate of the cache, it also reduces unnecessary scanning and prefetching operations, reduces the latency and power consumption of the memory system, and improves the efficiency of data prefetching in the cache.

[0084] In an optional embodiment of the present application, the step 104 of performing continuous prefetching using the target pointer in the first cache block as a triggering starting point for prefetching includes:

[0085] Step 1041: Perform continuous prefetching using the target pointer in the first cache block as a triggering starting point for prefetching.

[0086] Step 1042: When the value of the first parameter is equal to the second threshold, set the prefetch flag of the data block prefetched this time to the first flag.

[0087] The second threshold is smaller than the first threshold, and the second threshold is greater than 1.

[0088] In an embodiment of the present application, during the process of continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching, the prefetch flag of the data block whose value of the first parameter of the prefetch is equal to the second threshold can be set to the first flag. When the prefetch termination condition is met, the continuous prefetching operation with the target pointer in the first cache block as the trigger starting point for prefetching is stopped. When the memory access address carried in the memory access request sent again by the processor hits the data block whose value of the first parameter is equal to the second threshold, the operations corresponding to steps 1022 and 1023 can be continued to avoid interruption of the continuous prefetching process.

[0089] It is understood that if the value of the first parameter is not equal to the second threshold, the prefetch flag of the data block being prefetched is set to the second flag. In other words, during the process of continuous prefetching with the target pointer in the first cache block as the triggering starting point for prefetching, the prefetch flags of all prefetched data blocks, except for the data block for which the value of the first parameter is equal to the second threshold, are all set to the second flag.

[0090] In an embodiment of the present application, the number of the second threshold value may be at least one, and in the process of continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching, the number of data blocks with the prefetch flag bit being the first flag bit in the prefetched data blocks is less than or equal to the number of the second threshold value. Specifically, in the process of continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching, when the value of the first parameter of the prefetched data block is less than the second threshold value, and the data block does not contain a target pointer pointing to an address space in which a cache miss has occurred in a historical period, then the number of data blocks with the prefetch flag bit being the first flag bit in the prefetched data block is less than the number of the second threshold value; when the data blocks with the first parameter value less than or equal to the second threshold value all contain a target pointer pointing to an address space in which a cache miss has occurred in a historical period, then the number of data blocks with the prefetch flag bit being the first flag bit in the prefetched data block is equal to the number of the second threshold value.

[0091] It is understood that the second threshold can be any integer between 1 and the first threshold. To avoid repeated scanning and prefetching of data blocks, an integer close to the first threshold can be selected as the second threshold. For example, if the first threshold is 4, the second threshold can be 3; if the first threshold is 5, the second threshold can be 4.

[0092] As an example, referring to FIG3 , another logical diagram of continuous prefetching provided by an embodiment of the present application is shown. As shown in FIG3 , a is 0, n is 1, the first threshold is 3, and the second threshold is 2; after step 103, the value of the first parameter of the first cache block is 1. Specifically:

[0093] First, when the memory access address hits the first cache block in the cache and the prefetch flag of the first cache block is the first flag "1", it is determined that there is a target pointer in the first cache block pointing to the address space where a cache miss has occurred in a historical period, and the prefetch flag of the first cache block is set from the first flag "1" to the second flag "0"; 1 is added to the value of the first parameter of the first cache block, at this time, the value of the first parameter of the first cache block is 1; it is determined that the value of the first parameter of the first cache block is less than the first threshold and not equal to the second threshold; the first data block pointed to by the target pointer in the first cache block is prefetched, and the prefetch flag of the first data block prefetched this time is set to the second flag "0", and the prefetch depth of this prefetch is 1.

[0094] Then, before backfilling the first data block into the cache, the first data block is scanned to determine whether there is a target pointer in the first data block pointing to the address space where a cache miss has occurred in the historical period, and the value of the first parameter of the first data block is increased by 1. At this time, the value of the first parameter of the first data block is 2; it is determined that the value of the first parameter of the first data block is less than the first threshold and equal to the second threshold; the second data block pointed to by the target pointer in the first data block is prefetched, and the prefetch flag of the second data block prefetched this time is set to the first flag "1", and the prefetch depth of this prefetch is 2.

[0095] Then, before backfilling the second data block into the cache, the second data block is scanned to determine whether there is a target pointer in the second data block pointing to the address space where a cache miss has occurred in the historical period, and the value of the first parameter of the second data block is increased by 1. At this time, the value of the first parameter of the second data block is 3; it is determined that the value of the first parameter of the second data block is equal to the first threshold and not equal to the second threshold; the third data block pointed to by the target pointer in the second data block is prefetched, and the prefetch flag of the third data block prefetched this time is set to the second flag "0", and the prefetch depth of this prefetch is 3.

[0096] Finally, before backfilling the third data block into the cache, the third data block is scanned to determine whether there is a target pointer in the third data block pointing to the address space where a cache miss has occurred in the historical period, and the value of the first parameter of the third data block is increased by 1. At this time, the value of the first parameter of the third data block is 4; it is determined that the value of the first parameter of the third data block is greater than the first threshold, and prefetching is stopped; in this way, continuous prefetching is performed with the target pointer in the first cache block as the trigger starting point for prefetching, and the prefetch flag of the second data block whose prefetched first parameter value is equal to the second threshold is set to the first flag "1". When the memory access address carried in the memory access request sent by the processor again hits the second data block, the target pointer in the second data block can be continued as the trigger starting point for prefetching, and continuous prefetching can be performed to prefetch the fourth data block and the fifth data block, and the cycle is repeated to avoid interruption of the continuous prefetching process.

[0097] It should be noted that the operation of setting the prefetch flag of the prefetched data block can be performed after the data block is prefetched and before the prefetched data block is backfilled into the cache, or it can be performed after the prefetched data block is backfilled into the cache. The embodiments of the present application do not specifically limit this.

[0098] The prefetch method provided in the embodiment of the present application is further provided with a second threshold value which is greater than 1 and less than the first threshold value. In the process of continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching, when the value of the first parameter is equal to the second threshold value, the prefetch flag of the data block prefetched this time is set to the first flag bit. This can improve the cache hit rate of the data block prefetched to the cache, avoid continuing to issue multiple erroneous prefetches in the case of prefetch errors, causing problems of cache storage space pollution and memory bandwidth occupation, and avoid interruption of the continuous prefetch process, thereby realizing selective continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching.

[0099] In an optional embodiment of the present application, the cache further includes a cache miss table, the cache miss table being used to record cache miss addresses in a historical period; and in step 102, if a first cache block corresponding to the memory access address exists in the cache, scanning the first cache block to determine whether a target pointer pointing to an address space in which a cache miss has occurred in the historical period is included:

[0100] Step S11: When a first cache block corresponding to the memory access address exists in the cache, determine a first address pointed to by a first pointer in the first cache block.

[0101] Step S12: If there is a cache miss address matching the first address in the cache miss table, determine that the first pointer is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period.

[0102] In an embodiment of the present application, a cache miss table is provided in the cache to record cache miss addresses in a historical period, wherein the cache miss address is a memory access address corresponding to an address space where a cache miss occurred in the historical period or an address range corresponding to the memory access address.

[0103] Specifically, first, when there is a first cache block corresponding to the memory access address in the cache, the cache determines the first pointer in the first cache block by scanning the first cache block; then, the first address pointed to by the first pointer is determined, and the first address is matched with the cache miss table; finally, when there is a cache miss address matching the first address in the cache miss table, the first pointer is determined to be a target pointer of the first cache block pointing to the address space where a cache miss has occurred in a historical period; when there is no cache miss address matching the first address in the cache miss table or the first pointer does not exist in the first cache block, it is determined that there is no target pointer in the first cache block pointing to the address space where a cache miss has occurred in a historical period.

[0104] It can be understood that the first pointer can be any pointer in the first cache block.

[0105] It should be noted that, when the cache miss address is the memory access address corresponding to the address space where the cache miss occurred in the historical period, the first address pointed to by the first pointer is the memory access address corresponding to the data block pointed to by the first pointer; when the cache miss address is the address interval corresponding to the memory access address corresponding to the address space where the cache miss occurred in the historical period, the first address pointed to by the first pointer is the address interval corresponding to the memory access address of the data block pointed to by the first pointer.

[0106] As an example, with reference to FIG4 , a flow chart of determining a target pointer provided by an embodiment of the present application is shown. As shown in FIG4 , the processor is a RISC-V processor, and the virtual address of the data structure in the processor is an Sv39 virtual address structure. In the Sv39 virtual address structure, a virtual address has 39 bits; of the 39 bits, the upper 27 bits are respectively the first-level page table number (9 bits), the second-level page table number (9 bits) and the third-level page table number (9 bits), and the lower 12 bits are the intra-page address offset. The cache miss table in the cache is used to record the cache miss addresses of 128 cache misses in the historical cycle, wherein the cache miss address is the upper 18 bits of the memory access address corresponding to the address space where the cache has had a cache miss in the historical cycle.

[0107] In the process of determining whether there is a target pointer pointing to an address space in which a cache miss has occurred in a historical period in a first cache block, the cache specifically proceeds as follows: first, all 64-bit words in the first cache block are obtained, and the upper 25 bits and the last two bits of each word are confirmed in turn to be all 0; then, among the 64-bit words in the first cache block, the word whose upper 25 bits and the last two bits are all 0 is determined as the first pointer in the first cache block, and bits 21 to 38 of the first pointer are determined as the first address pointed to by the first pointer, that is, the first address is the upper 18 bits of the memory access address of the data block pointed to by the first pointer; then, the first address pointed to by the first pointer is matched with a cache miss address in a cache miss table. If there is a cache miss address in the cache miss table that matches the first address, the first pointer is determined to be the target pointer pointing to the address space in the first cache block in which a cache miss has occurred in a historical period.

[0108] The prefetch method provided in the embodiment of the present application determines the target pointer in the first cache block by matching the first address pointed to by the first pointer in the first cache block with the cache miss address in the cache miss table. The implementation process is simple. While improving the cache hit rate of the prefetched data block in the cache, it also simplifies the pointer identification process and improves the efficiency of the cache in data prefetching.

[0109] In an optional embodiment of the present application, the method further includes:

[0110] In a case where the first cache block corresponding to the memory access address does not exist in the cache, the memory access address is added to the cache miss table.

[0111] In an embodiment of the present application, when the cache determines that the first cache block corresponding to the memory access address does not exist in the cache, the cache may add the memory access address carried in the memory access request to the cache miss table, or add the address range corresponding to the memory access address carried in the memory access request to the cache miss table, such as the upper 18 bits of the memory access address, as the cache miss address in the cache miss table, thereby realizing real-time updating of the cache miss table, improving the timeliness and reliability of steps S11 and S12 in determining the target pointer in the first cache block based on the cache miss address table, and thereby improving the cache hit rate of data blocks that are continuously prefetched with the target pointer in the first cache block as the trigger starting point for prefetching.

[0112] Specifically, when there is a blank entry in the cache miss table, the cache can directly add the memory access address or the address interval corresponding to the memory access address to the blank entry in the cache miss table; when there is no blank entry in the cache miss table, the cache can replace the cache miss address first stored in the cache miss table with the memory access address or the address interval corresponding to the memory access address according to the "first in first out" principle.

[0113] In an optional embodiment of the present application, after receiving the memory access request sent by the processor and obtaining the memory access address carried in the memory access request in step 101, the method further includes:

[0114] In a case where the first cache block corresponding to the memory access address does not exist in the cache, a data block corresponding to the memory access address is obtained from a downstream node, and the data block is backfilled into the cache.

[0115] In an embodiment of the present application, when the cache determines that there is no first cache block corresponding to the memory access address in the cache, it can also obtain the data block corresponding to the memory access address from the downstream node and backfill the data block into the cache.

[0116] Among them, after obtaining the sixth data block corresponding to the memory access address from the downstream node, the cache can set the prefetch flag of the sixth data block to the second flag; before backfilling the sixth data block into the cache and returning it to the processor, the cache can scan the sixth data block to confirm whether there is a target pointer pointing to the address space where a cache miss has occurred in a historical period in the sixth data block; when there is a target pointer in the sixth data block, a single prefetch is performed on the seventh data block pointed to by the target pointer in the sixth data block, and the prefetch flag of the seventh data block is set to the first flag, so that when the subsequent memory access address hits the seventh data block, continuous prefetching with the target pointer in the seventh data block as the triggering starting point for prefetching is triggered; when there is no target pointer in the sixth data block, the sixth data block is backfilled into the cache and returned to the processor.

[0117] The prefetching method provided in an embodiment of the present application obtains the data block corresponding to the memory access address from a downstream node and backfills the data block into the cache when the first cache block corresponding to the memory access address does not exist in the cache, thereby improving the feasibility of data prefetching in the cache.

[0118] Referring to Figure 5, a logic block diagram of a prefetch method provided by an embodiment of the present application is shown. As shown in Figure 5, the cache includes a secondary cache (L2Cache), a secondary cache register (L2MSHR), a prefetcher, a pointer identifier, and a secondary cache prefetch queue. The secondary cache register serves as a downstream node of the secondary cache; the pointer identifier includes a cache miss table.

[0119] Specifically, the secondary cache is used to receive a memory access request sent by the processor and obtain a memory access address carried in the memory access request; if there is a first cache block corresponding to the memory access address in the secondary cache, the first cache block is transmitted to the pointer identifier; if there is no first cache block corresponding to the memory access address in the secondary cache, the memory access address is transmitted to the pointer identifier.

[0120] The pointer identifier is used to determine the first address pointed to by the first pointer in the first cache block or the prefetched data block when the first cache block or the prefetched data block is received, and to determine that the first pointer is a target pointer pointing to an address space in the first cache block or the prefetched data block where a cache miss has occurred in a historical period when a cache miss address matching the first address exists in the cache miss table; to add n to the value of the first parameter of the first cache block or the prefetched data block, and to transmit the target pointer and the first parameter in the first cache block or the prefetched data block to the prefetcher when the first cache block or the prefetched data block does not exist, thereby not transmitting data to the prefetcher, thereby stopping the prefetch operation; and to add the memory access address to the cache miss table when a memory access address is received.

[0121] The prefetcher is used to generate a prefetch request based on the target pointer in the first cache block or the prefetched data block and the first parameter when the value of the first parameter is less than or equal to the first threshold, and transmit the prefetch request to the secondary cache prefetch queue, so that the secondary cache prefetch queue can perform prefetch in the secondary cache register based on the prefetch request, thereby realizing continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching; when the value of the first parameter is greater than the first threshold, the operation of generating the prefetch request is not performed, thereby realizing the stopping of the prefetch operation.

[0122] When the first cache block corresponding to the memory access address does not exist in the secondary cache register, the secondary cache register can also continue to obtain the data block corresponding to the memory access address from the downstream node of the secondary cache register and backfill the data block into the cache. To avoid repetition, it will not be repeated here.

[0123] In summary, the embodiments of the present application provide a prefetching method. According to the principle of program locality, an address space that has experienced a cache miss in the recent period is more likely to experience a cache miss again. The pointer in the first cache block that points to the address space that has experienced a cache miss in the historical period is determined as the target pointer, and the target pointer is used as the trigger starting point for prefetching to perform continuous prefetching, which can improve the cache hit rate of the data blocks prefetched into the cache; when the prefetch termination condition is met during the continuous prefetching process, the prefetching operation is stopped, which can avoid continuing to issue multiple erroneous prefetches in the case of prefetch errors, causing problems of cache storage space pollution and memory bandwidth occupation, thereby improving the speed of data access and reducing the impact of the gap between the processor's computing speed and data access speed on the performance of the computer system.

[0124] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0125] Device embodiment

[0126] 6 , a block diagram of a prefetching device of the present invention is shown, which is applied to a cache. The device may specifically include:

[0127] The receiving module 601 is configured to receive a memory access request sent by the processor and obtain a memory access address carried in the memory access request;

[0128] a determination module 602 configured to, if a first cache block corresponding to the memory access address exists in the cache, scan the first cache block to determine whether there is a target pointer in the first cache block pointing to an address space in which a cache miss has occurred in a historical period;

[0129] A calculation module 603 is configured to, if the first cache block contains a target pointer pointing to an address space in which a cache miss has occurred in a historical period, add n to the value of a first parameter of the first cache block; the first parameter is used to indicate a prefetch depth corresponding to the cache block, and a starts at a value a; n is a positive integer, and a is a natural number;

[0130] a prefetch module 604 configured to perform continuous prefetching using the target pointer in the first cache block as a triggering starting point for prefetching until a prefetching termination condition is satisfied, and then stop the prefetching operation; each time a prefetch is triggered, the value of the first parameter is incremented by n;

[0131] The pre-fetch termination condition includes at least one of the following:

[0132] The value of the first parameter is greater than a first threshold;

[0133] There is no target pointer in the prefetched data block pointing to the address space where a cache miss occurred in the historical cycle.

[0134] Optionally, the determining module includes:

[0135] an acquisition submodule, configured to acquire a prefetch flag of a first cache block corresponding to the memory access address if the first cache block exists in the cache; the prefetch flag is used to indicate whether to trigger continuous prefetching;

[0136] a first determining submodule, configured to, when the prefetch flag is a first flag, scan the first cache block to determine whether there is a target pointer in the first cache block pointing to an address space in which a cache miss has occurred in a historical period; the first flag is used to indicate triggering of continuous prefetching;

[0137] The first setting submodule is used to set the prefetch flag of the first cache block to a second flag; the second flag is used to indicate that continuous prefetching is not triggered.

[0138] Optionally, the pre-fetch module includes:

[0139] a prefetch submodule, configured to perform continuous prefetching by taking the target pointer in the first cache block as a triggering starting point for prefetching;

[0140] The second setting submodule is used to set the prefetch flag of the prefetched data block to the first flag when the value of the first parameter is equal to a second threshold; the second threshold is less than the first threshold, and the second threshold is greater than 1.

[0141] Optionally, the cache further includes a cache miss table, which is used to record cache miss addresses in a historical period; the determining module includes:

[0142] a second determining submodule, configured to determine, when a first cache block corresponding to the memory access address exists in the cache, a first address pointed to by a first pointer in the first cache block;

[0143] The third determining submodule is configured to determine, when there is a cache miss address in the cache miss table that matches the first address, that the first pointer is a target pointer in the first cache block pointing to an address space where a cache miss has occurred in a historical period.

[0144] Optionally, the device further comprises:

[0145] An adding module is configured to add the memory access address to the cache miss table when a first cache block corresponding to the memory access address does not exist in the cache.

[0146] Optionally, the device further comprises:

[0147] The acquisition module is configured to acquire a data block corresponding to the memory access address from a downstream node and backfill the data block into the cache when there is no first cache block corresponding to the memory access address in the cache.

[0148] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0149] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0150] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0151] Referring to Figure 7, there is a block diagram of a prefetching electronic device provided in an embodiment of the present application. As shown in Figure 7, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory is used to store executable instructions, which enable the processor to execute the prefetching method of the aforementioned embodiment.

[0152] The processor may be a CPU, a general-purpose processor, a DSP (Digital Signal Processor), an ASIC, an FPGA, or other programmable device, a transistor logic device, a hardware component, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0153] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG7 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0154] The memory may be a ROM (Read-Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read-Only Memory), a CD-ROM (Compact Disc Read-Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0155] An embodiment of the present application also provides a non-temporary computer-readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute the prefetching method shown in Figure 1.

[0156] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0157] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0158] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0159] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0160] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0161] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0162] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0163] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0164] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0165] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0166] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0167] It is understood that the embodiments described in the present disclosure may be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the modules, units, and subunits may be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, or other electronic units or combinations thereof for performing the functions described in the present disclosure.

[0168] For software implementation, the techniques described in the embodiments of the present disclosure can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of the present disclosure. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0169] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0170] The above is a detailed introduction to a prefetching method, device, electronic device and readable storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A prefetching method, applied to a cache, the method comprising: Receiving a memory access request sent by a processor, and obtaining a memory access address carried in the memory access request; When there is a first cache block corresponding to the memory access address in the cache, scanning the first cache block to determine whether there is a target pointer in the first cache block that points to an address space where a cache miss occurred in a historical period; When there is a target pointer in the first cache block that points to an address space where a cache miss occurred in a historical period, adding the value of a first parameter of the first cache block by n; The first parameter is used to indicate the prefetch depth corresponding to the cache block, and the starting value of the first parameter is a; n is a positive integer, and a is a natural number; Using the target pointer in the first cache block as the trigger starting point for prefetching, performing continuous prefetching until a prefetch abort condition is met, and then stopping the prefetch operation; each time prefetching is triggered, the value of the first parameter is added by n; Wherein, the prefetch abort condition includes at least one of the following: The value of the first parameter is greater than a first threshold; There is no target pointer in the prefetched data block that points to an address space where a cache miss occurred in a historical period.

2. The method according to claim 1, wherein When there is a first cache block corresponding to the memory access address in the cache, scanning the first cache block to determine whether there is a target pointer in the first cache block that points to an address space where a cache miss occurred in a historical period, includes: When there is a first cache block corresponding to the memory access address in the cache, obtaining a prefetch flag bit of the first cache block; the prefetch flag bit is used to indicate whether to trigger continuous prefetching; When the prefetch flag bit is a first flag bit, scanning the first cache block to determine whether there is a target pointer in the first cache block that points to an address space where a cache miss occurred in a historical period; the first flag bit is used to indicate triggering continuous prefetching; Setting the prefetch flag bit of the first cache block to a second flag bit; the second flag bit is used to indicate not triggering continuous prefetching.

3. The method according to claim 2, wherein, The performing continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching, includes: Performing continuous prefetching with the target pointer in the first cache block as the trigger starting point for prefetching; When the value of the first parameter is equal to a second threshold, setting the prefetch flag bit of the currently prefetched data block to the first flag bit; the second threshold is less than the first threshold and greater than 1.

4. The method according to claim 1, wherein The cache further includes a cache miss table, and the cache miss table is used to record cache miss addresses in a historical period; When there is a first cache block corresponding to the memory access address in the cache, scanning the first cache block to determine whether there is a target pointer in the first cache block that points to an address space where a cache miss occurred in a historical period, includes: When there is a first cache block corresponding to the memory access address in the cache, determining the first Address pointed to by a first pointer in the cache block; In the case that there is a cache miss address matching the first address in the cache miss table, determine the first pointer as the target pointer in the first cache block that points to the address space where a cache miss occurred in the historical period.

5. The method according to claim 4, wherein, The method further includes: In the case that there is no first cache block corresponding to the memory access address in the cache, add the memory access address to the cache miss table.

6. The method according to claim 1, wherein After receiving a memory access request sent by a processor and obtaining the memory access address carried in the memory access request, the method further includes: In the case that there is no first cache block corresponding to the memory access address in the cache, obtain the data block corresponding to the memory access address from a downstream node and backfill the data block into the cache.

7. The method according to claim 1, wherein The method further includes: In the case that there is a pointer in the first cache block, match the virtual address in the first cache block with the memory access address corresponding to the address space where a cache miss occurred in the historical period; In the case that the virtual address in the first cache block matches the memory access address corresponding to any address space where a cache miss occurred in the historical period, determine the virtual address as the target pointer; In the case that the virtual address in the first cache block does not match the memory access address corresponding to the address space where a cache miss occurred in the historical period, determine that there is no target pointer in the first cache block.

8. The method according to claim 7, wherein The method further includes: Scan and obtain the virtual address in the first cache block; In the case that there is a virtual address in the first cache block, determine that there is a pointer in the first cache block; In the case that there is no virtual address in the first cache block, determine that there is no pointer in the first cache block.

9. The method according to claim 7, characterized in that, The method further includes: Initialize the value of the first parameter of the data block backfilled into the cache by prefetching to the starting value a.

10. The method according to claim 7, characterized in that, The cache further includes a first parameter record table for recording the values of the first parameters of the respective data blocks prefetched during continuous prefetching with the target pointer in the first cache block as the prefetch trigger starting point; The method further includes: Determine whether the value of the first parameter of the prefetched data block is greater than the first threshold based on the first parameter record table.

11. The method according to claim 3, wherein The number of the second thresholds is greater than or equal to 1; during continuous prefetching with the target pointer in the first cache block as the prefetch trigger starting point, the number of data blocks with the prefetch flag bit being the first flag bit among the prefetched data blocks is less than or equal to the number of the second thresholds.

12. A prefetch device applied to a cache, the device includes: A receiving module, configured to receive a memory access request sent by a processor and obtain the memory access address carried in the memory access request; A determining module, configured to, in the case that there is a first cache block corresponding to the memory access address in the cache, scan the first cache block to determine whether there is a target pointer in the first cache block that points to the address space where a cache miss occurred in the historical period; A calculation module, configured to add n to the value of a first parameter of the first cache block when there is a target pointer in the first cache block that points to an address space where a cache miss occurred during a historical period; The first parameter is used to indicate the prefetch depth corresponding to the cache block, and the starting value of the first parameter is a; n is a positive integer, and a is a natural number; A prefetch module, configured to use the target pointer in the first cache block as the trigger start point for prefetching, perform continuous prefetching until a prefetch abort condition is met, and then stop the prefetch operation; each time prefetching is triggered, the value of the first parameter is incremented by n; Wherein, the prefetch abort condition includes at least one of the following: The value of the first parameter is greater than a first threshold; There is no target pointer in the prefetched data block that points to an address space where a cache miss occurred during a historical period.

13. The device according to claim 12, wherein, The determination module includes: An acquisition sub-module, configured to acquire a prefetch flag bit of the first cache block when there is a first cache block corresponding to the memory access address in the cache; the prefetch flag bit is used to indicate whether to trigger continuous prefetching; A first determination sub-module, configured to scan the first cache block to determine whether there is a target pointer in the first cache block that points to an address space where a cache miss occurred during a historical period when the prefetch flag bit is a first flag bit; the first flag bit is used to indicate triggering continuous prefetching; A first setting sub-module, configured to set the prefetch flag bit of the first cache block to a second flag bit; the second flag bit is used to indicate not triggering continuous prefetching.

14. The apparatus according to claim 13, wherein, The prefetch module includes: A prefetch sub-module, configured to use the target pointer in the first cache block as the trigger start point for prefetching and perform continuous prefetching; A second setting sub-module, configured to set the prefetch flag bit of the data block prefetched this time to the first flag bit when the value of the first parameter is equal to a second threshold; the second threshold is less than the first threshold and greater than 1.

15. The device according to claim 12, wherein The cache further includes a cache miss table, which is used to record cache miss addresses during a historical period; The determination module includes: A second determination sub-module, configured to determine a first address pointed to by a first pointer in the first cache block when there is a first cache block corresponding to the memory access address in the cache; A third determination sub-module, configured to determine that the first pointer is a target pointer in the first cache block that points to an address space where a cache miss occurred during a historical period when there is a cache miss address matching the first address in the cache miss table.

16. The apparatus according to claim 15, wherein, The apparatus further includes: An addition module, configured to add the memory access address to the cache miss table when there is no first cache block corresponding to the memory access address in the cache in this case.

17. The device according to claim 12, wherein The apparatus further includes: An acquisition module, configured to acquire a data block corresponding to the memory access address from a downstream node and write the data block back to the cache when there is no first cache block corresponding to the memory access address in the cache.

18. An electronic device, the electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions, and the executable instructions cause the processor to execute the prefetching method according to any one of claims 1 to 11.

19. A readable storage medium, when the instructions in the readable storage medium are executed by a processor of an electronic device, enabling the processor to execute the prefetching method according to any one of claims 1 to 11.

20. A prefetching device / equipment, including that the device / equipment is configured to execute the prefetching method according to any one of claims 1 to 11.

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