Baseband chip, signal system and baseband chip control method

Abstract

The present application belongs to the technical field of communications, and provides a baseband chip, a signal system and a baseband chip control method. The baseband chip comprises: a channel estimation module, which is configured to calculate first descrambled data and a noise variance on the basis of a GAMP algorithm so as to obtain a channel estimation matrix, and which performs sub-carrier-antenna dimensional data conversion on the channel estimation matrix to obtain a target matrix; a MIMO signal detection module, which is configured to use a GAI-BP algorithm and Ping-Pong storage technology to process second descrambled data and the target matrix, so as to obtain bit soft information; and a decoding module, which is configured to decode and verify the bit soft information to obtain an original bit message, so as to achieve Ethernet frame encapsulation and transmission.

Description

Baseband chip, signal system and baseband chip control method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 202410079121.3, filed on January 18, 2024, entitled “BASEBAND CHIP, SIGNAL SYSTEM AND BASEBAND CHIP CONTROL METHOD,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to a baseband chip, a signal system, and a baseband chip control method. Background Art

[0004] The global success of 5G wireless technology has had a significant impact on many aspects of human life. In the upcoming 5G (B5G) and 6G eras, wireless networks urgently need to evolve from consumer applications to production-centric needs, ultimately providing comprehensive support for diverse vertical industries. In this context, baseband chipsets, as one of the most technologically intensive components of mobile communication systems, are crucial to supporting the development of the B5G / 6G industries.

[0005] In related technologies, the system-level baseband chip has relatively simple functions and cannot meet the rapidly growing signal processing needs. When the baseband chip is designed by combining different functional modules, the information transmission efficiency between modules is low, resulting in low communication efficiency.

[0006] Summary of the Invention

[0007] In response to the problems existing in the related technologies, the embodiments of the present application provide a baseband chip, a signal system and a baseband chip control method.

[0008] In a first aspect, the present application provides a baseband chip, comprising:

[0009] a channel estimation module configured to receive first descrambled data, calculate the first descrambled data and noise variance according to a Gaussian approximate message passing (GAMP) algorithm to obtain a channel estimation matrix, and perform subcarrier-antenna dimension data conversion on the channel estimation matrix to obtain a target matrix;

[0010] a multi-antenna transmission and reception MIMO signal detection module, the MIMO signal detection module being configured to iteratively process the second descrambled data and the target matrix using Gaussian approximation interference belief propagation (GAI_BP), cache and read control processing of the data during the iteration using ping-pong storage technology, and soft-demodulate the final iteration result after a target number of iterations to obtain bit soft information;

[0011] A decoding module configured to decode the bit soft information according to a belief propagation BP algorithm to obtain a decoding result, and to verify the decoding result to obtain verification data to implement Ethernet frame encapsulation and transmission;

[0012] The channel estimation module, the MIMO signal detection module, and the decoding module are all constructed based on a message passing factor graph model; the noise variance is determined based on the first descrambling data, and the first descrambling data and the second descrambling data are both obtained by sequentially acquiring, parsing, and preprocessing Ethernet frames on input signal data.

[0013] Optionally, the baseband chip further includes:

[0014] An Ethernet interface configured to perform target processing on the input signal data to obtain a receiving-side Ethernet frame; the target processing includes at least one of serial communication, clock recovery, channel equalization, signal scrambling / descrambling, signal encoding / decoding, elastic caching, link monitoring, data forwarding control, data framing, marking, and data verification.

[0015] Optionally, the Ethernet interface includes:

[0016] SerDes, the SerDes being configured to perform serial communication, clock recovery, and channel equalization processing on the input signal data to obtain first processed data;

[0017] a physical coding sublayer (PCS), wherein the PCS is configured to perform signal scrambling or descrambling, signal encoding or decoding, elastic buffering, and link monitoring on the first processed data to obtain second processed data;

[0018] A media access control layer MAC is configured to perform data forwarding control, data framing, marking, and data verification on the second processed data to obtain the receiving-side Ethernet frame.

[0019] Optionally, the baseband chip further includes:

[0020] A parsing module configured to parse the receiving side Ethernet frame and identify error packets to obtain a target Ethernet frame data field;

[0021] a preprocessing module configured to perform cross-clock processing, bit width conversion, phase compensation, and data descrambling on the target Ethernet frame data field to obtain a plurality of descrambled data; the plurality of descrambled data includes the first descrambled data and the second descrambled data; the parsing module and the preprocessing module adopt a pipeline design;

[0022] an encapsulation module configured to sequentially perform bit width conversion and cross-clock domain conversion on the check data to obtain converted data, and, if the converted data belongs to service data, mark the converted data according to an Ethernet frame format to obtain encapsulated data;

[0023] The encapsulation module is further configured to send the encapsulated data to an Ethernet interface.

[0024] Optionally, the decoding module includes:

[0025] at least two different decoders, the two different decoders being configured to determine the decoding result;

[0026] The decoding standard configuration unit is arranged outside the at least two different decoders, and includes a high-speed data cache and control module, a rate matching module, and a decoding-related parameter configuration module.

[0027] Optionally, the at least two different decoders include:

[0028] A low-density parity-check code (LDPC) decoder, wherein the LDPC decoder adopts a block-parallel and row-update decoding architecture; the LDPC decoder is configured to perform iterative update decoding and CRC check on bit soft information to obtain first check data;

[0029] a polar code decoder, wherein the polar decoder adopts a single-column decoding architecture and is configured to perform rapid iteration and CRC check on decoded soft information through parallel processing of arithmetic units to obtain second check data;

[0030] The verification data is one of the first verification data and the second verification data.

[0031] Optionally, the MIMO signal detection module is obtained by adopting a fully deployed architecture and pipeline design.

[0032] Optionally, the baseband chip further includes:

[0033] An SPI interface and configuration management module, wherein the SPI interface is configured to configure the user number, decoding mode, parallelism, iteration count, check mode, phase compensation value, and scrambling code vector of the baseband chip;

[0034] The SPI interface is also configured to monitor the status of the baseband chip and enable extended deployment of multiple baseband chips.

[0035] Optionally, the computing unit of the baseband chip adopts a universal design architecture.

[0036] In a second aspect, the present application further provides a signaling system, comprising:

[0037] Multiple baseband chips, each reception chip supports multiple-receive and multiple-transmit MIMO scenarios to realize user-side baseband signal processing of large-scale MIMO systems.

[0038] In a third aspect, the present application further provides a baseband chip control method, comprising:

[0039] receiving first descrambled data, calculating the first descrambled data and noise variance according to a Gaussian approximate message passing (GAMP) algorithm to obtain a channel estimation matrix, and performing subcarrier-antenna dimension data conversion on the channel estimation matrix to obtain a target matrix; the noise variance is determined based on the first descrambled data;

[0040] Iteratively processing the second descrambled data and the target matrix using Gaussian approximation interference belief propagation (GAI_BP), caching and reading control processing of the data during the iteration using a ping-pong storage technique, and soft-demodulating the final iteration result after a target number of iterations to obtain bit soft information; the first descrambled data and the second descrambled data are both obtained by sequentially acquiring, parsing, and preprocessing Ethernet frames on the input signal data;

[0041] The bit soft information is decoded according to the belief propagation BP algorithm to obtain a decoding result, and the decoding result is verified to obtain verification data to realize Ethernet frame encapsulation and transmission.

[0042] In a fourth aspect, the present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned baseband chip control method when executing the program.

[0043] In a fifth aspect, the present application also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the baseband chip control method as described above is implemented.

[0044] In a sixth aspect, the present application also provides a computer program product, comprising a computer program, which implements the above-mentioned baseband chip control method when executed by a processor.

[0045] The baseband chip, signal system and baseband chip control method provided in the present application calculate the channel estimation matrix by calculating the first descrambled data and noise variance through the channel estimation module, obtain bit soft information by using Gaussian approximate interference confidence propagation and ping-pong storage technology through the MIMO signal detection module, decode and verify the bit soft information through the decoding module, and complete the frame structure encapsulation and transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in this application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] FIG1 is a schematic diagram of the structure of a baseband chip provided by the present application;

[0048] FIG2 is a schematic diagram of information interaction between the Ethernet interface, preprocessing module and channel estimation module provided by the present application;

[0049] FIG3 is a schematic diagram of the working mechanism of the Ethernet interface provided by the present application;

[0050] FIG4 is a schematic diagram of the structure of the decoding module provided by the present application;

[0051] FIG5 is a schematic diagram of the working mechanism of the 8×8 MIMO detector provided by this application;

[0052] FIG6 is a second structural diagram of the baseband chip provided by the present application;

[0053] FIG7 is a third structural diagram of the baseband chip provided by the present application;

[0054] FIG8 is a schematic structural diagram of a signal system provided by the present application;

[0055] FIG9 is a flow chart of a baseband chip control method provided in the present application;

[0056] FIG10 is a schematic diagram of a process of MIMO signal detection provided by the present application;

[0057] FIG11 is a second flow chart of the baseband chip control method provided by the present application;

[0058] FIG12 is a schematic structural diagram of the electronic device provided in this application.

[0059] Reference numerals: 100: baseband chip; 110: Ethernet interface; 120: parsing module; 130: pre-processing module; 140: channel estimation module; 150: MIMO signal detection module; 160: decoding module; 170: encapsulation module; 180: SPI interface. DETAILED DESCRIPTION

[0060] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0061] The baseband chip, signal system and baseband chip control method of the present application are described below with reference to FIG1-FIG11.

[0062] FIG1 is one of the structural diagrams of the baseband chip provided in this application. As shown in FIG1 , the baseband chip 100 includes: a channel estimation module 140 , a multi-antenna transmission and reception MIMO signal detection module 150 , and a decoding module 160 .

[0063] The channel estimation module 140 is configured to calculate a channel estimation matrix based on the first descrambled data and the noise variance using a Gaussian approximate message passing (GAMP) algorithm, and perform data conversion of the channel estimation matrix in the subcarrier-antenna dimension to obtain a target matrix; the noise variance is determined based on the first descrambled data, and the first descrambled data belongs to multiple descrambled data.

[0064] Optionally, multiple descrambled data are obtained by performing Ethernet frame acquisition, parsing and preprocessing (such as data descrambling) on ​​the input signal data, wherein the first descrambled data and the second descrambled data are respectively part of the multiple descrambled data.

[0065] Optionally, the noise variance is determined by channel parameters of the channel estimation module 140 and is independent of the input descrambled data.

[0066] Optionally, Ethernet frame parsing and preprocessing adopt a pipeline design to achieve high-speed data transmission; a portion of the multiple descrambled data (corresponding to the first descrambled data) is input into the channel estimation module 140, wherein a portion of the first descrambled data is set to calculate the noise variance, and the other portion of the data is first cached, and the corresponding channel estimation matrix is ​​obtained by using the Gaussian Approximation Message Passing (GAMP) algorithm and the above-mentioned noise variance calculation.

[0067] Optionally, the channel estimation matrix needs to undergo data conversion in the subcarrier-antenna dimension to obtain a target matrix, which is set as a subsequent signal detection module.

[0068] Specifically, the channel estimation module 140 caches the first descrambled data, estimates the noise variance and the first descrambled data using the GAMP algorithm, outputs the corresponding channel estimation matrix, and stores the channel estimation matrix in the FIFO after dimension transformation, providing an array for storing messages for subsequent multi-antenna transmission and reception (Multiple-Input Multiple-Output, MIMO) signal detection of the descrambled data.

[0069] The MIMO signal detection module 150 is configured to iteratively process the second descrambled data and the target matrix using Gaussian approximate interference belief propagation GAI_BP, and to cache and read the data in the iterative process using ping-pong storage technology, and to soft-demodulate the final iterative result after the target number of iterations to obtain bit soft information.

[0070] Optionally, the target number of iterations can be set according to user needs, for example, the target number of iterations is 5 times.

[0071] Optionally, the bit soft information includes bit log likelihood ratio (LLR) information.

[0072] Optionally, the MIMO signal detection module 150 adopts the Gaussian Approximation Of Interference Belief Propagation (GAI_BP) algorithm. After each iterative update, the MIMO signal detection module 150 sends the interference received by the data transmitted through the channel to the receiving side, and calculates the posterior information from the receiving side to the sending side.

[0073] Optionally, the bit soft information is stored in a channel estimation matrix output by the channel estimation module 140 .

[0074] Optionally, during actual operation, the processing delay of the MIMO signal detection module 150 is 1.44 ms.

[0075] The decoding module 160 is configured to decode the bit soft information according to the belief propagation BP algorithm to obtain a decoding result, and verify the decoding result to obtain verification data; the channel estimation module 140, the MIMO signal detection module 150 and the decoding module 160 are all constructed based on a message passing factor graph model.

[0076] Optionally, the decoding module 160 may support multiple different decoding methods. For example, the decoding module 160 includes a low-density parity-check code (LDPC) decoder, which is configured to perform LDPC decoding on the bit LLR message. The decoding module 160 may also include a polar code (Polar Codes) decoder and other decoders, which are configured to perform Polar decoding and other types of decoding on the bit LLR message.

[0077] Optionally, when decoding the bit soft information, the decoding module 160 can update the LLR information through the Belief Propagation (BP) algorithm, and transform the position of the bit soft information through the lightweight neural network Shuffle, and output the decision result after decoding.

[0078] Optionally, decoding results output by different decoders may all be checked using a CRC (Cyclic Redundancy Check) algorithm.

[0079] The baseband chip provided in the embodiment of the present application calculates the first descrambling data and the noise variance through the channel estimation module 140 to obtain a channel estimation matrix, obtains bit soft information through the MIMO signal detection module 150 using Gaussian approximate interference confidence propagation and ping-pong storage technology, decodes and verifies the bit soft information through the decoding module 160, and completes the frame structure encapsulation and transmission, and constructs each module with a message passing factor graph model, so that the baseband chip simultaneously has functions such as descrambling, channel estimation, MIMO detection, channel decoding, and CRC check, thereby improving the baseband signal processing efficiency.

[0080] Optionally, the baseband chip implements core baseband signal processing functions such as channel estimation, massive MIMO detection, channel coding decoding and CRC checking through a full message passing algorithm.

[0081] Optionally, the baseband chip 100 also includes: an Ethernet interface 110, which is configured to perform target processing on the input signal data to obtain a receiving side Ethernet frame; the target processing includes at least one of serial communication, clock recovery, channel equalization, signal scrambling / descrambling, signal encoding / decoding, elastic caching, link monitoring, data forwarding control, data framing, marking and data verification.

[0082] Optionally, the Ethernet interface 110 can receive data and send encapsulated data; the type of the Ethernet interface can be set according to user needs. For example, the Ethernet interface includes a 1G Ethernet interface, an XGE (Ten-Gigabit Ethernet, 10G Ethernet) interface or other interfaces. Moreover, the protocol types supported by the Ethernet interface include but are not limited to the IEEE 802.3 protocol.

[0083] Optionally, the baseband chip can realize the baseband receiving side signal processing function, specifically receiving input data through the high-speed Ethernet interface, and obtaining the receiving side Ethernet frame, that is, the Ethernet data frame through corresponding target processing. By adopting the IEEE 802.3 protocol to transmit data, it can support a maximum throughput of 9.6Gbps, meeting the high throughput requirements of the above-mentioned baseband chip.

[0084] Optionally, the target processing can be performed by different functional units. For example, the input parallel data is converted into serial data through SerDes (Serializer / Deserializer), and serial communication, clock recovery and channel equalization are performed in the physical medium attachment (PMA). The processed data is then processed by PCS (Physical Coding Sublayer) through frame synchronization, signal descrambling, signal decoding and elastic caching. Finally, MAC (Physical Coding Sublayer) performs packet parsing, status monitoring and asynchronous caching on the data output by PCS, and outputs the corresponding Ethernet frame.

[0085] Figure 2 is a schematic diagram of information interaction between the Ethernet interface, preprocessing module and channel estimation module provided by the present application. In the embodiment shown in Figure 2, the input data is converted into Ethernet frames through the Ethernet interface in sequence, frame parsing is performed through the parsing module, and the parsed data is preprocessed through the FIFO, specifically including cross-clock caching and processing of the parsed frame data, phase compensation, and descrambling through the pipeline beat register and configuration module, and a part of the descrambled data (first descrambled data) is input into the channel estimation module, specifically performing input caching and noise calculation, channel estimation using the GAMP algorithm, and output data conversion and caching operations to obtain the corresponding channel estimation matrix.

[0086] The baseband chip provided in the embodiment of the present application meets the high throughput performance requirements of the baseband chip by adopting the Ethernet interface 110 supporting the IEEE 802.3 protocol to send and receive data.

[0087] Optionally, the Ethernet interface 110 includes: a SerDes, which is configured to perform serial communication, clock recovery, and channel equalization on the input signal data to obtain first processed data; a physical coding sublayer PCS, which is configured to perform signal scrambling or descrambling, signal encoding or decoding, elastic caching, and link monitoring on the first processed data to obtain second processed data; a media access control layer MAC, which communicates with the MAC through a 10G media independent XGMII interface, and the MAC is configured to perform data forwarding control, data framing, marking, and data verification on the second processed data to obtain a receiving side Ethernet frame.

[0088] Optionally, a SerDes (SERializer / DESerializer) is configured to convert parallel data into serial data at the transmitting end of the Ethernet interface 110 or convert serial data into parallel data (at the receiving end of the Ethernet interface 110). In the Ethernet interface 110, the SerDes module is configured to serialize and deserialize data in the physical layer. The physical coding sublayer PCS is a sublayer in the Ethernet interface 110, configured to process data encoding and decoding and physical layer signal processing. The PCS processes data received from the MAC. The serial data is encoded and then passed to the SerDes module for serialization. At the receiving end, the PCS module deserializes and decodes the serial data received from the SerDes module and passes the decoded data to the MAC. The media access control layer MAC is configured to process the encapsulation, decapsulation, and transmission of data frames. In the Ethernet interface 110, the MAC is responsible for encapsulating the data from the upper layer into Ethernet frames and passing the encapsulated frames to the PCS for encoding and transmission. At the receiving end, the MAC receives the decoded data from the PCS layer, decapsulates it, and passes the data to the upper layer application.

[0089] Optionally, the SerDes, PCS, and MAC in the Ethernet interface 110 work in a collaborative manner to jointly complete data transmission and processing at the physical layer.

[0090] Optionally, the data link layer corresponding to the Ethernet interface 110 includes a serializer / deserializer SerDes, a physical coding sublayer PCS, and a media access control layer MAC in sequence, wherein the PCS interacts with the MAC through an XGMII (Ten Media Independent Interface) interface.

[0091] FIG3 is a schematic diagram of the working mechanism of the Ethernet interface provided by the present application. In the embodiment shown in FIG3 , at the transmitting end of the Ethernet interface, input data is sent to the SerDes through a pair of differential pins rxd_n and rxd_p of the optical port SFP+. The PMARX and corresponding control logic convert the input parallel data into serial data and send the serial data to the PCS for frame synchronization, 64B / 66B encoding, descrambling, decoding, status detection, and FIFO elastic buffering. The decoded data is then passed to the MAC. The MAC performs packet parsing and classification, status detection, asynchronous caching, and processing on the processed data to obtain an Ethernet frame. That is, the MAC receives the decoded data from the PCS, decapsulates it, and passes the data to the upper-layer application. At the receiving end, the MAC encapsulates the data from the upper layer into an Ethernet frame (performing status detection, pre-reading the first-in-first-out buffer FWFT in sequence). The SFP+ optical port is used to transmit the data in parallel to the serial data. ...

[0092] Optionally, the clock frequency of the SerDes is 10.3125 GHz, and the clock frequency of the MAC is 156.25 MHz.

[0093] The baseband chip provided in the embodiment of the present application sequentially processes the input data through SerDes, PCS, and MAC to obtain Ethernet frames, provides data support for subsequent data descrambling and data encapsulation, and can meet the high throughput requirements of the system bandwidth.

[0094] Optionally, the baseband chip 100 further includes: a parsing module 120 , a pre-processing module 130 and a packaging module 170 .

[0095] The parsing module 120 is configured to parse the receiving side Ethernet frame and identify error packets to obtain the target Ethernet frame data field.

[0096] Optionally, the parsing module 120 can parse the OFDM number, subband number and baseband data from the receiving side Ethernet frame, and identify error packets on the parsed data packets to ensure the accuracy and consistency of the link data.

[0097] The preprocessing module 130 is configured to perform cross-clock processing, bit width conversion, phase compensation and data descrambling on the target Ethernet frame data field to obtain multiple descrambled data; the multiple descrambled data include first descrambled data and second descrambled data; the parsing module 120 and the preprocessing module 130 adopt a pipeline design.

[0098] Optionally, the preprocessing module 130 is configured to perform cross-clock processing and bit width conversion on the parsed data (target Ethernet frame data field), so that one clock cycle of the baseband chip can just process the data of one antenna, and by performing phase compensation and data descrambling on the data after bit width conversion, descrambled data that can be set for channel estimation is obtained.

[0099] Optionally, the preprocessing module 130 uses FIFO (First Word Fall Through, first-in-first-out data storage, buffer) to perform cross-clock processing and bit width conversion on the target Ethernet frame after the error packet identification to obtain antenna data to adapt to the chip main frequency of 200MHz and the quantization bit width of the antenna data; then the antenna data is subjected to phase compensation and data descrambling calculation to obtain multiple descrambled data, which are set for subsequent channel estimation and MIMO signal detection.

[0100] Optionally, both the parsing module 120 and the pre-processing module 130 adopt a pipeline processing method to achieve high throughput requirements of the baseband chip.

[0101] The encapsulation module 170 is configured to perform bit width conversion and cross-clock domain conversion on the verification data in sequence to obtain converted data, and when the converted data belongs to business data, the converted data is marked according to the Ethernet frame format to obtain encapsulated data; the encapsulation module 170 is also configured to send the encapsulated data to the Ethernet interface 110; the Ethernet interface 110 is also configured to send the encapsulated data.

[0102] Optionally, the encapsulation module 170 encapsulates the verification data including the following steps:

[0103] (1) performing bit width conversion on the check data to obtain first converted data;

[0104] (2) converting the first conversion data from a clock frequency of 200 MHz to a clock frequency of 156.25 MHz to achieve cross-clock domain conversion, thereby obtaining second conversion data;

[0105] (3) When the second conversion data is determined to be business data based on the data frame length of the second conversion data, the second conversion data is determined to be data to be encapsulated, and then the second conversion data is marked according to the Ethernet frame format to obtain encapsulated data; finally, the encapsulation module 170 sends the encapsulated data to the Ethernet interface 110 and sends it out, thereby realizing the data automatic encapsulation function of the baseband chip.

[0106] Optionally, after obtaining the encapsulated data, the encapsulation module 170 is further configured to send the encapsulated data to the Ethernet interface 110, and perform status detection, pre-reading of the first-in-first-out buffer FWFT FIFO mode, CRC check and frame encapsulation on the Ethernet frame in the encapsulated data through MAC in sequence, and then perform FIFO elastic caching, encoding, scrambling, 66B / 64B decoding and PRBS (Pseudo-Random Binary Sequence) logical operation output on the data output by MAC through PCS, and finally output the corresponding encapsulated data through the control logic of SerDes.

[0107] The baseband chip provided in the embodiment of the present application parses the Ethernet frame on the receiving side and identifies error packets through the parsing module 120, and implements cross-clock processing, bit width conversion, phase compensation and data descrambling of the data through the preprocessing module 130, thereby providing effective descrambling data for subsequent channel detection and MIMO signal detection, thereby improving the detection accuracy; through the encapsulation module 170, the check data output by the decoding is sequentially subjected to bit width conversion, cross-clock domain conversion and Ethernet frame marking, thereby implementing Ethernet frame encapsulation, so that the baseband chip simultaneously has the functions of Ethernet frame parsing, descrambling and encapsulation, thereby improving the overall performance of the baseband chip.

[0108] Optionally, the decoding module 160 includes: at least two different decoders, the two different decoders are configured to determine the decoding results; a decoding standard configuration unit, which is arranged outside the at least two different decoders, and the decoding standard configuration unit includes a high-speed data cache and control module, a rate matching module, and a decoding-related parameter configuration module.

[0109] Optionally, the decoding standard configuration unit is configured to configure decoding-related parameters and is compatible with any of the 5G, B5G and 6G decoding standards.

[0110] Optionally, the decoding module 160 mainly includes decoders corresponding to the two encodings involved in the 5G standard, for example, including LDPC decoders and Polar decoders supporting the data channel and control channel in the 5G standard. In the specific decoding process, the corresponding decoding mode can be flexibly configured for different channel scenarios, that is, one of the decoders can be arbitrarily set to decode the bit soft information to obtain the corresponding decoding result.

[0111] The baseband chip provided in the embodiment of the present application meets different decoding requirements of users by setting two different decoders, and realizes flexible configuration of different decoders through a decoding standard configuration unit, thereby improving the decoding efficiency of the baseband chip.

[0112] Optionally, the at least two different decoders include: a low-density parity-check code LDPC decoder, which adopts a block-parallel and row-update decoding architecture; the LDPC decoder is configured to perform iterative update decoding and CRC check on bit soft information to obtain first check data; a polar code Polar decoder, which adopts a single-column decoding architecture, and is configured to perform rapid iteration and CRC check on the decoded soft information through parallel processing of operation units to obtain second check data; wherein the check data is one of the first check data and the second check data.

[0113] Optionally, the LDPC decoder supports multiple communication standard rates, including any one of the 5G standard rate, the B5G standard rate, and the 6G standard rate.

[0114] Optionally, the LDPC decoder and the polar code decoder support 3GPP (3rd Generation Partnership Project).

[0115] Optionally, after the bit LLR message output by the MIMO signal detection module 150 is dimensionally converted and rate matched, the decoding module 160 is configured to decode the bit LLR message; specifically, the two decoders used in this implementation, namely the LDPC decoder and the Polar decoder, both of which use the BP algorithm to decode the bit LLR messages separately.

[0116] Optionally, an LDPC decoder and a Polar decoder are set to decode the bit LLR messages in parallel respectively, which has low computational complexity and is easy to implement in hardware.

[0117] Optionally, the LDPC decoder and Polar decoder implement LDPC and Polar standards that meet 5G NR.

[0118] Optionally, the baseband chip is adapted to a frequency domain data processing scenario including multiple sub-bands. For example, for a frequency domain data processing scenario with 32 sub-bands, 32 sub-band data are allocated to one of the LDPC decoder and the Polar decoder. The BP algorithms of these two decoders update the LLR information and transform the position of the LLR information through the shuffle network. After decoding judgment, two decoding results are finally output.

[0119] Optionally, both of the above two decoding results are verified using a CRC algorithm to ensure decoding accuracy.

[0120] FIG4 is a schematic diagram of the structure of the decoding module provided by the present application. In the embodiment shown in FIG4 , the LLR storage array sent by the pre-processing module includes multiple bit LLR messages. The LDPC decoder sequentially implements barrel left shift calculation, CN / VN calculation (implemented based on the pipeline beat register), and barrel right shift calculation to obtain a first decoding result. The Polar decoder polarizes the information to be transmitted according to specific rules, that is, converts the input information sequence into a polarization sequence (the polarization sequence consists of a series of 1s and -1s, representing different polarization states). The polarization-encoded signal is transmitted through a channel to a receiver. The receiver first estimates the polarization of the received signal and decodes it using a decoding algorithm based on the polarization estimate. The decoder then outputs the recovered original information sequence to obtain a second decoding result. The first and second decoding results are stored in an array and verified using a CRC algorithm. Flexibly configure the decoding mode, iteration count, verification mode, and other status messages in the decoding module using configurable registers in the SPI. The decoding module also includes subband buffering and rate matching processes during operation.

[0121] Optionally, the decoding algorithm includes maximum likelihood decoding and soft decoding, and the goal of decoding is to restore the original information sequence encoded by the transmitter.

[0122] The baseband chip provided in the embodiment of the present application designs an LDPC decoder through a block-parallel and row-update decoding architecture, supports 5G standard rate matching, and designs a Polar decoder through a single-column decoding architecture, which can meet the baseband chip system bandwidth requirements in large-capacity communication applications.

[0123] Optionally, the MIMO signal detection module 150 is obtained by adopting a fully deployed architecture and a pipeline design.

[0124] Optionally, the MIMO signal detection module 150 includes an 8x816-QAM MIMO belief propagation detector designed with a fully expanded architecture.

[0125] Alternatively, by implementing an 8x8 16-QAM MIMO belief propagation detector design with an iterative fully expanded architecture, the system latency can be improved to 1.61ms, a 2.5x reduction compared to the user plane latency (4ms) required for 5G networks.

[0126] Figure 5 is a schematic diagram of the working mechanism of the 8×8 MIMO detector provided in the present application. In the embodiment shown in Figure 5, an 8×8 MIMO detector is used to receive the second descrambled data sent by the data conversion module, and after at least five iterations of the BP algorithm, the output data is soft-demodulated to obtain the corresponding bit LLR message; wherein, the 8×8 MIMO detector caches data by adopting a ping-pong storage method and transforms the matrix dimension, and is set to calculate the accumulated value of the posterior information and the prior probability, and then caches and transforms the matrix dimension again; after reaching 5 iterations, the soft demodulation module in the MIMO detection module recovers the bit LLR message from the prior probability and passes the bit LLR message to the decoding module for decoding processing.

[0127] The baseband chip provided in the embodiment of the present application can meet the low latency requirements in B5G / 6G by adopting an iterative fully expanded architecture to design a MIMO signal detector.

[0128] Optionally, the baseband chip 100 also includes: an SPI interface 180, which is configured to configure the user number, decoding mode, parallelism, iteration count, check mode, phase compensation value and scrambling code vector of the baseband chip; the SPI interface 180 is also configured to monitor the status of the baseband chip and realize the extended deployment of multiple baseband chips.

[0129] Optionally, the user number, decoding mode, parallelism, iteration count, check mode, phase compensation value and scrambling code vector of the baseband chip can be set according to user requirements.

[0130] Figure 6 is a second structural diagram of the baseband chip provided by the present application. In the embodiment shown in Figure 6, input data is obtained through the receiving side of the high-speed Ethernet interface, and Ethernet frame parsing, cross-clock caching and processing, phase compensation and descrambling are performed in sequence through the pre-processing module to obtain multiple descrambled data, and the first descrambled data is sent to the channel estimation module, which specifically performs input caching and noise calculation, GAMP channel estimation, output data conversion and caching operations to obtain a channel estimation matrix, and the second descrambled data is sent to the MIMO signal detection module, which specifically performs data conversion, BP MIMO detection and soft demodulation are performed to obtain corresponding bit LLR messages, i.e., bit soft information. The bit LLR messages are stored in the converted matrix. The clock frequencies of the baseband chip include: SerDes clock frequency: 10.3125 GHz, MAC clock frequency: 156.25 MHz, and system clock frequency: 200 MHz. The bit LLR messages in the LLR storage array are input into the decoding module for channel decoding. Specifically, the decoding mode can be configured to select an LDPC decoder or a Polar decoder for decoding, and the decoding results are output to a decoding storage sequence. The respective decoding processes are as described in the above embodiments and will not be repeated in this embodiment. The decoding results are subjected to CRC check and Ethernet frame encapsulation, and finally output through the high-speed Ethernet interface transmission side. The system configuration in the decoding module is flexibly configured by the configurable register of the SPI.

[0131] Figure 7 is the third structural schematic diagram of the baseband chip provided by the present application. In the embodiment shown in Figure 7, the branch prediction unit (BPU) includes a parsing module, a preprocessing module, a channel estimation module, a MIMO signal detection module, a decoding module and an encapsulation module; the Ethernet interface receiving end processes the input data through SerDes to obtain an Ethernet frame, and performs Ethernet frame parsing, descrambling, channel estimation, MIMO detection, decoding and verification on the Ethernet frame in sequence through the BPU to obtain verification data, set it as an Ethernet frame encapsulation, and send the encapsulated data through the Ethernet interface transmitting end; the clock signal clk and reset signal rst_n between the above modules are distributed by the clock and reset control module, and the relevant parameters between the modules are configured and managed by the SPI Slave module through the SPI interface; the baseband processing module based on the full message passing algorithm includes a channel estimation module, a MIMO signal detection module and a decoding module.

[0132] The baseband chip provided in the embodiment of the present application configures the user number, decoding mode, parallelism, iteration count, check mode, phase compensation value and scrambling code vector of the baseband chip through the SPI interface 180, which can meet the flexible and configurable requirements of the baseband chip parameters.

[0133] Optionally, the computing unit of the baseband chip adopts a universal design architecture.

[0134] Optionally, data transmission between the above modules is realized by using a message passing factor graph model, thereby improving the efficiency of information transmission between modules;

[0135] Optionally, the computing unit of the baseband circuit has a universal design architecture, which improves the flexibility of circuit design and thereby improves hardware operating efficiency.

[0136] The baseband chip provided in the embodiment of the present application can ensure that the baseband chip simultaneously meets high throughput, ultra-low latency, and flexible configurability and scalability.

[0137] The signal system provided in this application is described below. The signal system described below and the baseband chip described above can be referenced to each other.

[0138] FIG8 is a schematic structural diagram of a signal system provided in the present application. As shown in FIG8 , the signal system 800 includes a plurality of baseband chips 100 .

[0139] Each reception chip supports multiple-receive and multiple-transmit MIMO scenarios to implement user-side baseband signal processing in large-scale MIMO systems.

[0140] Optionally, the baseband chip 100 includes an Ethernet interface, a parsing module, a preprocessing module, a channel estimation module, a MIMO signal detection module, a decoding module, an encapsulation module and an SPI interface; wherein the Ethernet interface includes SerDes, PCS and MAC; the decoding module includes an LDPC decoder, a Polar decoder and a decoding standard configuration unit; the functions and connection relationships of each module correspond to the modules in the above embodiments, and are not repeated in this embodiment.

[0141] Optionally, each baseband chip supports 8-transmit 8-receive MIMO scenarios, capable of frequency domain data processing of 32 sub-bands; in addition, the signal system expands and deploys multiple baseband chips to achieve 128x128 large-scale MIMO system user-side baseband signal processing.

[0142] In the embodiment shown in FIG. 8 , the signal system 800 supports extended deployment of n baseband chips 100 , where n is a natural number greater than 1.

[0143] Optionally, the baseband chip based on Bayesian learning can support 8-transmit 8-receive MIMO scenarios, realize frequency domain data processing including multiple sub-bands, and support the expansion deployment of multiple chips to realize 128x128 large-scale MIMO system user-side baseband signal processing, thereby improving the scalability of the baseband chip design.

[0144] The signal system provided in the embodiment of the present application realizes that the B5G / 6G system-level baseband chip simultaneously has core baseband signal processing functions such as descrambling, channel estimation, MIMO detection, channel decoding, and CRC check, thereby improving the baseband signal processing efficiency and supporting the expanded deployment of multiple baseband chips mentioned above, thereby improving the scalability of the baseband chip.

[0145] The baseband chip control method provided in the present application is described below. The baseband chip control method described below and the baseband chip described above can be referenced to each other.

[0146] FIG9 is a flow chart of a baseband chip control method provided in the present application. As shown in FIG9 , the baseband chip control method includes the following steps:

[0147] Step 910: Receive first descrambled data, calculate the first descrambled data and noise variance according to the Gaussian Approximate Message Passing (GAMP) algorithm to obtain a channel estimation matrix, and perform data conversion of the channel estimation matrix in the subcarrier-antenna dimension to obtain a target matrix; the noise variance is determined based on the first descrambled data.

[0148] Optionally, multiple descrambled data are obtained by performing Ethernet frame parsing and descrambling on the input signal data, wherein the first descrambled data is a part of the multiple descrambled data.

[0149] Optionally, the noise variance is determined by channel parameters of a channel estimation module and is independent of the input descrambled data.

[0150] Optionally, Ethernet frame parsing and preprocessing adopt a pipeline design to achieve high-speed data transmission; a part of the multiple descrambled data (corresponding to the first descrambled data) is input into the channel estimation module, wherein a part of the first descrambled data is set to calculate the noise variance, and the other part of the data is first cached, and the corresponding channel estimation matrix is ​​obtained by using the GAMP algorithm and the above-mentioned noise variance calculation.

[0151] Optionally, the channel estimation matrix needs to undergo data conversion in the subcarrier-antenna dimension before being output to the subsequent detection module.

[0152] Specifically, a channel estimation module can be used to execute step 910. The channel estimation module caches the first demodulated data and uses the GAMP algorithm to estimate the noise variance and the first demodulated data, outputs the corresponding channel estimation matrix, and stores the channel estimation matrix in the FIFO after dimension transformation, providing an array for storing messages for subsequent multi-antenna transmission and reception MIMO signal detection of the demodulated data.

[0153] Step 920: The second descrambled data and the target matrix are iteratively processed using Gaussian approximation interference belief propagation (GAI_BP), and the data in the iterative process are cached and read controlled using ping-pong storage technology. After the target number of iterations, the final iterative result is soft-demodulated to obtain bit soft information. The first descrambled data and the second descrambled data are both obtained by sequentially acquiring, parsing, and preprocessing the input signal data through Ethernet frames.

[0154] Optionally, the target number of iterations can be set according to user needs, for example, the target number of iterations is 5 times.

[0155] Optionally, the bit soft information includes a bit log-likelihood ratio (LLR) message.

[0156] Optionally, by adopting the GAI_BP algorithm, the MIMO signal detection module sends interference to the data transmitted through the channel to the receiving side after each iterative update, and calculates the a posteriori information from the receiving side to the sending side.

[0157] Optionally, the bit soft information is stored in a channel estimation matrix output by the channel estimation module.

[0158] Optionally, in actual operation, step 920 is performed by the MIMO signal detection module 150, and the corresponding processing delay is 1.44 ms.

[0159] Step 930: Decode the bit soft information according to the belief propagation BP algorithm to obtain a decoding result, and verify the decoding result to obtain verification data to implement Ethernet frame encapsulation and transmission.

[0160] Optionally, a decoding module is used to perform step 930; the decoding module supports multiple different decoding methods, for example, the decoding module LDPC decoder is configured to perform LDPC decoding on the bit LLR message; the decoding module can also include a Polar decoder and other decoders, which are configured to perform Polar decoding and other types of decoding on the bit LLR message.

[0161] Optionally, when decoding the bit soft information, the decoding module can update the LLR information through the BP algorithm, transform the position of the bit soft information through the Shuffle network, and output the decision result after decoding.

[0162] Optionally, the decoding results output by different decoders may all be verified using a CRC algorithm.

[0163] Optionally, the baseband chip implements core baseband signal processing functions such as channel estimation, massive MIMO detection, channel coding decoding and CRC checking through a full message passing algorithm.

[0164] Figure 10 is a flow chart of MIMO signal detection provided by the present application. In the embodiment shown in Figure 9, the MIMO detector calculates the interference received by the receiving side of the transmitted data through the channel transmission, calculates the a posteriori information from the receiving side to the transmitting side, and uses a ping-pong storage method to cache the data and transform the matrix dimension. The cumulative value of the a posteriori information is calculated using the transformed matrix dimension, and then the corresponding prior probability is calculated, which is set as a soft demodulation process; at the same time, the ping-pong storage method is used to cache the data and transform the matrix dimension, and iterates in sequence. After meeting the target number of iterations, the corresponding bit LLR message, that is, the bit soft information, is obtained.

[0165] Figure 11 is the second flow chart of the baseband chip control method provided by the present application. In the embodiment shown in Figure 10, the baseband chip control method also includes the following steps: the transmitting end sends high-definition video data, the chip is powered on, and the interface status information is read through the SPI interface to check whether the power-on is successful; the initial information is configured through the SPI interface, such as the user number, the scrambling code vector and phase compensation vector set for preprocessing, the decoding mode, the number of iterations, the CRC check mode and other status messages; the data reception is enabled, the receiving status register in the Ethernet frame parsing module is read, and the baseband processing is started when the OFDM received is 1; the data undergoes preprocessing, channel estimation, MIMO detection, decoding, and CRC check, and the status registers of each module are read regularly to determine whether the decoding is successful and the check status; the message sending information in the Ethernet frame encapsulation is monitored to check whether the sent message matches the interface; the high-definition video stream is checked through the server side to see whether it is played normally. If it is played normally, the entire chip is flowing.

[0166] The baseband chip control method provided in the embodiment of the present application obtains a channel estimation matrix by calculating the first descrambling data and the noise variance, obtains bit soft information by adopting Gaussian approximate interference belief propagation and ping-pong storage technology, decodes and verifies the bit soft information, completes frame structure encapsulation and transmission, and constructs each module through a message passing factor graph model, so that the baseband chip simultaneously has functions such as descrambling, channel estimation, MIMO detection, channel decoding, CRC check, etc., thereby improving the baseband signal processing efficiency.

[0167] Figure 11 is a structural diagram of the electronic device provided in the present application. As shown in Figure 11, the electronic device may include: a processor (processor) 1210, a communication interface (Communications Interface) 1220, a memory (memory) 1230 and a communication bus 1240, wherein the processor 1210, the communication interface 1220, and the memory 1230 communicate with each other through the communication bus 1240. The processor 1210 can call the logic instructions in the memory 1230 to execute the above-mentioned baseband chip control method, which includes: receiving first descrambled data, calculating the first descrambled data and noise variance according to the Gaussian approximate message passing (GAMP) algorithm to obtain a channel estimation matrix, and performing data conversion of the channel estimation matrix in the subcarrier-antenna dimension to obtain a target matrix; the noise variance is determined based on the first descrambled data; iteratively processing the second descrambled data and the target matrix using the Gaussian approximate interference belief propagation (GAI_BP), caching and reading control processing of the data in the iterative process using the ping-pong storage technology, and soft-demodulating the final iterative result after the target number of iterations to obtain bit soft information; the first descrambled data and the second descrambled data are both obtained by sequentially acquiring, parsing, and preprocessing the input signal data through Ethernet frames; decoding the bit soft information according to the belief propagation BP algorithm to obtain a decoding result, and verifying the decoding result to obtain verification data to achieve Ethernet frame encapsulation and transmission.

[0168] In addition, the logic instructions in the above-mentioned memory 1230 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0169] On the other hand, the present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the above-mentioned baseband chip control method, the method comprising: receiving first descrambling data, calculating the first descrambling data and the noise variance according to the Gaussian approximate message passing GAMP algorithm to obtain a channel estimation matrix, and performing data conversion of the channel estimation matrix in the subcarrier-antenna dimension to obtain a target matrix; the noise variance is determined based on the first descrambling data; the second descrambling data and the target matrix are iteratively processed using Gaussian approximate interference belief propagation GAI_BP, and the data in the iterative process are cached and read controlled using ping-pong storage technology, and the final iterative result is soft-demodulated after the target number of iterations to obtain bit soft information; the first descrambling data and the second descrambling data are both obtained by sequentially acquiring, parsing and preprocessing the input signal data through Ethernet frames; decoding the bit soft information according to the belief propagation BP algorithm to obtain a decoding result, and verifying the decoding result to obtain verification data to realize Ethernet frame encapsulation and transmission.

[0170] On the other hand, the present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the baseband chip control method provided by the above methods, the method comprising: receiving first descrambled data, calculating the first descrambled data and the noise variance according to the Gaussian approximate message passing GAMP algorithm to obtain a channel estimation matrix, and performing data conversion of the channel estimation matrix in the subcarrier-antenna dimension to obtain a target matrix; the noise variance is determined based on the first descrambled data; the second descrambled data and the target matrix are iteratively processed using Gaussian approximate interference belief propagation GAI_BP, and the data in the iterative process is cached and read controlled using ping-pong storage technology, and the final iterative result is soft-demodulated after the target number of iterations to obtain bit soft information; the first descrambled data and the second descrambled data are both obtained by sequentially acquiring, parsing and preprocessing the input signal data through Ethernet frames; decoding the bit soft information according to the belief propagation BP algorithm to obtain a decoding result, and verifying the decoding result to obtain verification data to achieve Ethernet frame encapsulation and transmission.

[0171] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0172] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A baseband chip, comprising: A channel estimation module, which is configured to receive first descrambled data, calculate the first descrambled data and the noise variance according to the Gaussian approximation message passing (GAMP) algorithm to obtain a channel estimation matrix, and perform subcarrier-antenna dimension data conversion on the channel estimation matrix to obtain a target matrix; A multiple-input multiple-output (MIMO) signal transmitting and receiving module, which is configured to perform iterative processing on second descrambled data and the target matrix using Gaussian approximation interference belief propagation (GAI_BP), and use a ping-pong storage technique to perform cache and read control processing on the data during the iterative process, and perform soft demodulation on the final iterative result after a target number of iterations to obtain bit soft information; A decoding module, which is configured to decode the bit soft information according to the belief propagation (BP) algorithm to obtain a decoding result, and perform verification on the decoding result to obtain verification data, so as to implement Ethernet frame encapsulation and transmission; Wherein, the channel estimation module, the MIMO signal detection module and the decoding module are all constructed based on a message passing factor graph model; the noise variance is determined based on the first descrambled data, and the first descrambled data and the second descrambled data are both obtained by sequentially performing Ethernet frame acquisition, parsing and preprocessing on the input signal data.

2. The baseband chip according to claim 1, wherein, The baseband chip further comprises: An Ethernet interface; the Ethernet interface is configured to perform target processing on the input signal data to obtain a receive-side Ethernet frame; the target processing includes at least one of serial communication, clock recovery, channel equalization, signal scrambling / descrambling, signal encoding / decoding, elastic buffering, link monitoring, data forwarding control, data framing, marking and data verification.

3. The baseband chip according to claim 2, wherein, The Ethernet interface includes: A SerDes, which is configured to perform serial communication, clock recovery and channel equalization processing on the input signal data to obtain first processed data; A physical coding sublayer (PCS), which is configured to perform signal scrambling or descrambling, signal encoding or decoding, elastic buffering and link monitoring processing on the first processed data to obtain second processed data; A media access control layer (MAC), which is configured to perform data forwarding control, data framing, marking and data verification processing on the second processed data to obtain the receive-side Ethernet frame.

4. The baseband chip according to claim 1, wherein, The baseband chip further comprises: An analysis module, which is configured to analyze and identify mispackets in the receive-side Ethernet frame to obtain a target Ethernet frame data field; A preprocessing module, which is configured to perform cross-clock processing, bit width conversion, phase compensation and data descrambling on the target Ethernet frame data field to obtain a plurality of descrambled data; the plurality of descrambled data includes the first descrambled data and the second descrambled data; the analysis module and the preprocessing module adopt a pipeline design; An encapsulation module, which is configured to perform bit-width conversion and cross-clock domain conversion on the verification data in sequence to obtain the converted data, and when the converted data belongs to service data, mark the converted data in the format of an Ethernet frame to obtain encapsulated data; Wherein, the encapsulation module is further configured to send the encapsulated data to an Ethernet interface.

5. The baseband chip according to claim 1, wherein, The decoding module includes: At least two different decoders, and the two different decoders are configured to determine the decoding result; A decoding standard configuration unit, disposed around the at least two different decoders, and the decoding standard configuration unit includes a high-speed data cache and control module, a rate matching module, and a decoding-related parameter configuration module.

6. The baseband chip according to claim 5, wherein, The at least two different decoders include: A low-density parity-check (LDPC) decoder, and the LDPC decoder adopts a block-parallel and row-update decoding architecture; the LDPC decoder is configured to perform iterative update decoding and CRC check on bit soft information to obtain first verification data; A Polar decoder, and the Polar decoder adopts a single-column decoding architecture, and the Polar decoder is configured to perform fast iteration and CRC check on decoding soft information through parallel processing of an arithmetic unit to obtain second verification data; Wherein, the verification data is one of the first verification data and the second verification data.

7. The baseband chip according to claim 1, wherein, The MIMO signal detection module is obtained by adopting a fully-expanded architecture and a pipeline design.

8. The baseband chip according to claim 1, wherein The baseband chip further includes: An SPI interface and a configuration management module, and the SPI interface is configured to configure the user number, decoding mode, parallelism, iteration count, verification mode, phase compensation value, and scrambling vector of the baseband chip; The SPI interface is further configured to monitor the status of the baseband chip and implement extended deployment of multiple baseband chips.

9. The baseband chip according to claim 1, wherein, The arithmetic unit of the baseband chip is determined by adopting a general design architecture.

10. A signal system, including: Multiple baseband chips as described in any one of claims 1-9, and each receiving chip supports a multi-receive and multi-transmit MIMO scenario to implement baseband signal processing on the user side of a large-scale MIMO system.

11. A method for controlling a baseband chip, including: Receiving first descrambled data, calculating the first descrambled data and noise variance according to the Gaussian approximation message passing (GAMP) algorithm to obtain a channel estimation matrix, and performing subcarrier-antenna dimension data conversion on the channel estimation matrix to obtain a target matrix; The noise variance is determined based on the first descrambled data; Performing iterative processing on second descrambled data and the target matrix by using Gaussian approximation interference belief propagation (GAI_BP), and adopting a ping-pong storage technology to perform cache and read control processing on the data in the iterative process, and performing soft demodulation on the final iterative result after a target number of iterations to obtain bit soft information; both the first descrambled data and the second descrambled data are obtained by sequentially performing Ethernet frame acquisition, parsing, and preprocessing on the input signal data; Decode the bit soft information according to the belief propagation (BP) algorithm to obtain a decoding result, and check the decoding result to obtain check data, so as to implement Ethernet frame encapsulation and transmission.

12. The baseband chip control method according to claim 11, wherein, The method further includes: Perform target processing on the input signal data to obtain an Ethernet frame on the receiving side; the target processing includes at least one of serial communication, clock recovery, channel equalization, signal scrambling / descrambling, signal encoding / decoding, elastic buffering, link monitoring, data forwarding control, data framing, tagging, and data checking.

13. The baseband chip control method according to claim 12, wherein, The performing target processing on the input signal data to obtain an Ethernet frame on the receiving side includes: Perform serial communication, clock recovery, and channel equalization processing on the input signal data to obtain first processed data; Perform signal scrambling or descrambling, signal encoding or decoding, elastic buffering, and link monitoring processing on the first processed data to obtain second processed data; Perform data forwarding control, data framing, tagging, and data checking processing on the second processed data to obtain the Ethernet frame on the receiving side.

14. The baseband chip control method according to claim 11, wherein, The method further includes: Parse the Ethernet frame on the receiving side and identify mispackets to obtain a target Ethernet frame data field; Perform cross-clock processing, bit-width conversion, phase compensation, and data descrambling on the target Ethernet frame data field to obtain multiple descrambled data; the multiple descrambled data include the first descrambled data and the second descrambled data; the parsing module and the preprocessing module adopt a pipeline design; Perform bit-width conversion and cross-clock domain conversion on the check data in sequence to obtain converted data, and when the converted data belongs to service data, mark the converted data in the Ethernet frame format to obtain encapsulated data, and send the encapsulated data to the Ethernet interface.

15. The baseband chip control method according to claim 11, wherein, The decoding the bit soft information according to the belief propagation (BP) algorithm to obtain a decoding result includes: Determine the decoding result based on at least two different decoders; a decoding standard configuration unit is arranged around the at least two different decoders, and the decoding standard configuration unit includes a high-speed data cache and control module, a rate matching module, and a decoding related parameter configuration module.

16. The baseband chip control method according to claim 15, wherein, The decoding the bit soft information according to the belief propagation (BP) algorithm to obtain a decoding result, and checking the decoding result to obtain check data includes: Perform iterative update decoding and CRC check on the bit soft information to obtain first check data; Perform fast iteration and CRC check on the decoded soft information through parallel processing of an arithmetic unit to obtain second check data; Wherein, the check data is one of the first check data and the second check data.

17. The baseband chip control method according to claim 11, wherein, The bit soft information is obtained through a multi-antenna transmission and reception MIMO signal detection module; the MIMO signal detection module is obtained by adopting a fully expanded architecture and a pipeline design.

18. The baseband chip control method according to claim 11, wherein, The method further includes: Configure the user number, decoding mode, parallelism, iteration count, check mode, phase compensation value, scrambling vector of the baseband chip through an SPI interface, monitor the state of the baseband chip, and implement extended deployment of multiple baseband chips.

19. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein, When the processor executes the program, it implements the baseband chip control method described in any one of claims 11-18.

20. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein, When the computer program is executed by the processor, it implements the baseband chip control method described in any one of claims 11-18.

21. A computer program product, comprising a computer program, wherein, When the computer program is executed by the processor, it implements the baseband chip control method described in any one of claims 11-18.

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