Cache request processing method and apparatus, device, storage medium and program

Abstract

Provided in the present application are a cache request processing method and apparatus, an electronic device, a computer-readable storage medium and a computer program. The method comprises: on the basis of to the types of requests obtained by a secondary cache, selecting a target request from all the requests, and enabling the target request to enter a pipeline queue of the secondary cache from a specific data bit of the pipeline queue for executing same; when the pipeline queue has successfully executed the target request, returning a response generated by executing the target request; and when the pipeline queue has failed to successfully execute the target request, allocating a corresponding missing status register to the target request, and executing the target request by means of the missing status register. The present application allocates a corresponding missing status register to a target request only when the target request has failed to be successfully executed, such that the present application reduces the allocation consumption of missing status register resources while meeting the requirement of re-executing the target request which has failed to be successfully executed, thus reducing the delay caused by the resource allocation of missing status registers.

Description

Cache request processing method, device, equipment, storage medium and program

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 15, 2024, with application number 202410057628.9 and application name “Method, device, equipment and storage medium for processing cache requests”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a method, device, electronic device, computer-readable storage medium, and computer program for processing a cache request. Background Art

[0004] Cache is an important component in modern high-performance processors. By setting up a cache between the processor and the memory, the cache can be used to store data that the processor frequently accesses, thereby improving the access speed of the processor.

[0005] Currently, modern processors generally have three levels of cache: L1 cache, L2 cache, and L3 cache. The processor's memory access instructions access the cache data by sequentially accessing L1 cache, L2 cache, and L3 cache. L2 cache is generally exclusive to a single core and needs to balance low access latency and high throughput. A good L2 cache design can significantly improve processor performance. Specifically, L2 cache will allocate a miss status register (MSHR) for each input request. MSHR is a register used to record each incomplete request. MSHR can help previously incomplete requests to be successfully executed again.

[0006] However, in the above process, allocating a corresponding MSHR for each request will result in excessive consumption of MSHR resources and increased latency. Summary of the Invention

[0007] Embodiments of the present application provide a method, device, electronic device, computer-readable storage medium, and computer program for processing a cache request to solve problems in related technologies.

[0008] In a first aspect, an embodiment of the present application provides a method for processing a cache request, the method comprising:

[0009] Selecting a target request from all requests according to the type of the request obtained by the secondary cache, and entering the target request from a specific data bit of a pipeline queue of the secondary cache into the pipeline queue for execution; the pipeline queue includes a plurality of data bits arranged in sequence;

[0010] When the pipeline queue successfully executes the target request, a response generated by executing the target request is returned;

[0011] When the pipeline queue fails to successfully execute the target request, a corresponding missing status register is allocated to the target request, and the target request is executed through the missing status register.

[0012] In a second aspect, an embodiment of the present application provides a cache request processing device, the device comprising:

[0013] an enqueue module, configured to select a target request from all requests obtained by the secondary cache according to the type of the request, and enter the target request from a specific data bit of a pipeline queue of the secondary cache into the pipeline queue for execution; the pipeline queue includes a plurality of data bits arranged in sequence;

[0014] A return module, configured to return a response generated by executing the target request when the pipeline queue successfully executes the target request;

[0015] An execution module is used to allocate a corresponding missing status register to the target request when the pipeline queue fails to successfully execute the target request, and execute the target request through the missing status register.

[0016] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor;

[0017] a memory for storing instructions executable by the processor;

[0018] The processor is configured to execute the instructions to implement the method of the first aspect.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0020] In a fifth aspect, an embodiment of the present application provides a computer program, comprising a computer-readable code, which, when executed on a computing and processing device, causes the computing and processing device to execute the method of the first aspect.

[0021] In an embodiment of the present application, a target request can be selected from all requests according to the type of request obtained by the secondary cache to enter the pipeline queue for execution. When the pipeline queue fails to successfully execute the target request, a corresponding missing status register is allocated to the target request for processing. In the present application, when the target request enters the pipeline queue of the secondary cache, the corresponding missing status register is not allocated to it. Only when the target request fails to be successfully executed is the corresponding missing status register allocated to it. This allows the present application to reduce the allocation consumption of missing status register resources on the basis of meeting the need to re-execute the target request that has not been successfully executed, and reduces the delay caused by the allocation of missing status register resources.

[0022] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is an architecture diagram of an implementation scenario provided by an embodiment of the present application;

[0025] FIG2 is a flowchart of a method for processing a cache request according to an embodiment of the present application;

[0026] FIG3 is a flowchart of the specific steps of a method for processing a cache request provided in an embodiment of the present application;

[0027] FIG4 is a diagram of a secondary cache architecture provided by an embodiment of the present application;

[0028] FIG5 is a block diagram of a cache request processing device provided in an embodiment of the present application;

[0029] FIG6 schematically shows a block diagram of a computing and processing device for executing the method according to the present application;

[0030] FIG7 schematically shows a storage unit for holding or carrying program codes for implementing the method according to the present application;

[0031] FIG8 is a block diagram of an electronic device provided in an embodiment of the present application. Specific embodiments

[0032] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0034] Referring to Figure 1, Figure 1 is an architecture diagram of an implementation scenario provided by an embodiment of the present application. In order to improve execution efficiency and reduce the interaction between the processor and the memory, modern processors can integrate a multi-level cache architecture on the processor. The common architecture is the three-level cache structure of Figure 1, including: Level 1 cache L1, Level 2 cache L2 and Level 3 cache L3. Level 1 cache L1 is the cache closest to the processor, with the smallest capacity and the fastest speed; Level 2 cache L2 has a larger capacity but is slower than Level 1 cache L1. Level 2 cache L2 is the buffer of Level 1 cache L1. The function of Level 2 cache L2 is to store data that is needed for processor processing but cannot be stored by Level 1 cache L1; Level 3 cache L3 has the largest capacity and is also the slowest level. Level 3 cache L3 and memory can be regarded as buffers of Level 2 cache L2.

[0035] When the processor is running, it will first search the L1 cache for the required data according to the memory access instruction, then the L2 cache, and then the L3 cache. If the data is not found in the L3 cache, it will be retrieved from the main memory. The longer the search path, the longer it takes. Therefore, if certain data needs to be retrieved frequently, it is best to ensure that this data is in the L1 cache, so that the speed will be very fast. Among them, the memory access instruction is an instruction to obtain data from a specified address in the main memory, or to store data to a specified address in the main memory.

[0036] Preferably, the secondary cache L2 can adopt a 5-level pipeline architecture, and the pipeline queue can include 5 sequentially arranged data bits: data bit S1-data bit S5, each data bit corresponds to a pipeline moment, and different data bits correspond to different pipeline moments. The request is used to enter the pipeline from the initial data bit of the pipeline queue and change the data bit with the passage of time. In addition, for different types of requests, the embodiments of the present application can design the operation performed on the data bit according to the type of request, the status of the data block accessed by the request, and the data bit of the request in the pipeline queue (one data bit is used to represent a pipeline moment), so that when the request is in a specific target data bit in the pipeline queue, it can perform the operation corresponding to the type of request and the target data bit.

[0037] FIG2 is a flowchart of a method for processing a cache request provided by an embodiment of the present application. As shown in FIG2 , the method may include:

[0038] Step 101: Select a target request from all requests according to the type of request obtained by the secondary cache, and enter the target request from a specific data bit of the pipeline queue of the secondary cache into the pipeline queue for execution; the pipeline queue includes multiple data bits arranged in sequence.

[0039] In an embodiment of the present application, the secondary cache may adopt a multi-stage pipeline architecture, that is, it includes a pipeline queue having multiple sequentially arranged data bits, each data bit corresponds to a pipeline moment, and different data bits correspond to different pipeline moments. The function of the pipeline queue is to receive and issue instructions and maintain the status of the instructions according to the timing. Preferably, the specific data bit can be a starting data bit, and the instruction can specifically enter the pipeline for execution from the starting data bit of the pipeline queue. Of course, the specific data bit can also be a data bit other than the starting data bit, and this application does not limit this.

[0040] The secondary cache can process many requests during operation, thereby realizing functions related to data access. The requests processed by the secondary cache are of various types, and when different types of requests are executed, corresponding operations will be performed at different times. Based on this feature, the embodiment of the present application can design the operation performed at the data bit according to the type of request, the directory status of the data block accessed by the request, and the data bit where the request is located in the pipeline queue (one data bit is used to represent a pipeline moment), so that when the request is in a specific target data bit in the pipeline queue, the operation corresponding to the type of request and the target data bit can be performed.

[0041] For example, the types of requests obtained by the secondary cache include: channel task types issued by the processor, missing status register types generated by missing status registers (registers used to handle unsuccessfully executed requests), etc., among which the channel task types further include data acquisition types (used to read data in the secondary cache), data release types (used to release data in the secondary cache), data exploration types (used to invalidate data in the secondary cache), etc.

[0042] Specifically, the secondary cache may receive multiple requests at the same time, but the pipeline design of the secondary cache requires that only one request enter the pipeline queue at the same time. Therefore, when the secondary cache receives multiple requests at the same time, a target request can be selected from all requests to enter the pipeline queue from a specific data bit (preferably data bit S1 in Figure 1), thereby starting the secondary cache to execute the target request. In one implementation, a target request can be selected from all requests based on the type of request. That is, the embodiment of the present application sets the priority of each type of request based on the characteristics of different types of requests. Based on the priority size of the type, a request of a type with a high priority can be selected as the target request.

[0043] Step 102: When the pipeline queue successfully executes the target request, a response generated by executing the target request is returned.

[0044] In the embodiment of the present application, the response results generated by executing the target request vary depending on the type of target request. For example, after a data acquisition type target request is successfully executed, the response result generated includes the read data; after a data release type target request is successfully executed, the response result generated includes a notification message that the data has been released. In the embodiment of the present application, when the pipeline queue successfully executes the target request, the response generated by executing the target request is returned, that is, the response result of the request is fed back to the initiator of the request.

[0045] Step 103: When the pipeline queue fails to successfully execute the target request, a corresponding missing status register is allocated to the target request, and the target request is executed through the missing status register.

[0046] In an embodiment of the present application, for a target request that is not successfully executed in the secondary cache, a corresponding missing status register (MSHR) can be assigned to the target request, and the target request is entered into the missing status register for waiting, and the target request is executed through the missing status register. Specifically, the missing status register is a register used to record each unfinished transaction. The recorded information includes the failed address, information about the unfinished execution instruction, directory status, etc., and the sub-requests required to complete the execution of the request are sent to the upper and lower level caches. Once the subsequent secondary cache has the conditions to execute the target request, the target request in the missing status register can be separated from the missing status register and enter the pipeline queue of the secondary cache for re-execution.

[0047] In the cache architecture, the number of missing status registers is limited. If a corresponding missing status register is allocated for each request entering the L2 cache pipeline queue, then when the number of requests is large, it will lead to insufficient missing status register resources. Moreover, when the number of requests is large and the missing status register resources are insufficient, it will block the entry of new requests, and actually limit the maximum number of parallel requests that the L2 cache can process. In addition, in this allocation method, the target instructions that can be successfully executed by the L2 cache pipeline queue do not actually need to enter the missing status register for processing. Therefore, the missing status registers allocated to these target instructions that can be successfully executed actually result in a waste of resources.

[0048] However, in the embodiment of the present application, when the target request enters the pipeline queue of the secondary cache, the corresponding missing status register is not allocated for it. The corresponding missing status register is allocated only when the target request fails to be successfully executed. The embodiment of the present application reduces the allocation consumption of missing status register resources on the basis of meeting the demand for re-execution of the target request that has not been successfully executed, thereby reducing the probability of blocking the entry of new requests due to insufficient missing status register resources. For target requests that can be successfully executed, there is no need to allocate missing status registers, thereby avoiding the waste of missing status register resources.

[0049] In summary, in the embodiment of the present application, a target request can be selected from all requests according to the type of request obtained by the secondary cache to enter the pipeline queue for execution. When the pipeline queue fails to successfully execute the target request, a corresponding missing status register is allocated to the target request for processing. In the present application, when the target request enters the pipeline queue of the secondary cache, the corresponding missing status register is not allocated to it. Only when the target request fails to be successfully executed is the corresponding missing status register allocated to it. This allows the present application to reduce the allocation consumption of missing status register resources on the basis of meeting the demand for re-execution of the target request that has not been successfully executed, and reduces the delay caused by the allocation of missing status register resources.

[0050] FIG3 is a flowchart of specific steps of a method for processing a cache request provided by an embodiment of the present application. As shown in FIG3 , the method may include:

[0051] Step 201: Select a target request from all requests according to the type of request obtained by the secondary cache.

[0052] This step may be specifically referred to the above step 101 and will not be described in detail here.

[0053] Optionally, step 201 may specifically include sub-steps 2011-2014:

[0054] Sub-step 2011: When there is a request of a missing status register type among all the requests, use the request of the missing status register type as the target request.

[0055] Sub-step 2012: Among all the requests, if there is no request of missing status register type but there is a request of data release type, use the request of data release type as the target request.

[0056] Sub-step 2013: Among all the requests, if there is no missing status register type or data release type request, but there is a data exploration type request, use the data exploration type request as the target request.

[0057] Sub-step 2014: Among all the requests, if there is no request of missing status register type, data release type, or data exploration type, but there is a request of data acquisition type, the request of data acquisition type is used as the target request.

[0058] In an embodiment of the present application, for sub-steps 2011-2014, the requests processed by the secondary cache are of multiple types. When different types of requests are executed, corresponding operations will be performed at different times. In addition, the secondary cache may obtain multiple requests at the same time, but the pipeline design of the secondary cache requires that only one request enters the pipeline queue at the same time. Therefore, when the secondary cache obtains multiple requests at the same time, a target request can be selected from all requests to enter the pipeline queue from a specific data bit, thereby starting the execution of the target request by the secondary cache.

[0059] Specifically, the embodiment of the present application can select a target request from all requests based on the priority of the request type, that is, the embodiment of the present application sets the priority of each type of request based on the characteristics of different types of requests, and then based on the priority size of the type, a request of a type with a high priority can be selected as the target request. Among them, the types of requests obtained by the secondary cache include: channel task types issued by the processor, missing status register types generated by missing status registers, etc., wherein the channel task types further include data acquisition types, data release types, data exploration types, etc. The embodiment of the present application can set the priority strategy as: priority of missing status register type > priority of data release type > priority of data exploration type > priority of data acquisition type. Through the division of priorities, the embodiment of the present application can satisfy that only one target request enters the pipeline queue of the secondary cache at the same time. According to the above-mentioned priority division, the secondary cache can give priority to the target request of the missing status register type, thereby ensuring the timely re-execution of the request that was not successfully executed in the missing status register, and avoiding the request waiting time being too long. The priority of data release request is higher than that of data exploration request, which in turn has a higher priority than that of data acquisition request. Based on this division, while ensuring that each request enters the pipeline queue smoothly, the stability and efficiency of the pipeline queue's request execution are improved.

[0060] Step 202: Enter the target request into the pipeline queue from the starting data bit.

[0061] The specific data bit is a starting data bit.

[0062] In an embodiment of the present application, referring to Figure 1, a target request newly entering the pipeline queue can specifically enter the pipeline queue from the starting data bit (data bit S1). After the target request enters the pipeline queue, it will not stay at any data bit. At each moment, the target request will move one data bit.

[0063] Step 203: According to the type of the target request, when the target request is at the target data position of the pipeline queue, perform an operation corresponding to the type and the target data position.

[0064] In an embodiment of the present application, different types of target requests have different timings for executing operations and different operations are executed. Based on this feature, the embodiment of the present application can design the operations executed at the data bit according to the type of request, the directory status of the data block accessed by the request, and the data bit where the request is located in the pipeline queue (one data bit is used to represent a pipeline moment), so that when the request is at a specific target data bit in the pipeline queue, it can execute the operation corresponding to the type of request and the target data bit.

[0065] For example, for a target request of the data acquisition type, it can be designed that when it is at the target data position S1, the cache directory of the secondary cache is read; when it is at the target data position S3, the directory result is obtained, and an operation is performed to determine whether the target request hits in the cache directory, and if it hits, the data reading operation is performed; when it hits and is at the target data position S5, the data is obtained, and the operation of feeding back the data to the upper layer is performed.

[0066] For the target request of data release type, it can be designed to read the cache directory of the secondary cache when it is at the target data position S1; when it is at the target data position S3, the directory result is obtained, and the data released by the upper layer is stored in the secondary cache and the release completion message is fed back to the upper layer.

[0067] For target requests of the data exploration type, it can be designed to read the cache directory of the second-level cache when it is in the target data position S1; when it is in the target data position S3, the directory result is obtained, and an operation is performed to determine whether the target request hits the cache directory. If it is a miss, the target data position S3 is simultaneously responded to the third-level cache that the data does not exist; if the directory result is a hit (the target data is only in the second-level cache), the target data is read at the target data position S3 at the same time, and the target data read at the target data position S5 is invalidated, and a response is made to the third-level cache.

[0068] Optionally, the type of the target request is in a channel task type set, and the channel task type set includes types of requests sent by the processor to the secondary cache. Step 203 may specifically include sub-steps 2031-2033:

[0069] Sub-step 2031: When the target data bit is the starting data bit, read the cache directory of the secondary cache and block all requests except the target request.

[0070] Sub-step 2032: When the target data bit is the first data bit (S3), determine the hit result of the target request in the secondary cache according to the cache directory, and when the hit result is a miss, determine that the pipeline queue has not successfully executed the target request, and when the hit result is a hit, start reading the target data corresponding to the target request; the first data bit and the starting data bit are separated by a first number of data bits.

[0071] Sub-step 2033: When the hit result is a hit and the target data bit is a second data bit, read and obtain the target data, and generate a response for the target data, where the second data bit is separated from the first data bit by a second number of data bits.

[0072] In the embodiment of the present application, for substeps 2031-2033, target requests fall into two categories: one is a set of channel task types including requests sent by the processor to the L2 cache, and the other is requests generated by missing status registers. The L2 cache of the embodiment of the present application has different strategies for processing these two categories of target requests.

[0073] When the target request type is in the channel task type set, as shown in Figure 1, the target request can read the cache directory of the secondary cache at the starting data position S1, while blocking all other requests except the target request. The purpose of reading the cache directory is to traverse the data blocks in the secondary cache and determine the status of the data blocks (whether the data to be accessed is stored). In data position S2, it waits for the cache directory to return.

[0074] Afterwards, the target request can obtain the cache directory read in the first data bit S3, and determine the hit result of the target request in the secondary cache based on the cache directory. When the hit result is a miss (the data to be accessed is not stored in the secondary cache, and the secondary cache currently needs to interact with other caches), it is determined that the pipeline queue has not successfully executed the target request. When the hit result is a hit (the data to be accessed is stored in the secondary cache), it starts reading the target data corresponding to the target request. The first data bit S3 is separated from the starting data bit S1 by a first number (2) of data bits. In data bit S4, the target data is waited for to be returned.

[0075] In an embodiment of the present application, if the hit result is a miss, the process will jump to the processing strategy for the target request of the missing status register type; and when the hit result is a hit and the target data bit is the second data bit S5, the target data required to be accessed by the target request is read and obtained, and a response is generated to the target data (read, release, invalid, etc.) according to the specific type of the target request, and the second number (2) of data bits are separated from the first data bit S3.

[0076] It can be seen that the embodiment of the present application clearly designs the operations performed by the target request at each pipeline moment (data bit) for the target request in the channel task type set. The shortest processing flow is adopted for each target request in the channel task type set. Except for the operations necessary to implement the target request response, there are no other additional operations in the middle. Each target request in the channel task type set strictly performs the corresponding operation according to the designed pipeline moment, which greatly improves the efficiency of the secondary cache processing request and reduces the delay during processing.

[0077] Step 204: When the pipeline queue successfully executes the target request, a response generated by executing the target request is returned.

[0078] This step may be specifically referred to the above step 102 and will not be described in detail here.

[0079] Optionally, when the type of the target request belongs to the data acquisition type in the channel task type set, the target data is the data stored in the secondary cache, and the response generated for the target data is: refilling the target data into the primary cache for the target request to read.

[0080] In an embodiment of the present application, a target request of the data acquisition type is intended to read the target data from the secondary cache and feed it back to the upper-level primary cache. Therefore, when the type of the target request belongs to the data acquisition type in the channel task type set, if the first data bit S3 in Figure 1 obtains the read cache directory and determines that the hit result of the target request in the secondary cache is a hit according to the cache directory (if it is a miss, a missing status register needs to be allocated for processing), then the target data corresponding to the target request is read starting from the first data bit S3, and the second data bit S5 in Figure 1 will obtain the target data. At this time, the response to the target data is: the target data is fed back to the upper-level primary cache Grant (containing the target data, used to refill the target data into the primary cache) for the processor to finally read. After the upper layer receives the Grant, it can reply GrantAck to the lower-level secondary cache, indicating that the upper layer has received the target data. In addition, regardless of whether the hit result is a hit or a miss, when sending the Grant to the primary cache, the request will also be recorded at the same time; after the primary cache returns GrantAck, it will mark that the request has been processed.

[0081] It should be noted that a hit result indicates that the target data requested for reading is present in the L2 cache. Therefore, the L1 cache seeks to have the L2 cache refill the target data into the L1 cache. The L2 cache then needs to send a wake-up request and a refill request to the L1 cache. The wake-up request is used to wake up the operation of reading the target data from the L1 cache through the target request; the refill request is used to write the target data into the L1 cache for the target request to read. In other words, the wake-up request issued by the L2 cache can wake up the target request that did not hit the L1 cache. After waking up, the target request can quickly read the target data from the L1 cache, so that the processor's target request can normally implement the function of reading data.

[0082] However, if the target request is awakened to access the first-level cache after the second-level cache refills the target data into the first-level cache, the refilled data will have to wait for the target request to be awakened, and the whole process will produce a long delay (that is, after refilling the data, it takes a certain amount of time to wake up the target request, and the target request still needs several cycles to actually read the refilled target data). In order to reduce this delay, the embodiment of the present application can control the second-level cache to allow it to issue a wake-up request in advance before issuing the refill request, and ensure that the advance amount is fixed and accurate.

[0083] In order to achieve this purpose, referring to Figure 1, in an embodiment of the present application, for the case where the hit result is a hit, at the moment when the hit result is obtained (the moment corresponding to data bit S3), the second-level cache can immediately generate a wake-up request and send it to the first-level cache by the wake-up queue, and after an interval of 2 data bits at the moment when the hit result is obtained (the moment corresponding to data bit S3), the target data read by the target request is obtained at the moment corresponding to data bit S5, and the target request is sent as a refill request by the refill queue to the first-level cache at the moment corresponding to data bit S5, wherein the refill request carries the target data.

[0084] Since the first-level cache receives the wake-up request at the moment corresponding to data bit S3, it can start executing the wake-up of the target request in advance. The first-level cache can immediately read the target data for the refill request received subsequently, so there is no need to wait for the time spent on waking up the target request, which significantly saves the delay in the process of the target request reading the target data.

[0085] For example, referring to Figure 1, when the hit result is a hit, the actual sending time of the wake-up request is the moment corresponding to data bit S3. Since the refill request has to wait in the refill queue for the length of time represented by a data bit (ensuring that the refill request at the exit of the refill queue is issued in time to reduce the probability of congestion in the refill queue), the actual sending time of the refill request is the moment corresponding to data bit S6 (not drawn). It can be seen that the embodiment of Figure 1 of the present application can ensure that for each refill request, there is a wake-up request issued three data bits in advance.

[0086] The embodiments of the present application manage memory access requests through the concise, multi-stage pipeline queue architecture of the secondary cache. Based on the pipeline queue architecture and the design of the various processing timings of requests in the pipeline, precise and stable control of the fixed lead time for issuing wake-up requests can be achieved, ensuring the accuracy and coverage of the memory access request reading process. The entire process does not require reading the status of requests at each stage of the pipeline, nor does it require real-time calculation of the lead time based on the status of the refill queue request. Therefore, complexity is extremely low, reducing circuit cost and power consumption.

[0087] When the type of the target request belongs to the data release type in the channel task type set, the target data is the data stored in the first-level cache, and the response generated for the target data is: receiving and storing the target data sent by the first-level cache through the second-level cache, so as to realize the release of the target data by the first-level cache.

[0088] In an embodiment of the present application, a target request of the data release type is intended to be received and stored by the secondary cache in the target data released by the upper-level primary cache. Therefore, when the type of the target request belongs to the data release type in the channel task type set, the first data bit S3 in Figure 1 obtains the result of reading the cache directory and stores the target data released by the upper-level primary cache into the data block, that is, the response to the target data is: the target data sent by the primary cache is received and stored by the secondary cache. After the secondary cache completes the storage of the target data, it can respond to the upper-level primary cache with ReleaseAck, indicating that the release is complete.

[0089] When the type of the target request belongs to the data exploration type in the channel task type set, the target data is data stored in the secondary cache, and the response generated for the target data is: setting the target data to an invalid state.

[0090] In an embodiment of the present application, in a multi-core processor system, there may be access to shared data. In order to ensure access consistency (i.e., each read can read the most recently written value), it must be ensured that at the same time, either multiple processor cores have read permissions, or only one processor core has write permissions. There cannot be multiple processor cores with write permissions, nor can there be a processor core with write permissions and other readers at the same time. In order to meet such properties, the cache design must also support a type of invalidation operation that can invalidate the data of a specified data block in the cache.

[0091] For example: Processor core 1 now has write permission. At this time, processor core 2 also wants to write data. It needs to obtain write permission from the third-level cache. At this time, the third-level cache will invalidate processor core 1 to revoke its write permission and let processor core 1 return the data to the third-level cache. Therefore, the target request of the data exploration type is intended to invalidate the requested target data by the second-level cache based on the request of the lower-level third-level cache.

[0092] Specifically, when the type of the target request belongs to the data exploration type in the channel task type set, if the first data bit S3 in Figure 1 obtains the cache directory to be read, and the hit result is determined to be a hit based on the cache directory (if it is a miss, a missing status register needs to be allocated for processing), then the target data is read at the first data bit S3, and the target data is obtained at the second data bit S5 in Figure 1, and the response to the target data is: set the target data to an invalid state. Among them, the second-level cache needs to respond ProbeAck to the third-level cache of the lower layer (if the data block where the target data is located has been modified by the upper layer, the target data is also called dirty data, and the dirty data must be included in the ProbeAck; otherwise, the second-level cache can ProbeAck without data).

[0093] Referring to Figure 4, it shows a diagram of the secondary cache architecture of an embodiment of the present application, including an arbitration module, a miss status register, a cache directory, a refill buffer, a bus, a release buffer, a data storage array, a request buffer, and a channel controller. The bus includes five channels: A, B, C, D, and E, wherein the channel controllers: sink node A (SinkA), sink node C (SinkC), source channel B (SourceB), source channel D (SourceD), and sink node E (SinkE) are connected to the bus of the upper cache, and the channel controllers: source channel A (SourceA), source channel C (SourceC), sink node B (SinkB), sink node D (SinkD), and source channel E (SourceE) are connected to the bus of the lower cache. Among them, the request buffer can save some requests that cannot enter the pipeline queue temporarily, so that other requests that can enter the pipeline queue can be executed first, and then the requests in the request buffer can enter the pipeline queue when the conditions are met. The release buffer is used to temporarily store data released by the upper cache. The refill buffer is used to temporarily store refill data.

[0094] Requests from the processor reach the L2 cache via the bus and are converted by the channel controller into internal L2 cache tasks. The request format is different before and after the conversion, but the content remains the same. The channel controller can also convert L2 cache internal tasks into bus responses.

[0095] The arbitration module is used to arbitrate the requests of each channel, and select the target request to enter the pipeline of the secondary cache for processing. In one implementation method, the embodiment of the present application can select the target request according to the priority of the request type, and set the priority strategy for selecting the target request as follows: priority of missing status register type > priority of data release type > priority of data exploration type > priority of data acquisition type.

[0096] The above architecture includes multiple miss status registers, which are used to store requests that cannot be directly executed on the pipeline queue (such as access miss requests). In addition, the secondary cache architecture of the embodiment of the present application can adopt an all-inclusive strategy, that is, all data in the first-level cache exists in the second-level cache, that is, the first-level cache is a subset of the second-level cache.

[0097] Specifically, during the execution of various types of target requests, the target requests in the pipeline queue can enter the channel controllers SourceC and SourceD at data bits S3, S4, and S5. However, because the channel controller can only enter one request at a time, if multiple requests want to enter, arbitration will be performed to select one request and block the rest. The priority is data bit S5>data bit S4>data bit S3.

[0098] Furthermore, SinkA is configured to receive data acquisition type target requests and convert them into bus-type requests. The data acquisition type target requests are then used to respond via SourceD. If a data acquisition type target request misses, SourceA can send a request to the L3 cache, and SinkD can receive a response from the L3 cache.

[0099] SinkB is used to receive target requests of the data exploration type and convert them into internal tasks; and the target requests of the data exploration type are used to respond to the third-level cache through SourceC, and send requests to the first-level cache through SourceB.

[0100] SinkC is used to receive target requests of the data release type and convert them into internal tasks; and the target requests of the data release type are used to feedback responses through SourceD.

[0101] Step 205: When the pipeline queue fails to successfully execute the target request, a corresponding missing status register is allocated to the target request, and the target request is executed through the missing status register.

[0102] This step may be specifically referred to the above step 103 and will not be described in detail here.

[0103] Optionally, the type of the target request is a channel task type set including a data acquisition type; the pipeline queue fails to execute the target request, indicating that the secondary cache does not store the data requested by the target request; step 205 may specifically include sub-steps 2051-2052:

[0104] Sub-step 2051: After the target request is removed from the pipeline queue, the target request is controlled to enter the allocated missing status register for waiting, and a new target request of the missing status register type is generated through the missing status register.

[0105] Sub-step 2052: When the refill data is obtained from the L3 cache and refilled into the L2 cache through the new target request, the access operation of the data acquisition type target request to the refill data in the L2 cache is awakened through the new target request.

[0106] In an embodiment of the present application, when the target request type is a channel task type set including a data acquisition type, the above embodiment describes the execution process when the pipeline queue successfully executes the target request (hit). If the pipeline queue fails to successfully execute the target request (miss), the secondary cache will assign a missing status register to the target request, causing the unsuccessfully executed target request to leave the pipeline queue and enter the assigned missing status register to wait, so that a new target request of the missing status register type can be generated later through the missing status register.

[0107] The hit result is a miss, which means that the data requested by the target is not stored in the second-level cache. At this time, it is necessary to check whether the data is stored in the third-level cache of the lower layer. If the data is stored in the third-level cache, the third-level cache will refill the data into the second-level cache, and then the second-level cache will refill the data into the first-level cache for the target request to read; if the data is not stored in the third-level cache, the data will be read from the memory and refilled into the third-level cache, and then the third-level cache will refill the data into the second-level cache, and finally the second-level cache will refill the data into the first-level cache for the target request to read.

[0108] Specifically, when the hit result is a miss, since it is necessary to wait for the L3 cache to refill the data into the L2 cache, the data acquisition type target request can be controlled to exit the pipeline queue first to wait for the L3 cache to refill. After the L3 cache refills the data into the L2 cache, a new target request generated by the miss status register can be used to wake up the data acquisition type target request to access the refilled data in the L2 cache.

[0109] Optionally, sub-step 2052 may specifically include sub-steps 20521-20522:

[0110] Sub-step 20521: Through the new target request, control the target request of the data acquisition type to enter the pipeline queue from the specific data bit, and at the same time generate a wake-up request through the second-level cache and send it to the first-level cache from the wake-up queue.

[0111] Sub-step 20522: After the third number of data bits are separated, refill data is read from the secondary cache, and the target request of the data acquisition type is sent as a refill request from the refill queue to the primary cache.

[0112] Among them, the wake-up request is used to wake up the operation of reading data from the first-level cache through the target request of the data acquisition type; the refill request is used to write the refill data into the first-level cache for reading by the target request of the data acquisition type.

[0113] In an embodiment of the present application, for sub-steps 20521-20522, the access operation of the target request of the data acquisition type that is awakened by a new target request to refill the data in the secondary cache specifically refers to re-executing the target request that was not successfully executed before so that it can successfully obtain the target data. This requires sending a wake-up request and a refill request to the first-level cache through the secondary cache.

[0114] Referring to Figure 1, after waiting for the third-level cache to refill the second-level cache, the new target request generated by the missing status register controls the target request to re-enter the pipeline queue from a specific data bit (preferably data bit S1), and at the same time, a wake-up request is generated through the second-level cache and issued by the wake-up queue (the moment of entering the wake-up queue and issuing the wake-up request is the moment corresponding to data bit S1); and after an interval of the third number of data bits (an interval of 2 data bits), at data bit S3, the refill data is obtained through the second-level cache, and the target request is issued as a refill request by the refill queue.

[0115] For example, referring to Figure 1, when the hit result is a miss, the actual sending time of the wake-up request is the moment corresponding to data bit S1. Since the refill request has to wait in the refill queue for the length of time represented by a data bit (ensuring that the refill request at the exit of the refill queue is issued in time to reduce the probability of congestion in the refill queue), the actual sending time of the refill request is the moment corresponding to data bit S4. It can be seen that the embodiment of Figure 1 of the present application can ensure that for each refill request, there is a wake-up request issued three data bits in advance. The embodiment of the present application can control the secondary cache so that it issues a wake-up request in advance before issuing the refill request, and ensures that the advance amount is fixed and accurate. This can solve the problem in the related art that the data that has been refilled needs to wait for the target request to wake up, and the whole process will have a long delay (that is, after refilling the data, it takes a certain amount of time to wake up the target request, so the target request still needs several cycles to actually read the refilled target data).

[0116] The embodiment of the present application is based on a pipeline queue, and is designed to obtain the hit result of the target request and send a wake-up request at a fixed data bit, as well as obtain the refill data at another fixed data bit and send the refill request through the refill queue; based on the architecture of the pipeline queue and the design of each processing timing of the instruction in the pipeline, it can achieve accurate and stable control of the fixed advance amount of issuing the wake-up request, thereby ensuring the accuracy and coverage of the target request reading process.

[0117] Optionally, in order to implement the process of obtaining refill data from the L3 cache and refilling it into the L2 cache, step 205 may further include sub-steps 2053-2054:

[0118] Step 2053: According to the new target request, request the third-level cache to obtain the refill data.

[0119] Step 2054: When the refill data is received through the new target request, the new target request enters the pipeline queue from the specific data bit, executes the operations of determining the target data block from the secondary cache, releasing the old data stored in the target data block, and writing the refill data into the target data block.

[0120] In the embodiment of the present application, with respect to steps 2053-2054, when the processor is operating, the processor will first search for the required data in the first-level cache L1 according to the memory access instruction, then search for the data in the second-level cache L2, and then search for the data in the third-level cache L3. In the above process, if the memory access instruction does not hit in the first-level cache L1 (meaning that the data requested to be read by the memory access instruction is not stored in the first-level cache L1), the processor will continue to search whether the memory access instruction hits in the second-level cache L2. If it hits in the second-level cache L2, the second-level cache L2 will refill the data requested to be read by the memory access instruction into the first-level cache L1; if it does not hit in the second-level cache L2, the processor will continue to search whether the memory access instruction hits in the third-level cache L3. If it hits in the third-level cache L3, the third-level cache L3 will refill the data requested to be read by the memory access instruction into the second-level cache L2, and then the second-level cache L2 will refill the data into the first-level cache L1.

[0121] However, due to the limited cache space, when a cache capacity conflict occurs (i.e., the cache space is full and insufficient to continue storing the refilled data), it is necessary to select a data block in the secondary cache waiting for refilling to release the old data therein, thereby freeing up space to store the refilled data.

[0122] The related technology is that while the L2 cache notifies the lower L3 cache to refill data, it selects a data block in the L2 cache and releases the old data. When the L3 cache sends the refill data, the refill data is written into the data block to achieve data refill. This results in the vacant data block being continuously occupied while waiting for the refill data. In addition, if the old data is needed during this process, it cannot be successfully accessed because the old data has been released.

[0123] In order to solve this problem, the embodiment of the present application may not select a data block for release when the memory access instruction does not hit in the secondary cache, but instead notify the lower-level third-level cache to obtain the refill data required for the memory access request, wait for the third-level cache to obtain the refill data and send the refill data to the secondary cache, and then determine the target data block from the secondary cache, release the old data stored in the target data block, and write the refill data to the target data block. In this way, during the period before the refill data arrives, the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally. In addition, after the secondary cache receives the refill data, the present application releases the old data stored in the selected target data block and writes the refill data to the target data block, which also ensures the normal implementation of the memory access instruction to read the old data during this period.

[0124] Specifically, the process of the third-level cache responding to the acquisition request to find and obtain the refill data and sending it to the second-level cache usually takes a long time. However, during the period when the second-level cache waits for the refill data to be sent, the embodiment of the present application does not release or occupy the data block containing the old data. On the basis of ensuring that the old data can be accessed normally, the utilization rate of the cache resources is improved.

[0125] Furthermore, in the embodiment of the present application, the target data block is selected only when the refill data sent by the third-level cache is received through the second-level cache. If the target data block contains old data, the old data is released and the refill data is written into the target data block. In this way, during the period before the refill data arrives, the data blocks in the second-level cache that contain old data can operate normally and are not vacant or occupied. After the second-level cache receives the refill data, the old data stored in the selected target data block is released and the refill data is written into the target data block, thus ensuring the normal implementation of the data reading process of the memory access instruction.

[0126] Furthermore, the preferred new target request enters the pipeline queue from the starting data position S1 of Figure 1 and starts to read the cache directory, wherein the secondary cache needs to temporarily store the refill data before writing the refill data into the target data block when it just receives the refill data sent by the tertiary cache (at this time the refill data has not yet been written into the target data block). Therefore, an independent refill buffer area can be set up in the secondary cache, and the secondary cache can write the refill data into the refill buffer area for temporary storage. At data position S2, the secondary cache reads the refill buffer area, and at data position S3, determines the target data block from the secondary cache according to the obtained cache directory, and reads the refill data, writes the refill data read into the write buffer area of ​​the secondary cache, and reads the old data in the target data block. At data position S5, the old data in the target data block can be read, and the old data is read out from the target data block. At data position S5, the old data read can also be sent to the tertiary cache to complete the release of the target data block.

[0127] When it is detected that the operation of reading the target data block is completed, the refill data in the write buffer area is written into the target data block to complete the data refilling.

[0128] In an embodiment of the present application, the function of the write buffer section is to determine whether to write the refill data to the target data block based on the determination of the read operation performed on the target data block. Specifically, in an embodiment of the present application, a higher priority is set for the operation of reading the target data block. Therefore, the write buffer section needs to wait until all read operations on the target data block are completed before it can begin the operation of writing the refill data in the write buffer section to the target data block. That is, when the write buffer section determines that all read operations performed on the target data block are completed, the write buffer section executes the operation of writing the refill data in the write buffer section to the target data block, thereby completing the operation of refilling the refill data into the secondary cache.

[0129] In one implementation, the cache directory records the last access time of each data block in the secondary cache. In this case, the embodiment of the present application can obtain the last access time of each data block in the secondary cache based on the cache directory, and use the data block with the earliest last access time as the target data block. The data block with the earliest last access time indicates that the data stored in the data block is the least active. Therefore, using the data block with the earliest last access time as the target data block can minimize the impact on the more active data in other data blocks. In another implementation, a data block can be randomly selected from the secondary cache as the target data block. The embodiment of this application does not specifically limit the strategy for selecting the target data block.

[0130] Optionally, step 205 may further include sub-steps 2055-2058:

[0131] Sub-step 2055: Obtain a first number of requests contained in the first n data bits of the pipeline queue.

[0132] Sub-step 2056: Obtain a second number of allocated missing status registers among all the missing status registers.

[0133] Sub-step 2057: If the sum of the first number and the second number is greater than or equal to the total number of missing status registers, prevent new requests from entering the pipeline queue.

[0134] Sub-step 2058: When the sum of the first number and the second number is less than the total number of missing status registers, allocate an idle missing status register to the target request.

[0135] In the embodiment of the present application, for sub-steps 2055-2058, since the pipeline queue of the secondary cache is non-blocking (that is, the request in the pipeline queue will move one data bit at each moment, and the request will not stay at a certain data bit), it is necessary to carefully arrange the pipeline queue entry conditions to ensure that the requests entering the pipeline queue can either be processed directly on the pipeline queue or a missing status register can be allocated to it. There should be no situation where a missing status register is needed but there is currently no idle missing status register.

[0136] Therefore, the embodiment of the present application designs a back pressure control logic, that is, first obtaining the first number of requests contained in the first n data bits of the pipeline queue and the second number of allocated missing status registers, and then calculating the sum of the first number and the second number. When the sum is greater than or equal to the total number of missing status registers, it is considered that the number of idle missing status registers is insufficient, and new requests are prevented from entering the pipeline queue. When the sum is less than the total number of missing status registers, it is considered that the number of idle missing status registers is sufficient, and the target request is allocated an idle missing status register. In addition, the present application also needs to ensure that the buffers in SourceC and SourceD of Figure 4 will not overflow, that is, to ensure that the number of data acquisition type requests and data release type requests contained in the pipeline queue + the number of occupied buffer items ≥ the total number of buffer items.

[0137] Optionally, when the type of the target request is a data exploration type in the channel task type set, the target request is issued by a third-level cache, and the method may further include steps 206-208:

[0138] Step 206: When the hit result is a miss, feedback is given to the L3 cache that the invalid target data requested by the target request is not stored in the L2 cache.

[0139] Step 207: When the hit result is a hit and the target data is only stored in the secondary cache, start reading the target data corresponding to the target request.

[0140] Step 208: When the hit result is a hit and the target data is stored in both the L2 cache and the L1 cache, start reading the target data in the L2 cache and simultaneously request the L1 cache to invalidate the stored target data.

[0141] Specifically, for steps 206-208, the cache directory is read according to the first data bit S3 in Figure 1. If the hit result is a hit, and the target data is only in the second-level cache but not in the first-level cache, the target data is read at the first data bit S3, and the target data is obtained at the second data bit S5, and a response is made to the third-level cache (if the target data is dirty data, the response includes the target data); if the hit result is a hit, and the target data is in both the second-level cache and the first-level cache, the second-level cache must first invalidate the target data stored in the first-level cache, and then invalidate the target data stored by itself. At this time, a missing status register is first allocated to the target request to record the information of this target request. At the same time, the target data is read at the first data bit S3, and the target data is obtained at the second data bit S5 and written into the release buffer.

[0142] The missing status register sends a data exploration type request to the first-level cache and waits, requesting the first-level cache to invalidate the target data stored therein. For the response result returned by the first-level cache, if there is data in it, it is written into the release buffer to overwrite the target data just read, and at the same time, the missing status register is awakened, so that it issues a new target request to enter the pipeline queue of the second-level cache. The new target request will read the release buffer at data bit S2 in the pipeline queue, read the data at data bit S3, and can respond to the data to the third-level cache at data bits S3-S5. The reason for reading data and writing to the release buffer is that if there is no data returned in the response of the first-level cache, but the target data of the second-level cache itself is dirty data, it is necessary to add dirty data to the response of the third-level cache. In this case, the data in the release buffer can be read out in advance to speed up the response process.

[0143] Optionally, the secondary cache includes multiple data block groups, each data block group includes multiple data blocks; the data block groups are used to parallel process target requests accessing data blocks included in the data block groups; the target data blocks are: data blocks in the secondary cache that are not occupied by other requests.

[0144] In an embodiment of the present application, the secondary cache includes multiple data block groups (sets), and each data block group includes multiple data blocks. The cache design of the related art is blocked according to the data block group, that is, only one request for the same data block group can be processed at the same time, which reduces the cache throughput and causes serious performance loss in specific memory access modes.

[0145] To address this issue, embodiments of the present application can employ a strategy for selecting a target data block for storing refill data: selecting a data block in the L2 cache that is not occupied by other requests as the target data block. Specifically, when selecting the target data block, data blocks occupied by other requests in the missing cache register that belong to the same data block group as the target request are avoided.

[0146] This allows each data block group to process multiple requests in parallel, and the data blocks associated with each of these multiple requests are independent of each other, which means that the requests do not interfere with each other, ensuring the correctness of parallel processing. In other words, this strategy ensures that before a request is processed, no other request will occupy the data block of this request, that is, no two requests being processed will select the same data block. Based on this strategy, especially when the program's memory access sequence jumps at intervals of the size of the data block group (for example, if the data block group size is 100, the memory access sequence is 0 / 100 / 200 / 300...), the strategy of this application will have a very significant performance improvement.

[0147] Optionally, the secondary cache includes multiple data block groups, and the data block groups are used to process target requests for access to data blocks included in the data block groups in parallel. Before step 202, the method may further include steps 209-210:

[0148] Step 209: When it is determined that the target request and the write buffer directory request in the pipeline queue both access the same data block group, the target request is prevented from entering the pipeline queue; wherein the write buffer directory request is in the first three data bits in the pipeline queue, and the third data bit is used to perform the write buffer directory operation.

[0149] Step 210: When it is determined that the target request and the request in the missing state register both access the same data, prevent the target request from entering the pipeline queue.

[0150] In an embodiment of the present application, for steps 209-210, when it is determined that the target request and the write buffer directory request in the pipeline queue both access the same data block group, the target request is prevented from entering the pipeline queue. The purpose of doing this is to prevent conflicts between write operations and read operations, that is, to ensure that the read operation performed by data bit S1 can definitely read the data to be written by data bits S2 and S3.

[0151] In addition, when it is determined that the target request and the request in the missing state register both access the same data, the target request is prevented from entering the pipeline queue. This is done to ensure consistency in operations on the same data.

[0152] In summary, in the embodiment of the present application, a target request can be selected from all requests according to the type of request obtained by the secondary cache to enter the pipeline queue for execution. When the pipeline queue fails to successfully execute the target request, a corresponding missing status register is allocated to the target request for processing. In the present application, when the target request enters the pipeline queue of the secondary cache, the corresponding missing status register is not allocated to it. Only when the target request fails to be successfully executed is the corresponding missing status register allocated to it. This allows the present application to reduce the allocation consumption of missing status register resources on the basis of meeting the demand for re-execution of the target request that has not been successfully executed, and reduces the delay caused by the allocation of missing status register resources.

[0153] FIG5 is a block diagram of a cache request processing device provided by an embodiment of the present application, the device comprising:

[0154] an enqueue module 301 for selecting a target request from all requests obtained by the secondary cache according to the type of the request, and entering the target request from a specific data bit of a pipeline queue of the secondary cache into the pipeline queue for execution; the pipeline queue includes a plurality of data bits arranged in sequence;

[0155] A return module 302 is configured to return a response generated by executing the target request when the pipeline queue successfully executes the target request;

[0156] The execution module 303 is configured to allocate a corresponding missing status register to the target request when the pipeline queue fails to execute the target request successfully, and execute the target request through the missing status register.

[0157] Optionally, the specific data bit is a starting data bit, and the queue entry module 301 includes:

[0158] an enqueue submodule, configured to enter the target request into the pipeline queue from the starting data position;

[0159] The execution submodule is used to execute an operation corresponding to the type and the target data bit when the target request is in the target data bit of the pipeline queue according to the type of the target request.

[0160] Optionally, the type of the target request is in a channel task type set, and the channel task type set includes types of requests sent by the processor to the secondary cache;

[0161] The execution submodule includes:

[0162] a blocking unit, configured to read a cache directory of the secondary cache when the target data bit is a starting data bit, and simultaneously block all requests except the target request;

[0163] a first execution unit, configured to, when the target data bit is a first data bit, determine, based on the cache directory, a hit result of the target request in the secondary cache, and, when the hit result is a miss, determine that the pipeline queue has not successfully executed the target request, and, when the hit result is a hit, start reading target data corresponding to the target request; a first number of data bits being spaced between the first data bit and the start data bit;

[0164] The second execution unit is used to read and obtain the target data and generate a response for the target data when the hit result is a hit and the target data bit is a second data bit, and the second data bit is separated from the first data bit by a second number of data bits.

[0165] Optionally, the type of the target request is a data acquisition type included in a channel task type set, and the channel task type set includes types of requests sent by the processor to the secondary cache; the pipeline queue fails to execute the target request, which is used to indicate that the secondary cache does not store the data requested by the target request;

[0166] The execution module 303 includes:

[0167] a generating submodule, configured to control the target request to enter the allocated missing status register for waiting after removing the target request from the pipeline queue, and generate a new target request of the missing status register type through the missing status register;

[0168] The wake-up submodule is used to wake up the access operation of the data acquisition type target request to the refill data in the second-level cache through the new target request when the refill data is obtained from the third-level cache and refilled into the second-level cache through the new target request.

[0169] Optionally, when the type of the target request is a data exploration type in a channel task type set, the target request is issued by a third-level cache, and the apparatus further includes:

[0170] a first judgment module, configured to, when the hit result is a miss, feedback to the third-level cache that the invalid target data requested by the target request is not stored in the second-level cache;

[0171] A second judgment module is configured to start reading the target data corresponding to the target request when the hit result is a hit and the target data is only stored in the secondary cache;

[0172] The third judgment module is used to start reading the target data in the second-level cache when the hit result is a hit and the target data is stored in both the second-level cache and the first-level cache, and at the same time request the first-level cache to invalidate the stored target data.

[0173] Optionally, the device further includes:

[0174] a refill data module, configured to request the third-level cache to obtain the refill data according to the new target request;

[0175] A refill module is used to, when receiving the refill data through the new target request, enter the new target request from the specific data bit into the pipeline queue, execute the operations of determining the target data block from the secondary cache, releasing the old data stored in the target data block, and writing the refill data into the target data block.

[0176] Optionally, the secondary cache includes multiple data block groups, and each data block group includes multiple data blocks;

[0177] The data block group is used for parallel processing of target requests for access to data blocks included in the data block group;

[0178] The target data block is: a data block in the secondary cache that is not occupied by other requests.

[0179] Optionally, the wake-up submodule includes:

[0180] a first sending submodule, configured to control the target request of the data acquisition type to enter the pipeline queue from the specific data bit through the new target request, and simultaneously generate a wake-up request through the secondary cache and send the wake-up request from the wake-up queue to the primary cache;

[0181] a second sending submodule, configured to read refill data from the secondary cache after the third number of data bits have passed, and send the target request of the data acquisition type as a refill request from the refill queue to the primary cache;

[0182] Among them, the wake-up request is used to wake up the operation of reading data from the first-level cache through the target request of the data acquisition type; the refill request is used to write the refill data into the first-level cache for reading by the target request of the data acquisition type.

[0183] Optionally, when the type of the target request belongs to the data acquisition type in the channel task type set, the target data is data stored in the secondary cache, and generating a response for the target data is: refilling the target data into the primary cache for reading by the target request;

[0184] When the type of the target request belongs to the data release type in the channel task type set, the target data is data stored in the first-level cache, and generating a response for the target data is: receiving and storing the target data sent by the first-level cache through the second-level cache, so as to realize the release of the target data by the first-level cache;

[0185] When the type of the target request belongs to the data exploration type in the channel task type set, the target data is data stored in the secondary cache, and the response generated for the target data is: setting the target data to an invalid state.

[0186] Optionally, the queue entry module 301 includes:

[0187] A first selection submodule is configured to, when a request of a type with a missing status register exists among all the requests, use the request of the type with a missing status register as the target request;

[0188] A second selection submodule is configured to, when there is no request of a missing status register type among all the requests, but there is a request of a data release type, use the request of the data release type as the target request;

[0189] A third selection submodule is configured to, when there is no missing status register type request or data release type request among all the requests, but there is a data exploration type request, use the data exploration type request as the target request;

[0190] The fourth selection submodule is configured to, when there are no requests of missing status register type, data release type, or data exploration type among all the requests, but there are requests of data acquisition type, use the requests of data acquisition type as the target request.

[0191] Optionally, the execution module 303 includes:

[0192] a first statistics submodule, configured to obtain a first number of requests included in the first n data bits of the pipeline queue;

[0193] A second statistical submodule is configured to obtain a second number of allocated missing status registers among all the missing status registers;

[0194] a request blocking submodule, configured to block new requests from entering the pipeline queue if a sum of the first number and the second number is greater than or equal to the total number of missing status registers;

[0195] An allocating submodule is configured to allocate an idle missing status register to the target request when a sum of the first number and the second number is less than the total number of missing status registers.

[0196] Optionally, the secondary cache includes a plurality of data block groups, and the data block groups are used to process in parallel target requests for access to data blocks included in the data block groups;

[0197] The device further comprises:

[0198] a first blocking module, configured to block the target request from entering the pipeline queue when it is determined that the target request and a write buffer directory request in the pipeline queue both access the same data block group; the write buffer directory request is in at least one third data bit in the pipeline queue, the third data bit being used to perform a write buffer directory operation;

[0199] Optionally, the request type includes: a channel task type issued by a processor, a missing status register type generated by a missing status register;

[0200] The channel task types include data acquisition type, data release type, and data exploration type;

[0201] The priority of the missing status register type is higher than the priority of the data release type, the priority of the data release type is higher than the priority of the data detection type, and the priority of the data detection type is higher than the priority of the data acquisition type.

[0202] Optionally, the pipeline queue includes 5 sequentially arranged data bits: data bit S1 to data bit S5;

[0203] For a target request of the data acquisition type, when it is configured to be in data position S1, the cache directory of the secondary cache is read; when it is in data position S3, the directory result is obtained, and an operation is performed to determine whether the target request hits in the cache directory, and if so, the data is read; when it hits and is in data position S5, the data is obtained and the data is fed back to the upper layer;

[0204] For a target request of the data release type, when the data position is S1, the cache directory of the secondary cache is read; when the data position is S3, the directory result is obtained, and the data released by the upper layer is stored in the secondary cache and a release completion message is fed back to the upper layer;

[0205] For the target request of the data exploration type, it is configured to read the cache directory of the second-level cache when it is in data position S1; when it is in data position S3, the directory result is obtained, and an operation is performed to determine whether the target request hits the cache directory. If it is a miss, the data does not exist at the third-level cache at the same time in data position S3; if the directory result is a hit, the target data is read at the same time in data position S3, and the read target data is invalidated at data position S5, and a response is made to the third-level cache.

[0206] Optionally, the first quantity and the second quantity are 2.

[0207] Optionally, the device further includes:

[0208] The second blocking module is configured to prevent the target request from entering the pipeline queue when it is determined that the target request and the request in the missing state register both access the same data.

[0209] In summary, in the embodiment of the present application, a target request can be selected from all requests according to the type of request obtained by the secondary cache to enter the pipeline queue for execution. When the pipeline queue fails to successfully execute the target request, a corresponding missing status register is allocated to the target request for processing. In the present application, when the target request enters the pipeline queue of the secondary cache, the corresponding missing status register is not allocated to it. Only when the target request fails to be successfully executed is the corresponding missing status register allocated to it. This allows the present application to reduce the allocation consumption of missing status register resources on the basis of meeting the demand for re-execution of the target request that has not been successfully executed, and reduces the delay caused by the allocation of missing status register resources.

[0210] The various component embodiments of the present application can be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the computing processing equipment according to the embodiment of the present application. The application can also be implemented as a device or apparatus program (for example, a computer program and a computer program product) for performing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0211] For example, FIG6 illustrates a computing device that can implement the methods according to the present application. The computing device typically includes a processor 1010 and a computer program product or computer-readable medium in the form of a memory 1020. Memory 1020 can be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, a hard disk, or ROM. Memory 1020 has storage space 1030 for program code 1031 for executing any of the method steps described above. For example, storage space 1030 for program code can include individual program codes 1031 for implementing various steps in the method described above. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks. Such computer program products are typically portable or fixed storage units, as described with reference to FIG7 . This storage unit can have storage segments, storage space, and the like arranged similarly to memory 1020 in the computing device of FIG6 . The program code can, for example, be compressed in a suitable form. Typically, the storage unit includes computer-readable codes 1031 ′, ie, codes that can be read by a processor such as 1010 , which, when executed by a computing device, cause the computing device to perform the steps of the method described above.

[0212] Figure 8 is a block diagram of an electronic device according to an embodiment of the present invention. As shown in Figure 8 , the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores executable instructions that cause the processor to execute the cache request processing method according to the aforementioned embodiment.

[0213] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0214] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG8 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0215] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0216] An embodiment of the present application also provides a computer program product, including a computer program, and a method for processing cache requests implemented when the computer program is executed by a processor.

[0217] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0218] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0219] In the claims, any reference signs placed between brackets shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0220] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0221] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0222] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

[0223] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0224] The above is a detailed introduction to the cache request processing method, device, electronic device, computer-readable storage medium and computer program provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for processing cache requests, wherein, The method includes: Selecting a target request from all the requests according to the type of the request obtained from the secondary cache, and entering the target request into the pipeline queue for execution from a specific data bit of the pipeline queue of the secondary cache; the pipeline queue includes a plurality of sequentially arranged data bits; When the target request is successfully executed in the pipeline queue, returning the response generated by executing the target request; When the target request is not successfully executed in the pipeline queue, allocating a corresponding miss status register for the target request, and executing the target request through the miss status register.

2. The method for processing a cache request according to claim 1, wherein, The specific data bit is the starting data bit, and the entering the target request into the pipeline queue for execution from the specific data bit of the pipeline queue of the secondary cache includes: Entering the target request into the pipeline queue from the starting data bit; According to the type of the target request, when the target request is at the target data bit of the pipeline queue, performing an operation corresponding to the type and the target data bit.

3. The method for processing a cache request according to claim 2, wherein, The type of the target request is in a set of channel task types, and the set of channel task types includes the types of requests sent by the processor to the secondary cache; The performing an operation corresponding to the type and the target data bit when the target request is at the target data bit of the pipeline queue includes: When the target data bit is the starting data bit, reading the cache directory of the secondary cache and blocking the remaining requests except the target request; When the target data bit is the first data bit, determining the hit result of the target request in the secondary cache according to the cache directory, and when the hit result is a miss, determining that the pipeline queue fails to execute the target request successfully, and when the hit result is a hit, starting to read the target data corresponding to the target request; the first data bit is separated from the starting data bit by a first number of data bits; When the hit result is a hit and the target data bit is the second data bit, reading and obtaining the target data and generating a response for the target data, and the second data bit is separated from the first data bit by a second number of data bits.

4. The method for processing a cache request according to claim 1 or 3, wherein, The type of the target request is a data acquisition type included in the set of channel task types, and the set of channel task types includes the types of requests sent by the processor to the secondary cache; the failure of the pipeline queue to execute the target request successfully is used to indicate that the secondary cache does not store the data requested by the target request; The allocating a corresponding miss status register for the target request and executing the target request through the miss status register includes: After detaching the target request from the pipeline queue, controlling the target request to enter the allocated miss status register to wait, and generating a new target request of the miss status register type through the miss status register. When obtaining refill data from the tertiary cache through the new target request and refilling it into the secondary cache, the access operation of the target request of the data acquisition type to the refill data in the secondary cache is awakened through the new target request.

5. The method for processing a cache request according to claim 3, wherein, When the type of the target request is the data probing type in the channel task type set, the target request is issued by the tertiary cache, and the method further includes: When the hit result is a miss, feedback to the tertiary cache that the target data requested by the target request is not stored in the secondary cache. When the hit result is a hit and the target data is only stored in the secondary cache, start reading the target data corresponding to the target request. When the hit result is a hit and the target data is stored in both the secondary cache and the primary cache, start reading the target data in the secondary cache, and at the same time request the primary cache to invalidate the stored target data.

6. The method for processing a cache request according to claim 4, wherein, The method further includes: Request the tertiary cache to obtain the refill data according to the new target request. When receiving the refill data through the new target request, enter the new target request into the pipeline queue from the specific data bit, perform operations of determining the target data block from the secondary cache, releasing the old data stored in the target data block, and writing the refill data into the target data block.

7. The method for processing a cache request according to claim 6, wherein, The secondary cache includes multiple data block groups, and each database group includes multiple data blocks. The data block groups are used to parallel process the access of the target request to the data blocks included in the data block groups. The target data block is: a data block in the secondary cache that is not occupied by other requests.

8. The method for processing a cache request according to claim 4, wherein, The operation of awakening the access operation of the target request of the data acquisition type to the refill data in the secondary cache through the new target request includes: Through the new target request, control the target request of the data acquisition type to enter the pipeline queue from the specific data bit, and at the same time generate a wake-up request through the secondary cache and issue it to the primary cache by the wake-up queue. After an interval of the third number of data bits, read the refill data from the secondary cache, and issue the target request of the data acquisition type as a refill request to the primary cache by the refill queue. Wherein, the wake-up request is used to wake up the operation of reading data from the primary cache through the target request of the data acquisition type; the refill request is used to write the refill data into the primary cache for the target request of the data acquisition type to read.

9. The method for processing a cache request according to claim 3, wherein, When the type of the target request belongs to the data acquisition type in the channel task type set, the target data is the data stored in the secondary cache, and the response to the target data is: refilling the target data into the primary cache for the target request to read. When the type of the target request belongs to the data release type in the set of channel task types, the target data is the data stored in the first-level cache, and the response generated for the target data is: receiving the target data sent by the first-level cache through the second-level cache and storing it to implement the release of the target data by the first-level cache; When the type of the target request belongs to the data probing type in the set of channel task types, the target data is the data stored in the second-level cache, and the response generated for the target data is: setting the target data to an invalid state.

10. The method for processing a cache request according to claim 1, wherein, The types of the requests include: the channel task types issued by the processor and the missing status register types generated by the missing status register; The channel task types include the data acquisition type, the data release type, and the data probing type; The priority of the missing status register type is higher than that of the data release type, the priority of the data release type is higher than that of the data probing type, and the priority of the data probing type is higher than that of the data acquisition type.

11. The method for processing a cache request according to claim 10, wherein, The selecting of the target request from all the requests according to the type of the request includes: When there is a request of the missing status register type among all the requests, taking the request of the missing status register type as the target request; When there is no request of the missing status register type among all the requests but there is a request of the data release type, taking the request of the data release type as the target request; When there is no request of the missing status register type and the data release type among all the requests but there is a request of the data probing type, taking the request of the data probing type as the target request; When there is no request of the missing status register type, the data release type, and the data probing type among all the requests but there is a request of the data acquisition type, taking the request of the data acquisition type as the target request.

12. The method for processing a cache request according to claim 10, wherein, The pipeline queue includes 5 sequentially arranged data bits: data bit S1 - data bit S5; For a target request of the data acquisition type, when it is configured to be at data bit S1, an operation of reading the cache directory of the second-level cache is performed; When at data bit S3, a directory result is obtained, and an operation of determining whether the target request hits in the cache directory is performed, and if it hits, an operation of reading the data is performed; When it hits and is at data bit S5, the data is obtained, and an operation of feeding back the data to the upper layer is performed; For a target request of the data release type, when it is configured to be at data bit S1, an operation of reading the cache directory of the second-level cache is performed; when at data bit S3, a directory result is obtained, and an operation of storing the data released by the upper layer in the second-level cache and feeding back a release completion message to the upper layer is performed; For a target request of the data exploration type, when configured to be at data bit S1, an operation of reading the cache directory of the secondary cache is performed; when at data bit S3, a directory result is obtained, and an operation of determining whether the target request hits in the cache directory is performed. If it does not hit, at data bit S3, a response that the data does not exist is sent to the tertiary cache; if the directory result is a hit, at data bit S3, the target data is read, and at data bit S5, the read target data is invalidated, and a response is sent to the tertiary cache.

13. The method for processing cache requests according to claim 1, wherein, The assigning of a corresponding miss status register to the target request includes: Obtaining a first quantity of requests included in the first n data bits of the pipeline queue; Obtaining a second quantity of miss status registers that have been assigned among all the miss status registers; When the sum result of the first quantity and the second quantity is greater than or equal to the total number of the miss status registers, preventing new requests from entering the pipeline queue; When the sum result of the first quantity and the second quantity is less than the total number of the miss status registers, assigning an idle miss status register to the target request.

14. The method for processing a cache request according to claim 1, wherein, The secondary cache includes a plurality of data block groups, and the data block groups are used to parallel-process accesses of the target request to data blocks included in the data block groups; Before the target request enters the pipeline queue from a specific data bit of the pipeline queue of the secondary cache for execution, the method further includes: When it is determined that the target request and a write buffer directory request in the pipeline queue both access the same data block group, preventing the target request from entering the pipeline queue; the write buffer directory request is at at least one third data bit in the pipeline queue, and the third data bit is used to perform the operation of the write buffer directory.

15. The method for processing a cache request according to claim 1, wherein, The first quantity and the second quantity are 2.

16. The method for processing a cache request according to claim 1, wherein, Before the target request enters the pipeline queue from a specific data bit of the pipeline queue of the secondary cache for execution, the method further includes: When it is determined that the target request and requests in the miss status register both access the same data, preventing the target request from entering the pipeline queue.

17. A processing device for cache requests, wherein, The apparatus includes: An enqueue module, configured to select a target request from all the requests according to the type of the request obtained from the secondary cache, and enter the target request into the pipeline queue from a specific data bit of the pipeline queue of the secondary cache for execution; the pipeline queue includes a plurality of sequentially arranged data bits; A return module, configured to return a response generated by executing the target request when the pipeline queue successfully executes the target request; An execution module, configured to, when the pipeline queue fails to successfully execute the target request, assign a corresponding miss status register to the target request, and execute the target request through the miss status register.

18. An electronic device, wherein, Including: A processor; A memory for storing instructions executable by the processor; Wherein, the processor is configured to execute the instructions to implement the method according to any one of claims 1 to 16.

19. A computer-readable storage medium, wherein, When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method according to any one of claims 1 to 16.

20. A computer program comprising computer-readable code which, when run on a computing processing device, causes the computing processing device to execute the method according to any one of claims 1 - 16.

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