Access method and apparatus

Abstract

Provided in the present application are an access method and an apparatus. The method is applied to a computer device, the computer device comprising a processor and a memory, the computer device further comprising at least one physical memory page and at least one temporary page, and each physical memory page being mapped to the memory. The method comprises: during the process of accessing a target virtual memory page on the basis of an access instruction, if the target virtual memory page is not mapped to a physical memory page, allocating a target temporary page for the target virtual memory page; and executing access operation on a cache space corresponding to the target temporary page. Thus, the present application effectively reduces the impact of page faults on program access, thus improving the access efficiency.

Description

Access method and device Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to an access method and device. Background Art

[0002] When a program is executed by a central processing unit (CPU), all addresses in the program are virtual addresses. If a page fault exception is triggered when an application accesses a virtual address, the computer's execution context switches from user mode to kernel mode. The operating system (OS) then handles the page fault exception, allocating a physical page to the virtual page and updating the page table. The execution context then switches back from kernel mode to user mode, and the application re-executes the access operation. Summary of the Invention

[0003] The present application provides an access method and apparatus, wherein when a page fault exception occurs in a computer device, temporary pages are allocated to virtual memory pages, thereby effectively improving access efficiency and preventing the interruption of page fault exceptions from affecting program access.

[0004] In a first aspect, the present application provides an access method. The method is applied to a computer device, which includes a processor and a memory. The computer device also includes at least one physical memory page and at least one temporary page, each physical memory page is mapped to the memory, and the method includes: the computer device obtains an access instruction, and the access instruction is used to indicate access to a target virtual memory page. In response to the access instruction, the computer device queries whether the target virtual memory page is mapped to a physical memory page. In the case that the target virtual memory page is not mapped to a physical memory page, the computer device allocates a target temporary page to the target virtual memory page. An access operation is performed on the cache space corresponding to the target temporary page. In this way, the computer device avoids interruptions caused by page fault exceptions during program access by mapping virtual pages to temporary pages, thereby improving access efficiency and reducing the impact of page fault exceptions on program access.

[0005] Exemplarily, the processor stores (or maintains, provides) at least one physical memory page and at least one temporary memory page.

[0006] Illustratively, the scratch page is not mapped to memory.

[0007] In one possible implementation, the processor stores usage information and physical memory page allocation information for each temporary page. The usage information indicates whether the corresponding temporary page is available, and the physical memory page allocation information indicates the physical memory page allocated to the corresponding temporary page. In this way, the computer device can also allocate temporary pages to virtual memory based on the availability status. Furthermore, the computer device can execute a delay processing flow based on the physical memory page allocation information. By maintaining the status of temporary pages in real time, flexible allocation and dynamic maintenance of temporary pages can be achieved.

[0008] For example, the physical memory page allocation information may be the flush to PPN identifier in the embodiment of the present application (the name is merely an illustrative example and is not limited in this application).

[0009] In one possible implementation, allocating a target temporary page to a target virtual memory page includes: a computer device selecting a target temporary page from temporary pages indicated as available by usage information. The computer device allocates the target temporary page to the target virtual memory page. The computer device updates usage information of the target temporary page to unavailable. In this way, by marking the usage status of the temporary page, the computer device can prevent the same temporary page from being reused.

[0010] Illustratively, the computer device may select temporary pages in sequence, or may randomly select an available temporary page, which is not limited in this application.

[0011] Exemplarily, the “unusable” of a temporary page may also be understood as the temporary page being invalid or occupied, that is, the temporary page marked as unavailable cannot be allocated to other virtual memory pages.

[0012] In one possible implementation, the access instruction is a write instruction, and the corresponding access operation is performed on the cache space corresponding to the target temporary page, including writing data to the cache space corresponding to the target temporary page. In this way, after allocating the temporary page, the present application can directly write data to the cache without executing the interrupt process for the page fault exception, which can effectively improve access efficiency and shorten the time taken to handle the page fault exception. In particular, for user-side program access, by shortening the processing time, the user can be "unaware".

[0013] In a possible implementation, after performing the corresponding access operation on the cache space corresponding to the target temporary page, it also includes: allocating the target physical memory page to the target temporary page when the preset conditions are met. Updating the physical memory page allocation information of the target temporary page, and the updated physical memory page allocation information is used to indicate that the target physical memory page is allocated to the target temporary page. The usage information of the target temporary page is updated to available. In this way, after the access is executed, the relevant process of the page fault exception is executed to avoid program interruption and reduce the system processing pressure. In addition, the page fault exception handling process is executed only when the preset conditions are met, and the OS executes the allocation of physical memory pages to avoid OS interruption when the application reads, thereby improving efficiency.

[0014] Exemplarily, when a preset condition is met, the execution context is switched from user mode to kernel mode, and the OS allocates a target physical memory page for the target temporary page.

[0015] In one possible implementation, after performing a corresponding access operation on the cache space corresponding to the target temporary page, the method further includes: detecting that the usage information of the target temporary page is updated to be available, and based on the physical memory page allocation information of the target temporary page, writing the data in the cache space corresponding to the target temporary page to the memory corresponding to the target physical memory page. In this way, the hardware monitors the status of the usage information of the temporary page in real time, and can write the data in the cache to the memory in a timely manner by switching the status of the usage information, thereby releasing cache resources in a timely manner. In addition, writing the data back to the physical memory in a timely manner can ensure the security and stability of the data.

[0016] In a possible implementation, the preset condition includes at least one of the following: a processor load is less than a first threshold, the number of temporary pages indicated as unavailable by usage information exceeds a second threshold, and a timer expires.

[0017] In one possible implementation, the processor stores a retention flag corresponding to each cache line, indicating whether the data in the corresponding cache line should be retained. After writing the data to the cache space corresponding to the target temporary page, the processor also includes updating the retention flag corresponding to each cache line in the cache space to "retain." This prevents the data corresponding to the temporary page from being deleted by setting the retention flag, allowing the data to be retained until the deferred processing stage (i.e., the data write-back stage).

[0018] In one possible implementation, the processor stores a page table, which includes allocatable information of each virtual memory page, and the allocatable information is used to indicate whether the corresponding virtual memory page can be allocated a temporary page. In this way, by recording the AAV (allocatable information) of each virtual page, it is possible to mark which virtual memory pages can be allocated a temporary page. When traversing the page table, it is possible to obtain whether the virtual page can be mapped to a physical memory page or a temporary page through the AAV, without having to wait for the page fault process to find that the virtual page is unavailable, thereby avoiding the overhead caused by the process.

[0019] In one possible implementation, allocating a target temporary page to a target virtual memory page includes: querying allocatable information of the target virtual memory page; finding that the allocatable information of the target virtual memory page indicates that the target virtual memory page is allocatable, and allocating the target temporary page to the target virtual memory page. In this way, the computer device can also allocate temporary pages to virtual memory based on the availability status. Furthermore, the computer device can execute a deferred processing flow based on the physical memory page allocation information. By maintaining the status of the temporary page in real time, flexible allocation and dynamic maintenance of the temporary page can be achieved.

[0020] In a second aspect, the present application provides an access method. The method is applied to a computer device, and the method includes: the memory management unit MMU queries whether the first virtual memory page is mapped to a physical memory page in response to the obtained first access instruction, and the first access instruction is used to instruct to read the first virtual memory page. When the first virtual memory page is not mapped to the physical memory page, the MMU allocates a target physical memory page to the first virtual memory page, and the target physical page includes specified data. In this way, in the data reading scenario, the present application can avoid program interruptions caused by page fault exceptions by allocating specified physical pages, thereby effectively improving the efficiency of program reading.

[0021] In one possible implementation, allocating a target physical memory page to the first virtual memory page includes: the MMU marking the first virtual memory page as a read-only page. Thus, by marking the virtual memory page as a read-only page, a temporary page can be allocated to the virtual memory page based on the marking in a subsequent write scenario.

[0022] In one possible implementation, a computer device includes a processor and a memory, the processor maintains at least one physical memory page and at least one temporary page, each physical memory page is mapped to the memory, and the method further includes: the MMU queries whether the first virtual memory page is mapped to the physical memory page in response to the obtained second access indication; the second access indication is sent to the MMU by the application in response to the received second access instruction, and the second access instruction is used to instruct to write to the first virtual memory page; the MMU allocates a target temporary page to the first virtual memory page when the first virtual memory page has been mapped to the target physical memory page and the first virtual memory page is a read-only page.

[0023] In one possible implementation, the method also includes: the MMU queries whether the second virtual memory page is mapped to a physical memory page in response to the obtained third access instruction, and the third access instruction is used to instruct to read the second virtual memory page; when the second virtual memory page is not mapped to the physical memory page, the MMU allocates a target physical memory page to the second virtual memory page, and the target physical page includes specified data.

[0024] In a possible implementation, the designated data is all-0 data.

[0025] In a third aspect, the present application provides an access device. The device is applied to a computer device, which includes a processor and a memory. The computer device also includes at least one physical memory page and at least one temporary page, each physical memory page is mapped to the memory, and the device includes: an acquisition module, a query module, a first allocation module and an execution module. The acquisition module is used to obtain an access instruction, and the access instruction is used to indicate access to a target virtual memory page; the query module is used to query whether the target virtual memory page is mapped to a physical memory page in response to the access instruction; the first allocation module is used to allocate a target temporary page to the target virtual memory page if the target virtual memory page is not mapped to a physical memory page; the execution module is also used to perform an access operation on the cache space corresponding to the target temporary page.

[0026] In a possible implementation, the processor stores usage information and physical memory page allocation information of each temporary page, where the usage information is used to indicate whether the corresponding temporary page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated to the corresponding temporary page.

[0027] In a possible implementation, the allocation module is specifically configured to: select a target temporary page from temporary pages indicated as available by usage information; allocate the target temporary page to a target virtual memory page; and update usage information of the target temporary page to unavailable.

[0028] In a possible implementation, the access instruction is a write instruction, and the execution module is specifically configured to write data into a cache space corresponding to a target temporary page.

[0029] In one possible implementation, the device also includes: a second allocation module, used to allocate a target physical memory page to the target temporary page when a preset condition is met; a first update module, used to update the physical memory page allocation information of the target temporary page, and the updated physical memory page allocation information is used to indicate that the target physical memory page is allocated to the target temporary page; a second update module, used to update the usage information of the target temporary page to available.

[0030] In one possible implementation, the device also includes: a data processing module, which is used to detect that the usage information of the target temporary page is updated to available, and based on the physical memory page allocation information of the target temporary page, write the data in the cache space corresponding to the target temporary page to the memory corresponding to the target physical memory page.

[0031] In a possible implementation, the preset condition includes at least one of the following: a processor load is less than a first threshold, the number of temporary pages indicated as unavailable by usage information exceeds a second threshold, and a timer expires.

[0032] In one possible implementation, the processor stores a retention tag corresponding to each cache line, where the retention tag is used to indicate whether data in the corresponding cache line is retained; the device also includes: a third update module, which is used to update the retention tag corresponding to each cache line in the cache space to retained.

[0033] In a possible implementation, the processor stores a page table, where the page table includes allocatable information of each virtual memory page, where the allocatable information is used to indicate whether a temporary page can be allocated to the corresponding virtual memory page.

[0034] In a possible implementation, the allocation module is specifically configured to: query allocatable information of a target virtual memory page; if the allocatable information of the target virtual memory page is found to indicate that the target virtual memory page can allocate a temporary page, allocate the target temporary page to the target virtual memory page.

[0035] In a fourth aspect, embodiments of the present application provide a computer device comprising: a transceiver / transceiver pin and a processor, and optionally, a memory. The transceiver / transceiver pin, the processor, and the memory communicate with each other via an internal connection path; the processor is configured to execute instructions to control the transceiver / transceiver pin to send or receive signals; and the memory is configured to store instructions. When the processor executes the instructions, it performs the method described in the first aspect or any possible implementation of the first aspect.

[0036] In a fifth aspect, an embodiment of the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0037] In a sixth aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0038] In a seventh aspect, embodiments of the present application provide a chip comprising a processing circuit and transceiver pins. The transceiver pins and the processing circuit communicate with each other via an internal connection path, and the processing circuit executes the method of the first aspect or any possible implementation of the first aspect to control the receive pin to receive a signal and to control the transmit pin to send a signal.

[0039] In an eighth aspect, an embodiment of the present application provides a computer cluster, which includes at least one computer device, and the computer device is used to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram showing an exemplary correspondence relationship between virtual addresses and physical addresses;

[0041] FIG2 is a schematic diagram of an exemplary TLB;

[0042] FIG3 is a schematic diagram illustrating an exemplary TLB query;

[0043] FIG4 is a schematic diagram illustrating an exemplary program access flow;

[0044] FIG5 is a schematic diagram showing an exemplary mapping relationship between virtual pages and physical pages;

[0045] FIG6 is a schematic diagram illustrating an exemplary memory allocation process;

[0046] FIG7 is a schematic diagram showing an exemplary memory allocation;

[0047] FIG8 is a schematic diagram showing an exemplary access process;

[0048] FIG9 is a schematic diagram showing an exemplary memory page division;

[0049] FIG10 is a schematic diagram showing an exemplary process of writing data;

[0050] FIG11 is a schematic diagram illustrating an exemplary process of reading data;

[0051] FIG12 is a schematic diagram illustrating an exemplary delay processing flow;

[0052] FIG13 is a schematic diagram showing an exemplary correspondence between temporary pages and cache;

[0053] FIG14 is a schematic diagram showing one of the structures of the device;

[0054] FIG. 15 is one of the schematic structural diagrams of the device shown as an example. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0057] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0058] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0059] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0060] Before introducing the technical solutions in the embodiments of the present application, a brief introduction to the background technologies that may be involved in the present application is first given:

[0061] 1. Virtual address and physical address

[0062] During the execution of a program (also known as an application program, which is not limited in this application), the addresses used by the program are all virtual addresses (VA). When the operating system loads a program into memory, it allocates an available physical address space for the program, i.e., physical memory space; the operating system maps the virtual addresses used in the program to specific physical addresses (PA). This mapping is done in units of pages.

[0063] In computer systems, the memory management unit (MMU) implements the mapping between a program's virtual address and physical address through a paging mechanism. The virtual space in the operating system is divided into pages, which are virtual memory pages, also called virtual pages. Correspondingly, the physical address space is also divided into pages, and the pages of the physical address space are called physical pages.

[0064] The pages corresponding to both virtual and physical addresses are sequentially numbered, called page numbers. Address mapping involves mapping a virtual page to a physical page. In other words, the high-order bits of the virtual address are replaced with the high-order bits of the physical address.

[0065] During this mapping process, as shown in Figure 1, both the virtual address and the physical address are 64 bits, corresponding to a 4KB page size. The lower 12 bits of the virtual and physical addresses (i.e., Addr[11:0]) remain unchanged, meaning they are identical. This is because these 12 bits represent the offset within the 4KB page. The upper portions of the virtual and physical addresses, i.e., the Addr[63:12] fields, are called VPN (Virtual Page Number) in virtual addresses and PPN (Physical Page Number) in physical addresses. The lower portion of the address, i.e., the Addr[11:0] fields, is called the Offset. As can be seen, the Offset portion of the address remains unchanged during the mapping process.

[0066] 2. Page Table Cache and Page Table

[0067] The TLB (Translation Lookaside Buffer), also known as the page table cache, is a translation lookaside buffer. During program execution, the operating system creates a complete mapping from virtual addresses to physical addresses for the program. This mapping is stored in a data structure called the page table. Each entry in the page table contains the corresponding VPN and PPN information. Address translation within the processor is typically performed by hardware, known as the TLB (Translation Lookaside Buffer), which stores a portion of the page table.

[0068] Figure 2 shows the general structure of a page table within a TLB, which contains 32 entries. The structure of each entry in the TLB is similar to the structure of each page table entry (PTE) in the page table. The TLB can be thought of as a cache for the page table, storing a portion of the complete page table.

[0069] VPN represents the high-order bits of the virtual address. For example, with a 64-bit address width (i.e., a 64-bit address), a virtual address can be represented as Vir_Addr[63:0]. When the page size is 4KB, VPN is Vir_Addr[63:12], meaning VPN does not include the lower 12 bits of the address. PPN represents the high-order bits of the physical address. When the physical address is 64 bits wide, it can be represented as Phy_Addr[63:0]. When the page size is 4KB, PPN is Phy_Addr[63:12]. As you can see, PPN also does not include the lower 12 bits of the address.

[0070] As shown in Figure 3, when the processor performs an address fetch or memory access, the corresponding virtual address is entered into the TLB. The TLB extracts the VPN from the virtual address and compares it with the various entries in the TLB. If the VPN matches the VPN in an entry, the PPN field in that entry is output, which is considered a TLB hit. If no entry's VPN matches the VPN to be translated, a TLB miss occurs.

[0071] When a TLB miss occurs, the page table is searched for the PPN corresponding to the VPN, and the VPN and PPN information is then populated into the TLB (usually overwriting an existing entry). This process is called a page table walk. The page table walk can be performed automatically by the hardware or by the operating system.

[0072] 3. Page Fault (PF)

[0073] Page Fault, also known as page fault, may also be referred to as page fault exception, page error, etc., which is not limited in this application. As described above, during the address mapping process, the CPU first accesses the TLB. If the TLB Miss, the CPU further performs a page table walk (PTW) based on the virtual address, that is, searches for the PPN corresponding to the virtual address in the Page Table. If there is no table entry whose VPN is the same as the VPN to be converted, it is considered that a Page Table Miss has occurred, and the MMU triggers a page fault exception, passing the control in the CPU to the page fault exception handler in the operating system kernel. The operating system (specifically the page fault exception handler in the operating system kernel, which will not be repeated below) executes the Page Fault process, allocates the corresponding physical memory for the virtual address, and updates the page table.

[0074] This method, known as lazy allocation, is a physical memory allocation strategy. Specifically, physical memory pages are allocated only when they are accessed. This ensures that the OS allocates the corresponding physical memory only when the memory is actually needed, that is, upon first use. Lazy allocation works because it is rare for an application to immediately access all requested pages. Typically, programs operate using much less memory than the memory space they request. This characteristic of programs allows the memory subsystem to run multiple applications concurrently, improving overall system performance without causing memory shortages. Even though lazy allocation reduces the actual memory allocated to applications, it is still possible that all memory will be allocated when many applications are running simultaneously on the system. If memory is exhausted, a swapping mechanism is used to store the contents of some memory pages in non-volatile storage. These pages can then be reused and reallocated to other applications after their contents are cleared.

[0075] These two mechanisms (i.e., delayed allocation and swapping) are typically implemented as part of PF exception handling. When memory is "allocated" (via mmap or malloc), the processor (specifically, the OS) actually only creates a portion of the VA space for the calling program. It's not until they are accessed that physical memory pages are paired with these virtual memory pages, establishing a mapping relationship. Memory accesses within this newly created area trigger PF by the MMU, and the OS exception handler then checks to confirm the legality of the access and allocates a physical page.

[0076] The following briefly describes the memory access process in conjunction with the program access process diagram shown in FIG4 , referring to FIG4 , specifically including:

[0077] The CPU Core executes the access instructions in the program. The access instructions are used to instruct access to virtual space (also known as virtual memory space, not limited in this application). For example, the CPU Core inputs a virtual address (also known as a virtual memory address, not limited in this application) to the MMU. The MMU performs address translation on the virtual address to query its corresponding physical address.

[0078] Specifically, the TLB searches for a corresponding page table entry in the TLB page table based on the virtual address. In one example, if the TLB hits, the MMU performs address translation based on the PPN to obtain the corresponding physical address.

[0079] For example, as shown in Figure 5, assume that the four virtual pages VPN0 through VPN3 are on the left, and the physical pages PPN0 through PPN7 are on the right. The mapping relationship between the virtual and physical pages is shown by the arrows: VPN1 maps to PPN1, and VPN2 maps to PPN2. The TLB contains the page table entries corresponding to these two mappings. If a program accesses VPN1, the TLB traverses the page table entry corresponding to VPN1 and, based on the mapping relationship, retrieves the corresponding physical page, PPN1.

[0080] In another example, if the TLB misses, the MMU traverses the page table based on the virtual address. If the page table hits, the MMU obtains the corresponding physical address, and the MMU updates the TLB, that is, inserts the page table entry of the virtual page into the TLB. If the page table misses, the Page Fault process is executed. The MMU triggers a page fault exception. Specifically, the MMU outputs an interrupt signal to the OS, and the execution context switches from user mode to kernel mode, which can also be understood as transferring control in the CPU to the operating system. The OS detects the validity of the virtual address. If the virtual address is valid, the OS allocates a physical page for the virtual page from available and idle physical pages. The OS updates the page table entry in the page table. The execution context switches from kernel mode back to user mode, the processor re-executes the access instruction, the TLB hits, and the corresponding access operation can be performed on the physical page corresponding to the virtual page.

[0081] For example, referring still to Figure 5 , a program requests access to VPN0, but neither the TLB nor the page table hits. The OS experiences a page fault interrupt, checks the validity of VPN0, and if it determines VPN0 is valid, assigns it PPN5. The OS updates the page table, and the TLB optionally updates it simultaneously. The updated page table includes a page table entry for VPN0, which maps VPN0 to PPN5. After the PF exception handler completes its work, the system switches from kernel mode back to user mode, and the program re-executes the accessed instruction. This mode change (from user mode to kernel mode and then back to user mode) requires storing (or pushing) certain program "state" (such as local variables, hardware registers, and the program counter) onto the stack. The final operations of the PF handler pop this state from the stack and return it to its original location so that the faulting instruction can continue execution. In addition to the overhead of stack pushes and pops, context switches also pollute architectural resources such as caches, TLBs, and branch predictors.

[0082] Exemplarily, there are two types of page fault exceptions in the system: 1. Major Page Fault, also known as Hard Page Fault, means that the memory to be accessed is not in the virtual memory space, nor in the physical memory space, and needs to be loaded from a slow device. A slow device refers to an end device (host or storage) in the Storage Area Network (SAN) network with an abnormal state. The abnormal state is manifested as the inability of the end device (host or storage) to respond normally and quickly. 2. Minor Page Fault, also known as Soft Page Fault, means that the memory to be accessed is not in the virtual memory space, but in the physical memory space. The MMU only needs to establish a mapping relationship between the physical page and the virtual page.

[0083] The method in the embodiment of the present application can be applied to the Minor Page Fault scenario, which can effectively avoid business interruption caused by PF during program access, improve the processing efficiency of programs, especially user-side programs, and enhance the user experience.

[0084] The technical solution in the embodiment of the present application is divided into three parts for description, the first part is memory allocation, the second part is program access, and the third part is delay processing. Among them, memory allocation is the allocation of virtual memory space, and the operating system can allocate corresponding virtual pages to the program based on the needs of the program (which can also be understood as virtual memory space, virtual address, virtual memory address, etc., which are not limited in this application). During the program access process, the program accesses the virtual address. During this process, if a page fault exception occurs, the corresponding temporary page is allocated for the virtual page (the concept of temporary page will be described in detail below). In the embodiment of the present application, program access can be understood as a command included in the program for indicating access to the virtual address, or it can be understood as the CPU running the program and executing the access command in the program. Delay processing can optionally be if a page fault exception occurs during the program access process and after allocating a temporary page, when predetermined conditions are met, a data write back operation is performed on the data of the temporary page. The following is a detailed description of each part in conjunction with the flowchart corresponding to each part:

[0085] 1. Memory allocation

[0086] FIG6 is a schematic diagram of an exemplary memory allocation process. Referring to FIG6 , the process specifically includes but is not limited to the following steps:

[0087] S601, the OS determines whether the virtual memory space is available.

[0088] Exemplarily, the program sends an operating system request, which includes the required memory space size (for example, 4K, which can be set according to actual needs and is not limited in this application) to request the operating system to allocate corresponding memory space for the program.

[0089] Based on the program's request, the operating system detects whether the operating system's virtual memory space is available, that is, whether there is enough remaining virtual memory space to allocate a virtual memory space of a corresponding size to the program.

[0090] In one example, if the virtual memory space is available, S602 is executed.

[0091] In another example, if the virtual memory space is not available (which can also be understood as insufficient virtual memory space), the program is informed that the virtual memory space is not available. The program can optionally prompt the user that the current memory space is not available.

[0092] S602: OS allocates corresponding virtual memory space according to the request.

[0093] Exemplarily, the OS allocates a sufficiently large virtual memory space to the program in the virtual memory space according to the requirements of the program.

[0094] In the standard C library, functions such as malloc and mmap are provided. The operating system can call the corresponding function to complete memory allocation. Figure 7 is an exemplary memory allocation diagram. Please refer to Figure 7. After the process calls A=malloc(4K), the operating system pushes the pointer to a higher address of 4K, thereby completing the memory allocation. Among them, this memory allocation is only an allocation of the virtual memory space of the operating system. This virtual memory space does not have a physical page corresponding to it, that is, the virtual page is not mapped to a physical page. When the process (or program) reads and writes this virtual memory for the first time, a page fault interrupt, i.e. PF, will occur. In an embodiment of the present application, the operating system allocates a corresponding physical page or temporary page to the virtual page, that is, establishes a mapping relationship between the virtual page and the temporary page (or physical page). The specific implementation method will be described in detail in the second part.

[0095] S603, the OS traverses the page table, creates a page table entry, and sets AAV to 1.

[0096] Exemplarily, after the OS allocates virtual memory space, the OS updates the page table (including the Page Table, or the Page Table and a portion of the page table cached by the TLB), and creates a corresponding PTE for the virtual page.

[0097] In the embodiment of the present application, the PTE includes an Automatic Assignment Valid (AAV) flag (1 bit), which can also be called allocatable information, and is used to identify whether the corresponding virtual page can be allocated a temporary page, as shown in Table 1:

[0098] Table 1

[0099] Refer to Table 1. The PTE is represented by the solid line. The dashed line represents the corresponding VPN. The MMU uses the VPN as an index to traverse the page table and find the corresponding PTE. The PPN is the physical page number corresponding to the virtual page (see Figure 1 for the concept).

[0100] PPN is used to identify the memory page mapped by the virtual page. In the embodiment of the present application, the memory page includes a temporary page or a physical page, which will not be repeated below. Of course, in other embodiments, the memory page may also refer to a virtual page and a physical page, which is not limited in the present application. In this example, as described above, during the virtual memory space allocation process, the OS does not temporarily allocate the corresponding physical page for it. Accordingly, the content corresponding to the PPN is empty or other meaningless data (which can be set according to actual needs and is not limited in the present application). After the memory page is allocated for the first access, the PPN is updated accordingly.

[0101] Present (available) is used to identify whether the corresponding virtual page has been allocated a memory page (temporary page or physical page). Similarly, since no memory page is currently allocated, Present is empty or has other values ​​(can be set according to actual needs, not limited by this application). In the embodiment of the present application, the unallocated memory page is marked as "0" and the allocated memory page is marked as "1". The values ​​are only for illustrative purposes and are not limited by this application.

[0102] Writable is used to identify whether the corresponding virtual page is writable. In the embodiment of the present application, the types of virtual pages include "writable" and "read-only" (which can also be understood as "non-writable"), where "writable" type virtual pages are readable and writable, and "read-only" type virtual pages can only be read, not written. In the embodiment of the present application, the "writable" mark is "1" and the "read-only" mark is "0". The numerical values ​​are only illustrative examples and are not limited in this application. The Writable mark can be set according to user needs (the specific setting method can refer to the existing technical embodiments, which will not be repeated in this application), or it can be set to a default value. In the embodiment of the present application, the default value is 1, that is, each virtual page is "writable" when it is initially created.

[0103] AAV is used to identify whether the corresponding virtual page can be allocated a temporary page. In an embodiment of the present application, the computer device may be configured with a temporary page allocation function option, through which the user can choose to turn on or off the function of automatically allocating temporary pages. In one example, the computer device determines to turn on the automatic allocation of temporary pages in response to the received user settings, and the AAVs in the PTE of the newly created virtual page are all marked as "available", that is, temporary pages can be automatically allocated. In another example, the computer device determines to turn off the automatic allocation of temporary pages in response to the received user settings, and the AAVs in the PTE of the newly created virtual page are all marked as "unavailable", that is, temporary pages cannot be automatically allocated. After the function is turned off, the computer device allocates physical pages according to the existing process, and the specific process will be described below. In an embodiment of the present application, the temporary page that can be automatically allocated is marked as "1", and the temporary page that cannot be automatically allocated is marked as "0" or other numerical values. The numerical values ​​are only illustrative examples and are not limited in this application.

[0104] It should be noted that this application only represents the contents of each register in a tabular manner. This method is only an illustrative example and this application does not limit it.

[0105] 2. Program Access

[0106] FIG8 is a schematic diagram of an exemplary access process. Please refer to FIG8 , which specifically includes but is not limited to the following steps:

[0107] S801: Query whether a virtual page is mapped to a physical page.

[0108] 4 , the MMU receives an access instruction sent by a program, the access instruction being used to instruct access to a corresponding virtual page. The access instruction includes a virtual address, which includes but is not limited to the page number and offset of the virtual page.

[0109] The MMU traverses the page table cached by the TLB based on the virtual address. In one example, if the TLB hits, the MMU translates the virtual address based on the PPN in the page table entry to obtain the corresponding physical address. Hardware (such as the cache controller or memory controller) can then access the memory corresponding to the physical address.

[0110] In another example, if the TLB misses, the MMU further performs a PTW based on the virtual address, i.e., walks the page table. If a page table hit occurs, the MMU translates the virtual address based on the PPN in the page table entry to obtain the corresponding physical address, and then updates the TLB. The hardware (e.g., the memory controller) can access the memory corresponding to the physical address. If the page table misses, the process proceeds to S802.

[0111] S802: Allocate a temporary page for the virtual page.

[0112] Exemplarily, when the MMU determines that the virtual page is not mapped to a physical page, that is, both the page table and the TLB are hit, the MMU allocates a temporary page for the virtual page.

[0113] The following is a detailed description of the temporary page in the embodiment of the present application:

[0114] In the embodiment of the present application, the page size is pre-configured in the processor architecture (configured by the operator before leaving the factory). Optionally, the physical page and the temporary page are the same size, for example, both are 4KB, which can be set according to actual needs and is not limited by this application.

[0115] FIG9 is a schematic diagram of memory page partitioning shown as an example. Referring to FIG9 , the processor divides the physical space (part of the physical space) into normal space and temporary space according to the page size. The sizes of the normal space and the temporary space are configured by the operator before leaving the factory, and the corresponding parameters are pre-configured in the processor architecture. Among them, the normal space includes physical memory. In the embodiment of the present application, the physical memory can be referred to as memory, and the memory can optionally be a dynamic random access memory (DRAM). The processor divides the physical memory into multiple pages, i.e., physical pages, according to the preset page size.

[0116] For example, the processor sets a page size and divides the temporary memory into multiple temporary pages, referred to as temporary pages. In the embodiments of the present application, temporary pages are not mapped to memory. It can be understood that physical pages are mapped to memory, and the processor maintains a mapping between physical pages and memory. Reading and writing physical pages is equivalent to reading and writing the physical memory corresponding to the physical page. Optionally, in some instances, to speed up access, when a program reads or writes data on a physical page, the cache typically allocates corresponding cache space for the physical page. For example, when writing data, the cache allocates corresponding cache space for the physical page, and the processor writes the data to the cache. The hardware then writes the data back to the physical memory corresponding to the physical page. The cache has a caching mechanism. If a portion of the data in the cache is not accessed within a certain period of time, the cache will clear the cache space of this portion of data. It can be understood that the correspondence between the cache and the physical page is temporary. After the data is written back or if the data has not been accessed for a certain period of time, the cache will clear the data, and the correspondence no longer holds. The mapping relationship between physical pages and physical memory is usually fixed. Units or modules (including hardware and software) can access the corresponding physical memory to read and write data based on the mapping relationship between physical pages and physical memory. For temporary pages, they are mapped to physical memory. That is, they have no corresponding memory space, and the data on the temporary pages can only be stored in the corresponding cache.

[0117] In the embodiment of the present application, the processor configures a corresponding management register (Temporary Page Management Register, TPMR) for each temporary page, as shown in Table 2:

[0118] Table 2

[0119] Please refer to Table 2. Temporary PPN (temporary physical memory page number, referred to as temporary page number) is the page number of the temporary page. Its definition is similar to the physical page number, that is, the temporary page corresponding to the temporary page address (also called temporary address) is numbered sequentially, called the temporary page number.

[0120] The Temporary PPN can be used as the index of the TPMR of each temporary page, and the unit or module can find the corresponding register based on the Temporary PPN.

[0121] For example, an ASID (Address Space ID) is a virtual address, and may also be referred to as a virtual address ID.

[0122] VPN is a virtual page number, which is used to indicate the virtual page corresponding to the temporary page.

[0123] Used can be called usage information, which indicates whether the temporary page is available, or whether the temporary page can be allocated. In the embodiment of the present application, the allocable flag is "0" and the non-allocable flag is "1". It can be set according to actual needs and is not limited in this application.

[0124] Flush to PPN (Flush Physical Page Number) can be called physical memory page allocation information, which is used to indicate the physical page allocated for the temporary page. During the third part of the deferred processing phase, the system writes back (or writes) the data in the cache space corresponding to the temporary page to the memory corresponding to the physical page identified by Flush to PPN.

[0125] In one possible implementation, if it is a multi-core CPU, the TPMR of the temporary pages needs to be uniformly managed by all CPUs to avoid VPNs of the same process being assigned to different temporary pages.

[0126] In another possible implementation, other modules or units (such as an OS) may access the TPMR, where access includes reading or modifying.

[0127] In another possible implementation, the information not filled in the register can be empty or a meaningless value, which can be set according to actual needs and is not limited by this application. In the embodiment of this application, the filled data is taken as an example for explanation. For example, as shown in Table 2, in the current scenario, the ASID, VPN and Flush to PPN of each temporary page are all empty, and Used is all 0.

[0128] In an embodiment of the present application, the MMU can traverse the TPMR corresponding to each temporary page and select a temporary page from the available (i.e., the Used mark is "0") temporary pages and assign it to the virtual page. The order of MMU traversal can be set according to actual needs and is not limited by this application. Accordingly, the MMU updates the TPMR of the temporary page and updates the PTE (including page table and TLB) corresponding to the virtual page. The specific update method will be illustrated below.

[0129] S803: Perform a corresponding access operation on the cache space corresponding to the temporary page.

[0130] Exemplarily, the CPU re-executes the access instruction. The MMU, in response to the access instruction, traverses the TLB based on the virtual address. Since the MMU allocated a corresponding temporary page for the virtual page and updated the page table in S802, the MMU can accordingly find the corresponding temporary page in the TLB based on the virtual address.

[0131] The MMU can perform address translation on the virtual address to obtain a temporary address. The hardware can access the cache space corresponding to the temporary address. For example, the correspondence between the virtual address and the temporary address is similar to the mapping relationship between the virtual address and the physical address (i.e., the physical address corresponding to the physical page). Please refer to the relevant content in Figure 1 above and will not be repeated here. The processor can access the cache space corresponding to the temporary physical page.

[0132] Specifically, the cache space corresponding to a temporary page is allocated by the cache (e.g., a cache controller) for the temporary page. The cache allocates the corresponding cache space for the temporary page. For example, when writing data, the cache allocates the corresponding cache space for the temporary page, and the cache controller writes the data to the cache.

[0133] In an embodiment of the present application, the cache can allocate corresponding cache space, i.e., a cache line, for a temporary page. Optionally, a 4KB temporary page can correspond to 64 cache lines. Accordingly, the hardware can find the corresponding cache line based on the temporary address.

[0134] In one possible implementation, if the amount of data being written does not occupy all temporary pages, then when writing to the cache, only the number of cache lines corresponding to the amount of data is occupied. For example, assuming that the written data can occupy 4 cache lines, the cache space only includes the first 4 cache lines, and the addresses corresponding to the pages where the data is not written do not occupy cache space. In the embodiment of the present application, the address in the cache is called a cache line, and the address no longer in the cache is called XX address. For a detailed description, please refer to Figure 13.

[0135] As mentioned above, the cache sets a caching mechanism, and data that has not been accessed within a certain period of time will be cleared. In an embodiment of the present application, in order to ensure that the data in the cache corresponding to the temporary page is not cleared before the data is written back (that is, written back from the cache to the memory corresponding to the physical page), the processor in the embodiment of the present application sets a Do Not Evict (DNE) mark for each Cache Line, which can also be called a retention mark, which is used to indicate that the data in the Cache line cannot be removed. In other words, if the DNE mark is "retained", after the data in the Cache line reaches a certain length of time, the CPU will still retain the cached data based on the mark. In an embodiment of the present application, the DNE mark "1" indicates "retained", and the DNE mark "0" indicates "not retained", which can be set according to actual needs and is not limited by this application. Table 3 is an exemplary structure of the Cache Line:

[0136] Table 3

[0137] Please refer to Table 3. Tag is an index. In this embodiment of the present application, the index can be a temporary address or a physical address. The cache controller can search for the corresponding cache line based on the index. If an index address can find multiple cache lines, these multiple cache lines are called a set.

[0138] The Data part is used to store data, which can also be called cache data.

[0139] The Valid flag (also referred to as V) is used to identify whether the data in the Cache Line is valid data. In an embodiment of the present application, a Valid flag of "1" indicates valid data, and a Valid flag of "0" indicates invalid data. Optionally, if the Valid flag is "0", that is, invalid data, the cache controller can reclaim the Cache Line, that is, clear the data in the Cache Line, or overwrite it with new data. In an embodiment of the present application, if the DNE flag is "1", that is, it indicates retention, and the Valid flag is "0", that is, invalid data, the cache controller also reclaims the Cache Line. That is, after the hardware writes the data in the Cache Line corresponding to the temporary page back to the memory, the operating system updates the Valid of the Cache Line to "0", and the DNE of the Cache Line can remain at "1" or be updated to "0" (that is, not retained), and the cache controller will reclaim the Cache Line.

[0140] For example, program access may include but is not limited to: writing a page (or writing data) and reading a page (or reading data). The following describes the scenarios of writing data and reading data respectively:

[0141] 1) Write the scene

[0142] FIG10 is a schematic diagram of an exemplary data writing process. Please refer to FIG10 , which specifically includes but is not limited to the following steps:

[0143] S1001, query TLB.

[0144] Exemplarily, the processor executes a write instruction of the program, where the write instruction is used to instruct the execution of a write operation. The write instruction includes but is not limited to: a virtual address and data.

[0145] Exemplarily, the MMU traverses the page table cached in the TLB based on the virtual address.

[0146] In one example, if the TLB hits (Hit), that is, the page table of the TLB includes a page table entry of the virtual address, S1011 is executed.

[0147] In another example, if the TLB misses, that is, the page table of the TLB does not include the page table entry of the virtual address, S1002 is executed.

[0148] S1002, traverse the page table.

[0149] Exemplarily, the MMU further traverses the page table based on the virtual address and searches for a page table entry corresponding to the virtual address.

[0150] S1003, query PTE Present.

[0151] In the embodiment of the present application, each virtual page allocated by the OS corresponds to an AAV. Optionally, if the queried virtual address is not in the page table, that is, no corresponding AAV is found, the MMU may determine that the virtual address accessed by the program is an "invalid" (also known as non-compliant) virtual address, and the MMU will feedback a virtual address exception indication to the program.

[0152] As mentioned above, in the prior art embodiment, the MMU will execute the Page Fault process when the page table misses (including the case where the virtual address does not exist or the physical page is not allocated). The program is interrupted, and the execution context is switched from user mode to kernel mode. When the OS executes the Page Fault process, it performs a compliance (or invalidity) check on the virtual page to determine whether the virtual address is invalid. In the embodiment of the present application, the MMU can determine whether the corresponding virtual address is invalid based on the AAV in the register corresponding to the page table, without the need for the OS to execute a page fault exception interrupt, and can timely feedback the exception while reducing the complexity of system processing.

[0153] When the MMU determines that the virtual address is valid, the MMU queries the Present of the PTE, as shown in Table 1.

[0154] In one example, if Present is "0" (or empty, or other meaningless values), it is used to indicate that the virtual page is not mapped to the physical page, and the corresponding temporary page is not allocated (in the embodiment of the present application, Present will be updated to 1 after the temporary page is allocated, and the specific implementation can be referred to below), and S1004 is executed. Optionally, in the embodiment of the present application, "mapping" refers to a stable mapping relationship, such as between a virtual page and a physical page, or between a physical page and a memory. "Correspondence" in the embodiment of the present application refers to a certain correspondence, but the correspondence is not stable and will be released when needed, for example, the correspondence between the virtual page and the temporary page, and the correspondence between the temporary page and the cache. The correspondence between the virtual page and the temporary page is optionally released after the OS allocates a physical page to the virtual page, and the correspondence between the temporary page and the cache is optionally released after the hardware writes the data in the cache back to the memory, which will not be repeated below.

[0155] In another example, if Present is "1", it indicates that the virtual page has been mapped to the physical page, or the corresponding temporary page has been allocated, that is, the page table hits, the MMU performs address translation on the virtual page, obtains the corresponding physical address or temporary address, and executes S1015.

[0156] S1004, check whether it is writable.

[0157] Exemplarily, the MMU determines whether the virtual page is writable based on Writable in the page table entry.

[0158] In one example, if Writable is “0”, indicating that the virtual page is not writable (or can be understood as read-only), S1021 is executed.

[0159] In another example, if Writable is “1”, indicating that the virtual page is writable, S1005 is executed.

[0160] S1005, query AAV.

[0161] Exemplarily, the MMU determines whether the virtual page can be allocated a temporary page based on the AAV of the page table entry.

[0162] In one example, if AAV is "1", it indicates that the virtual page can be allocated a temporary page, and S1006 is executed.

[0163] In another example, if AAV is “0” (or empty, or other meaningless values), it indicates that the virtual page cannot be allocated as a temporary page, and S1021 is executed.

[0164] S1006: Determine whether there is an available temporary page.

[0165] Exemplarily, when the MMU determines that a temporary page can be allocated for a virtual page, it detects whether the temporary page is available. As described above, the computer device includes a TPMR corresponding to each temporary page, and the TPMR includes a Used flag to indicate whether the temporary page is available. The MMU can traverse the TPMRs of each temporary page to determine whether there is a temporary page with a Used flag of "0". The Used flag of "0" indicates that the temporary page is available.

[0166] In an example, if there is no available temporary page, for example, all existing temporary pages have been allocated to corresponding virtual pages, that is, the Used flags of all temporary pages are “1”, S1021 is executed.

[0167] In another example, if there is an available temporary page, S1007 is executed.

[0168] S1007, allocating temporary pages.

[0169] Exemplarily, the MMU determines that there are available temporary pages and selects one of the available temporary pages to allocate to the virtual page. Optionally, the temporary page selection can be random, or the first temporary page with a Used flag of "0" can be selected in the traversal order. This can be set according to actual needs and is not limited in this application.

[0170] Exemplarily, after the MMU allocates a temporary page to a virtual page, it updates the TPMR corresponding to the temporary page. As shown in Table 2, the MMU updates the ASID, VPN, and Used of the TPMR of the temporary page (i.e., the temporary page allocated to the virtual page). The ASID and VPN are updated based on the virtual address, and Used is updated to "1" to indicate that the temporary page is unavailable (which can also be understood as being occupied, invalid, etc., which is not limited in this application). The specific update method will be illustrated in the following embodiments.

[0171] S1008, update the PPN in the PTE, clear the AAV, and set Writable to "1".

[0172] Exemplarily, after the MMU allocates a temporary page to the virtual page, it updates the PTE corresponding to the virtual page in the page table. Specifically, referring to Table 1, the MMU updates the PPN in the PTE of the virtual page to the PPN of the temporary page (which may be referred to as the temporary page number in the embodiment of the present application). The MMU updates Present to "1" to indicate that the virtual page has been allocated a memory page. In this example, the allocated memory page is the temporary page. In addition, the MMU sets Writable to "1" to indicate that the virtual page is a writable page. Among them, the value of Writable may originally be "1", and there is no need to update Writable in this example. In addition, the MMU clears the value in AAV. Optionally, the MMU can also set AAV to "0" to indicate that the virtual page cannot be allocated a temporary page. That is to say, after the virtual page has been allocated a temporary page, no temporary page will be allocated for the virtual page.

[0173] S1009, insert TLB.

[0174] Exemplarily, the MMU inserts a new PTE into the TLB. The memory page indicated by the PPN in the new PTE can be a physical page or a temporary page. For example, after executing S1022, S1009 is executed, where the page indicated by the PPN in the page table entry inserted into the TLB is a physical page. After executing S1008, S1009 is executed, where the page indicated by the PPN in the page table entry inserted into the TLB is a temporary page.

[0175] S1010: The processor re-executes the write instruction.

[0176] In this example, the process in Figure 10 proceeds to S1001. Since the MMU has already allocated a temporary page for the virtual page, the MMU queries the TLB and determines a TLB hit. The MMU then performs address translation on the virtual address based on the PPN in the TLB (which may be the page number of the temporary page or the page number of the physical page), obtains a physical address, and continues to execute S1011. It should be noted that the MMU considers the translated address to be a physical address. In fact, it can be a physical address corresponding to a physical page or a temporary address corresponding to a temporary page.

[0177] S1011, check whether it is writable.

[0178] In the case of a TLB hit, the MMU queries whether the virtual page is writable based on the page table entry. This process can be referred to the relevant description of S1004 and will not be repeated here.

[0179] In one example, if the virtual page is writable, step S1012 is executed.

[0180] In another example, if the virtual page is not writable, execute S1016.

[0181] S1012: Whether the PPN is a temporary page.

[0182] In an embodiment of the present application, the processor may configure a physical page list and a temporary page list (which may also be in other forms, which are not limited by the present application). The temporary page list is used to record information such as the page number and temporary address of the temporary page. If the temporary page is removed, the temporary page in the list can be deleted. The physical page list is similar and will not be repeated here.

[0183] In a possible implementation, if the processor in the computer device is a single-core processor, the cache controller may determine whether the memory page corresponding to the virtual page is a temporary page by accessing the temporary page list.

[0184] In another possible implementation, if the processor of the computer device is a multi-core processor, and the multiple processors correspond to multiple caches, the computer device includes a cache agent that accesses a temporary page list maintained (or stored) by the processor to determine whether the page indicated by the physical address converted by the MMU is a temporary page.

[0185] In one example, if the page is a temporary page, execute S1013.

[0186] In another example, if the page is a physical page, execute S1014.

[0187] S1013: Data is written into the cache corresponding to the temporary page, and the DNE flag of the cache line is 1.

[0188] Exemplarily, the cache controller allocates corresponding cache space for the temporary page and writes the data into the cache space. Specifically, the cache controller allocates the corresponding cache line based on the temporary address (i.e., the physical address converted by the MMU as described above) and writes the data into the data portion of the cache line. The cache line structure can be seen in Table 3.

[0189] Optionally, as described above, a 4K temporary page may correspond to 64 cache lines. Only cache lines with written data are stored in the cache. The cache line without written data is called the XX address, which may be called the nth 64B in the embodiment of the present application.

[0190] Exemplarily, the cache agent described above can also be used to maintain (or store) the correspondence between physical pages or temporary pages and caches. For example, the cache agent is provided with a cache correspondence table (taking a list as an example only, it can be in other forms, and this application does not limit it), and the correspondence table includes the correspondence between each cache line in the cache and the physical address (including the physical address of the physical page and the temporary address of the temporary page), as well as a table for recording the cache to which the cache line belongs. The cache controller can retrieve the cache correspondence table based on the physical address to query whether the physical address corresponds to a cache line and to which cache the corresponding cache line belongs.

[0191] In the embodiment of the present application, after the cache controller allocates cache for the temporary page, the cache agent updates the cache correspondence table to save the correspondence between the temporary address and the cache line.

[0192] S1014, data is written into the cache or memory.

[0193] Exemplarily, if the page to be written is a physical page, the hardware writes the data into the cache or the memory corresponding to the physical page. Optionally, as described above, if the data is written into the cache, under certain conditions (the hardware condition setting can be set according to actual needs), the hardware writes the data into the memory corresponding to the physical page. It should be noted that although the data of the physical page can be written into the cache first and then into the memory, it is different from the temporary page in that the physical page will be interrupted by the OS during the Page Faulte process. After the interruption, that is, after the physical page is allocated, the data can be written into the cache allocated by the cache for the physical page.

[0194] Similarly, in a multi-core scenario, if data is written to the cache, the cache agent updates the cache correspondence table to save the correspondence between the physical address and the cache line.

[0195] S1015, check whether it is writable.

[0196] For example, when the page table hits, the MMU queries whether the virtual page is writable. Specific implementation methods can refer to the relevant content of S1004 and will not be repeated here.

[0197] In one example, if the virtual page is writable, S1009 is executed.

[0198] In another example, if the virtual page is not writable, execute S1016.

[0199] S1016, query AAV.

[0200] For example, when a virtual page corresponds to a memory page and the virtual page is a non-pageable page (i.e., a read-only page), in an embodiment of the present application, a writable temporary page will be allocated to the virtual page to write data into the cache space corresponding to the temporary page without the need for an OS interrupt (OS interruption allows the OS to allocate a physical page to the virtual page).

[0201] The implementation method of this step can refer to S1005 and will not be repeated here.

[0202] In one example, if the AAV identifier is "1", S1021 is executed.

[0203] In another example, if the AAV identifier is "0", S1017 is executed.

[0204] S1017, determine whether there is an available temporary page.

[0205] For the specific implementation method, please refer to the relevant content of S1006, which will not be repeated here.

[0206] S1018, allocate temporary pages.

[0207] For the specific implementation method, please refer to the relevant content of S1007, which will not be repeated here.

[0208] S1019, flush TLB.

[0209] For example, in this example, there is a page table entry for a virtual page in the TLB. After the MMU reallocates a memory page (i.e., a temporary page) for the virtual page, the MMU removes the page table entry corresponding to the virtual page in the TLB. A new page table entry will be reinserted when executing S1009.

[0210] S1020, copy the non-zero data of the old page.

[0211] In some examples, non-zero data may exist in the memory page (which may be a physical page or a temporary page) previously corresponding to the virtual page. The non-zero data of the physical page may be in the cache or in the memory. The non-zero data of the temporary page is in the cache. Accordingly, the cache controller can copy the non-zero data from the cache, or the memory controller can copy the non-zero data from the memory. It can be understood that this step is to copy the non-zero data in the old memory page to migrate the data to the cache space corresponding to the new temporary page.

[0212] S1021, normal Page Fault.

[0213] For example, in an embodiment of the present application, if a virtual page has not been allocated a memory page, and the virtual page is not writable; or, a virtual page has not been allocated a memory page, the virtual page is writable, but allocation of a temporary page is not allowed (i.e., the AAV identifier is "0"); or, a virtual page has been allocated a memory page, the virtual page is not writable, and allocation of a temporary page is not allowed (i.e., AAV is 0); or, a temporary page needs to be allocated for the virtual page, but the temporary space is insufficient (i.e., all temporary pages are unavailable), in any of the above cases, a normal Page Fault process is executed, i.e., the MMU outputs an interrupt instruction to the OS. The execution context is switched from user mode to kernel mode, and the OS allocates physical pages to the virtual page. The relevant process can be referred to the description in Figure 4, which will not be repeated here.

[0214] S1022, update PTE.

[0215] Exemplarily, the OS updates the PTE based on the physical page allocated to the virtual page. Specifically, the OS updates the PPN of the virtual page to the PPN of the physical page.

[0216] 2) Read data

[0217] FIG11 is a schematic diagram of an exemplary data reading process. Please refer to FIG11 , which specifically includes but is not limited to the following steps:

[0218] S1101, query TLB.

[0219] Exemplarily, the processor executes a read instruction of the program, where the read instruction is used to instruct to perform a read operation. The read instruction includes but is not limited to: a virtual address.

[0220] Exemplarily, the MMU traverses the page table cached in the TLB based on the virtual address.

[0221] In one example, if the TLB hits (Hit), that is, the page table of the TLB includes a page table entry of the virtual address, S1111 is executed.

[0222] In another example, if the TLB misses, that is, the page table of the TLB does not include the page table entry of the virtual address, S1102 is executed.

[0223] S1102, traverse the page table.

[0224] Exemplarily, the MMU further traverses the page table based on the virtual address and searches for a page table entry corresponding to the virtual address.

[0225] S1103, query PTE Present.

[0226] In the embodiment of the present application, each virtual page allocated by the OS corresponds to an AAV. Optionally, if the queried virtual address is not in the page table, that is, no corresponding AAV is found, the MMU may determine that the virtual address accessed by the program is an "invalid" (also known as non-compliant) virtual address, and the MMU will feedback a virtual address exception indication to the program.

[0227] As mentioned above, in the prior art embodiment, the MMU will execute the Page Fault process when the page table misses (including the case where the virtual address does not exist or the physical page is not allocated). The program is interrupted, and the execution context is switched from user mode to kernel mode. When the OS executes the Page Fault process, it performs a compliance (or invalidity) check on the virtual page to determine whether the virtual address is invalid. In the embodiment of the present application, the MMU can determine whether the corresponding virtual address is invalid based on the AAV in the register corresponding to the page table, without the need for the OS to execute a page fault exception interrupt, and can timely feedback the exception while reducing the complexity of system processing.

[0228] When the MMU determines that the virtual address is valid, the MMU queries the Present of the PTE, as shown in Table 1.

[0229] In one example, if Present is "0" (or empty, or other meaningless values), it is used to indicate that the virtual page is not mapped to the physical page and the corresponding temporary page is not allocated (in the embodiment of the present application, Present will be updated to 1 after the temporary page is allocated, and the specific implementation can be referred to below), and S1104 is executed.

[0230] In another example, if Present is "1", it indicates that the virtual page has been mapped to the physical page, or the corresponding temporary page has been allocated, that is, the page table hits, the MMU performs address translation on the virtual page, obtains the corresponding physical address or temporary address, and executes S1105.

[0231] S1104, query AAV.

[0232] Exemplarily, in this example, AAV can also be used to indicate whether a specified physical page can be allocated. In the embodiment of the present application, the specified physical page is a zero page, that is, a physical page with all 0 data. In other embodiments, it can also be other specified physical pages, such as a page with all 1 data, which is not limited in this application.

[0233] The MMU determines whether the virtual page can be allocated to the specified physical page based on the AAV of the page table entry.

[0234] In one example, if AAV is "1", indicating that the virtual page can be allocated to a specified physical page, S1106 is executed.

[0235] In another example, if AAV is “0” (or empty, or other meaningless values), it indicates that the virtual page cannot be allocated to the specified physical page, and S1107 is executed.

[0236] S1105, insert TLB.

[0237] Exemplarily, the MMU inserts a new PTE into the TLB. The memory page indicated by the PPN in the new PTE may be a physical page or a temporary page. For example, after executing S1107, executing S1105, the page indicated by the PPN in the page table entry inserted into the TLB is a physical page. After executing S1108, executing S1105, the page indicated by the PPN in the page table entry inserted into the TLB is a temporary page. After executing S1103 and then executing S1105, the page indicated by the PPN in the page table entry inserted into the TLB may be a temporary page or a physical page.

[0238] S1106, check whether it is writable.

[0239] Exemplarily, the MMU determines whether the virtual page is writable based on Writable in the page table entry.

[0240] In one example, if Writable is “0”, indicating that the virtual page is not writable (or can be understood as read-only), S1109 is executed.

[0241] In another example, if Writable is “1”, indicating that the virtual page is writable, S1108 is executed.

[0242] S1107, normal Page Fault.

[0243] The normal Page Fault process can be referred to Figure 4 and will not be described in detail here. After the Page Fault process is executed, ie after the OS allocates the corresponding physical page for the virtual page, the OS updates the page table and executes S1105, ie inserting the new PTE into the TLB.

[0244] S1108, allocate zero page, update PTE, and set Writable to "0".

[0245] The processor is pre-configured with a zero page, which is a physical page containing all zeros.

[0246] In an embodiment of the present application, in a read scenario, if a memory page needs to be allocated for a virtual page, the memory page allocated by the MMU for the virtual page is a designated page. In the embodiment of the present application, the designated page is described as a zero page, i.e., the data in the page is all 0s. In other embodiments, other designated pages may be used, for example, the data in the page may be all 1s, and this application does not limit this.

[0247] In the embodiment of the present application, if there are other programs executing the read process in FIG. 11 , the MMU will allocate a zero page to them when executing S1008 .

[0248] S1109, clear AAV.

[0249] Exemplarily, the MMU clears the AAV corresponding to the virtual page, for example, setting the AAV to "0" or clearing it to indicate that the virtual page cannot be allocated a temporary page or a specified physical page. In other words, if the virtual address is accessed again, the AAV identifier of the virtual address is "0".

[0250] S1110, the processor re-executes the read instruction.

[0251] In this example, the process in Figure 11 proceeds to S1101. Since the MMU has allocated a zero page for the virtual page, the MMU queries the TLB and determines that the TLB hits. The MMU performs address translation on the virtual address to obtain a physical address or a temporary address, and executes S1111.

[0252] S1111, determine whether the PPN is a temporary page.

[0253] For example, the specific description can refer to the relevant description of S1012, which will not be repeated here.

[0254] S1112, obtain data from the cache or memory.

[0255] Exemplarily, in a single-core processor scenario, the cache controller parses the physical address and searches for the corresponding Cache Line. For example, the cache controller takes the middle 8 bits of the physical address (e.g., bits [5,12]) to find which Cache Line group the physical address belongs to. Optionally, the cache can include 256 groups. After the group is determined, the cache controller compares the bits [13,31] in the physical address with the 256 Cache Lines in the group. If the bits [13,31] are consistent with the Tag field in the Cache Line, and the Valid field of the Cache Line is marked as "1", indicating that the Cache Line is valid, a cache hit is determined. The cache controller reads data from the hit Cache Line. If the cache misses, the memory controller can obtain the corresponding data in the memory based on the physical page address.

[0256] In another example, in a multi-core processor scenario, the cache agent can traverse the cache correspondence table based on the physical address to determine whether the physical address corresponds to a cache line and the cache to which the cache line belongs. If the query finds that the physical address corresponds to a cache line and locates the corresponding cache, the cache controller can search for the corresponding cache line based on the physical address and obtain the data from the corresponding cache. The search method can refer to the single-core scenario and will not be repeated here. If the query finds that the physical address does not correspond to a cache line, the memory controller can obtain the corresponding data in the memory based on the physical page address.

[0257] S1113, query cache.

[0258] In one example, in a single-core processor scenario, the cache controller parses the physical address and searches for the corresponding Cache Line. For example, the cache controller takes the middle 8 bits of the physical address (e.g., bits [5,12]) to find which Cache Line group the physical address belongs to. Optionally, the cache can include 256 groups. After the group is determined, the cache controller compares the bits [13,31] in the physical address with the 256 Cache Lines in the group. If the bits [13,31] are consistent with the Tag field in the Cache Line, and the Valid field of the Cache Line is marked as "1", indicating that the Cache Line is valid, a cache hit is determined and S1115 is executed. If the cache misses, S1114 is executed.

[0259] In another example, in a multi-core processor scenario, the cache agent can traverse the cache correspondence table based on the physical address to determine whether the physical address corresponds to a cache line and the cache to which the cache line belongs. If the physical address is found to correspond to a cache line and the corresponding cache is located, then S1115 is executed. The search method can be referred to in the single-core scenario and will not be further described here. If the physical address is found to not correspond to a cache line, then S1114 is executed.

[0260] For situations where the cache may miss, as described above, only cache lines with non-zero data will be cached in the cache. Accordingly, in some instances, if the data in the cache line corresponding to the temporary page is all 0, there will be no cache line data corresponding to the temporary page in the cache.

[0261] S1114, feedback all 0 data.

[0262] Exemplarily, if there is no data corresponding to the temporary page in the cache, the cache controller feeds back all-0 data.

[0263] S1115, obtain data from the cache.

[0264] For example, as shown in the process of Figure 10, data from the temporary page is written to one or more cache lines corresponding to the temporary page. The cache controller can retrieve the data from the corresponding cache line based on the temporary address. The specific retrieval method can be referred to in S1112 and will not be repeated here.

[0265] 3. Delayed processing

[0266] FIG12 is a schematic diagram of an exemplary delay processing flow. Referring to FIG12 , the process specifically includes but is not limited to the following steps:

[0267] S1201: Detecting that a preset condition is met.

[0268] Exemplarily, the processor sets a preset condition, which is used to indicate the execution of the delay processing flow. In an embodiment of the present application, the preset condition includes but is not limited to at least one of the following: the CPU load is less than a first threshold (which can also be understood as the CPU being idle), the number of available temporary pages is less than a second threshold, and the timer expires (which can also be understood as being set with an execution cycle).

[0269] The processor executes the delay processing flow when it detects that a preset condition is met. In an embodiment of the present application, by using preset conditions, the computer device can execute an OS interrupt to execute the delay processing flow when the preset conditions are met. In this way, when a program is accessed, the program can be not interrupted. Instead, under conditions such as CPU idleness, the page fault exceptions of one or more virtual pages can be uniformly processed, that is, physical page allocation and data writing are performed according to the PF processing logic in the existing embodiment.

[0270] S1202, searching for used temporary pages.

[0271] For example, when the processor detects that a preset condition is met, it sends an interrupt to the OS, interrupting all programs currently running on the processor (which may be background programs, or of course, no programs are running). The OS traverses the TPMR of each temporary page and finds a used temporary page, that is, a temporary page with Used set to "0".

[0272] S1203: Allocate physical pages.

[0273] Exemplarily, the OS allocates physical pages for the used temporary pages. The specific allocation method is similar to the Page Fault process and will not be described in detail here.

[0274] The OS updates the Flush to PPN in the TPMR of the temporary page and updates the parameter to the PPN of the physical page.

[0275] Optionally, as described above, the processor maintains (or stores) a temporary page list, and the processor may also maintain (or store) a physical page list, which may include tracking information to indicate the usage of the physical page. If the physical page is used frequently, the count value in the tracking information is large, and the physical page will be counted each time it is used. If the technical value in the tracking information is less than a preset threshold (which can be set according to actual needs and is not limited in this application), that is, the physical page is accessed less times, the memory controller may migrate the data in the memory of the physical page to auxiliary storage such as a hard disk.

[0276] S1204, write the data in the cache into the memory of the physical page.

[0277] Exemplarily, the OS updates the Used field in the TPMR of the temporary page to which the physical page has been allocated to “0” to indicate that the temporary page is available.

[0278] When the processor detects that the Used flag of any temporary page changes from "1" to "0", the CPU controls the cache controller to extract the data in the cache space corresponding to the temporary page, and the memory controller can write the data to the memory of the corresponding physical page based on the Flush to PPN in the TPMR of the temporary page. In the embodiment of the present application, there is a certain delay between the time when the OS updates the Used flag in the TPMR to "0" and the time when the data is migrated to the memory of the physical page. During this delay, since the current execution context is kernel mode, all programs are in an interrupted state when executing in kernel mode, and no new user mode access instructions will be executed, and the allocation of temporary pages will not be executed. Therefore, the data of the temporary page whose Used flag is updated to "0" will not be allocated to other virtual pages before it is successfully written back.

[0279] S1205, update PTE.

[0280] Exemplarily, the OS updates the page table, or the page table and the PTE of the virtual page in the TLB, and updates the PPN in the PTE of the temporary page corresponding to the written-back temporary page to the PPN of the physical page allocated in S1203.

[0281] The schemes in FIG. 10 , FIG. 11 and FIG. 12 are described in detail below with reference to specific examples.

[0282] Scenario 1:

[0283] In this scenario, we'll use the example of a program writing to and then reading from a virtual page. For example, let's assume the program's ASDI is 0x2. In this scenario, the program requires 2KB of memory. Following the process in Figure 8, the OS allocates a virtual page with a base address (i.e., VPN) of 0x1000. The OS configures the PTE for this virtual page, as shown in Table 4:

[0284] Table 4

[0285] Please refer to Table 4, where the Present flag of virtual address 0x1000 is "0" (in hexadecimal not repeated below), indicating that the virtual page has not been allocated a memory page. The Writable flag is "1", indicating that the virtual page is writable. The AAV flag is "1", indicating that a temporary page can be allocated.

[0286] 10 , the processor executes a program's write instruction to write to a virtual page. The write instruction includes, but is not limited to, the virtual address 0x1000(xxx) and data. The offset is in brackets.

[0287] The step proceeds to S1001, where the MMU queries the TLB based on VPN (0x1000). In this example, the MMU does not find the corresponding page table entry, which is a TLB Miss.

[0288] The step proceeds to S1002, where the MMU further queries the page table based on the VPN and reads the corresponding PTE, such as Table 4.

[0289] The step proceeds to S1003, where the MMU queries the Present flag. In this example, the MMU queries that the Present flag is "0", indicating that the virtual page has not been allocated a memory page.

[0290] The step proceeds to S1004 , where the MMU queries whether the virtual page is writable. In this example, the MMU queries and finds that the Writable flag in the PTE is “1”, indicating that the virtual page is writable.

[0291] The step proceeds to S1005 , where the MMU queries the AAV. In this example, the MMU queries that the AAV flag is “1”, indicating that the virtual page can be allocated to a temporary page.

[0292] The step proceeds to S1006, and the MMU queries whether there is an available temporary page, as shown in Table 5:

[0293] Table 5

[0294] Referring to Table 5, the MMU traverses each TPMR and finds that there is a temporary page with a Used flag of "0", thereby determining that there is an available temporary page.

[0295] The step proceeds to S1007, where the MMU allocates a temporary page. In this example, the MMU allocates temporary page 0x8000 to virtual page 0x1000. The MMU updates the TPMR of temporary page 0x8000, as shown in Table 6:

[0296] Table 6

[0297] As shown in Table 6, the MMU updates the TPMR for temporary page 0x8000, setting the ASID to "0x2." It also sets the VPN to "0x1000" to indicate that temporary page 0x8000 is allocated to page 0x1000. The MMU also sets the Used bit to "1" to indicate that temporary page 0x8000 is unavailable.

[0298] The step proceeds to S1008, where the MMU updates the PPN in the PTE, clears the AAV, and sets the Writable bit to 1. In this example, the updated PTE is shown in Table 7:

[0299] Table 7

[0300] As shown in Table 7, the MMU updates the PPN to the page number corresponding to the temporary page, which is 0x8000. The MMU also updates the Present flag to "1" to indicate that the corresponding memory page has been allocated for virtual page 0x1000. The MMU also updates the AAV flag to "0" to indicate that the virtual page cannot be allocated as a temporary page. If the Writable flag is "1," no update is required.

[0301] The step proceeds to S1009 , where the MMU inserts the PTE in Table 6 into the TLB. In this example, the MMU inserts the PTE in Table 6 into the TLB.

[0302] The step proceeds to S1010, and the processor re-executes the write instruction.

[0303] The process proceeds to S1001, where the MMU queries the TLB. In this example, the MMU traverses the TLB based on the virtual page VPN: 0x1000. As shown in Table 7, the MMU finds the corresponding page table entry. Based on the PPN, the MMU performs address translation on the virtual address 0x1000(xxx), obtaining the corresponding temporary address 0x8000(xxx). The translation method is described in Figure 3 and will not be further described here.

[0304] The step proceeds to S1011 , where the MMU queries whether the virtual page is writable. As shown in Table 7, in this example, the MMU queries the Writable flag in the PTE to be "1," indicating that the virtual page is writable.

[0305] The process proceeds to S1012, where the cache controller module queries whether the PPN is a temporary page. As described above, the processor is configured with a temporary page list, which includes information such as the VPNs of all temporary pages. For example, in a single-core CPU, the cache controller can traverse the temporary page list based on the PPN (0x8000) in the PTE to query whether the memory page is a temporary page. In this example, the cache proxy module determines that the memory page indicated by the PPN is a temporary page.

[0306] The step proceeds to S1013, and the cache controller writes the data into the cache space corresponding to the temporary page. Specifically, the cache controller allocates a Cache Line to the temporary page based on the temporary address converted by the MMU. The cache controller writes the non-zero data into the corresponding Cache Line. For example, as shown in Figure 13, each temporary address corresponds to a 64B space, and the temporary page 0x8000 corresponds to n 64B. Among them, the data written to the temporary page 0x8000 occupies the 1st 64B to the 3rd 64B, that is, it occupies Cache Line 1 to Chache Line 3 (Cache Line can be continuous or discontinuous, and this application does not limit it). Accordingly, Cache Line 1 to Chache Line 3 are in the cache, and other temporary addresses (for example, the 4th 64B to the 64th 64B) are not in the cache. Cache Line is shown in Table 8:

[0307] Table 8

[0308] Please refer to Table 7. The cache controller sets the Valid flag to "1" to indicate that the data in the cache line is valid data. The cache controller sets the DNE flag to "1" to indicate that the data in the cache line is retained. For example, when the cache controller queries that the data in multiple cache lines (including the cache lines in Table 7) has not been accessed for a long time, the cache controller clears the cache lines with the DNE flag set to "0" and / or the Valid flag set to "0" (used to indicate that the cache line is invalid). The cache lines with the DNE flag set to "1" and the Valid flag set to "1" are retained.

[0309] In this example, it is assumed that the processor executes a read instruction of a program to perform a read operation on a virtual page. The read instruction includes but is not limited to a virtual address.

[0310] Referring to Figure 11 , the process proceeds to S1101 , where the MMU queries the TLB. In this example, in a write scenario, the TLB has already been updated. Accordingly, the MMU traverses the TLB (as shown in Table 7) based on the virtual address 0x1000(xxx) and finds the corresponding page table entry. The MMU performs address translation based on the PPN (0x8000) in the PTE, obtaining a temporary address (which the MMU considers to be a physical address).

[0311] The step proceeds to S1111, where the cache controller determines whether the PPN is a temporary page. In this example, taking a single-core CPU as an example, the cache controller can determine that the page at physical address 0x8000(xxx) is a temporary page based on the temporary page list.

[0312] The process proceeds to S1113, where the cache controller queries the cache based on the temporary address. In the above embodiment, data is written to the portion of the cache line corresponding to the temporary page. Accordingly, in this step, taking a single-core CPU as an example, the cache controller can search the cache for the corresponding cache line based on the temporary address.

[0313] The step proceeds to S1115 , where the cache controller obtains data from at least one cache line corresponding to the temporary page (0x8000).

[0314] The following is an example of the delay processing process in Figure 12 based on the scenario in the above embodiment. Referring to Figure 12, the step proceeds to S1201. In this scenario, the processor detects that a preset condition is met, for example, the CPU load is less than a first threshold. The processor sends an interrupt to the OS to instruct the OS to execute the delay processing process. All programs running on the processor (which can include user programs or background programs (i.e., programs that the user does not perceive)) are interrupted, and the execution context is switched from user mode to kernel mode.

[0315] The step proceeds to S1202 , where the OS searches for used temporary pages. Specifically, the OS traverses the TPMRs of each temporary page, searching for a temporary page with a Used flag of "0." As shown in Table 6, the OS traverses the TPMRs and finds that the Used flags for temporary page N, temporary page N+1, temporary page N+2, and temporary page 0x8000 are all marked as "0."

[0316] The step proceeds to S1203, and the OS allocates physical pages. Specifically, the OS allocates physical pages to the used temporary pages. In one possible implementation, the OS can traverse all TPMRs, find all used temporary pages, and allocate physical pages for each used temporary page. Then execute S1204. In another possible implementation, the OS can also find a used temporary page, that is, execute S1203 and S1204, and repeat S1202 to S1204 until the traversal is completed (that is, all TPMRs are traversed). For example, in this example, the OS traverses to the Used flag of temporary page 0x8000, which is "0", and determines that temporary page 0x8000 is used and no physical page is allocated (that is, Flush to PPN is empty). The OS selects a physical page from the available physical pages (the selection method can refer to the existing embodiment and will not be repeated in this application), for example, physical page 0x2000. The OS allocates physical page 0x2000 to temporary page 0x8000.

[0317] For example, the OS updates the TPMR of temporary page 0x8000, as shown in Table 9:

[0318] Table 9

[0319] Referring to Table 9, based on Table 6, the OS updates the Flush to PPN in the TPMR at 0x8000 to the physical page's PPN, which is 0x2000. Furthermore, the OS updates the Used flag to "0" to indicate that the temporary page is available.

[0320] The step proceeds to S1204, and the hardware writes the data in the cache to the memory of the physical page. Specifically, when the processor detects that the Used flag of the temporary page 0x8000 is updated from "1" to "0", it instructs the cache controller to extract the data in the Cache Line corresponding to the temporary page 0x8000. For example, the Data part of the Cache Line in Table 8. The cache controller updates the Valid of the Cache Line and sets the Valid flag to "0" to indicate that the data in the Cache Line is invalid data. Optionally, the cache controller updates the DNE flag to "0" to indicate that the data in the Cache Line is not retained, as shown in Table 10:

[0321] Table 10

[0322] The cache controller may clear the cache line whose valid flag is "0" under certain conditions according to the preset rules of the cache controller.

[0323] After the cache controller extracts the data, the memory controller writes the data to the memory corresponding to 0x2000 based on the Flush to PPN of the TPMR at 0x8000.

[0324] The step proceeds to S1205, where the OS updates the PTE. Specifically, based on Table 7, the OS updates the PTE of virtual page 0x1000. The updated PTE is shown in Table 11:

[0325] Table 11

[0326] Referring to Table 11, the OS updates the PPN to the physical page's PPN, which is 0x2000, indicating that virtual page 0x1000 is mapped to physical page 0x2000. The Present flag is not updated and remains "1," indicating that the memory page has been allocated. The Writable flag is not updated and remains "1," indicating that virtual page 0x1000 is writable. The OS updates the AAV flag to "1," indicating that a temporary page can be allocated for the virtual page.

[0327] Scenario 2:

[0328] In this scenario, we will use the example of a program reading and then writing to a virtual page. For example, let's assume the program's ASDI is 0x3. In this scenario, the program requires 1KB of memory space. Following the process in Figure 8, the OS allocates a virtual page with a base address (i.e., VPN) of 0x2000. The OS configures the PTE for this virtual page, as shown in Table 12:

[0329] Table 12

[0330] Please refer to Table 12, where the Present flag of the virtual address 0x2000 is "0", indicating that the virtual page has not been allocated a memory page. The Writable flag is "1", indicating that the virtual page is writable. The AAV flag is "1", indicating that a temporary page can be allocated.

[0331] 11 , the processor executes a program's read instruction to write to a virtual page. The write instruction includes, but is not limited to, the virtual address 0x1000(xxx) and the data. The offset is in brackets.

[0332] The step proceeds to S1101, where the MMU queries the TLB. The MMU queries the TLB based on VPN (0x2000). In this example, the MMU does not find the corresponding page table entry, which is a TLB Miss.

[0333] The step proceeds to S1102 , where the MMU further queries the page table based on the VPN and reads the corresponding PTE, such as Table 12.

[0334] The step proceeds to S1103 , where the MMU queries the Present flag. In this example, the MMU queries that the Present flag is “0”, indicating that the virtual page has not been allocated a memory page.

[0335] The step proceeds to S1104, where the MMU queries the AAV. In this example, the MMU queries that the AAV flag is "1," indicating that the virtual page can be allocated a temporary page or a designated physical page. In this example, the designated physical page is a zero page, i.e., a physical page with all 0s in its data.

[0336] The step proceeds to S1105 , where the MMU queries whether the virtual page is writable. In this example, the MMU queries and finds that the Writable flag in the PTE is “1”, indicating that the virtual page is writable.

[0337] The step proceeds to S1106, where the MMU allocates page zero, updates the PTE, and sets Writable to "0". Specifically, the MMU allocates page zero for virtual page 0x2000 and updates the PTE. The updated PTE is shown in Table 13:

[0338] Table 13

[0339] As shown in Table 13, the MMU updates the PPN to the zero page PPN, which is 0x0. The MMU also updates the Present flag to "1" to indicate that the memory page has been allocated. The MMU also sets the Writable flag to "0" to indicate that virtual page 0x2000 is not writable and is read-only. The AAV flag remains "1" to indicate that a temporary page can be allocated.

[0340] The step proceeds to S1105 , where the MMU inserts the PTE in Table 13 into the TLB. In this example, the MMU inserts the PTE in Table 13 into the TLB.

[0341] The step proceeds to S1110, and the processor re-executes the read instruction.

[0342] The process proceeds to S1101, where the MMU queries the TLB. In this example, the MMU traverses the TLB based on the VPN of the virtual page 0x2000. As shown in Table 13, the MMU finds the corresponding page table entry. Based on the PPN, the MMU performs address translation on the virtual address 0x2000(xxx), obtaining the corresponding physical address 0x000(xxx). The translation method is described in Figure 3 and will not be further described here.

[0343] The step proceeds to S1111, where the cache controller determines whether the PPN is a temporary page. In this example, the cache controller may determine that the page at the physical address 0x000(xxx) is not a temporary page based on the temporary page list.

[0344] The step proceeds to S1112, where the memory controller obtains data from the memory. Specifically, the memory controller can find the corresponding data (i.e., all 0 data) in the memory based on the physical page address (0x0000(xxx)) and read the data.

[0345] In this example, it is assumed that the processor executes a write instruction of the program to perform a write operation on the virtual page (0x2000). The read instruction includes but is not limited to the virtual address and data.

[0346] Referring to Figure 10 , the process proceeds to S1001 , where the MMU queries the TLB. In this example, in a write scenario, the TLB has already been updated. Accordingly, the MMU searches the TLB (as shown in Table 13) based on the virtual address 0x2000(xxx) and finds the corresponding page table entry. The MMU performs address translation based on the PPN (0x0000) in the PTE to obtain the physical address.

[0347] The step proceeds to S1011, where the MMU queries whether the virtual page is writable. As shown in Table 13, in this example, the MMU queries the Writable flag in the PTE to be "0", indicating that the virtual page is not writable, that is, it is a read-only page.

[0348] The step proceeds to S1016 , where the MMU queries the AAV. In this example, the MMU queries that the AAV flag is “1”, indicating that the virtual page can be allocated to a temporary page.

[0349] The step proceeds to S1017, and the MMU queries whether there is an available temporary page, as shown in Table 14:

[0350] Table 14

[0351] Referring to Table 14, the MMU traverses each TPMR and finds that there is a temporary page with a Used flag of "0", thereby determining that there is an available temporary page.

[0352] The step proceeds to S1018, where the MMU allocates a temporary page. In this example, the MMU allocates temporary page 0x9000 to virtual page 0x2000. The MMU updates the TPMR of temporary page 0x9000, as shown in Table 15:

[0353] Table 15

[0354] As shown in Table 15, the MMU updates the TPMR for temporary page 0x9000, setting the ASID to 0x3. It also sets the VPN to 0x2000 to indicate that temporary page 0x9000 is allocated to page 0x2000. The MMU also sets the Used bit to 1 to indicate that temporary page 0x9000 is unavailable.

[0355] The step proceeds to S1019, where the MMU flushes the TLB. In this example, there is a page table entry for the virtual page (0x2000) in the TLB. After the MMU reallocates a memory page (i.e., a temporary page) for the virtual page (0x2000), the MMU removes the page table entry corresponding to the virtual page (0x2000) in the TLB.

[0356] The step proceeds to S1020. In this example, since the previously allocated physical page is a zero page, its data is all zero data. Accordingly, in this step, the cache controller does not need to copy the data of the old page, and there is no need to execute S1013 again.

[0357] The step proceeds to S1008, where the MMU updates the PPN in the PTE, clears the AAV, and sets the Writable bit to 1. In this example, the updated PTE is shown in Table 16:

[0358] Table 16

[0359] As shown in Table 16, the MMU updates the PPN to the page number corresponding to the temporary page, which is 0x9000. The Prensent flag remains "1," indicating that a corresponding memory page has been allocated to virtual page 0x2000. The MMU updates the AAV flag to "0," indicating that a temporary page cannot be allocated to the virtual page. The MMU sets the Wtritable flag to "1," indicating that virtual page 0x2000 is writable.

[0360] The step proceeds to S1009 , where the MMU inserts the PTE in Table 16 into the TLB. In this example, the MMU inserts the PTE in Table 16 into the TLB.

[0361] The step proceeds to S1010, and the processor re-executes the write instruction.

[0362] The process proceeds to S1001, where the MMU queries the TLB. In this example, the MMU traverses the TLB based on the VPN of the virtual page 0x2000. As shown in Table 16, the MMU finds the corresponding page table entry. Based on the PPN, the MMU performs address translation on the virtual address 0x2000(xxx), obtaining the corresponding temporary address 0x9000(xxx). The translation method is described in Figure 3 and will not be further described here.

[0363] The step proceeds to S1011, where the MMU queries whether the virtual page is writable. As shown in Table 16, in this example, the MMU queries the Writable flag in the PTE to be "1", indicating that the virtual page is writable.

[0364] The step proceeds to S1012, where the cache controller queries whether the PPN is a temporary page. The description can be found above and will not be repeated here.

[0365] The process proceeds to S1013 , where the cache controller writes the data into the cache space corresponding to the temporary page. Specifically, the cache controller allocates a cache line to the temporary page based on the temporary address converted by the MMU. The cache controller writes the non-zero data into the corresponding cache line and sets the cache line's DNE to 1. This description is referenced above and is not repeated here.

[0366] The delay processing process in this scenario can be referred to Scenario 1 and will not be repeated here.

[0367] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the interaction between various network elements. It can be understood that in order to realize the above functions, the access device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software-driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0368] In the embodiments of the present application, the access device can be divided into functional modules according to the above-mentioned method examples. For example, each functional module can be divided into corresponding functional modules, or two or more functions can be integrated into a single processing module. The above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the module division in the embodiments of the present application is illustrative and is only a logical functional division. In actual implementation, other division methods may be used.

[0369] In the case of dividing each functional module according to each function, FIG14 shows a possible structural diagram of the access device 1400 involved in the above embodiment. As shown in FIG14 , the access device may include: an acquisition module 1401, a query module 1402, a first allocation module 1403, and an execution module 1404. The acquisition module 1401 is used to acquire an access instruction, where the access instruction is used to instruct to access a target virtual memory page; the query module 1402 is used to query whether the target virtual memory page is mapped to a physical memory page in response to the access instruction; the first allocation module 1403 is used to allocate a target temporary page to the target virtual memory page if the target virtual memory page is not mapped to a physical memory page; and the execution module 1404 is used to perform an access operation on the cache space corresponding to the target temporary page.

[0370] In a possible implementation, the processor stores usage information and physical memory page allocation information of each temporary page, where the usage information is used to indicate whether the corresponding temporary page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated to the corresponding temporary page.

[0371] In a possible implementation, the first allocation module 1403 is specifically configured to: select a target temporary page from temporary pages indicated as available by usage information; allocate the target temporary page to the target virtual memory page; and update usage information of the target temporary page to unavailable.

[0372] In a possible implementation, the access instruction is a write instruction, and the execution module 1404 is specifically configured to write the data into the cache space corresponding to the target temporary page.

[0373] In one possible implementation, the device also includes: a second allocation module 1405, which is used to allocate a target physical memory page to the target temporary page when a preset condition is met; a first update module 1406, which is used to update the physical memory page allocation information of the target temporary page, and the updated physical memory page allocation information is used to indicate that the target physical memory page is allocated to the target temporary page; a second update module 1407, which is used to update the usage information of the target temporary page to available.

[0374] In one possible implementation, the device also includes: a data processing module 1408, which is used to detect that the usage information of the target temporary page is updated to available, and based on the physical memory page allocation information of the target temporary page, write the data in the cache space corresponding to the target temporary page to the memory corresponding to the target physical memory page.

[0375] In a possible implementation, the preset condition includes at least one of the following: a processor load is less than a first threshold, the number of temporary pages indicated as unavailable by usage information exceeds a second threshold, and a timer expires.

[0376] In one possible implementation, the processor stores a retention tag corresponding to each cache line, where the retention tag is used to indicate whether the data in the corresponding cache line is retained; the device also includes: a third update module 1409, which is used to update the retention tag corresponding to each cache line in the cache space to retained.

[0377] In a possible implementation, the processor stores a page table, where the page table includes allocatable information of each virtual memory page, where the allocatable information is used to indicate whether a temporary page can be allocated to the corresponding virtual memory page.

[0378] In a possible implementation, the first allocation module 1402 is specifically configured to: query allocatable information of a target virtual memory page; if the allocatable information of the target virtual memory page indicates that the target virtual memory page can allocate a temporary page, allocate a target temporary page to the target virtual memory page.

[0379] In another example, Figure 15 shows a schematic block diagram of an access device 1500 according to an embodiment of the present application. The access device may include a processor 1501 and a transceiver / transceiver pin 1502, and optionally, a memory 1503. The processor 1501 may be configured to execute the steps performed by the access device in each method of the aforementioned embodiments, and control the receive pin to receive signals and the transmit pin to send signals.

[0380] The various components of access device 1500 are coupled together via bus 1504. Bus system 1504 includes not only a data bus but also a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus system 1504 in the figure.

[0381] Optionally, the memory 1503 may be used to store instructions in the aforementioned method embodiment.

[0382] It should be understood that the access device 1500 according to the embodiment of the present application may correspond to the computer device in each method of the aforementioned embodiment, and the above-mentioned and other management operations and / or functions of each element in the access device 1500 are respectively for implementing the corresponding steps of each of the aforementioned methods. For the sake of brevity, they will not be repeated here.

[0383] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0384] Based on the same technical concept, an embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. The computer program includes at least one section of code, and the at least one section of code can be executed by a computer device to control the computer device to implement the above method embodiment.

[0385] Based on the same technical concept, an embodiment of the present application also provides a computer program, which, when executed by a computer device, is used to implement the above method embodiment.

[0386] The program may be stored in whole or in part on a storage medium packaged with the processor, or may be stored in whole or in part on a memory not packaged with the processor.

[0387] Based on the same technical concept, the embodiment of the present application further provides a processor, which is used to implement the above method embodiment. The above processor can be a chip.

[0388] The steps of the method or algorithm described in conjunction with the disclosure of the embodiments of the present application can be implemented in a hardware manner, or can be implemented by a processor executing a software instruction. The software instruction can be composed of corresponding software modules, and the software module can be stored in a random access memory (Random Access Memory, RAM), a flash memory, a read-only memory (Read Only Memory, ROM), an erasable programmable read-only memory (Erasable Programmable ROM, EPROM), an electrically erasable programmable read-only memory (Electrically EPROM, EEPROM), a register, a hard disk, a mobile hard disk, a read-only compact disc (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0389] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0390] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. An access method, characterized in that, Applied to a computer device, the computer device includes a processor and a memory, and the computer device further includes at least one physical memory page and at least one scratch page. Each of the physical memory pages is mapped to the memory. The method includes: Obtain an access instruction, where the access instruction is used to indicate accessing a target virtual memory page; In response to the access instruction, query whether the target virtual memory page is mapped to a physical memory page; In the case where the target virtual memory page is not mapped to a physical memory page, allocate a target scratch page for the target virtual memory page; Perform an access operation on the cache space corresponding to the target scratch page.

2. The method according to claim 1, wherein The processor stores usage information of each scratch page and physical memory page allocation information. The usage information is used to indicate whether the corresponding scratch page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated for the corresponding scratch page.

3. The method according to claim 2, wherein The allocating a target scratch page for the target virtual memory page includes: Select the target scratch page from the scratch pages indicated as available by the usage information; Allocate the target scratch page for the target virtual memory page; Update the usage information of the target scratch page to unavailable.

4. The method according to claim 3, wherein The access instruction is a write instruction. The performing a corresponding access operation on the cache space corresponding to the target scratch page includes: Write data into the cache space corresponding to the target scratch page.

5. The method according to claim 4, wherein After performing the corresponding access operation on the cache space corresponding to the target scratch page, it further includes: Under a preset condition, allocate a target physical memory page for the target scratch page; Update the physical memory page allocation information of the target scratch page. The updated physical memory page allocation information is used to indicate the target physical memory page allocated for the target scratch page; Update the usage information of the target scratch page to available.

6. The method according to claim 5, wherein After performing the corresponding access operation on the cache space corresponding to the target scratch page, it further includes: Detect that the usage information of the target scratch page is updated to available. Based on the physical memory page allocation information of the target scratch page, write the data in the cache space corresponding to the target scratch page into the memory corresponding to the target physical memory page.

7. The method according to claim 5, characterized in that, The preset condition includes at least one of the following: The load of the processor is less than a first threshold, the number of scratch pages indicated as unavailable by the usage information exceeds a second threshold, and the timer timing ends.

8. The method according to claim 4, characterized in that, The processor stores a reservation flag corresponding to each cache line. The reservation flag is used to indicate whether to reserve the data in the corresponding cache line. After writing data into the cache space corresponding to the target scratch page, it further includes: Update the reservation flag corresponding to each cache line of the cache space to reserved.

9. The method according to any one of claims 1 to 8, characterized in that The processor stores a page table, and the page table includes allocatable information of each virtual memory page. The allocatable information is used to indicate whether the corresponding virtual memory page can be allocated a scratch page.

10. The method according to claim 9, characterized in that The allocating a target scratch page for the target virtual memory page includes: Query the allocatable information of the target virtual memory page; When it is queried that the allocable information of the target virtual memory page indicates that the target virtual memory page can allocate a scratch page, allocate the target scratch page for the target virtual memory page.

11. An access device, characterized in that, Applied to a computer device, the computer device includes a processor and a memory, and the computer device further includes at least one physical memory page and at least one scratch page. Each of the physical memory pages is mapped to the memory. The apparatus includes: An acquisition module, configured to acquire an access instruction, where the access instruction is used to indicate accessing a target virtual memory page; A query module, configured to query whether the target virtual memory page is mapped to a physical memory page in response to the access instruction; A first allocation module, configured to allocate a target scratch page for the target virtual memory page when the target virtual memory page is not mapped to a physical memory page; An execution module, configured to perform an access operation on a cache space corresponding to the target scratch page.

12. The device according to claim 11, characterized in that, The processor stores usage information of each of the scratch pages and physical memory page allocation information. The usage information is used to indicate whether the corresponding scratch page is available, and the physical memory page allocation information is used to indicate a physical memory page allocated for the corresponding scratch page.

13. The device according to claim 12, characterized in that, The first allocation module is specifically configured to: Select the target scratch page from the scratch pages indicated by the usage information as available; Allocate the target scratch page for the target virtual memory page; Update the usage information of the target scratch page to unavailable.

14. The device according to claim 13, characterized in that, When the access instruction is a write instruction, the execution module is specifically configured to: Write data into a cache space corresponding to the target scratch page.

15. The device according to claim 14, characterized in that, The apparatus further includes: A second allocation module, configured to allocate a target physical memory page for the target scratch page when a preset condition is satisfied; A first update module, configured to update the physical memory page allocation information of the target scratch page. The updated physical memory page allocation information is used to indicate that the allocated physical memory page for the target scratch page is the target physical memory page; A second update module, configured to update the usage information of the target scratch page to available.

16. The device according to claim 15, characterized in that, The apparatus further includes: A data processing module, configured to detect that the usage information of the target scratch page is updated to available, and based on the physical memory page allocation information of the target scratch page, write data in a cache space corresponding to the target scratch page into a memory corresponding to the target physical memory page.

17. The device according to claim 15, characterized in that, The preset condition includes at least one of the following: The load of the processor is less than a first threshold, the number of scratch pages indicated by the usage information as unavailable exceeds a second threshold, and the timer timing ends.

18. The device according to claim 14, wherein The processor stores a reservation flag corresponding to each cache line, and the reservation flag is used to indicate whether to reserve data in the corresponding cache line; the apparatus further includes: A third update module, configured to update the reservation flag corresponding to each cache line of the cache space to reserved.

19. The device according to any one of claims 11 to 18, characterized in that, The processor stores a page table, and the page table includes allocable information of each virtual memory page. The allocable information is used to indicate whether the corresponding virtual memory page can allocate a scratch page.

20. The device according to claim 19, wherein The first allocation module is specifically configured to: Query the allocable information of the target virtual memory page; The allocable information of the target virtual memory page is queried to indicate that the target virtual memory page can allocate a scratch page, and the target scratch page is allocated to the target virtual memory page.

21. A computer cluster, characterized in that, The computer cluster includes at least one computer device, and the computer device is configured to execute the method according to any one of claims 1 to 10.

22. A computer storage medium, characterized in that, It includes computer instructions that, when the computer instructions run on a computer device, cause the computer device to execute the method according to any one of claims 1-10.

23. A computer program product, characterized in that, When the computer program product runs on a computer device, it causes the computer device to execute the method according to any one of claims 1-10.

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