Data processing method and apparatus

Abstract

Provided in the embodiments of the present application is a data processing method. The method may be applied to a first communication apparatus. The first communication apparatus may acquire a first FEC codeword which is sent by a second communication apparatus. The first communication apparatus does not decode the first FEC codeword in a traditional FEC decoding manner, but decodes the first FEC codeword on the basis of a first allocation relationship, wherein the first allocation relationship is used for indicating an allocation relationship between a first error correction capability and first error detection capability for processing of the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in the cyclic code codeword. In other words, in the embodiments of the present application, an error correction capability and error detection capability for decoding cyclic code codewords can be flexibly allocated, thereby enabling the performance provided by an FEC technique to meet requirements.

Description

Data processing method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 19, 2024, with application number 202410083451.X and invention name “A Data Processing Method and Device”, the entire contents of which are incorporated by reference into this application. Background Art

[0002] With the development of information technologies such as cloud computing, big data, artificial intelligence, and the Internet of Things, the amount of data transmitted over Ethernet networks is increasing. Due to non-ideal characteristics of transmission channels, such as transmission loss, crosstalk, and noise, signals are distorted after passing through the channel, resulting in bit errors. This is particularly true for high-speed links, where signal distortion can be severe, leading to high bit error rates.

[0003] Forward error correction (FEC) is a crucial technology for ensuring accurate information transmission and improving channel error performance in communication links. FEC involves encoding the signal according to a specific algorithm before it is sent into the transmission channel, adding a certain amount of redundant bits that reflect the signal's inherent characteristics. At the receiving end, the received signal is decoded according to the corresponding algorithm, thereby enabling error detection and correction.

[0004] The performance of current FEC technology cannot meet the requirements. Therefore, a solution is urgently needed to solve the above problems. Summary of the Invention

[0005] The embodiments of the present application provide a data processing method that can improve the performance provided by FEC.

[0006] In a first aspect, an embodiment of the present application provides a data processing method that can be applied to a first communication device. The first communication device can obtain a first FEC codeword sent by a second communication device. The first communication device does not decode the first FEC codeword according to a traditional FEC decoding method, but decodes the first FEC codeword according to a first allocation relationship. The first allocation relationship is used to indicate the allocation relationship between the first error correction capability and the first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic code codeword. In other words, in an embodiment of the present application, the error correction capability and error detection capability for decoding the cyclic code codeword can be flexibly allocated, so that the performance provided by the FEC technology can meet the requirements.

[0007] In one possible implementation, in order to ensure the error detection performance of the communication device, the first error correction capability may be smaller than the first error detection capability. In this case, the first communication device can detect a maximum number of error symbols, thereby improving the error detection performance of the first communication device. Accordingly, the Ethernet standard's requirements for MTTFPA can be more easily met.

[0008] In one possible implementation, considering that in some scenarios, the error correction performance of a traditional FEC decoding method is redundant, but the error detection performance cannot meet the mean time to false packet acceptance (MTTFPA) requirements of the Ethernet standard. Therefore, in order to ensure that the error detection performance provided by FEC meets the MTTFPA requirements of the Ethernet standard as much as possible, the redundant error correction capability can be reduced based on the traditional FEC decoding method to improve the error detection capability. Therefore, in one example, the first error correction capability can be less than the first error detection capability.

[0009] In one possible implementation, the first allocation relationship may be determined based on the link quality between the first communication device and the second communication device. Specifically, the first communication device may dynamically adjust the allocation relationship between the error correction capability and the error detection capability for processing a specific type of cyclic code codeword based on the link quality, thereby obtaining the first allocation relationship. This ensures that when decoding the specific type of cyclic code codeword based on the first allocation relationship, the resulting link quality meets the link quality requirement.

[0010] In one possible implementation, considering that the link bit error rate and the number of data frame retransmissions can reflect link quality, the link quality may include the link bit error rate and / or the number of data frame retransmissions. Accordingly, satisfying the link quality requirement may mean that the link bit error rate satisfies the bit error rate requirement and / or the number of data frame retransmissions satisfies the retransmission number requirement.

[0011] In one possible implementation, if the first allocation relationship satisfies the link quality requirement, that is, when decoding the aforementioned specific type of cyclic code codeword based on the first allocation relationship, the link quality between the first communication device and the second communication device meets the link quality requirement, then in order to further improve the error correction performance so that the error detection performance provided by the FEC meets the Ethernet standard's MTTFPA requirements as much as possible, the first error correction capability in the first allocation relationship may be further reduced to increase the first error detection capability in the first allocation relationship, thereby obtaining a second allocation relationship to facilitate subsequent decoding of the aforementioned specific type of cyclic code codeword based on the second allocation relationship. Because the first error correction capability is reduced, when processing the aforementioned specific type of cyclic code codeword based on the second allocation relationship, the link quality between the first communication device and the second communication device will be reduced. In this embodiment of the present application, the first error correction capability is not reduced indefinitely, but rather the second allocation relationship can be controlled to still meet the link quality requirement after the first error correction capability is reduced.

[0012] In one possible implementation, the first communication device decodes the first FEC codeword according to the first allocation relationship. In a specific implementation, the first FEC codeword can be first corrected according to the first error correction capability to obtain a second FEC codeword; then, the second FEC codeword can be error detected according to the second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

[0013] In one possible implementation, P represents the second error detection capability. That is, if the second error detection capability is P, then "performing error detection on the second FEC codeword based on the second error detection capability" can be specifically implemented by calculating 2*P syndromes based on the second FEC codeword. Furthermore, based on the 2*P syndromes, it is determined whether the second FEC codeword contains errors. Specifically, if the 2*P syndromes are all zeros, it can be determined that the second FEC codeword does not contain an error codeword; if the 2*P syndromes are not all zeros, it can be determined that the second FEC codeword contains an error codeword.

[0014] In a possible implementation, considering that the Reed-Solomon (RS) code is currently a commonly used encoding method in FEC, the first FEC codeword may be an RS code.

[0015] In one possible implementation, the sum of the first error correction capability and the first error detection capability is equal to dmim-1, where dmin is the minimum Hamming distance between RS codes. In other words, the sum of the error correction capability and error detection capability provided by the RS code is a constant value. Therefore, if the error correction capability is reduced, the error detection capability can be correspondingly improved.

[0016] In one possible implementation, if the first FEC codeword is RS(128,120), the minimum Hamming distance of RS(128,120) is 9. Therefore, the sum of the first error correction capability and the first error detection capability is 8. Therefore, in one example, the first error correction capability may be 1, and the first error detection capability may be 7; in another example, the first error correction capability may be 2, and the first error detection capability may be 6; in yet another example, the first error correction capability may be 3, and the first error detection capability may be 5; in another example, the first error correction capability and the first error detection capability may both be 4.

[0017] In the second aspect, an embodiment of the present application provides a data processing device, which is applied to a first communication device, wherein the first communication device includes a receiving unit and a processing unit; the receiving unit is used to obtain a first forward error correction (FEC) codeword sent by the second communication device; the processing unit is used to decode the first FEC codeword according to a first allocation relationship, wherein the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, wherein the first error correction capability indicates a maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates a maximum number of error symbols that can be detected in a cyclic code codeword.

[0018] In a possible implementation, the first error correction capability is smaller than the first error detection capability.

[0019] In a possible implementation manner, the first allocation relationship is determined according to link quality between the first communication device and the second communication device.

[0020] In one possible implementation, the first allocation relationship meets the link quality requirements, and the processing unit is further used to: reduce the first error correction capability in the first allocation relationship and increase the first error detection capability in the first allocation relationship to obtain a second allocation relationship, and the second allocation relationship meets the link quality requirements.

[0021] In a possible implementation, the link quality includes: a link bit error rate, and / or the number of data frame retransmissions.

[0022] In one possible implementation, the processing unit is configured to: perform error correction on the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; and perform error detection on the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

[0023] In one possible implementation, performing error detection on the second FEC codeword according to the second error detection capability includes: calculating 2*P syndromes based on the second FEC codeword, where P corresponds to the second error detection capability; if the 2*P syndromes are all 0, determining that the second FEC codeword does not include an error codeword; or, if the 2*P syndromes are not all 0, determining that the second FEC codeword includes an error codeword.

[0024] In a possible implementation, the first FEC codeword is a Reed-Solomon RS code.

[0025] In a possible implementation, the sum of the first error correction capability and the first error detection capability is equal to dmim-1, where dmin is the minimum Hamming distance between RS codes.

[0026] In one possible implementation, the first FEC codeword is RS(128, 120), then: the first error correction capability is 1, and the first error detection capability is 7; or, the first error correction capability is 2, and the first error detection capability is 6; or, the first error correction capability is 3, and the first error detection capability is 5; or, the first error correction capability is 4, and the first error detection capability is 4.

[0027] In a third aspect, an embodiment of the present application provides a device. The device includes a processor and a memory. The memory is configured to store instructions or computer programs. The processor is configured to execute the instructions or computer programs in the memory to perform the method described in the first aspect and any one of the above aspects.

[0028] In a fourth aspect, an embodiment of the present application provides an optical module, comprising an interface circuit and a processing circuit, wherein the interface circuit is used to receive and / or send data, and the processing circuit is used to perform data processing. In a specific example, the interface circuit is used to obtain a first forward error correction (FEC) codeword sent by a second communication device, and the processing circuit is used to decode the first FEC codeword according to a first allocation relationship, wherein the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, wherein the first error correction capability indicates a maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates a maximum number of error symbols that can be detected in a cyclic code codeword.

[0029] In a fifth aspect, an embodiment of the present application provides a physical layer (PHY) chip, the PHY chip including an interface circuit and a processing circuit, the interface circuit being used to receive and / or send data, and the processing circuit being used to perform data processing. In a specific example, the interface circuit is used to obtain a first forward error correction (FEC) codeword sent by a second communication device, and the processing circuit is used to decode the first FEC codeword according to a first allocation relationship, wherein the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, the first error correction capability indicating a maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicating a maximum number of error symbols that can be detected in a cyclic code codeword.

[0030] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising instructions or a computer program, which, when executed on a computer, enables the computer to execute the method described in the first aspect and any one of the above first aspects.

[0031] In a seventh aspect, an embodiment of the present application provides a computer program product comprising instructions or a computer program, which, when executed on a computer, enables the computer to execute the method described in the first aspect and any one of the above first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] FIG1a shows a schematic diagram of a process of decoding a cyclic code in a conventional technique;

[0034] FIG1b is a schematic diagram of a codeword miscorrection according to an embodiment of the present application;

[0035] FIG1c is a schematic diagram of a decoding effect provided by an embodiment of the present application;

[0036] FIG2 is a flow chart of a data processing method provided in an embodiment of the present application;

[0037] FIG3 is a schematic diagram of a decoding process provided by an embodiment of the present application;

[0038] FIG4 is a schematic diagram of another decoding process provided in an embodiment of the present application;

[0039] FIG5 is a schematic structural diagram of a data processing device provided in an embodiment of the present application;

[0040] FIG6 is a schematic diagram of the structure of an optical module provided in an embodiment of the present application;

[0041] FIG7 is a schematic diagram of the structure of a PHY chip provided in an embodiment of the present application;

[0042] FIG8 is a schematic structural diagram of a device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application provide a data processing method that can improve the performance provided by FEC.

[0044] Currently, there are many encoding algorithms supported by FEC technology. Among them, cyclic codes are a type of code with both error correction and detection capabilities that has been extensively researched, has relatively mature theoretical foundations, and has a wide range of applications. Examples of cyclic codes include RS codes, cyclic redundancy check (CRC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and Fire codes.

[0045] FEC can be used for both error correction and error detection. However, current FEC has fixed error correction and error detection performance for a fixed code type, and generally, these two performances are identical. Error correction performance refers to the maximum number of erroneous symbols that can be corrected in a cyclic codeword, while error detection performance refers to the maximum number of erroneous symbols that can be detected in a cyclic codeword. For example, for a certain codetype, both error correction and error detection performance are a. This means that when at most a symbols in a codeword are erroneous, the erroneous symbols can be corrected to correct symbols. Similarly, when at most a symbols in a codeword are erroneous, the codeword can be detected as erroneous. In this scenario, as an example, detecting an error in a codeword can mean outputting an error detection result indicating that the error occurred. This error detection result does not necessarily identify the specific codeword within the codeword where the error occurred. As another example, this detection result can also locate the specific codeword where the error occurred. This is because error detection performance and error correction performance are identical, while error correction necessarily requires identifying the specific codeword where the error occurred.

[0046] Because the error correction and detection performance for a fixed code pattern is fixed, the performance provided by current FEC technology falls short of demand. As a specific example, the error detection performance provided by current FEC technology fails to meet the Ethernet standard's requirements for MTTFPA. MTTFPA is a key parameter in the Ethernet standard, which specifically requires that only one error frame be received within the lifetime of the universe (approximately 13.8 billion years). This means that over the lifetime of the universe, a communication device must only misdetect a single error frame as a correct data frame.

[0047] In order to ensure that the performance provided by FEC can meet the requirements, an embodiment of the present application provides a data processing method and device.

[0048] Before introducing the data processing method and device provided in the embodiments of the present application, the relevant contents of FEC and cyclic codes are first introduced.

[0049] 1. Related terms

[0050] 1. Symbol of cyclic code word: The basic unit of cyclic code word is also the basic unit for RS code encoding and decoding calculation. A symbol can include one or more bits. The number of bits contained in a symbol can be represented by the letter m. When m = 1, the symbol and the bit have the same meaning.

[0051] 2. (N, K, T, m) are the four parameters of the cyclic code, where:

[0052] N represents the length of a cyclic code word;

[0053] K represents the length of the valid symbol (also called payload) included in a cyclic code;

[0054] T represents the maximum error correction capability of a codeword, that is, a codeword can correct errors of up to T symbols, T = (NK) / 2;

[0055] m represents the number of bits in a symbol and is a positive integer greater than or equal to 1. For BCH, CRC, and Fire Code, m is usually 1. For RS codes, m is usually greater than 1.

[0056] 3. RS(N,K): RS code representation, RS(N,K) represents an RS codeword with a codeword length of N and an information length of K.

[0057] 4. RS codeword length: The number of symbols contained in an RS codeword, usually represented by the letter N.

[0058] 5. Information length of RS codeword: The number of valid symbols contained in an RS codeword, usually represented by the letter K.

[0059] 6. Redundancy length of RS codeword: The number of redundant symbols contained in an RS codeword, usually represented by the letter R, R=NK.

[0060] 7. Hamming distance (HD): This represents the number of different characters in corresponding positions of two strings of the same length. For cyclic codes, once the encoding method is determined, the minimum Hamming distance between the encoded codewords is also determined. Specifically, the minimum Hamming distance for a cyclic code (N, K, T, m) is dmin = N - K + 1. For example, for RS (128, 120), the minimum Hamming distance is 9.

[0061] 2. Cyclic code encoding and decoding principles

[0062] The payload part M(x) of a cyclic code of length K can be expressed by the polynomial shown in formula (1): M(x)=m K-1 ·x K-1 +m K-2 ·x K-2 +…+m1·x+m0 Formula (1)

[0063] The generating polynomial g(x) of the cyclic code can be expressed as formula (2): g(x) = g N-K ·x N-K +g N-K-1 ·x N-K-1 +…+g1·x+g0 Formula (2)

[0064] The cyclic code encoding process is to divide M(x) by g(x) to obtain the remainder P(x). The codeword polynomial C(x) of a cyclic code can be composed of M(x) and P(x), as shown in formula (3): C(x) = x N-K M(x)+p(x) Formula (3)

[0065] Among them, x N-K M(x) satisfies the following formula (4): N-K M(x) = q(x) g(x) + p(x) Formula (4)

[0066] Substituting formula (4) into formula (3) yields the following formula (5): C(x) = q(x) g(x) Formula (5)

[0067] According to formula (5), the roots of the generator polynomial g(x) are also the roots of the codeword polynomial C(x).

[0068] The polynomial r(x) received by the cyclic code decoder can be expressed by formula (6): r(x) = C(x) + e(x) = r0 + r1x + ... + r n-1 x n-1 Formula (6)

[0069] In formula (6), e(x) represents the error polynomial caused by channel transmission, which can be expressed by the following formula (7):

[0070] If the cyclic code word does not have any error during transmission, then e(x) is 0, and the decoder receives a correct code word; if the cyclic code word has an error during transmission, then e(x) is not 0. α is GF(2 m ) on the primitive element, α b+i ∈GF(2 m ),i=0,1,…,2t-1 are the roots of the generating polynomial. Among them: GF(2 m A Galois field, also known as a Galois field, was discovered by French mathematician Évariste Galois. It has multiplication, division, addition, and subtraction operations that follow certain rules and are closed, meaning that the results of operations between field elements remain within the field.

[0071] As mentioned above, the roots of the generator polynomial are also the roots of the codeword polynomial, so the following formula (8) holds. b+i )=e(α b+i ),i=0,1,…,2t-1 Formula (8)

[0072] The purpose of decoding is to determine the location of the error And the corresponding error value, then add the obtained error polynomial e(x) to the received polynomial r(x) to get the correct codeword polynomial.

[0073] Referring to Figure 1a, Figure 1a shows a schematic diagram of the process of decoding cyclic codes in conventional technology. As shown in Figure 1a, the decoding process includes the following four steps:

[0074] 1. Calculate 2*T syndromes to determine whether there are errors, where T is the maximum error correction capability.

[0075] 2. Solve the key equations according to the 2*T syndromes to determine the error position polynomial and the error value polynomial.

[0076] In one example, the RiBM (English: Reformulated inversionless Berlekamap-Massey) algorithm may be used to solve the key equations.

[0077] 3. Determine the position of the symbol where the error occurs in the cyclic code word based on the error position polynomial.

[0078] In one example, the error location polynomial may be processed using a Chien search algorithm to determine the location of the symbol where the error occurs in the codeword of the cyclic code.

[0079] 4. Determine the error value corresponding to the error symbol corresponding to the aforementioned position according to the error value polynomial, and perform error correction on the cyclic code word based on the error value.

[0080] In one example, the error value polynomial may be processed using a Forney algorithm to determine the error value.

[0081] For cyclic code (N, K, T, m), if it only works in error detection mode, its error detection performance can reach dmin-1 symbols. For example, for RS (128, 120), if it only works in error detection mode, its error detection performance can reach 8 symbols.

[0082] In traditional technologies, the error correction and error detection performance of (N, K, T, m) cyclic codes are fixed. Specifically, all NK redundant symbols are used for error correction, meaning the error correction capability can reach T symbols, where T is the maximum error correction capability of the (N, K, T, m) cyclic code. Correspondingly, its error detection capability is also T symbols. This approach can effectively reduce the bit error rate (BER) of data transmitted over the channel. For example, if the bit error rate (BER) is 1e-5 before error correction of the received codeword, the BER can be reduced to 4.2e-15 after using the aforementioned error correction capability.

[0083] However, the current approach of using all NK redundant symbols for error correction often fails to meet performance requirements. For example, while error correction performance is redundant, error detection performance falls short of the Ethernet standard's MTTFPA requirements. For example, in some scenarios, a bit error rate of 1e-9 or 1e-10 is sufficient, rather than the aforementioned 4.2e-15.

[0084] The inventors of this application have found that for a cyclic code (N, K, T, m), its generating polynomial can be expressed as the following formula (9) in addition to the form of formula (2). g(x) = (x - α 0 )·(x-α 1)·(x-α 2 )…·(x-α N-K-1 ) Formula (9)

[0085] Combining formula (9) and formula (6), we can see that the codeword polynomial C(x) satisfies the following formula (10): C(α i )=0,i=0,1,2,…Nk-1 Formula (10)

[0086] According to formula (10), C(x) can also be regarded as the following codeword:

[0087] 1. C(x) is The codeword polynomial for generating the polynomial has an error correction capability of 1 symbol;

[0088] 2. C(x) is The codeword polynomial for generating the polynomial has an error correction capability of up to 2 symbols;

[0089] And so on:

[0090] 3. C(x) is The codeword polynomial is a generator polynomial with an error correction capability of symbols.

[0091] Regardless of the above situation, C(x) has an error correction capability of T. Therefore, for a cyclic codeword, if T+1 symbols have errors, the codeword may be corrected to another codeword, i.e., a codeword miscorrection occurs. As shown in Figure 1b, Figure 1b is a schematic diagram of a codeword miscorrection provided in an embodiment of the present application.

[0092] As shown in Figure 1b, the codeword C w1 During the transmission, e errors occur and become codeword R. If codeword R is equal to codeword C, w2 If the HD is less than or equal to T, it may be mistakenly corrected as codeword C w2 Since the following formulas (11) to (14) are satisfied, formula (15) can be obtained. HD(C w1 ,C w2 )<= e+T Formula (15)

[0093] in:

[0094] HD(a,b) represents the Hamming distance between codeword a and codeword b, for example, HD(C w1 ,C w2 ) represents codeword Cw1 and codeword C w2 The Hamming distance between

[0095] Indicates the XOR calculation of codeword a and codeword b, for example, Indicates codeword C w1 and codeword C w2 Perform an XOR calculation.

[0096] According to formula (15), if a miscorrection occurs, the number of errors caused is at least e+T.

[0097] Therefore, for the cyclic code (N, K, T, m), as long as e+T is less than its dmin (i.e., N-K+1), it can be successfully detected and no false correction will occur. In other words, the sum of the error detection capability and the error correction capability can reach dmin-1. Therefore, for the cyclic code (N, K, T, m), if the error correction capability is t1 (t1 <= T), its error detection capability can reach dmin-1-t1 symbols. In other words, the error correction capability and error detection capability of a cyclic code are not necessarily fixed, but can be allocated. For the cyclic code (N, K, T, m), it can achieve the capability of "correcting t1 and detecting (dmin-1-t1)". The so-called "correcting t1 and detecting (dmin-1-t1)" means that the error correction capability is t1 and the error detection capability is (dmin-1-t1).

[0098] Taking RS(128,120) as an example, its dmin=9, then it can realize the capabilities of “correct 1 and check 7”, “correct 2 and check 6”, and “correct 3 and check 5”.

[0099] This can be understood in conjunction with FIG1c , which is a schematic diagram of a decoding effect provided in an embodiment of the present application.

[0100] As shown in the content (a) of Figure 1c, for codeword C w3 For example, if traditional FEC decoding is used, its decoding capability and error correction capability are both 4, that is, when the codeword C w3 After the codeword Q is programmed after transmission, if the codeword Q and codeword C w3 If the Hamming distance between codewords Q and C is less than or equal to 4, they can be corrected. However, when the decoding mode is "correct 1 check 7", as long as codewords Q and C w3 If the Hamming distance between codewords Q and C is less than or equal to 7, it can be detected that codeword Q is an incorrect codeword. w3 When the Hamming distance between them is greater than 1, the codeword Q cannot be corrected to C w3 .

[0101] Similarly, as shown in content (b) of Figure 1c, when the decoding mode is "correct 2 detect 6", as long as codeword Q and codeword C w3 If the Hamming distance between codewords Q and C is less than or equal to 6, it can be detected that codeword Q is an incorrect codeword. w3 When the Hamming distance between them is greater than 2, the codeword Q cannot be corrected to C w3 .

[0102] Similarly, as shown in content (c) in Figure 1c, when the decoding mode is "correct 3 check 5", as long as codeword Q and codeword C w3 If the Hamming distance between codewords Q and C is less than or equal to 5, it can be detected that codeword Q is an incorrect codeword. w3 When the Hamming distance between them is greater than 3, the codeword Q cannot be corrected to C w3 .

[0103] In view of this, an embodiment of the present application provides a data processing method, which can flexibly allocate the error correction capability and error detection capability of a cyclic code with a certain code type, so that the performance provided by the cyclic code can meet the requirements.

[0104] Next, the data processing method provided by the embodiment of the present application is introduced in conjunction with Figure 2. Figure 2 is a flow chart of a data processing method provided by the embodiment of the present application.

[0105] The method shown in Figure 2 can be applied to a first communication device. The communication devices mentioned in the embodiments of the present application (such as the first communication device and the second communication device) can be network devices such as switches and routers, or can be a component of a network device, such as a single board or line card on a network device, or a functional module on a network device, or a chip for implementing the method of the present application (such as a physical layer (PHY) chip), or a server or an optical module, etc., which is not specifically limited in the embodiments of the present application. The communication devices can be directly connected, for example, but not limited to, via an Ethernet cable or an optical cable.

[0106] The method shown in FIG. 2 may include the following steps S101 - S102 .

[0107] S101: A first communication device obtains a first FEC codeword sent by a second communication device.

[0108] In an embodiment of the present application, the second communication device may send a first FEC codeword to the first communication device, and accordingly, the first communication device may receive the first FEC codeword sent by the second communication device. The first FEC codeword may be a specific type of cyclic codeword, for example, the first FEC codeword may be a RS codeword, or, for another example, the first FEC codeword may be a CRC codeword, a BCH codeword, or a FIRE codeword. In a specific example, when the first FEC codeword is an RS codeword, the first FEC codeword may be RS(128,120), for example, that is, the first FEC codeword includes a total of 128 symbols, of which 120 symbols are information symbols and the remaining 8 symbols are redundant symbols.

[0109] In an example, the first communication device may be a network device serving as a receiving end, and correspondingly, the second communication device may be a network device serving as a sending end.

[0110] In another example, the first communication device and the second communication device may belong to the same network device. As a specific example, the first communication device may be an optical module on the network device, and the second communication device may be a PHY chip on the network device. As another specific example, the first communication device and the second communication device may be two different PHY chips on the network device, for example, the first communication device is the first PHY chip on the network device, and the second communication device is the second PHY chip on the network device.

[0111] S102: The first communication device decodes the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, where the first error correction capability indicates a maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates a maximum number of error symbols that can be detected in a cyclic code codeword.

[0112] After the first communication device obtains the first FEC codeword, it does not decode the first FEC codeword according to the traditional FEC decoding method, but decodes the first FEC codeword according to the first allocation relationship of flexible allocation. Taking the first FEC codeword as RS(128,120) as an example, the maximum error correction capability corresponding to RS(128,120) is 4, and accordingly, its error detection capability is also 4. That is, it can correct up to 4 erroneous symbols. When the number of erroneous symbols in the codeword is less than or equal to 4, it can be detected that an error has occurred in the codeword. The first communication device does not decode the first FEC codeword with the maximum decoding capability, but decodes the first FEC codeword based on the first allocation relationship of flexible allocation.

[0113] Among them, the first allocation relationship is used to indicate the allocation relationship between the first error correction capability and the first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of erroneous symbols that can be corrected in a cyclic code codeword. For example, the first error correction capability is a first number, indicating that when the erroneous symbols in the cyclic code codeword are less than or equal to the first number, the erroneous symbols can be corrected to correct symbols. The first error detection capability indicates the maximum number of erroneous symbols that can be detected in a cyclic code codeword. For example, the first error detection capability is a second number, indicating that when the erroneous symbols in the cyclic code codeword are less than or equal to the second number, the cyclic code codeword can be detected as having an error. In other words, in an embodiment of the present application, the error correction capability and error detection capability for decoding the cyclic code codeword can be flexibly allocated, so that the performance provided by the FEC technology can meet the requirements.

[0114] The embodiments of this application do not specifically limit the first error correction capability and the first error detection capability. As described above for cyclic codes, the error correction capability and error detection capability of traditional FEC decoding schemes are equal, and the error correction capability is the maximum error correction capability. In the embodiments of this application, it is considered that in some scenarios, the error correction performance of traditional FEC decoding schemes is redundant, while the error detection performance cannot meet the Ethernet standard requirements for MTTFPA. Therefore, in order to ensure that the error detection performance provided by FEC meets the Ethernet standard requirements for MTTFPA as much as possible, the redundant error correction capability can be reduced based on the traditional FEC decoding scheme. Since the sum of the error correction capability and the error detection capability is equal to dmin-1, reducing the redundant error correction capability can improve the error detection capability. Therefore, in one example, the first error correction capability can be less than the first error detection capability. That is, the first number can be less than the second number. For example, if the first FEC codeword is RS(128,120), then as described above, the sum of the first number and the second number is equal to 8. Thus: in one example, the first number may be 1 and the second number may be 7; in another example, the first number may be 2 and the second number may be 6; in yet another example, the first number may be 3 and the second number may be 5.

[0115] Of course, the first error correction capability and the first error detection capability may also be the same, for example, the first error correction capability and the first error detection capability are both 4. This embodiment of the present application does not specifically limit this.

[0116] In one example, the first allocation relationship may be manually specified by a user.

[0117] In another example, the first allocation relationship may also be determined based on the link quality between the first communication device and the second communication device. That is, the first communication device may dynamically adjust the allocation relationship between the error correction capability and the error detection capability for processing a specific type of cyclic codeword based on the link quality, thereby obtaining the first allocation relationship. This ensures that when decoding the specific type of cyclic codeword based on the first allocation relationship, the resulting link quality meets the link quality requirement.

[0118] The link quality mentioned in the embodiments of the present application includes but is not limited to any parameter that can reflect the quality of the link. As a specific example, considering that the link bit error rate and the number of data frame retransmissions can reflect the quality of the link, the link quality can include the link bit error rate and / or the number of data frame retransmissions. Accordingly, the link quality meets the link quality requirement, which can be that the link bit error rate meets the bit error rate requirement and / or the number of data frame retransmissions meets the retransmission number requirement. For example, the link quality meets the link quality requirement, which can be that the link bit error rate is lower than the bit error rate threshold and / or the number of data frame retransmissions is lower than the retransmission number threshold.

[0119] In a specific example, the first allocation relationship can be obtained by adjusting the third allocation relationship. The third allocation relationship indicates the allocation relationship between the second error correction capability and the third error detection capability for processing a specific type of cyclic code codeword. The embodiment of the present application does not specifically limit the second error correction capability and the third error detection capability. In an example, the second error correction capability can be the maximum error correction capability for processing a specific type of cyclic code codeword, and accordingly, the third error detection capability is equal to the second error correction capability. For example, if the specific type of cyclic code codeword is RS(128,120), then the second error correction capability and the third error detection capability are both 4. Of course, the second error correction capability may also be less than the third error detection capability, and the embodiment of the present application does not make specific limitations.

[0120] In one example, if the third allocation relationship meets the link quality requirement, then the second error correction capability meets the requirement and is even redundant. Therefore, the second error correction capability in the third allocation relationship can be reduced to increase the third error detection capability in the third allocation relationship, thereby obtaining the first allocation relationship. For example, this can be understood in conjunction with the following Table 1.

[0121] Table 1

[0122] As shown in Table 1, the second error correction capability and the third error detection capability of the third allocation relationship are both 4 characters. When the third allocation relationship meets the link quality requirements, the second error correction capability is reduced to obtain the first error correction capability. Correspondingly, the third error detection capability is improved to the first error detection capability.

[0123] Regarding the third allocation relationship satisfying the link quality requirement, it can be understood that when the aforementioned specific type of cyclic codeword is decoded based on the third allocation relationship, the link quality between the first communication device and the second communication device satisfies the link quality requirement.

[0124] In one example, if the first allocation relationship meets the link quality requirement, that is, when decoding the aforementioned specific type of cyclic code codeword based on the first allocation relationship, the link quality between the first communication device and the second communication device meets the link quality requirement, then in order to further improve the error correction performance, so that the error detection performance provided by FEC meets the Ethernet standard for MTTFPA as much as possible, the first error correction capability in the first allocation relationship can be further reduced to increase the first error detection capability in the first allocation relationship, and a second allocation relationship is obtained, so as to facilitate the subsequent decoding of the aforementioned specific type of cyclic code codeword based on the second allocation relationship. The second allocation relationship can indicate the allocation relationship between the third error correction capability and the fourth error detection capability for processing the aforementioned specific type of cyclic code codeword. It is not difficult to understand that since the first error correction capability is reduced, when processing the aforementioned specific type of cyclic code codeword based on the second allocation relationship, the link quality between the first communication device and the second communication device will be reduced. In this embodiment of the present application, the first error correction capability is not reduced indefinitely, but the second allocation relationship can be controlled to still meet the link quality requirement after the first error correction capability is reduced.

[0125] Table 2

[0126] In the embodiment of the present application, S102 may be specifically implemented, for example, including S1021-S1022 shown in Figure 3. Figure 3 is a schematic diagram of a decoding process provided by the embodiment of the present application.

[0127] S1021: The first communication device corrects the first FEC codeword according to the first error correction capability to obtain a second FEC codeword.

[0128] For ease of description, the first quantity is represented by t1, that is, the first error correction capability is t1. Then, when S1021 is specifically implemented, it may include the following steps:

[0129] First, 2*t1 syndromes are calculated based on the first FEC codeword. The syndrome calculation method can adopt a traditional syndrome calculation method, which will not be repeated here.

[0130] Then, the 2*t1 syndromes are used to solve the key equations to determine the error position polynomial and the error value polynomial. In one example, the RiBM algorithm can be used to solve the key equations.

[0131] Furthermore, the position of the erroneous symbol in the first FEC codeword is determined based on the error position polynomial. In one example, the error position polynomial can be processed using a Chien search algorithm to determine the position of the erroneous symbol in the first FEC codeword. Furthermore, the error value corresponding to the erroneous symbol at the position is determined based on the error value polynomial, and the first FEC codeword is corrected based on the error value to obtain a second FEC codeword. In one example, the error value polynomial can be processed using a Forney algorithm to determine the error value.

[0132] Regarding how to use the RiBM algorithm to solve the key equation, how to use the Chien search algorithm to process the error position polynomial, and how to use the Forney algorithm to process the error value polynomial, the traditional processing method can be used and will not be described in detail here.

[0133] S1022: The first communication device performs error detection on the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to a difference between a maximum error correction capability and the first error correction capability.

[0134] After obtaining the second FEC codeword, error detection can be further performed on the second FEC codeword based on the second error detection capability. The second error detection capability is equal to the difference between the maximum error correction capability T and the first error correction capability t1. Since the sum of the first error correction capability and the first error detection capability is equal to twice the maximum error correction capability, the second error detection capability is also equal to half the difference between the first error detection capability and the first error correction capability.

[0135] For ease of description, the second error detection capability is represented by P. That is, if the second error detection capability is P, then in a specific implementation, S1022 may calculate 2*P syndromes based on the second FEC codeword. Furthermore, based on the 2*P syndromes, it is determined whether the second FEC codeword contains errors. Specifically, if the 2*P syndromes are all zero, it can be determined that the second FEC codeword does not contain an error codeword; if the 2*P syndromes are not all zero, it can be determined that the second FEC codeword contains an error codeword. In other words, if the 2*P syndromes are all zero, the error detection result is: the second FEC codeword does not contain an error codeword. If the 2*P syndromes are not all zero, the error detection result is: the second FEC codeword contains an error codeword. In other words, the error detection result obtained by executing S1022 can be used to indicate whether the second FEC codeword contains an error (i.e., whether it contains an error codeword), but cannot be used to indicate the specific codeword in the second FEC codeword where the error occurred. In yet another example, a key equation may be further solved for the 2*P syndromes to determine an error location polynomial, thereby determining a specific codeword in which an error occurs in the second FEC codeword.

[0136] Next, the specific implementation of S102 is introduced in conjunction with the decoding flow chart shown in Figure 4. Figure 4 is a schematic diagram of another decoding flow provided by an embodiment of the present application.

[0137] As shown in Figure 4, the decoding process includes the following four steps:

[0138] 1. Based on the first FEC codeword, calculate the 2*t1 syndrome to determine whether an error exists, where t1 is the first error correction capability.

[0139] 2. Solve the key equations based on the 2*t1 syndromes to determine the error position polynomial and the error value polynomial.

[0140] In one example, the RiBM algorithm may be used to solve the key equations.

[0141] 3. Determine the position of the erroneous symbol in the first FEC codeword based on the error position polynomial.

[0142] In one example, the error location polynomial may be processed using a Chien search algorithm to determine the location of the symbol where the error occurs in the codeword of the cyclic code.

[0143] 4. Determine the error value corresponding to the error symbol corresponding to the aforementioned position according to the error value polynomial, and perform error correction on the first FEC codeword based on the error value to obtain a second FEC codeword.

[0144] In one example, the error value polynomial may be processed using a Forney algorithm to determine the error value.

[0145] 5. Calculate 2*P syndromes to determine whether there is an error in the second FEC codeword, where 2*P=2*(T-t1).

[0146] By comparing FIG4 and FIG1a, it can be seen that, compared with the decoding process of the conventional technology, the decoding process of the present application splits the syndrome calculation part in the conventional technology into two parts. In the error correction stage, the number of syndromes calculated is reduced (2*T is reduced to 2*P). Accordingly, the number of syndromes processed in the error correction stage is reduced, and accordingly, the power consumption of decoding is reduced.

[0147] Based on the data processing methods provided in the above method embodiments, embodiments of the present application also provide corresponding data processing devices. Referring to FIG. 5 , this figure is a schematic diagram of the structure of a data processing device provided in an embodiment of the present application. The data processing device 500 shown in FIG. 5 can be applied to the first communication device in the above method embodiments to execute the data processing methods provided by the first communication device in the above method embodiments.

[0148] As shown in FIG5 , the data processing device 500 includes a receiving unit 501 and a processing unit 502 .

[0149] The receiving unit 501 is configured to obtain a first forward error correction (FEC) codeword sent by a second communication device;

[0150] The processing unit 502 is used to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, the first error correction capability indicates a maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates a maximum number of error symbols that can be detected in a cyclic code codeword.

[0151] In a possible implementation, the first error correction capability is smaller than the first error detection capability.

[0152] In a possible implementation manner, the first allocation relationship is determined according to link quality between the first communication device and the second communication device.

[0153] In one possible implementation, the first allocation relationship meets the link quality requirements, and the processing unit 502 is further used to: reduce the first error correction capability in the first allocation relationship and increase the first error detection capability in the first allocation relationship to obtain a second allocation relationship, and the second allocation relationship meets the link quality requirements.

[0154] In a possible implementation, the link quality includes: a link bit error rate, and / or the number of data frame retransmissions.

[0155] In one possible implementation, the processing unit 502 is configured to: perform error correction on the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; and perform error detection on the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

[0156] In one possible implementation, performing error detection on the second FEC codeword according to the second error detection capability includes: calculating 2*P syndromes based on the second FEC codeword, where P corresponds to the second error detection capability; if the 2*P syndromes are all 0, determining that the second FEC codeword does not include an error codeword; or, if the 2*P syndromes are not all 0, determining that the second FEC codeword includes an error codeword.

[0157] In a possible implementation, the first FEC codeword is a Reed-Solomon RS code.

[0158] In a possible implementation, the sum of the first error correction capability and the first error detection capability is equal to dmim-1, where dmin is the minimum Hamming distance between RS codes.

[0159] In one possible implementation, the first FEC codeword is RS(128, 120), then: the first error correction capability is 1, and the first error detection capability is 7; or, the first error correction capability is 2, and the first error detection capability is 6; or, the first error correction capability is 3, and the first error detection capability is 5; or, the first error correction capability is 4, and the first error detection capability is 4.

[0160] Based on the data processing method provided in the above method embodiment, the present application also provides an optical module. Referring to Figure 6, this figure is a schematic diagram of the structure of an optical module provided in the present application embodiment. The optical module 600 shown in Figure 6 can correspond to the first communication device in the above method embodiment and be used to execute the data processing method provided by the first communication device in the above method embodiment.

[0161] As shown in FIG6 , the optical module 600 includes an interface circuit 601 and a processing circuit 602 .

[0162] The interface circuit 601 is used to receive and / or send data, and the processing circuit 602 is used to process data.

[0163] In a specific example, the interface circuit 601 is used to obtain a first forward error correction FEC codeword sent by the second communication device;

[0164] The processing circuit 602 is used to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, where the first error correction capability indicates a maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates a maximum number of error symbols that can be detected in a cyclic code codeword.

[0165] Regarding the specific implementation of the interface circuit 601 and the processing circuit 602, reference may be made to the relevant description of the above method embodiment, which will not be repeated here.

[0166] Based on the data processing method provided in the above method embodiment, the present application also provides a PHY chip. Referring to Figure 7, this figure is a schematic diagram of the structure of a PHY chip provided in the present application embodiment. The PHY chip 700 shown in Figure 7 can correspond to the first communication device in the above method embodiment and be used to execute the data processing method provided by the first communication device in the above method embodiment.

[0167] As shown in FIG. 7 , the PHY chip 700 includes an interface circuit 701 and a processing circuit 702 .

[0168] The interface circuit 701 is used to receive and / or send data, and the processing circuit 702 is used to process data.

[0169] In a specific example, the interface circuit 701 is used to obtain a first forward error correction FEC codeword sent by the second communication device;

[0170] The processing circuit 702 is used to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, where the first error correction capability indicates a maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates a maximum number of error symbols that can be detected in a cyclic code codeword.

[0171] For the specific implementation of the interface circuit 701 and the processing circuit 702, reference may be made to the relevant description of the above method embodiment, which will not be repeated here.

[0172] It should be noted that the hardware structures of the aforementioned data processing device 500, optical module 600 and PHY chip 700 can be the structure shown in FIG8 , which is a schematic structural diagram of a device provided in an embodiment of the present application.

[0173] As shown in Figure 8 , device 800 includes a processor 810, a communication interface 820, and a memory 830. The number of processors 810 in device 800 may be one or more, and Figure 8 illustrates a single processor as an example. In the embodiment of the present application, processor 810, communication interface 820, and memory 830 may be connected via a bus system or other means, and Figure 8 illustrates a connection via bus system 840 as an example.

[0174] Processor 810 may be a central processing unit (CPU), an NP, or a combination of a CPU and an NP. Processor 810 may further include a hardware chip. The hardware chip may be an ASIC, a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0175] Memory 830 may include volatile memory, such as random-access memory (RAM); non-volatile memory, such as flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); or a combination of these types of memory. Memory 830 may, for example, store the aforementioned first allocation relationship.

[0176] Optionally, the memory 830 stores an operating system and programs, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the programs may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks. The processor 810 can read the programs in the memory 830 to implement the data processing method provided in the embodiment of the present application.

[0177] Bus system 840 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. Bus system 840 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, FIG8 shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0178] An embodiment of the present application provides a computer-readable storage medium, including instructions or a computer program, which, when executed on a computer, enables the computer to execute the method described in the above method embodiment.

[0179] An embodiment of the present application provides a computer program product comprising instructions or a computer program, which, when executed on a computer, enables the computer to execute the method described in the above method embodiment.

[0180] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0181] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0182] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical business division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0183] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0184] In addition, each business unit in each embodiment of the present application can be integrated into a processing unit, each unit can exist physically separately, or two or more units can be integrated into a single unit. The above-mentioned integrated units can be implemented in the form of hardware or software business units.

[0185] If the integrated unit is implemented in the form of a software business unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0186] Those skilled in the art will appreciate that, in one or more of the above examples, the services described herein can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these services can be stored on a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transmission of computer programs from one location to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0187] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention.

[0188] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing method, characterized in that, The method includes: A first communication device obtains a first forward error correction (FEC) codeword sent by a second communication device; The first communication device decodes the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

2. The method according to claim 1, characterized in that, The first error correction capability is less than the first error detection capability.

3. The method according to claim 1 or 2, characterized in that, The first allocation relationship is determined according to the link quality between the first communication device and the second communication device.

4. The method according to claim 3, wherein The first allocation relationship meets the link quality requirement, and the method further includes: Reducing the first error correction capability in the first allocation relationship and increasing the first error detection capability in the first allocation relationship to obtain a second allocation relationship, where the second allocation relationship meets the link quality requirement.

5. The method according to claim 3 or 4, characterized in that The link quality includes: Link error rate, and / or, the number of data frame retransmissions.

6. The method according to claim 2, wherein The first communication device decodes the first FEC codeword according to the first allocation relationship, including: The first communication device corrects the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; The first communication device detects errors in the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

7. The method according to claim 6, wherein The first communication device detects errors in the second FEC codeword according to the second error detection capability, including: The first communication device calculates 2*P syndromes according to the second FEC codeword, where P corresponds to the second error detection capability; If all of the 2*P syndromes are 0, the first communication device determines that the second FEC codeword does not include an error codeword; or, If not all of the 2*P syndromes are 0, the first communication device determines that the second FEC codeword includes an error codeword.

8. The method according to any one of claims 1 to 7, characterized in that, The first FEC codeword is: Reed-Solomon (RS) code.

9. The method according to claim 8, characterized in that, The sum of the first error correction capability and the first error detection capability is equal to dmin - 1, where dmin is the minimum Hamming distance between RS codes.

10. The method according to claim 8, wherein If the first FEC codeword is RS(128, 120), then: The first error correction capability is 1 and the first error detection capability is 7; or, The first error correction capability is 2 and the first error detection capability is 6; or, The first error correction capability is 3 and the first error detection capability is 5; or, The first error correction capability is 4 and the first error detection capability is 4.

11. A data processing device, characterized in that, Applied to a first communication device, the first communication device includes a receiving unit and a processing unit; The receiving unit is configured to obtain a first forward error correction (FEC) codeword sent by a second communication device; The processing unit is configured to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, the first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

12. The device according to claim 11, characterized in that, The first error correction capability is less than the first error detection capability.

13. The device according to claim 11 or 12, characterized in that, The first allocation relationship is determined according to the link quality between the first communication device and the second communication device.

14. The device according to claim 13, characterized in that, The first allocation relationship meets the link quality requirement, and the processing unit is further configured to: Reduce the first error correction capability in the first allocation relationship and increase the first error detection capability in the first allocation relationship to obtain a second allocation relationship, where the second allocation relationship meets the link quality requirement.

15. The device according to claim 13 or 14, characterized in that, The link quality includes: Link error rate, and / or, the number of data frame retransmissions.

16. The device according to claim 12, characterized in that, The processing unit is configured to: Correct the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; Detect the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

17. The device according to claim 16, wherein The detecting the second FEC codeword according to the second error detection capability includes: Calculating 2*P syndromes according to the second FEC codeword, where P corresponds to the second error detection capability; If all of the 2*P syndromes are 0, determining that the second FEC codeword does not include an error codeword; or, If not all of the 2*P syndromes are 0, determining that the second FEC codeword includes an error codeword.

18. The device according to any one of claims 11-17, characterized in that, The first FEC codeword is: Reed Solomon (RS) code.

19. The device according to claim 18, characterized in that, The sum of the first error correction capability and the first error detection capability is equal to dmin - 1, where dmin is the minimum Hamming distance between RS codes.

20. The device according to claim 18, wherein, If the first FEC codeword is RS(128, 120), then: The first error correction capability is 1 and the first error detection capability is 7; or, The first error correction capability is 2 and the first error detection capability is 6; or, The first error correction capability is 3 and the first error detection capability is 5; or, The first error correction capability is 4 and the first error detection capability is 4.

21. A communication device, characterized in that, The communication device includes: an interface circuit and a processing circuit; The interface circuit is configured to obtain a first forward error correction (FEC) codeword sent by a second communication device; The processing circuit is configured to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, the first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

22. The communication device according to claim 21, wherein The communication device is: An optical module or a physical layer (PHY) chip.

23. A device, characterized in that, Including: A processor and a memory; The memory is configured to store instructions or computer programs; The processor is configured to execute the instructions or computer program and perform the method according to any one of claims 1-10.

24. A computer-readable storage medium, characterized in that, It includes instructions or a computer program which, when running on a computer, causes the computer to perform the method according to any one of claims 1-10 above.

25. A computer program product, characterized in that, It includes a computer program which, when running on a processor, performs the method according to any one of claims 1-10 above.

Images