Quantum bit mapping method and apparatus, and electronic device, computer-readable storage medium and computer program product

Abstract

A quantum bit mapping method and apparatus, and an electronic device, a computer-readable storage medium and a computer program product. The method comprises: acquiring a gate operation sequence used for executing target quantum computation, and a plurality of logical quantum bits, wherein each gate operation operator in the gate operation sequence is used for executing a gate operation on two logical quantum bits among the plurality of logical quantum bits; acquiring an initial mapping relationship, wherein the initial mapping relationship is used for mapping the plurality of logical quantum bits to a preset physical device, so as to obtain a plurality of first physical quantum bits; using a plurality of candidate adjustment modes to adjust the initial mapping relationship, so as to obtain a plurality of corresponding candidate mapping relationships, wherein the plurality of candidate mapping relationships are used for mapping the plurality of logical quantum bits to the physical device, and the plurality of candidate mapping relationships are different from the initial mapping relationship; using the plurality of candidate mapping relationships to respectively map the plurality of logical quantum bits to the physical device, so as to obtain a plurality of corresponding second physical quantum bit sets, wherein each second physical quantum bit set comprises a plurality of second physical quantum bits; for each candidate mapping relationship: for each gate operation operator, detecting whether two second physical quantum bits corresponding, on the basis of the candidate mapping relationship, to two logical quantum bits on which the gate operation operator executes the gate operation are adjacent on the physical device, so as to obtain a detection result, determining degrees of adaptation between the candidate mapping relationships and the gate operation sequence on the basis of a plurality of detection results correspondingly obtained by means of a plurality of gate operation operators, so as to obtain a plurality of degrees of adaptation corresponding to the plurality of candidate mapping relationships, and on the basis of the plurality of degrees of adaptation, obtaining, from among the plurality of candidate mapping relationships, a target mapping relationship conforming to a preset degree-of-adaptation condition; and using the target mapping relationship to map the plurality of logical quantum bits to the physical device, so as to obtain a plurality of target physical bit units.

Description

Quantum bit mapping method, device, electronic device, computer-readable storage medium, and computer program product

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on and claims the priority of Chinese patent application with application number 202410064675.6 and application date of January 16, 2024. The entire content of the Chinese patent application is hereby introduced into the embodiments of this application for reference. Technical Field

[0003] The present disclosure relates to the field of quantum technology, and in particular to a quantum bit mapping method, device, electronic device, computer-readable storage medium, and computer program product. Background Art

[0004] In quantum hardware, quantum bits are stored in qubit units, the basic unit for performing quantum computations. Quantum algorithms are often represented in the form of quantum circuits, which are generally assumed to be fully connected. However, on a real physical chip, qubits have limited connectivity and are constrained by the topology of the physical chip. Therefore, when executing a quantum algorithm, a qubit mapping strategy is often required to compensate for the limited connectivity of qubits on the physical chip. This quantum mapping strategy generally consists of two steps: the first is the initial mapping, which maps logical qubits to physical qubits; the second step is to add a controlled swap gate (i.e., a swap gate) during execution to exchange the mapping states of two logical qubits, thereby compensating for the connectivity between the individual qubits.

[0005] In the related art, there is basically no research on the initial mapping. In the mapping process, only direct mapping of quantum bits is used. This method will result in a large number of swap gates that need to be added, resulting in resource waste. It may also not be possible to use as few swap gates as possible to meet the requirements of bit mapping. Summary of the Invention

[0006] The embodiments of the present disclosure provide a quantum bit mapping method, apparatus, electronic device, computer-readable storage medium, and computer program product, which can reduce the number of swap gates required in the mapping process and improve the quality of bit mapping.

[0007] The present disclosure provides a quantum bit mapping method, which is applied to an electronic device. The method includes:

[0008] Obtaining a gate operation sequence for performing a target quantum computation and a plurality of logical qubits, wherein each gate operator in the gate operation sequence is used to perform a gate operation on two of the plurality of logical qubits;

[0009] Acquire an initial mapping relationship, where the initial mapping relationship is used to map the plurality of logical qubits to a preset physical device to obtain a plurality of first physical qubits;

[0010] Applying multiple candidate adjustment methods to adjust the initial mapping relationship to obtain multiple corresponding candidate mapping relationships, where the multiple candidate mapping relationships are used to map the multiple logical quantum bits to the physical device, and the multiple candidate mapping relationships are different from the initial mapping relationship;

[0011] Applying the multiple candidate mapping relationships, mapping the multiple logical qubits to the physical devices respectively to obtain corresponding multiple second physical qubit sets, wherein each second physical qubit set includes multiple second physical qubits;

[0012] For each candidate mapping relationship:

[0013] - for each of the gate operators, detecting whether the two logical qubits of the gate operator performing the gate operation are adjacent to the two second physical qubits corresponding to the candidate mapping relationship on the physical device, and obtaining a detection result;

[0014] - determining a degree of compatibility between the candidate mapping relationship and the gate operation sequence based on the plurality of detection results correspondingly obtained by the plurality of gate operation operators;

[0015] To obtain a plurality of the fitness degrees corresponding to the plurality of candidate mapping relationships;

[0016] Based on the multiple fitness degrees, obtaining a target mapping relationship that meets a preset fitness condition from the multiple candidate mapping relationships;

[0017] Applying the target mapping relationship, the multiple logical quantum bits are mapped to the physical device to obtain multiple target physical bit units.

[0018] The present disclosure provides a quantum bit mapping device, comprising:

[0019] an acquisition unit configured to acquire a gate operation sequence for performing a target quantum computation and a plurality of logical qubits, wherein each gate operator in the gate operation sequence is used to perform a gate operation on two of the plurality of logical qubits;

[0020] A first mapping unit is configured to obtain an initial mapping relationship, where the initial mapping relationship is used to map the plurality of logical qubits to a preset physical device to obtain a plurality of first physical qubits;

[0021] a generating unit configured to apply a plurality of candidate adjustment methods to adjust the initial mapping relationship to obtain a plurality of corresponding candidate mapping relationships, wherein the plurality of candidate mapping relationships are used to map the plurality of logical qubits to the physical device, and the plurality of candidate mapping relationships are different from the initial mapping relationship;

[0022] a determining unit configured to apply the multiple candidate mapping relationships to map the multiple logical qubits to the physical devices respectively, to obtain corresponding multiple second physical qubit sets, wherein each second physical qubit set includes multiple second physical qubits;

[0023] For each candidate mapping relationship:

[0024] - for each of the gate operators, detecting whether the two logical qubits of the gate operator performing the gate operation are adjacent to the two second physical qubits corresponding to the candidate mapping relationship on the physical device, and obtaining a detection result;

[0025] - determining a degree of compatibility between the candidate mapping relationship and the gate operation sequence based on the plurality of detection results correspondingly obtained by the plurality of gate operation operators;

[0026] To obtain a plurality of the fitness degrees corresponding to the plurality of candidate mapping relationships;

[0027] Based on the multiple fitness degrees, obtaining a target mapping relationship that meets a preset fitness condition from the multiple candidate mapping relationships;

[0028] The second mapping unit is configured to apply the target mapping relationship to map the multiple logical quantum bits to the physical device to obtain multiple target physical bit units.

[0029] An embodiment of the present disclosure provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the quantum bit mapping method described above when executing the computer program.

[0030] An embodiment of the present disclosure provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the quantum bit mapping method described above.

[0031] An embodiment of the present disclosure provides a computer program product, which includes a computer program. The computer program is read and executed by a processor of a computer device, so that the computer device executes the quantum bit mapping method described above.

[0032] The embodiments of the present disclosure provide a quantum computer operating system, which implements a quantum bit mapping program according to the quantum bit mapping method described above.

[0033] An embodiment of the present disclosure provides a quantum computer, which includes the quantum computer operating system described above.

[0034] In the embodiment of the present disclosure, when a quantum operation is required, a gate operation sequence and a plurality of logical qubits for executing the target quantum operation are first obtained, and an initial mapping relationship between the plurality of logical qubits and a plurality of first physical qubits of a physical device is obtained. Then, the initial mapping relationship is adjusted by applying a candidate adjustment method to obtain a plurality of corresponding candidate mapping relationships, so that various forms of mapping optimization can be adopted for the initial mapping relationship to obtain a more diverse candidate mapping relationship. Further, each candidate mapping relationship is applied to map the plurality of logical qubits to the physical device to obtain a second set of physical qubits including a plurality of second physical qubits, thereby determining, under each candidate mapping relationship, a target mapping relationship suitable for executing each gate operation in the gate operation sequence according to a plurality of fitness degrees, which can improve the matching accuracy of the logical qubit and the physical qubit. Finally, according to the target mapping relationship, the plurality of logical qubits are mapped to the physical device to obtain a plurality of target physical qubits. In summary, compared with the direct mapping in the related art, the embodiment of the present disclosure can provide a variety of optional mapping adjustment schemes, so as to determine a target mapping relationship corresponding to a mapping optimization scheme as the final mapping relationship according to the adaptability between each candidate mapping relationship and the gate operation sequence, and perform quantum bit mapping according to the final mapping relationship, which can reduce the number of swap gates that need to be added during the mapping process and improve the quality of bit mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0036] FIG1 is a diagram illustrating the architecture of a quantum computing system to which a quantum bit mapping method according to an embodiment of the present disclosure is applied;

[0037] FIG2A is a schematic diagram of a quantum bit mapping method of related art applied in a quantum bit mapping scenario;

[0038] FIG2B is a schematic diagram of an embodiment of the present disclosure applied in a quantum bit mapping scenario;

[0039] FIG3 is a flowchart of a quantum bit mapping method according to an embodiment of the present disclosure;

[0040] FIG4A is a schematic diagram of a gate operation sequence according to an embodiment of the present disclosure;

[0041] FIG4B is a schematic diagram of an initial mapping relationship according to an embodiment of the present disclosure;

[0042] 5 is a flowchart of determining multiple candidate adjustment methods for an initial mapping relationship according to an embodiment of the present disclosure;

[0043] FIG6 is a flowchart of determining multiple candidate swap gates according to an embodiment of the present disclosure;

[0044] FIG7A is a schematic diagram of an implementation process of exhaustively enumerating all candidate adjustment methods according to an embodiment of the present disclosure;

[0045] FIG7B is a schematic diagram of an implementation process of applying a candidate adjustment method to an initial mapping relationship to form a candidate mapping relationship according to an embodiment of the present disclosure;

[0046] FIG8 is a flowchart of determining a target mapping relationship according to an embodiment of the present disclosure;

[0047] FIG9 is a flowchart of determining a target mapping relationship according to an embodiment of the present disclosure;

[0048] FIG10 is a schematic diagram of an implementation process of determining a target mapping relationship according to an embodiment of the present disclosure;

[0049] FIG11 is a flowchart of determining a target mapping relationship according to an embodiment of the present disclosure;

[0050] FIG12 is a flowchart of adjusting an initial mapping relationship based on two physical qubits to be exchanged according to an embodiment of the present disclosure;

[0051] FIG13 is a schematic diagram of an implementation process of adjusting an initial mapping relationship based on two physical qubits to be exchanged according to an embodiment of the present disclosure;

[0052] FIG14 is a flowchart of determining the degree of compatibility between a plurality of mapped physical qubits and a gate operation sequence according to an embodiment of the present disclosure;

[0053] 15A-15B are schematic diagrams illustrating an implementation of determining a gate operation dependency graph in step 1410 in FIG. 14 ;

[0054] 16A-16B are schematic diagrams illustrating an implementation of determining the first gate operation and the second gate operation in step 1420 in FIG. 14 ;

[0055] FIG17 is a flowchart of determining the bit distance of the gate operation in step 430 of FIG14;

[0056] FIG18 is a flow chart of determining the degree of fitness in step 1440 of FIG14 ;

[0057] FIG19 is a flowchart of a quantum bit mapping method according to an embodiment of the present disclosure;

[0058] 20A-20B are detailed diagrams of the implementation of the quantum bit mapping method according to an embodiment of the present disclosure;

[0059] FIG21 is a module diagram of a quantum bit mapping device according to an embodiment of the present disclosure;

[0060] FIG22 is a terminal structure diagram of a quantum bit mapping method according to an embodiment of the present disclosure;

[0061] Figure 23 is a server structure diagram of the quantum bit mapping method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are not intended to limit the present disclosure.

[0063] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0064] Quantum computing: Quantum computing is a computing method designed using the principles of quantum mechanics. The key difference from traditional computing is that quantum computing uses quantum bits (qubits) rather than traditional binary bits. Qubits have distinct properties from traditional binary bits, the most important of which is that they can be in multiple states simultaneously. Because qubits can represent two states simultaneously, they carry more information. Using the same number of qubits, more data operations can be performed than with classical computing. Therefore, quantum computing significantly increases computer processing speed.

[0065] Quantum: The quantum in "quantum computing" refers to the smallest discrete unit a system can use to calculate output.

[0066] Qubit: The fundamental unit of information in quantum computing. Qubits play a role similar to bits in traditional computing, but they behave very differently.

[0067] A physical qubit, also known as a physical bit unit or quantum bit unit, is the physical carrier used in quantum computing devices to carry the logical qubits involved in the operation. It is also the basic physical entity used to perform quantum computing. For example, a physical qubit can be implemented by a variety of physical systems, such as superconducting circuits, ion traps, topological insulators, and quantum dots. Each physical system has its own unique physical properties and operation methods. A physical qubit can not only carry and represent quantum information but also directly participate in the operation of quantum logic gates, thereby realizing the computational process of quantum algorithms. In short, a physical qubit is the basic unit that carries quantum information, used to store quantum information until it is read or further operated on.

[0068] Swap Gate: In quantum computing, a swap gate is a two-qubit gate used to swap the states of two qubits. Specifically, a swap gate is used to swap the quantum states of two qubits.

[0069] In quantum hardware, quantum bits are stored in physical qubits as the basic unit to perform quantum computations. Currently, quantum algorithms are often represented in the form of quantum circuits, which are generally assumed to be fully connected. However, on a real physical chip, qubits have limited connectivity and are constrained by the topology of the physical chip. Therefore, when executing a quantum algorithm, a qubit mapping strategy is often required to compensate for the limited connectivity of qubits on the physical chip. This quantum mapping strategy generally consists of two steps: the first is the initial mapping, which is used to map logical qubits to physical qubits; the second step is to add a controlled swap gate (i.e., a swap gate) during execution to exchange the mapping states of two logical qubits, thereby compensating for the connectivity between the individual qubits.

[0070] In the related art, there is basically no research on the initial mapping. In the mapping process, only direct mapping of quantum bits is used. This method will result in a large number of swap gates being required, which may result in resource waste and may not meet the requirement of using as few swap gates as possible to achieve bit mapping.

[0071] Figure 1 is a diagram of the architecture of a quantum computing system used in the quantum bit mapping method according to an embodiment of the present disclosure. The quantum computing system includes a browser, a client, a quantum application, a quantum operating system, and quantum hardware resources.

[0072] Browsers and clients are executable programs used to generate quantum computing tasks. They typically run on terminals. Terminals include desktop computers, laptops, tablets, personal digital assistants (PDAs), mobile phones, and in-vehicle terminals. Quantum applications are deployed on quantum operating systems. The application's API (Application Programming Interface) receives quantum computing tasks. The task distribution system in quantum applications distributes quantum computing tasks to the quantum operating system. Quantum simulators within quantum applications can simulate the quantum computing of these tasks.

[0073] The quantum operating system (Qubit Operating System, QOS) is generally deployed in the cloud. The quantum operating system is generally installed on quantum hardware resources. The quantum operating system includes an intermediate representation, a quantum just-in-time compiler, a quantum cabin, resource configuration, isolation security, and resource checking. The intermediate representation serves as a common interface between quantum applications and the quantum operating system and can serve as an abstract representation of quantum computing tasks. The quantum just-in-time compiler (also known as quantum JIT, Qubit Just In Time) includes a task scheduling model and a topology compilation model, wherein the task scheduling model is used to perform task scheduling, and the topology compilation model is used to compile the scheduled tasks to obtain the quantum bit unit topology. The quantum cabin includes a checker and a database, wherein the checker is used to check quantum computing tasks, and the database is used to store data of quantum computing tasks, such as the quantum bit unit topology corresponding to the quantum computing task. Resource configuration is used to allocate virtualized resources for quantum computing tasks. Isolation security is used for data isolation and data security between the quantum operating system and quantum hardware resources. Resource checking is used to check quantum hardware resources for quantum computing tasks.

[0074] Quantum hardware resources are the physical space where quantum computing takes place. They are typically deployed in the cloud. They include two different types of Quantum Processing Units (QPUs): physical QPU1 and physical QPU2.

[0075] When a browser or client generates a task requiring quantum computing, it is first dispatched to the quantum operating system's task scheduling model via the quantum application's task distribution system. The quantum simulator within the quantum application can simulate the quantum computing of the task. The task is then scheduled by the task scheduling model within the quantum operating system. The task is then compiled using the topology compilation model to generate a qubit unit topology suitable for executing the task. A large number of qubit units are distributed across the quantum hardware resources. Adjacent physical qubits are connected via radio frequency beams, forming a network of qubit units.

[0076] As shown in Figure 2A, in the quantum bit mapping process of the related art, the physical device contains 9 physical quantum bits (referred to as physical bits). Among them, physical bit 0 is connected to physical bit 1 and physical bit 2 respectively; physical bit 2 is connected to physical bit 0, physical bit 5 and physical bit 3 respectively; physical bit 5 is connected to physical bit 2 and physical bit 8 respectively; physical bit 1 is connected to physical bit 0, physical bit 4 and physical bit 3 respectively; physical bit 3 is connected to physical bit 1, physical bit 6, physical bit 8 and physical bit 2 respectively; physical bit 7 is connected to physical bit 6 and physical bit 8 respectively; physical bit 6 is connected to physical bit 4, physical bit 3 and physical bit 7 respectively; physical bit 4 is connected to physical bit 1 and physical bit 6 respectively; physical bit 8 is connected to physical bit 3, physical bit 5 and physical bit 7 respectively. Based on this, multiple logical quantum bits (referred to as logical bits) in the quantum circuit are randomly mapped to the physical bits of the physical device. Among them, logical bit 7 is mapped to physical bit 4; logical bit 1 is mapped to physical bit 6; logical bit 0 is mapped to physical bit 7; logical bit 6 is mapped to physical bit 1; logical bit 5 is mapped to physical bit 3; logical bit 2 is mapped to physical bit 8; logical bit 8 is mapped to physical bit 0; logical bit 4 is mapped to physical bit 2; logical bit 3 is mapped to physical bit 5.

[0077] This method mainly uses direct mapping of quantum bits, randomly mapping the logical bits in the quantum circuit to the physical bits of the physical device, which often causes the problem of a large number of swap gates needing to be added.

[0078] Compared to related technologies, the embodiments of the present disclosure provide a solution that applies multiple adjustments to a given mapping relationship based on predetermined rules, forming multiple optimized mapping relationships, and then determines the final mapping relationship based on the optimal mapping relationship among the optimized mapping relationships. This solution can reduce the number of swap gates required during the mapping process. The embodiments of the present disclosure can be applied in various scenarios, such as the quantum bit mapping scenario shown in Table 1 and Figure 2B.

[0079] Table 1. Quantum bit mapping scenarios

[0080] As shown in Table 1, the logical bits in the quantum circuit are mapped to the physical bits of the physical device, with a search depth of 2. When there are n executable swap gates in the physical device, n×n different adjustment methods are generated according to predetermined rules. Each adjustment method adjusts the initial mapping relationship into a corresponding new mapping scheme. Next, the mapping score of each new mapping scheme is determined. Among the new mapping schemes corresponding to these n×n different adjustment methods, the new mapping scheme 3 with the highest mapping score is selected as the optimized solution for the given mapping relationship.

[0081] As shown in Figure 2B , new mapping scheme 3 indicates the execution of a swap gate between physical bits 1 and 0, and the execution of a swap gate between physical bits 4 and 6. According to new mapping scheme 3, multiple logical bits of the quantum circuit are mapped to physical bits on the physical device. For example, according to new mapping scheme 3, logical bit 1 is mapped to physical bit 4; logical bit 7 is mapped to physical bit 6; logical bit 0 is mapped to physical bit 7; logical bit 8 is mapped to physical bit 1; logical bit 5 is mapped to physical bit 3; logical bit 2 is mapped to physical bit 8; logical bit 6 is mapped to physical bit 0; logical bit 4 is mapped to physical bit 2; and logical bit 3 is mapped to physical bit 5.

[0082] According to an embodiment of the present disclosure, a quantum bit mapping method is provided.

[0083] This qubit mapping method is often used in qubit mapping scenarios such as those shown in Table 1 and Figure 2B. In related technologies, only direct mapping of qubits is used in the mapping process, which results in a large number of swap gates that need to be added. The disclosed embodiment adopts a solution that applies multiple adjustment methods to a given mapping relationship based on predetermined rules to form multiple optimized mapping relationships, and determines the final mapping relationship based on the optimal mapping relationship among the optimized mapping relationships. This solution can reduce the number of swap gates that need to be added in the mapping process and improve the quality of bit mapping.

[0084] As shown in FIG3 , the quantum bit mapping method according to an embodiment of the present disclosure may include:

[0085] Step 310: Obtain a gate operation sequence for performing a target quantum computation and a plurality of logical qubits, wherein each gate operator in the gate operation sequence is used to perform a gate operation on two logical qubits in the plurality of logical qubits;

[0086] Step 320: Obtain an initial mapping relationship, where the initial mapping relationship is used to map the multiple logical qubits to a preset physical device to obtain multiple first physical qubits;

[0087] Step 330: Apply multiple candidate adjustment methods to adjust the initial mapping relationship to obtain multiple corresponding candidate mapping relationships, where the multiple candidate mapping relationships are used to map the multiple logical qubits to physical devices, and the multiple candidate mapping relationships are different from the initial mapping relationship;

[0088] Step 340: Apply multiple candidate mapping relationships to map multiple logical qubits to physical devices respectively, and obtain corresponding multiple second physical qubit sets, wherein each second physical qubit set includes multiple second physical qubits; for each candidate mapping relationship: for each gate operator, detect whether two logical qubits on which the gate operator performs a gate operation are adjacent to two second physical qubits corresponding to the candidate mapping relationship on the physical device, and obtain a detection result; based on the multiple detection results corresponding to the multiple gate operators, determine the fitness between the candidate mapping relationship and the gate operation sequence to obtain multiple fitness levels corresponding to the multiple candidate mapping relationships; based on the multiple fitness levels, obtain a target mapping relationship that meets a preset fitness condition from the multiple candidate mapping relationships;

[0089] Step 350: Apply the target mapping relationship to map the multiple logical qubits to physical devices to obtain multiple target physical qubits.

[0090] Steps 310 - 350 are described in detail below.

[0091] In step 310 , a gate operation sequence for performing a target quantum computation and a plurality of logical qubits are obtained.

[0092] Among them, the logical quantum bit has the structure that a quantum bit should have mathematically or logically. It does not have to correspond to a specific physical medium. It is an ideal and abstract concept introduced to achieve fault tolerance in quantum computing.

[0093] Among them, the gate operation sequence for performing the target quantum calculation is used to indicate a series of gate operations that need to be performed in sequence. The execution of the gate operation corresponding to the gate operator in the gate operation sequence can realize quantum computing. Each gate operator in the gate operation sequence is used to perform a gate operation on two logical qubits in a plurality of logical qubits, that is, each gate operator in the gate operation sequence is applied to two logical qubits in a plurality of logical qubits. The gate operation in the embodiment of the present disclosure refers to a controlled NOT gate operation (CNOT gate). Among them, the controlled NOT gate operation (CNOT gate) in quantum computing is a quantum logic gate operation, which plays an extremely important role in quantum computing, similar to the logical NOT gate (NOT gate) in classical computing. In quantum computing, a controlled NOT gate operation is used to operate on two logical qubits, where one logical qubit is used as a control bit and the other logical qubit is used as a target bit. Specifically, the controlled NOT gate operation can be described as follows: if the control bit is in state |0> (representing 0), then the state of the target bit remains unchanged; if the control bit is in state |1> (representing 1), then the state of the target bit will change: if the target bit was originally |0>, the target bit becomes |1>; if the target bit was originally |1>, the target bit becomes |0>.

[0094] In the specific implementation of this embodiment, before executing each gate operation in the gate operation sequence, in order to reduce the number of swap gates that need to be added during the mapping process, the target object's separate permission or separate consent will be obtained through a pop-up window or jump to a confirmation page. After the target object's separate permission or separate consent is clearly obtained, the gate operation sequence and multiple logical quantum bits used to execute the target quantum calculation are obtained.

[0095] In step 320, an initial mapping relationship is obtained.

[0096] The physical devices in quantum computing refer to all the physical hardware and components that implement quantum computing functions, such as physical hardware chips and quantum computers. Physical hardware chips are the core of quantum computing, containing quantum bits and their control circuits. Physical hardware chips may use different technologies to implement quantum bits, such as superconducting circuits, ion traps, and quantum dots. Quantum computers contain physical hardware chips and all related equipment that supports the operation of physical hardware chips. Quantum computers may include multiple hardware chips as well as equipment for cooling, control, readout, and other auxiliary functions.

[0097] The initial mapping relationship is used to map multiple logical qubits to a pre-defined physical device, resulting in multiple first physical qubits. The first physical qubit refers to the physical qubit to which each logical qubit is mapped under the initial mapping relationship. It is the actual, fundamental unit of the physical device. For example, a first physical qubit can be a Josephson junction in a superconducting circuit, an ion energy level in an ion trap, and so on. These first physical qubits possess properties such as quantum superposition and quantum entanglement, and serve as the information carrier in quantum computing.

[0098] Among them, the mapping relationship between multiple logical quantum bits and multiple first physical quantum bits is the initial mapping relationship.

[0099] The initial mapping relationship in the embodiment of the present disclosure is a pre-set mapping relationship. The initial mapping relationship can be pre-set by relevant personnel or selected from multiple existing mapping relationships, without specific limitation.

[0100] To save space, the specific implementation process of mapping multiple logical qubits to multiple first physical qubits of a physical device in the embodiment of the present disclosure will be described in detail below and will not be repeated here.

[0101] In step 330, multiple candidate adjustment methods are applied to adjust the initial mapping relationship to obtain corresponding multiple candidate mapping relationships, where the multiple candidate mapping relationships are used to map multiple logical quantum bits to physical devices, and the multiple candidate mapping relationships are different from the initial mapping relationship.

[0102] For example, based on the first rule, multiple candidate adjustment methods for the initial mapping relationship are generated, wherein the first rule is used to limit the maximum number of swap gates added by the bit mapping transformer in the adjustment method for the initial mapping relationship, and to limit the search method for determining the adjustment method. Among them, the bit mapping transformer in quantum computing is a technology used in quantum computing for establishing an effective mapping relationship between the physical quantum bits and logical quantum bits of a quantum computer. The core of this technology is to optimize the arrangement and use of quantum bits to improve the execution efficiency and accuracy of quantum programs. Among them, the search method may include but is not limited to a heuristic search method based on depth restriction, a heuristic search method based on depth first, etc.

[0103] Among them, the candidate adjustment method is used to indicate the adjustment of the mapping relationship between the logical quantum bit and the first physical quantum bit in the initial mapping relationship. For example, the initial mapping relationship includes mapping relationship 1 between logical quantum bit 1 and physical quantum bit 1, mapping relationship 2 between logical quantum bit 2 and physical quantum bit 2, and mapping relationship 3 between logical quantum bit 3 and physical quantum bit 3. The candidate adjustment method indicates the adjustment of mapping relationship 1 and mapping relationship 2.

[0104] The candidate mapping relationship is a mapping relationship formed after adjusting some bit mapping relationships in the initial mapping relationship based on the candidate adjustment method.

[0105] To save space, the specific implementation process of generating multiple candidate adjustment methods for the initial mapping relationship based on the first rule in the disclosed embodiment, and the specific implementation process of adjusting the initial mapping relationship using the multiple candidate adjustment methods to obtain the corresponding multiple candidate mapping relationships will be described in detail below. Detailed description is not provided here.

[0106] In step 340, multiple candidate mapping relationships are applied to respectively map multiple logical qubits to physical devices to obtain corresponding multiple second physical qubit sets, wherein each second physical qubit set includes multiple second physical qubits; for each candidate mapping relationship: for each gate operator, detect whether the two logical qubits on which the gate operator performs a gate operation are adjacent to the two second physical qubits corresponding to the candidate mapping relationship on the physical device, and obtain a detection result; based on the multiple detection results correspondingly obtained by the multiple gate operators, determine the fitness between the candidate mapping relationship and the gate operation sequence to obtain multiple fitnesses corresponding to the multiple candidate mapping relationships; based on the multiple fitnesses, obtain a target mapping relationship that meets the preset fitness conditions from the multiple candidate mapping relationships.

[0107] Here, we need to clarify the difference between a mapping relationship and a mapping process. The mapping relationship refers to the mathematical rules between logical qubits and physical qubits. It is a static, design-level concept, and the mapping relationship is a pre-designed possible correspondence. The mapping process, on the other hand, is the dynamic process of implementing the mapping relationship on a physical device. The mapping process is the practical application of the mapping relationship and involves the operational aspects of the quantum computer, including hardware control, data reading, and state identification. The mapping relationship provides the rules and blueprint for the mapping process and serves as its foundation. The mapping process is the specific steps to implement the mapping relationship, enabling the logical qubits to be realized on the physical device. In short, the mapping relationship is at the theoretical and design level, while the mapping process is at the practical and implementation level. The two complement each other to achieve reliable and efficient quantum computing.

[0108] The second physical qubit refers to the physical qubit obtained after mapping multiple logical qubits to the physical device according to the candidate mapping relationship. That is, the second physical qubit is a physical qubit in the physical device that has established a real connection with the logical qubit (i.e., an actual physical qubit), so that the logical operation implemented by the logical qubit can be implemented on the physical device. In other words, before the multiple logical qubits are mapped to the physical device, the physical qubits in the physical device have not established a real connection with the logical qubits. Only a digital simulation candidate mapping relationship has been pre-designed for the physical qubits and the logical qubits. It should be noted that before the multiple logical qubits are mapped to the physical device, the physical qubits on the physical device are merely physical carriers on the physical device and have not yet established a real connection with the logical qubits. Therefore, actual quantum computing cannot be performed based on the logical qubits. After the multiple logical qubits are mapped to the physical device to obtain multiple second physical qubits, the second physical qubits can not only represent the physical carriers on the physical device (have a connection relationship with other physical qubits on the physical device), but also can perform actual quantum computing through the logical qubits that have established a real connection with the second physical qubits.

[0109] The degree of fitness refers to the degree of match between the second physical qubit obtained based on the candidate mapping relationship and the two logical qubits of the gate operation performed by each gate operator in the gate operation sequence. The greater the degree of fitness, the greater the probability that the mapping relationship between the logical qubit indicated by the candidate mapping relationship and the second physical qubit will enable the normal execution of each gate operation in the gate operation sequence. The normal execution of each gate operation in the gate operation sequence is determined by the connection relationship between the physical qubits (also known as physical carriers) in the physical device. The specific judgment process is described in detail below.

[0110] Among them, the target mapping relationship is used to indicate the final mapping relationship between the logical quantum bits in the gate operation sequence and the physical quantum bits in the physical device.

[0111] In the specific implementation of this embodiment, first, for each candidate mapping relationship, multiple logical qubits are mapped to a physical device based on the correspondence between the logical qubits and the physical qubits indicated by the candidate mapping relationship, thereby obtaining multiple second physical qubits under the candidate mapping relationship. Next, for each candidate mapping relationship: for each gate operator, it is detected whether the two logical qubits on which the gate operator performs the gate operation are adjacent to each other on the physical device based on the two second physical qubits corresponding to the candidate mapping relationship, and a detection result is obtained. Based on the multiple detection results correspondingly obtained by the multiple gate operators, the degree of compatibility between the candidate mapping relationship and the gate operation sequence is determined. Finally, the candidate mapping relationships are screened according to the degree of compatibility, and the target mapping relationship is determined based on the screening of the candidate mapping relationships.

[0112] To save space, the specific implementation process of obtaining a target mapping relationship that meets the preset fitness condition from multiple candidate mapping relationships based on multiple fitness levels in the embodiment of the present disclosure will be described in detail below.

[0113] In step 350, a target mapping relationship is applied to map the plurality of logical qubits to physical devices to obtain a plurality of target physical qubits.

[0114] Among them, the target physical qubit is the physical qubit in the physical device to which each logical qubit is to be mapped under the target mapping relationship, that is, the target physical qubit refers to the physical qubit to which the logical qubit ultimately needs to be mapped based on the execution of the above steps 330-340.

[0115] In a specific implementation of this embodiment, when executing each gate operation of a gate operation sequence, each logical qubit in the gate operation sequence is mapped to a target physical qubit, so that each gate operation can perform a corresponding quantum calculation according to the correspondence between the logical qubit and the target physical qubit.

[0116] Through the above steps 310-350, the embodiment of the present disclosure first obtains a gate operation sequence and multiple logical qubits for performing the target quantum calculation, and obtains an initial mapping relationship between the multiple logical qubits and the multiple first physical qubits of the physical device. Then, the candidate adjustment method is applied to adjust the initial mapping relationship to obtain multiple corresponding candidate mapping relationships, so that various forms of mapping optimization can be adopted for the initial mapping relationship to obtain a more diverse candidate mapping relationship. Further, each candidate mapping relationship is applied to map the multiple logical qubits to the physical device to obtain a second physical qubit set including multiple second physical qubits, thereby determining the target mapping relationship suitable for performing each gate operation in the gate operation sequence according to multiple fitness degrees under each candidate mapping relationship, which can improve the matching accuracy of the logical qubit and the physical qubit. Finally, according to the target mapping relationship, the multiple logical qubits are mapped to the physical device to obtain multiple target physical qubits. In summary, compared with the direct mapping in the related art, the embodiment of the present disclosure can provide a variety of optional mapping adjustment schemes, so as to determine a target mapping relationship corresponding to a mapping optimization scheme as the final mapping relationship according to the adaptability between each candidate mapping relationship and the gate operation sequence, and perform quantum bit mapping according to the final mapping relationship, which can reduce the number of swap gates that need to be added during the mapping process and improve the quality of bit mapping.

[0117] The above is a general description of steps 310-350. Step 310 and step 350 have been described in detail above. The specific implementation process of step 320, step 330, and step 340 will be described in detail below.

[0118] In step 320, an initial mapping relationship is obtained.

[0119] Among them, after obtaining the initial mapping relationship, each logical qubit is mapped to a physical device according to the initial mapping relationship to obtain a first physical qubit. The first physical qubit refers to the physical qubit obtained after mapping multiple logical qubits to the physical device according to the initial mapping relationship, that is, the first physical qubit is a physical qubit (that is, an actual physical qubit) in the physical device that has established a real connection with the logical qubit, so that the logical operation implemented by the logical qubit can be implemented on the physical device. In other words, before mapping multiple logical qubits to the physical device, the physical qubits and the logical qubits in the physical device do not establish a real connection, but only a digital simulation initial mapping relationship is pre-designed for the physical qubits and the logical qubits. Among them, according to the initial mapping relationship, each logical qubit has a unique corresponding first physical qubit in the physical device. One first physical qubit will only correspond to one logical qubit.

[0120] As shown in Figure 4A, Figure 4A is a schematic diagram of a gate operation sequence. The gate operation sequence [g0, g1, g2, g3, g4] contains five gate operators that need to be executed in sequence. Among them, gate operator g0 is applied to logical qubit q2 and logical qubit q3; gate operator g1 is applied to logical qubit q0 and logical qubit q2; gate operator g2 is applied to logical qubit q2 and logical qubit q4; gate operator g3 is applied to logical qubit q2 and logical qubit q5; gate operator g4 is applied to logical qubit q1 and logical qubit q2.

[0121] As shown in Figure 4B, the initial mapping relationship between logical qubits and physical qubits is shown. The logical qubit is represented as q, and the first physical qubit is represented as Q. Based on the initial mapping relationship, the logical qubit q0 is mapped to the first physical qubit Q7; the logical qubit q1 is mapped to the first physical qubit Q6; the logical qubit q2 is mapped to the first physical qubit Q8; the logical qubit q3 is mapped to the first physical qubit Q 10 ; Map the logical quantum bit q4 to the first physical quantum bit Q9; Map the logical quantum bit q5 to the first physical quantum bit Q3.

[0122] In the disclosed embodiments, after mapping multiple logical qubits to physical devices to obtain multiple first physical qubits, in order to determine whether the initial mapping relationship can enable each gate operation in the gate operation sequence to be properly executed, it is necessary to determine the executable gate operation set corresponding to the gate operation sequence based on the aforementioned mapping. The executable gate operation set is the set formed by the gate operation operators that can be executed in the gate operation sequence.

[0123] It should be noted that for a gate operator, if the gate operations corresponding to all gate operators preceding it in the gate operation sequence are executable, and the two logical qubits applied to the gate operator are mapped to the physical device, resulting in two adjacent first physical qubits in the physical device, then the gate operation corresponding to the gate operator is considered executable. If the gate operations corresponding to all gate operators preceding it in the gate operation sequence are executable, but the two logical qubits applied to the gate operator are mapped to the physical device, resulting in two adjacent first physical qubits in the physical device, or if the gate operator is placed after a gate operator that cannot execute a gate operation, then the gate operation corresponding to the gate operator is considered unexecutable.

[0124] In the disclosed embodiments, a scheme for determining whether individual gate operations are executable based on bit distance is introduced, which can improve the efficiency and accuracy of determining the set of executable gate operations. The bit distance in quantum computing refers to the physical distance between qubits, which is directly related to the ability of qubits to interact and communicate with each other. In a quantum computer, qubits are the basic units for implementing quantum information processing, and bit distance affects the efficiency and reliability of quantum computing.

[0125] In some embodiments, for any gate operation g = (q, q′) in the gate operation sequence, when the logical quantum bit is mapped to the physical device according to the initial mapping relationship, and the first physical quantum bit is recorded as mapping π, the bit distance of the gate operation g can be expressed as shown in formula (1): dist(g, π) = dist AG (π(q),π(q′)) Formula (1)

[0126] Where dist(g,π) refers to the bit distance of gate operation g, π(q) refers to the first physical qubit mapped from the logical qubit q in gate operation g to the physical device AG according to the initial mapping relationship, and π(q′) refers to the first physical qubit mapped from the logical qubit q′ in gate operation g to the physical device AG according to the initial mapping relationship. AG (π(q), π(q′)) represents the physical distance between the first physical qubit on the physical device AG mapped to the computational logical qubit q according to the initial mapping relationship and the first physical qubit on the physical device AG mapped to the logical qubit q′ according to the initial mapping relationship.

[0127] Based on this, the logical quantum bit is represented as q, the first physical quantum bit is represented as Q, and the physical distance between adjacent first physical quantum bits is 1. The logical quantum bits applied to each gate operation in the gate operation sequence in Figure 4A are mapped to the physical device AG according to the initial mapping relationship in Figure 4B, and the bit distances of each gate operation are obtained: dist(g0,π)=dist AG (π(q2),π(q3))=dist AG (Q8,Q 10 )=1; dist(g1,π)=dist AG (π(q0),π(q2))=dist AG (Q7, Q8)=1; dist(g2, π)=dist AG (π(q2),π(q4))=dist AG (Q8, Q9) = 1; dist (g3, π) = dist AG (π(q2),π(q5))=distAG (Q8, Q3) = 1; dist (g4, π) = dist AG (π(q1),π(q2))=dist AG (Q6, Q8)=2.

[0128] Based on this, the executable gate operation set corresponding to the gate operation sequence is [g0, g1, g2, g3], that is, the number of executable gates of the gate operation sequence is 4.

[0129] Since each of the above-mentioned logical qubits has a physical qubit that can be mapped to it in the physical device AG according to the initial mapping relationship, the above-mentioned mapping can be called a complete mapping.

[0130] Based on this, for each gate operation under complete mapping, the bit distance of the gate operation is dist(g,π)=dist AG (π(q),π(q′)).

[0131] This embodiment maps multiple logical qubits to multiple first physical qubits of a physical device based on an initial mapping relationship. Furthermore, a scheme that uses bit distance to determine whether each gate operation is executable under the initial mapping relationship is introduced, which can improve the efficiency and accuracy of determining the set of executable gate operations.

[0132] In step 330, multiple candidate adjustment methods are applied to adjust the initial mapping relationship to obtain corresponding multiple candidate mapping relationships, where the multiple candidate mapping relationships are used to map multiple logical quantum bits to physical devices, and the multiple candidate mapping relationships are different from the initial mapping relationship.

[0133] Since the goal of the embodiment of the present disclosure is to determine a target mapping relationship that can execute the gate operations corresponding to all gate operators of the gate operation sequence. Based on this, according to the initial mapping relationship, each logical quantum bit is mapped to a physical device to obtain a first physical quantum bit. When it is determined based on the first physical quantum bit that the executable gate operation set corresponding to the gate operation sequence does not contain all the gate operators, it indicates that the initial mapping relationship cannot enable all gate operations of the gate operation sequence to be executed normally, and the initial mapping relationship needs to be optimized and adjusted. Therefore, the embodiment of the present disclosure can determine a plurality of candidate adjustment methods for the initial mapping relationship based on the first rule, and determine the candidate mapping relationship formed by adjusting the initial mapping relationship based on each candidate adjustment method.

[0134] The first rule of the disclosed embodiment is used to limit the maximum number of swap gates that can be added by the bitmap converter in a candidate adjustment method and to determine multiple candidate adjustment methods using a depth-limited heuristic search method. In the depth-limited heuristic search, the maximum number of swap gates that can be added by the bitmap converter in a candidate adjustment method is represented by a set search depth.

[0135] The setting of the search depth is used to indicate the number of levels when exhaustively enumerating all candidate adjustment methods through a heuristic search method. In the field of quantum computing, a heuristic search method based on depth restriction is an optimization method that combines the characteristics of quantum computing with traditional heuristic search strategies. The heuristic search method based on depth restriction mainly utilizes the parallelism of quantum computing and the guidance of heuristic search to improve search efficiency and solution quality. That is, quantum computing can use quantum bits (qubits) for calculations and can represent multiple states simultaneously, thereby achieving parallel processing and high-speed computing. Heuristic search can use heuristic information to guide the search direction during the search process, reduce unnecessary search space, and speed up the process of finding the optimal solution. The depth-limited heuristic search method sets a search depth during the quantum search process to limit the search depth to avoid the time overhead caused by unlimited depth search. It also uses a heuristic function to evaluate each state to determine which paths are more likely to be solutions, and then performs a depth-limited search on these paths. The heuristic search method based on depth limit specifically includes the following application steps: 1. Use quantum bits to represent the state space of the problem, and each quantum bit can represent multiple states at the same time; 2. Evaluate each state through the heuristic function to assess its probability of approaching the target state; 3. Use quantum superposition to explore multiple states simultaneously, and select the state with the highest probability through quantum measurement; 4. Perform depth-limited search on the selected state until the predetermined depth is reached or a solution is found; 5. Verify the search results (such as candidate adjustment methods). If they do not meet the requirements, adjust the heuristic function or depth limit and repeat the search process. In short, the application of heuristic search methods based on depth limit in quantum computing combines the powerful computing power of quantum computers with the intelligent guidance of heuristic search, providing an efficient method for solving complex optimization problems.

[0136] Referring to FIG. 5 , in one embodiment, based on the first rule, a process of generating multiple candidate adjustment methods for the initial mapping relationship includes but is not limited to the following steps 510 - 530 :

[0137] Step 510: Determine multiple candidate switch gates in the physical device;

[0138] Step 520: combining multiple candidate exchange gates based on the set search depth to obtain multiple bit position exchange modes;

[0139] Step 530: Determine multiple candidate adjustment methods for the initial mapping relationship based on multiple bit position exchange methods.

[0140] Steps 510 - 530 are described in detail below.

[0141] In step 510, a plurality of candidate switch gates are determined in a physical device.

[0142] The candidate swap gate refers to a swap gate that can be executed in a physical device.

[0143] Referring to FIG. 6 , in some embodiments, step 510 is implemented by:

[0144] Step 610: Determine a connection relationship between a plurality of first physical quantum bits in a physical device;

[0145] Step 620: Determine multiple candidate switch gates based on multiple connection relationships.

[0146] The connection relationship between multiple first physical qubits represents the connection relationship between first physical qubits in the physical device. If two first physical qubits are adjacent, they are connected and can be connected through the action of the radio frequency beam. As shown in Figure 2A, the physical device contains nine first physical qubits, each of which contains qubits participating in the operation. Physical bit 0 is connected to physical bit 1 and physical bit 2; physical bit 2 is connected to physical bit 0, physical bit 5, and physical bit 3; physical bit 5 is connected to physical bit 2 and physical bit 8; physical bit 1 is connected to physical bit 0, physical bit 4, and physical bit 3; physical bit 3 is connected to physical bit 1, physical bit 6, physical bit 8, and physical bit 2; physical bit 7 is connected to physical bit 6 and physical bit 8; physical bit 6 is connected to physical bit 4, physical bit 3, and physical bit 7; physical bit 4 is connected to physical bit 1 and physical bit 6; and physical bit 8 is connected to physical bit 3, physical bit 5, and physical bit 7. Based on this, multiple logical bits in the quantum circuit are randomly mapped to physical bits of the physical device.

[0147] For example, first, the connection relationship between multiple first physical qubits is determined in the physical device, and an edge is determined between each of the connected first physical qubits, using the edge to represent the connection relationship between the first physical qubits. Next, each edge is used as an executable swap gate to obtain multiple candidate swap gates for the physical device.

[0148] For example, for Figure 4B, based on the initial mapping relationship, it is determined that the physical device contains 12 first physical quantum bits, and 15 edges are formed between the first physical quantum bits. Therefore, there are 15 candidate swap gates. These 15 candidate swap gates are swap(2,1), swap(1,3), swap(1,4), swap(1,0), swap(0,11), swap(11,3), swap(11,10), swap(10,8), swap(8,3), swap(8,9), swap(8,7), swap(7,6), swap(6,3), swap(6,5), and swap(6,4).

[0149] In step 520, multiple candidate swap gates are combined based on the set search depth to obtain multiple bit position swap modes.

[0150] Among them, the bit position exchange method is used to indicate the logical quantum bits whose mapping positions are to be exchanged.

[0151] For example, according to the heuristic search method, a search depth k (k is a positive integer) is set. The bit position exchange indicated by each candidate exchange gate is first considered as a bit position exchange method. This type of bit position exchange method only contains one candidate exchange gate. Then, based on the aforementioned bit position exchange, the bit position exchange indicated by each candidate exchange gate is again incorporated to obtain another type of bit position exchange method. This type of bit position exchange method contains two candidate exchange gates. Further, based on the aforementioned bit position exchange, the bit position exchange indicated by each candidate exchange gate is once again incorporated to obtain another type of bit position exchange method. This type of bit position exchange method contains three candidate exchange gates. And so on. Under the previously generated bit position exchange combination, the bit position exchange indicated by each candidate exchange gate is once again incorporated to generate a new bit position exchange combination. This new bit position exchange combination is then used as a new bit position exchange method. This continues until each new type of bit position exchange method contains k candidate exchange gates, and the combination generation operation is terminated.

[0152] In the embodiment of the present disclosure, when there are n candidate exchange gates in the physical device and the search depth is set to k, there are k bit position exchange modes. 1 +k 2 +…+k n Where n and k are both positive integers.

[0153] In step 530 , multiple candidate adjustment methods for the initial mapping relationship are determined based on multiple bit position swapping methods.

[0154] In the specific implementation of this embodiment, each bit position exchange method is regarded as a candidate adjustment method for the initial mapping relationship.

[0155] For example, with respect to FIG4B above, when the predetermined search depth is determined to be 2, there are 15+15×15=240 candidate adjustment methods, including swap(1,2), swap(1,3), swap(7,8),…, swap(7,8)+swap(1,2). Among them, the candidate adjustment method swap(1,2) is used to indicate that the logical qubits corresponding to physical qubit 1 and physical qubit 2 are mapped and swapped. The candidate adjustment method swap(7,8)+swap(1,2) is used to indicate that the logical qubits corresponding to physical qubit 7 and physical qubit 8 are mapped and swapped first, and then the logical qubits corresponding to physical qubit 1 and physical qubit 2 are mapped and swapped.

[0156] As shown in FIG7A , the generation of multiple candidate adjustment methods for the initial mapping relationship based on the first rule is regarded as a tree structure construction process. When the search depth is set to 3, it means that the depth of the constructed tree structure is 3, and the maximum number of swap gates added by the bit mapping converter in the candidate adjustment method is 3. Therefore, the number of swap gates indicated to be added in the candidate adjustment method can be 1, 2, or 3. For example, in the first round of determining multiple candidate adjustment methods for the initial mapping relationship, first, all candidate swap gates are listed one by one as nodes of the first level. Each node of the first level indicates a candidate adjustment method, and the candidate adjustment methods indicated by the nodes of the first level all have only one swap gate. For example, the candidate adjustment methods indicated by the nodes of the first level are swap (1, 2), ..., swap (7, 8). Then, under each node of the first level, all candidate swap gates are listed again, and the listed candidate swap gates are used as nodes of the second level. Among them, the combination of each second-level node and the node of the previous level indicates a candidate adjustment method, and the candidate adjustment method indicated by the combination of each second-level node and the node of the previous level includes 2 swap gates. For example, the candidate adjustment methods including 2 swap gates are swap(1,2)+swap(1,2), swap(1,2)+swap(7,8),…, swap(7,8)+swap(1,2),…, swap(7,8)+swap(7,8). Further, under each node of the first level and the second level, all candidate swap gates are listed again, and the listed candidate swap gates are used as each node of the third level. Among them, the combination of each third-level node and the nodes of all levels above it indicates a candidate adjustment method, and the candidate adjustment method indicated by the combination of each third-level node and the nodes of all levels above it includes 3 swap gates. For example, the candidate adjustment methods including three swap gates are swap(1,2)+swap(1,2)+swap(1,2), ..., swap(7,8)+swap(7,8)+swap(7,8). For all the above candidate mapping methods, it is determined whether there is a candidate mapping relationship corresponding to the candidate mapping method so that the gate operations corresponding to all gate operation operators in the gate operation sequence in Figure 4A are executed normally. If not, the candidate mapping method corresponding to the candidate mapping relationship with the largest fitness (swap(7,8)+swap(1,2)+swap(7,8)) is selected, and the initial mapping relationship is updated by adding three swap gates in the form of swap(7,8)+swap(1,2)+swap(7,8) to obtain a new initial mapping relationship. Based on the new initial mapping relationship, the next round of determining multiple candidate adjustment methods for the initial mapping relationship is carried out.Repeat the above method, from top to bottom, to determine the candidate adjustment method containing one swap gate, the candidate adjustment method containing two swap gates, and the candidate adjustment method containing three swap gates, until a candidate mapping relationship corresponding to a candidate adjustment method is found that can enable the gate operations corresponding to all gate operators in the gate operation sequence to be executed normally.

[0157] As shown in FIG7B , a candidate mapping relationship corresponding to one of the candidate adjustment methods, swap(1, 3)+swap(4, 6), for the initial mapping relationship (as shown in FIG4B ) is shown. For example, according to the candidate adjustment method, the logical qubits corresponding to physical qubit 1 and physical qubit 3 are first mapped and swapped, and then the logical qubits corresponding to physical qubit 4 and physical qubit 6 are mapped and swapped. Based on this, according to the candidate mapping relationship, logical qubit 5 in the gate operation sequence will change from being mapped to the first physical qubit 3 on the physical device to being mapped to the first physical qubit 1; logical qubit 6 will change from being mapped to the first physical qubit 1 on the physical device to being mapped to the first physical qubit 3; logical qubit 9 will change from being mapped to the first physical qubit 4 on the physical device to being mapped to the first physical qubit 6; and logical qubit 1 will change from being mapped to the first physical qubit 6 on the physical device to being mapped to the first physical qubit 4.

[0158] This embodiment combines all executable swap gates in the physical device in accordance with the set search depth in the first rule using a depth-limited heuristic search method, and exhaustively enumerates all combinations. Each exhaustively enumerated combination is used as a candidate adjustment method, which can maximize the determination of the adjustment method of the initial mapping relationship, increase the diversity of optimization methods for the initial mapping relationship, and thus improve the accuracy of mapping optimization.

[0159] In step 340, multiple candidate mapping relationships are applied to respectively map multiple logical qubits to physical devices to obtain corresponding multiple second physical qubit sets, wherein each second physical qubit set includes multiple second physical qubits; for each candidate mapping relationship: for each gate operator, detect whether the two logical qubits on which the gate operator performs a gate operation are adjacent to the two second physical qubits corresponding to the candidate mapping relationship on the physical device, and obtain a detection result; based on the multiple detection results correspondingly obtained by the multiple gate operators, determine the fitness between the candidate mapping relationship and the gate operation sequence to obtain multiple fitnesses corresponding to the multiple candidate mapping relationships; based on the multiple fitnesses, obtain a target mapping relationship that meets the preset fitness conditions from the multiple candidate mapping relationships.

[0160] In the specific implementation of this embodiment, under a candidate mapping relationship, since one logical qubit corresponds to one second physical qubit, multiple second physical qubits are obtained by mapping multiple logical qubits to physical devices according to a candidate mapping relationship. Therefore, each candidate mapping relationship will generate multiple second physical qubits, that is, a set of second physical qubits.

[0161] For each candidate mapping relationship: for each gate operator, detect whether the two logical quantum bits of the gate operator performing the gate operation are adjacent on the physical device based on the two second physical quantum bits corresponding to the candidate mapping relationship, and obtain a detection result; based on the multiple detection results correspondingly obtained by multiple gate operators, determine the fitness between the candidate mapping relationship and the gate operation sequence, thereby obtaining multiple fitnesses corresponding to multiple candidate mapping relationships, wherein the candidate mapping relationship and the fitness are in one-to-one correspondence; based on the multiple fitnesses corresponding to the multiple candidate mapping relationships, obtain a target mapping relationship that meets the preset fitness conditions from the multiple candidate mapping relationships.

[0162] As an example, the gate operation sequence includes gate operator 1 (applied to logical qubit 1 and logical qubit 2, that is, gate operation is performed on logical qubit 1 and logical qubit 2) and gate operator 2 (applied to logical qubit 3 and logical qubit 4, that is, gate operation is performed on logical qubit 3 and logical qubit 4). For a candidate mapping relationship, the logical qubit 1 and the logical qubit 2 on which gate operation is performed by gate operator 1 are first determined based on the two second physical qubits (that is, physical qubit 1 and physical qubit 2) corresponding to the candidate mapping relationship, and the gate operation sequence is determined based on the gate operator 2. The logical qubit 3 and the logical qubit 4 of the operation are based on the two second physical qubits (i.e., physical qubit 3 and physical qubit 4) corresponding to the candidate mapping relationship; then, the physical qubit 1 and the physical qubit 2 are detected to see whether they are adjacent on the physical device, and the detection result obtained by the gate operator 1 is obtained; the physical qubit 3 and the physical qubit 4 are detected to see whether they are adjacent on the physical device, and the detection result obtained by the gate operator 2 is obtained; then, based on the two detection results obtained by the gate operator 1 and the gate operator 2 respectively, the adaptability between the candidate mapping relationship and the gate operation sequence is determined.

[0163] Since the degree of fitness between each candidate mapping relationship and the gate operation sequence is used to indicate the execution of the gate operation of the gate operation sequence under the influence of the candidate mapping relationship. When the fitness is greater, it indicates that there are more gate operations that can be executed in the gate operation sequence. Therefore, it can be understood that when all gate operations in the gate operation sequence can be executed, the fitness is the largest, and the fitness that enables all gate operations in the gate operation sequence to be executed will be a fixed value. Based on this, the embodiment of the present disclosure provides a solution for obtaining a target mapping relationship that meets the preset fitness conditions from multiple candidate mapping relationships based on multiple fitnesses, which can more conveniently determine the target mapping relationship that meets the requirements and improve the efficiency of determining the mapping relationship.

[0164] Referring to FIG. 8 , in some embodiments, the fitness condition is to reach a first value (i.e., a fixed value). Based on multiple fitness degrees, a process of obtaining a target mapping relationship that meets the preset fitness condition from multiple candidate mapping relationships includes, but is not limited to, the following steps 810-820:

[0165] Step 810: Determine whether at least one degree of fitness corresponding to at least one candidate mapping relationship reaches a first value;

[0166] Step 820: Determine a target mapping relationship from at least one candidate mapping relationship.

[0167] Steps 810-820 are described in detail below.

[0168] In step 810 , it is determined whether at least one degree of adaptation corresponding to at least one candidate mapping relationship reaches a first value.

[0169] In the embodiment of the present disclosure, the first value is predetermined, and may be a fixed value preset based on engineering practice experience, or may be obtained through predictive analysis using a corresponding neural network model, which is not limited herein.

[0170] In a specific implementation of this embodiment, first, the degree of compatibility between each candidate mapping relationship and the gate operation sequence is determined. Next, candidate mapping relationships whose degree of compatibility reaches a first value are determined. If there is a candidate mapping relationship whose degree of compatibility between the gate operation sequence is greater than or equal to the first value, then at least one degree of compatibility corresponding to at least one candidate mapping relationship is determined to have reached the first value.

[0171] To save space, the specific implementation process of determining the adaptability of each candidate mapping relationship to the gate operation sequence in the embodiment of the present disclosure will be described in detail below and will not be repeated here.

[0172] In step 820 , a target mapping relationship is determined from at least one candidate mapping relationship.

[0173] During the specific implementation of this embodiment, since the at least one candidate mapping relationship mentioned above can enable all gate operations of the gate operation sequence to be executed, one of the at least one candidate mapping relationship can be randomly selected as the target mapping relationship.

[0174] In another embodiment, since the above-mentioned at least one candidate mapping relationship is obtained by applying different candidate adjustment methods to the initial mapping relationship, the number of swap gates required to be added for different candidate adjustment methods may be different. Therefore, among the at least one candidate mapping relationship, the candidate mapping relationship that indicates the least number of swap gates to be added in the candidate adjustment method corresponding to the candidate mapping relationship can be selected as the target mapping relationship.

[0175] This embodiment determines whether any candidate mapping relationships among the generated candidate mapping relationships enable execution of the gate operations corresponding to all gate operators in the gate operation sequence based on whether the degree of adaptability reaches a first value, thereby conveniently determining a candidate mapping relationship that meets the requirements. Furthermore, among the candidate mapping relationships that enable execution of the gate operations corresponding to all gate operators in the gate operation sequence, a target mapping relationship is quickly selected, thereby improving the efficiency of determining the mapping relationship.

[0176] In practical applications, there are often multiple candidate mappings generated, but none of them can execute all the gate operations corresponding to the gate operators in the gate operation sequence. Therefore, the disclosed embodiments provide a solution for determining a target mapping based on multiple loop traversals, which can find a candidate mapping that can serve as the target mapping by repeatedly executing the same process.

[0177] 9 , in some embodiments, the fitness condition is to reach a first value (i.e., a fixed value). Based on multiple fitness degrees, a process of obtaining a target mapping relationship that meets the preset fitness condition from multiple candidate mapping relationships includes but is not limited to the following steps 910-920:

[0178] Step 910: Determine whether the fitness corresponding to each candidate mapping relationship does not reach a first value;

[0179] Step 920: Replace the initial mapping relationship with the candidate mapping relationship with the greatest fitness, and return to the step of applying multiple candidate adjustment methods to adjust the initial mapping relationship until at least one fitness corresponding to at least one candidate mapping relationship reaches a first value.

[0180] Steps 910-920 are described in detail below.

[0181] In step 910 , it is determined that the degree of fitness corresponding to each candidate mapping relationship does not reach a first value.

[0182] In a specific implementation of this embodiment, first, the degree of compatibility between each candidate mapping relationship and the gate operation sequence is determined. Then, the candidate mapping relationship whose degree of compatibility reaches a first value is determined. If the degree of compatibility of each candidate mapping relationship is less than the first value, then it is determined that the degree of compatibility corresponding to each candidate mapping relationship does not reach the first value.

[0183] In step 920 , the candidate mapping relationship with the greatest fitness replaces the initial mapping relationship, and the process returns to the step of applying multiple candidate adjustment methods to adjust the initial mapping relationship until at least one fitness corresponding to at least one candidate mapping relationship reaches a first value.

[0184] In the specific implementation of this embodiment, since the size of the fitness can represent the degree of fitness between the candidate mapping relationship and the gate operation sequence. Based on this, the candidate mapping relationship with the largest fitness is selected as the mapping relationship determined in the current round, and the initial mapping relationship is replaced with the candidate mapping relationship with the largest fitness. However, since the candidate mapping relationship with the largest fitness cannot enable all gate operations of the gate operation sequence to be executed normally, the next round of mapping adjustment is required. Therefore, the step of applying multiple candidate adjustment methods to adjust the initial mapping relationship is returned until at least one fitness corresponding to at least one candidate mapping relationship reaches the first value.

[0185] Among them, the specific implementation process of returning to the step of applying multiple candidate adjustment methods to adjust the initial mapping relationship until at least one fitness degree corresponding to at least one candidate mapping relationship reaches a first value is similar to the specific implementation process of the above steps 320-330 and the above steps 810-820. In order to save space, they will not be repeated.

[0186] Table 2

[0187] As shown in Table 2, the candidate mapping relationships formed by applying multiple candidate adjustment methods to the initial mapping relationship of Figure 4B, as well as the adaptability of the multiple second physical quantum bits included in the second physical quantum bit set corresponding to each candidate mapping relationship to the gate operation sequence. For example, since the physical device has 15 candidate swap gates based on the initial mapping relationship of Figure 4B, under the premise of setting the search depth to 2, there are 15+15×15=240 candidate adjustment methods. Therefore, without considering the possibility of duplication of the candidate mapping relationship, 240 candidate mapping relationships will be generated. Since the adaptability of multiple mapped physical quantum bits corresponding to candidate mapping relationship 15 and the gate operation sequence reaches the first value among these 240 candidate mapping relationships, it is indicated that candidate mapping relationship 15 can enable all gate operations of the gate operation sequence to be executed. Based on this, it is necessary to adjust the initial mapping relationship to candidate mapping relationship 15 according to the candidate adjustment method swap(6,7), and use candidate mapping relationship 15 as the target mapping relationship.

[0188] As shown in Figure 10, a target mapping relationship is obtained by applying a candidate adjustment method to the initial mapping relationship, where the applied candidate adjustment method is swap(6,7). For example, according to the candidate adjustment method, the logical qubits corresponding to physical qubit 6 and physical qubit 7 are mapped and swapped. Based on this, according to the target mapping relationship, logical qubit 0 in the gate operation sequence will be mapped from the first physical qubit 7 on the physical device to the first physical qubit 6; logical qubit 1 will be mapped from the first physical qubit 6 on the physical device to the first physical qubit 7.

[0189] In each round of this embodiment, when there is no candidate mapping relationship that can execute all gate operations of the gate operation sequence, the initial mapping relationship is replaced by the candidate mapping relationship with the greatest adaptability, and the target mapping relationship is determined based on multiple loop traversals. By repeatedly executing the same process, a candidate mapping relationship that can serve as the target mapping relationship can be found, so that each round of mapping optimization has cycle consistency, thereby improving the reliability of mapping optimization.

[0190] In actual application scenarios, it is often the case that among the multiple candidate mappings generated, no candidate mapping can execute all the gate operations of the gate operation sequence. Based on this, two further situations may arise: the first situation is that at least one candidate mapping among the multiple candidate mappings can execute a portion of the gate operations of the gate operation sequence. The second situation is that no candidate mapping among the multiple candidate mappings can execute a portion of the gate operations of the gate operation sequence, that is, all the gate operations of the gate operation sequence cannot be executed under all candidate mappings. Regarding the first situation, it is shown that the various candidate mappings have advantages and disadvantages, so steps 910-920 can solve the corresponding technical problem. However, in the second situation, when multiple candidate mappings cannot execute at least one gate operation of the gate operation sequence, the candidate mappings are not ranked as superior or inferior, and no one of them can be selected to perform the next round of mapping adjustment. Based on this, the embodiments of the present disclosure provide a solution for adjusting the initial mapping based on a preset completeness strategy and determining the target mapping based on multiple cycles. This solution can perform mapping optimization for situations where multiple candidate mappings cannot execute at least one gate operation of the gate operation sequence, thereby improving the effectiveness of mapping optimization.

[0191] Referring to FIG. 11 , in some embodiments, based on multiple fitness levels, a process of obtaining a target mapping relationship that meets a preset fitness level condition from multiple candidate mapping relationships includes but is not limited to the following steps 1110 - 1130 :

[0192] Step 1110: for each candidate mapping relationship: for each gate operator, based on the detection result obtained by the gate operator, determine that the gate operation corresponding to each gate operator cannot be executed;

[0193] Step 1120: Determine two physical qubits to be exchanged among the plurality of first physical qubits to which the initial mapping relationship is mapped, wherein the physical distance between the two physical qubits to be exchanged is the smallest and corresponds to a gate operator in the gate operation sequence;

[0194] Step 1130: Adjust the initial mapping relationship based on the two physical qubits to be exchanged, and return to the step of applying multiple candidate adjustment methods to adjust the initial mapping relationship.

[0195] Steps 1110 - 1130 are described in detail below.

[0196] In step 1110 , for each candidate mapping relationship: for each gate operator, based on the detection result obtained corresponding to the gate operator, it is determined that the gate operation corresponding to each gate operator cannot be executed.

[0197] For example, first, for each candidate mapping relationship: for each gate operator, the two logical qubits of the gate operation performed by the gate operator are mapped to a physical device to obtain two second physical qubits. Next, the two second physical qubits are detected to determine whether they are adjacent on the physical device, and a detection result corresponding to the gate operator is obtained. If the two second physical qubits are adjacent on the physical device, a detection result indicating that the two second physical qubits are adjacent on the physical device is obtained; if the two second physical qubits are not adjacent on the physical device, a detection result indicating that the two second physical qubits are not adjacent on the physical device is obtained, thereby obtaining multiple detection results corresponding to multiple gate operators. Then, based on the multiple detection results corresponding to the multiple gate operators, it is determined that the gate operation corresponding to each gate operator cannot be executed. Among them, when the detection results corresponding to each gate operator indicate that the corresponding two second physical qubits are not adjacent, it is determined that the gate operation corresponding to each gate operator cannot be executed. To simplify the calculation, if the two second physical qubits corresponding to the logical qubit applied by the first gate operator in the gate operation sequence are not adjacent, then under this candidate mapping relationship, no gate operation in the gate operation sequence can be executed. Finally, with respect to the execution of the gate operation of the gate operation sequence under each candidate mapping relationship, if there is no candidate mapping relationship that allows the first gate operation of the gate operation sequence to be executed, it is determined that each candidate mapping relationship makes any gate operation in the gate operation sequence unable to be executed.

[0198] In step 1120, two physical qubits to be exchanged among the plurality of first physical qubits to which the initial mapping relationship is mapped are determined, wherein the physical distance between the two physical qubits to be exchanged is the smallest and corresponds to a gate operator in the gate operation sequence.

[0199] The physical quantum bit to be exchanged refers to the first physical quantum bit in the physical device whose mapping position needs to be exchanged.

[0200] For example, first, based on the initial mapping relationship, the logical qubits applied to one or more gate operators that are executed first in the gate operation sequence are mapped to the first physical qubit. Next, for each gate operator that is executed first, the physical distance between the first physical qubits mapped to the two logical qubits applied is calculated. Furthermore, the two first physical qubits with the smallest physical distance are selected as the physical qubits to be exchanged.

[0201] In some embodiments, when determining two physical qubits to be exchanged, the executable swap gate associated with the two physical qubits to be exchanged can be determined based on calculating the function value of the following function (as shown in formula (2)):

[0202] Wherein, frontlayer refers to the set of gate operators ranked first in the gate operation sequence, which is called the first-layer quantum gate. g∈frontlayer indicates that the gate operation belongs to the set of gate operators ranked first. dist(g,π) refers to the bit distance corresponding to the gate operation corresponding to the gate operator (i.e., the gate operation corresponding to the gate operator), wherein the bit distance of the gate operation corresponding to the gate operator is calculated in accordance with formula (1) in step 320 above. f(π) refers to the minimum value of the bit distance of the gate operation corresponding to the gate operator in the set of gate operators ranked first.

[0203] Based on the above formula (2), the minimum value of the bit distance of the gate operation corresponding to the gate operator in the set of gate operators ranked first is determined, thereby determining the gate operator corresponding to the minimum value. Then, an executable swap gate is selected from multiple executable swap gates associated with the gate operator corresponding to the minimum value for execution. The embodiments of the present disclosure are not limited to the selection method. For example, an executable swap gate can be randomly selected from multiple executable swap gates; a swap gate that best meets the task requirements can also be selected based on the specific task requirements of the quantum algorithm or quantum circuit; if the physical distance between qubits affects performance (such as in some quantum hardware), the closest swap gate is selected to reduce communication delay.

[0204] In step 1130 , the initial mapping relationship is adjusted based on the two physical qubits to be exchanged, and the process returns to the step of generating multiple candidate adjustment methods for the initial mapping relationship.

[0205] Referring to FIG. 12 , in some embodiments, based on two physical qubits to be exchanged, the process of adjusting the initial mapping relationship is implemented in the following manner:

[0206] Step 1210: Determine a connection path between two physical qubits to be exchanged;

[0207] Step 1220: Determine candidate adjustment switch gates based on the connection path.

[0208] Step 1230: Determine a target adjustment exchange gate from the candidate adjustment exchange gates, and adjust the initial mapping relationship based on the target adjustment exchange gate.

[0209] For example, first, based on the connection relationship between each of the first physical qubits in the initial mapping relationship, a connection path between the two physical qubits to be exchanged is determined. Next, based on the connection path, executable swap gates existing between the two physical qubits to be exchanged are determined. From the multiple executable swap gates determined, executable swap gates that are connected to at least one of the two physical qubits to be exchanged are selected as candidate adjustment swap gates. Finally, one of the candidate adjustment swap gates is randomly selected as the target adjustment swap gate, and based on the target adjustment swap gate, the bit mapping of the gate operation with the smallest physical distance among the first gate operations executed in the initial mapping relationship is adjusted.

[0210] As shown in Figure 13, for the gate operation sequence in Figure 4A, the gate operator at the first position in the gate operation sequence is only the gate operator g0. Therefore, the front layer of the gate operation sequence = [g0]. Since the gate operation corresponding to the gate operator is applied to the logical qubit q2 and mapped to the first physical qubit Q8, and the gate operation is applied to the logical qubit q3 and mapped to the first physical qubit Q 10 , the first physical quantum bit Q8 and the first physical quantum bit Q 10 The physical distance is 2, so Furthermore, since the first physical quantum bit Q8 and the first physical quantum bit Q 10The candidate swap gates on the connection path are swap(3,8) and swap(8,10), so the candidate adjustment swap gates are swap(3,8) and swap(8,10). Randomly select one of the two candidate adjustment swap gates as the target adjustment swap gate. For example, select swap(8,10) as the target adjustment swap gate. Based on the target adjustment swap gate swap(8,10), the logical qubit q2 is transformed from being mapped to the first physical qubit Q8 to being mapped to the first physical qubit Q 10 ; Map the logical quantum bit q2 to the first physical quantum bit Q 10 Transformed to map to the first physical quantum bit Q8.

[0211] It should be noted that in some gate operation sequences, multiple gate operations often need to be executed simultaneously. After multiple gate operations are completed, the next gate operation is executed. Therefore, a gate operation sequence often has multiple gate operations at the top. For example, in a gate operation sequence [(g0, g1, g2), g3, g4], the first gate operations to be executed are g0, g1, and g2. After gate operations g0, g1, and g2 are completed, gate operation g3 is executed, and finally gate operation g4. Based on this, according to the above method, when there is no candidate mapping relationship that allows all of g0, g1, g2, g3, and g4 to be executed, the bit distances of gate operations g0, g1, and g2 are calculated separately. If the bit distance of gate operation g0 is 4, the bit distance of gate operation g1 is 3, and the bit distance of gate operation g2 is 6, then f(π) = 3; the first physical qubits to which the two logical qubits applied to gate operation g1 are mapped are used as the two physical qubits to be exchanged. Furthermore, when the initial mapping relationship is as shown in FIG4B , the two logical qubits to which the gate operation g1 is applied are q1 and q3 , and the two physical qubits to be exchanged are Q6 and Q 10 , so the candidate adjustment swap gates are swap(6,7) and swap(10,8). Whether executing swap(6,7) or swap(10,8) can reduce the bit distance of gate operation g1 by 1.

[0212] This embodiment adjusts the initial mapping relationship based on a preset completeness strategy. For the situation where multiple candidate mapping relationships cannot enable at least one gate operation of the gate operation sequence to be executed, the two logical quantum bits applied to the multiple executable gate operations executed first in the gate operation sequence are selected for mapping adjustment, so that the bit distance of the gate operation with the smallest bit distance among the multiple executable gate operations executed first in the gate operation sequence becomes smaller, thereby improving the effectiveness and completeness of the mapping optimization.

[0213] Because when multiple logical quantum bits in a gate operation sequence are mapped to physical devices based on different candidate mapping relationships to obtain multiple second physical quantum bits, there are often gate operation operators that can perform gate operations and gate operation operators that cannot perform gate operations in the multiple gate operations in the gate operation sequence. The more gate operations that can be performed in the gate operation sequence, the better the match between the candidate mapping relationship and the gate operation sequence. Based on this, the embodiment of the present disclosure provides a universal fitness determination scheme that can simplify the fitness calculation process and improve the fitness calculation accuracy.

[0214] Referring to FIG. 14 , in some embodiments, the process of determining the compatibility of a plurality of mapped physical qubits with a gate operation sequence includes, but is not limited to, the following steps 1410 - 1440:

[0215] Step 1410: Determine a gate operation dependency graph based on the execution order of each gate operation operator in the gate operation sequence;

[0216] Step 1420: Determine, in the gate operation sequence, a first gate operation operator capable of performing the gate operation and a second gate operation operator incapable of performing the gate operation based on the multiple detection results corresponding to the multiple gate operation operators, the gate operation dependency graph, and the candidate mapping relationship.

[0217] Step 1430: Determine the bit distance between two logical qubits of each second gate operator performing a gate operation.

[0218] Step 1440: Determine the degree of fit between the candidate mapping relationship and the gate operation sequence based on the first total number of first gate operators and the bit distances corresponding to each second gate operator.

[0219] Steps 1410-1440 are described in detail below.

[0220] In step 1410 , a gate operation dependency graph is determined based on the execution order of each gate operator in the gate operation sequence.

[0221] The execution order is used to indicate the execution order of each gate operation in the gate operation sequence.

[0222] The gate operation dependency graph is used to indicate the dependencies between gate operations (i.e., gate operations corresponding to gate operators) during execution. The gate operation dependency graph is a directed graph, and the direction of the graph indicates the execution order and direction of each gate operation. For example, according to the gate operation dependency graph, if the previous gate operation cannot be executed, then subsequent gate operations that depend on the normal execution of the previous gate operation are also considered to be unable to execute. The gate operation dependency graph is a graphical representation used to describe the control dependencies and data dependencies between gate operations. The gate operation dependency graph consists of nodes and edges. Nodes represent gate operations, and edges represent the dependencies between gate operations. In gate operations, control dependency refers to the dependence of the execution of one gate operation on the result of another gate operation. For example, in a conditional branch, the result of the condition (usually the result of an AND or OR operation) determines which path to execute. Data dependency refers to the dependence of the input data of one gate operation on the output data of another gate operation. For example, when evaluating a logical expression, the output of one AND operation may serve as one of the inputs of the next AND operation.

[0223] In the specific implementation of this embodiment, the specific process of determining the gate operation dependency graph includes but is not limited to the following steps: determining multiple gate operators as nodes; determining the directed edges between the nodes based on the execution order of the gate operations corresponding to the multiple gate operators; and determining the gate operation dependency graph based on the multiple nodes and the multiple directed edges.

[0224] In this embodiment, a node is used to indicate a vertex in the gate operation dependency graph, that is, a gate operator or a gate operation corresponding to a gate operator. A directed edge is used to indicate the dependency relationship between gate operations in the gate operation dependency graph. Each directed edge connects two nodes.

[0225] For example, first determine the multiple gate operators included in the gate operation sequence. Then, determine each gate operator as a node in the gate operation dependency graph, and obtain multiple nodes in the gate operation dependency graph. Furthermore, based on the execution order of the gate operations, first determine whether the first gate operation (i.e., the gate operation corresponding to the first gate operator) and the next gate operation (i.e., the gate operation corresponding to the next gate operator) are applied to the same logical qubit. If the first gate operation and the next gate operation are applied to the same logical qubit, then determine that there is a directed edge between the node corresponding to the first gate operation and the node corresponding to the next gate operation. If the first gate operation and one of the next gate operations are applied to the same logical qubit, then determine that there is a directed edge between the node corresponding to the first gate operation and the node corresponding to the gate operation applied to the same logical qubit in the next gate operation. If the first gate operation and the next gate operation are not applied to the same logical qubit, then determine that there is no directed edge between the node corresponding to the first gate operation and the node corresponding to the next gate operation. Next, determine whether the second gate operation and the subsequent gate operation are applied to the same logical qubit. Similarly, determine the directed edges between all gate operations and other gate operations. Based on the dependencies between gate operations, use directed edges to connect each node to form a graph structure, which is used as the gate operation dependency graph.

[0226] As shown in Figure 15A, the gate operation sequence [g0, g1, g2, g3, g4, g5, g6] contains seven gate operations that are executed in sequence. Among them, gate operation g0 is applied to logical qubit q0 and logical qubit q2; gate operation g1 is applied to logical qubit q2 and logical qubit q3; gate operation g2 is applied to logical qubit q0 and logical qubit q3; gate operation g3 is applied to logical qubit q0 and logical qubit q2; gate operation g4 is applied to logical qubit q2 and logical qubit q3; gate operation g5 is applied to logical qubit q0 and logical qubit q3; gate operation g6 is applied to logical qubit q1 and logical qubit q3.

[0227] As shown in Figure 15B, since gate operation g0 is executed before gate operation g1 and gate operation g2, and gate operation g0 and gate operation g1 are applied to the same logical qubit q2, and gate operation g0 and gate operation g2 are applied to the same logical qubit q0, there is a directed edge between gate operation g0 and gate operation g1, and there is a directed edge between gate operation g0 and gate operation g1. Since gate operation g1 is executed before gate operation g2 and gate operation g3, and gate operation g1 and gate operation g2 are applied to the same logical qubit q3, and gate operation g1 and gate operation g3 are applied to the same logical qubit q2, there is a directed edge between gate operation g1 and gate operation g2, and there is a directed edge between gate operation g1 and gate operation g3. And so on, by analogy, all directed edges between gate operations are constructed, thus forming a gate operation dependency graph corresponding to the gate operation sequence.

[0228] This embodiment utilizes the nodes and directed edges in the gate operation dependency graph to more clearly reflect the gate operations included in the gate operation sequence and the dependency relationships between the gate operations, so that the executable status of each gate operation under different candidate mapping relationships can be conveniently inferred based on the gate operation dependency graph, thereby improving the screening efficiency and accuracy of multiple candidate mapping relationships.

[0229] In step 1420, based on the multiple detection results corresponding to the multiple gate operators, the gate operation dependency graph, and the candidate mapping relationship, a first gate operator that can perform the gate operation and a second gate operator that cannot perform the gate operation are determined in the gate operation sequence.

[0230] The first gate operator refers to a gate operator that can perform the gate operations corresponding to the preceding gate operators in the gate operation sequence, and the two physical qubits obtained by mapping the two logical qubits applied to the gate operator to the physical device are adjacent. It should be noted that when determining whether the first gate operator in the gate operation sequence can perform the gate operation, it is only necessary to determine whether the two physical qubits obtained by mapping the two logical qubits applied to the gate operator to the physical device are adjacent. If the two physical qubits obtained by mapping the two logical qubits applied to the gate operator to the physical device are adjacent, the first gate operator can perform the gate operation; if the two physical qubits obtained by mapping the two logical qubits applied to the gate operator to the physical device are not adjacent, the first gate operator cannot perform the gate operation. The gate operation corresponding to the first gate operator is the first gate operation. For example, in the gate operation sequence, gate operator g0 is arranged before gate operator g1, and gate operator g1 is arranged before gate operator g2. When gate operator g0 and gate operator g1 can perform gate operations, and the two logical quantum bits applied to gate operator g2 are mapped to the two physical quantum bits obtained by the physical device are adjacent, then gate operator g2 can perform the gate operation, that is, gate operator g2 is the first gate operator.

[0231] The second gate operator refers to a gate operator that can be executed by all preceding gate operators in the gate operation sequence, but the two logical qubits mapped to the physical device result in two non-adjacent physical qubits, as well as a gate operator that follows a gate operator that cannot be executed. The gate operation corresponding to the second gate operator is the second gate operation.

[0232] When this embodiment is implemented, each gate operation is executed in sequence according to the execution order of the gate operation and the candidate mapping relationship. For a gate operator, if the detection result obtained by the gate operator indicates that the corresponding two second physical quantum bits are adjacent, that is, the physical distance between the corresponding two second physical quantum bits is 1, then the gate operation corresponding to the gate operator is considered to be executable. If the detection result obtained by the gate operator indicates that the corresponding two second physical quantum bits are not adjacent, that is, the physical distance between the corresponding two second physical quantum bits is greater than 1, then the gate operation corresponding to the gate operator is considered to be unexecutable. Finally, the gate operator that can execute the gate operation is used as the first gate operator. When the gate operation corresponding to a gate operator is executed and it is determined that the gate operation cannot be executed, then according to the dependency relationship of the gate operation dependency graph, the gate operation and all gate operations after the gate operation are used as the second gate operation.

[0233] Figure 16A shows a candidate mapping relationship for mapping the logical qubits in the gate operation sequence [g0, g1, g2, g3, g4, g5, g6] of Figure 15A to the physical qubits on the physical device. In this candidate mapping relationship, logical qubit q0 maps to physical qubit Q0, logical qubit q1 maps to physical qubit Q1, logical qubit q2 maps to physical qubit Q2, and logical qubit q3 maps to physical qubit Q3.

[0234] As shown in Figure 16B, gate operation g0 is first executed. Since the logical qubit q0 and logical qubit q2 applied to gate operation g0 correspond to physical qubits Q0 and Q2, respectively, and the physical distance between physical qubits Q0 and Q2 is 1, gate operation g0 is determined to be executable. Next, gate operation g1 is executed. Since the logical qubit q2 and logical qubit q3 applied to gate operation g1 correspond to physical qubits Q2 and Q3, respectively, and the physical distance between physical qubits Q2 and Q3 is 1, gate operation g1 is determined to be executable. Next, gate operation g2 is executed. Since the logical qubit q0 and logical qubit q3 applied to gate operation g2 correspond to physical qubits Q0 and Q3, respectively, and the physical distance between physical qubits Q0 and Q3 is 2, gate operation g2 is determined to be inexecutable. Since the execution of the gate operations after g2 depends on the normal execution of g2, if g2 is not executable, the gate operations after g2 are also not executable. Based on this, for the above gate operation sequence and combination, the first gate operation includes g0 and g1, and the second gate operation includes g2, g3, g4, g5, and g6.

[0235] In step 1430 , the bit distance between the two logical qubits on which each second gate operator performs a gate operation is determined.

[0236] The bit distance is used to indicate the physical distance between two logical qubits mapped to two physical qubits of a physical device. When two physical qubits are adjacent, the bit distance is considered to be 1.

[0237] When implementing this embodiment, for each second gate operator, first, based on the candidate mapping relationship, the two logical qubits for the second gate operator to perform the gate operation are determined to correspond to the two second physical qubits based on the candidate mapping relationship. Next, the physical distance between the two second physical qubits is determined, and the physical distance between the two second physical qubits is used as the bit distance between the two logical qubits for the second gate operator to perform the gate operation (i.e., the bit distance of the second gate operator).

[0238] In step 1440 , the degree of compatibility between the candidate mapping relationship and the gate operation sequence is determined based on the first total number of first gate operators and the bit distances corresponding to the second gate operators.

[0239] The first total number is used to indicate the total number of first gate operation operators in the gate operation sequence.

[0240] In this embodiment, a first fitness subscore is first calculated based on the first total number of first gate operators. Next, a second fitness subscore is calculated based on the bit distances between each second gate operator. Finally, the degree of compatibility between the candidate mapping relationship and the gate operation sequence is determined based on the first fitness subscore and the second fitness subscore.

[0241] This embodiment provides a universal solution for determining the degree of fitness based on a combination of directed graphs, bit distance calculation, and the like, which can simplify the calculation process of the degree of fitness and improve the accuracy of the calculation of the degree of fitness.

[0242] The above is a general description of steps 1410-1440. Step 1430 and step 1440 are described in detail below.

[0243] Referring to FIG. 17 , in some embodiments, the two logical qubits on which the second gate operator performs the gate operation are a first logical bit and a second logical bit; step 1430 includes, but is not limited to, the following steps 1710 - 1720:

[0244] Step 1710: For each second gate operator, determine, based on the candidate mapping relationship, a first candidate physical qubit to which the first logical bit is mapped, and a second candidate physical qubit to which the second logical bit is mapped;

[0245] Step 1720: Determine the physical distance between the first candidate physical qubit and the second candidate physical qubit as the bit distance.

[0246] Steps 1710-1720 are described in detail below.

[0247] In step 1710, for each second gate operator, first, the two logical qubits on which the second gate operator performs the gate operation are determined to be a first logical bit and a second logical bit. Next, according to the candidate mapping relationship, the first logical bit is mapped to a physical device to obtain a first candidate physical qubit corresponding to the first logical bit (i.e., a physical qubit in the physical device that has a candidate mapping relationship with the first logical bit). Finally, according to the candidate mapping relationship, the second logical bit is mapped to the physical device to obtain a second candidate physical qubit corresponding to the second logical bit (i.e., a physical qubit in the physical device that has a candidate mapping relationship with the second logical bit).

[0248] In step 1720, on the physical device, the number of unit distances traveled from the location of the first candidate physical quantum bit to the location of the second candidate physical quantum bit is determined, and the product of the number of unit distances and the unit distance is used as the physical distance between the first candidate physical quantum bit and the second candidate physical quantum bit, thereby determining the bit distance of the second gate operation.

[0249] For example, for the second gate operation g2 in Figure 15A, the logical quantum bit q0 and the logical quantum bit q3 applied by the gate operation g2 correspond to the physical quantum bit Q0 and the physical quantum bit Q3 respectively, where the physical distance between the physical quantum bit Q0 and the physical quantum bit Q3 is 2, so the bit distance of the second gate operation g2 is 2.

[0250] This embodiment uses the physical distance between the physical qubits mapped to the two logical qubits applied to each second gate operation as the bit distance, which can simplify the calculation process of the bit distance and thus improve the mapping efficiency.

[0251] Referring to FIG. 18 , in some embodiments, step 1440 includes, but is not limited to, the following steps 1810 - 1830 :

[0252] Step 1810: Determine a first adapter fraction based on a product of the first total number, a second total number of first physical qubits in the physical device, and a first set parameter;

[0253] Step 1820: Determine a second adapter score based on the second total number, the second setting parameter, the third setting parameter, and the bit distance of each second gate operation;

[0254] Step 1830: Determine the degree of fitness based on the first aptamer score and the second aptamer score.

[0255] Steps 1810-1830 are described in detail below.

[0256] In step 1810 , a first adapter fraction is determined based on a product of the first total number, a second total number of first physical qubits in the physical device, and a first setting parameter.

[0257] The second total number is used to indicate the total number of first physical quantum bits in the physical device.

[0258] For example, the second total number in FIG. 16A is 4.

[0259] The first setting parameter is a parameter determined according to actual business needs and can be freely adjusted without restriction. The first setting parameter can be expressed as β.

[0260] The first fitness score is used to indicate the overall fitness of the combination (ie, the set formed by multiple second physical quantum bits obtained from the candidate mapping relationship) and the first gate operation that can be executed in the gate operation sequence.

[0261] In this embodiment, the first total number, the second total number, and the first setting parameter are multiplied to obtain the product of the first total number, the second total number, and the first setting parameter, and the product is used as the first aptamer score. The first aptamer score can be expressed as shown in formula (3): Score1 = P × n × β Formula (3)

[0262] Where Score1 is the first adapter score. P is the total number of all gate operations that can be performed in the gate operation sequence determined according to the combination, i.e., the first total number. n is the total number of first physical qubits in the physical device, i.e., the second total number. β is a first adjustable setting parameter.

[0263] In step 1820 , a second adapter score is determined based on the second total number, the second setting parameter, the third setting parameter, and the bit distances of the respective second gate operations.

[0264] The second setting parameter and the third setting parameter are parameters determined according to actual business needs and can be freely adjusted without restrictions. The second setting parameter is represented by α and the third setting parameter is represented by γ.

[0265] In the embodiment of the present disclosure, in order to improve the calculation accuracy of the adaptability, the third setting parameter is determined according to the diameter (diam) of the physical device. The third setting parameter determined in this way is expressed as γ diam .

[0266] The second fitness sub-score is used to indicate the overall fitness of the second gate operation that cannot be executed in the combined AND gate operation sequence.

[0267] When this embodiment is implemented, the process of determining the second adapter score based on the second total number, the second setting parameter, the third setting parameter, and the bit distance of each second gate operation can be expressed as shown in formula (4):

[0268] Where Score2 is the second aptamer score. n is the total number of first physical qubits in the physical device. α is the second setting parameter, γ diam Is the third setting parameter. x represents the xth logical quantum bit. When x = 0, it represents the logical quantum bit q0. x Representation and logical quantum bit q x The associated gate operation cannot be performed. x [i] represents the logical quantum bit q x The i-th gate operation in the associated gate operation that cannot be executed. dist(gate x [i],π) refers to the logical quantum bit q x The bit distance of the i-th gate operation in the associated gate operation that cannot be executed under the mapping π indicated by the combination. x ) represents the logical quantum bit q x The total length of the sequence of gate operations that cannot be performed when compared with the logical qubit q x When there are 6 gate operations that cannot be performed, len(gate x )=6.

[0269] For example, assuming that the gate operation sequence is the gate operation sequence in Figure 15A, the candidate mapping relationship is in the form of Figure 16A. Based on this, n-1=4-1=3. Further, for the logical quantum bit q0 in Figure 15A, its associated unexecutable gate operations are g2, g3, and g5. At this time, x=0, gate0[0]=g2; gate0[1]=g3; gate0[2]=g5. len(gate0)-1=3-1=2. Therefore, the bit distances of the unexecutable gate operations associated with the logical quantum bit q0 are: dist(gate0[0],π)=dist(g2,π)=dist AG (π(q0),π(q3))=2; dist(gate0[1],π)=dist(g3,π)=dist AG (π(q0),π(q2))=1; dist(gate0[2],π)=dist(g5,π)=dist AG (π(q0),π(q3))=2.

[0270] In step 1830 , a degree of fitness is determined based on the first aptamer score and the second aptamer score.

[0271] When implementing this embodiment, the first fitness score and the second fitness score are first added together to obtain a matching sum, and then the matching sum is divided by the total number of gate operations in the gate operation sequence to obtain the fitness of the combined gate operation sequence.

[0272] In the embodiment of the present disclosure, the overall calculation process of the fitness can be expressed in the form of a mapping evaluation function, the output function value of which is positively correlated with the gate operation sequence. When the output function value of the mapping evaluation function is larger, it indicates that the fitness of the multiple mapped physical quantum bits indicated by the candidate mapping relationship and the gate operation sequence LC is higher, and the candidate mapping relationship is more adapted to the gate operation sequence. The mapping evaluation function cost(π, LC) can be expressed as follows:

[0273] Wherein, π represents the mapping relationship between the logical qubit indicated by the candidate mapping relationship and the first physical qubit. M is the total number of gate operations in the gate operation sequence, that is, the number of CNOT gates.

[0274] This embodiment uses a mapping evaluation function to determine the compatibility of each candidate mapping relationship with the gate operation sequence. This introduction of the mapping evaluation function enables a versatile method for calculating mapping evaluations for different candidate mapping relationships, thereby improving the accuracy and efficiency of determining the target mapping relationship. Compared to related techniques that use multiple formulas for mapping evaluation, this disclosed embodiment effectively reduces computational complexity and errors, thereby improving the accuracy of the calculation of the compatibility.

[0275] Since quantum circuits are reversible, when optimizing quantum mapping, the quantum circuit is first executed according to the initially given mapping relationship (i.e., the initial mapping relationship). The initially given mapping relationship is optimized by introducing a bit mapping converter to add a swap gate. This can more conveniently obtain a mapping relationship that enables the gate operation sequence to execute normally, thereby achieving the initial optimization of the mapping relationship. In order to integrate the information of the entire quantum circuit into the mapping relationship and improve the mapping optimization effect, the inverse circuit of the quantum circuit can also be executed based on the mapping relationship that enables the gate operation sequence to execute normally, and the mapping relationship that enables the inverse circuit to execute normally is used as the final mapping relationship. Based on this, the embodiment of the present disclosure provides a solution for optimizing and adjusting the target mapping relationship, which can improve the accuracy of the final determined mapping relationship.

[0276] Referring to FIG. 19 , in one embodiment, after applying the target mapping relationship to map multiple logical qubits to physical devices to obtain multiple target physical qubits, the qubit mapping method further includes, but is not limited to, the following steps 1910-1950:

[0277] Step 1910: Determine the inverse sequence of the gate operation sequence;

[0278] Step 1920: Obtain a target mapping relationship of the inverse sequence, wherein the target mapping relationship of the inverse sequence is used to map multiple logical qubits in the inverse sequence to physical devices to obtain multiple third physical qubits;

[0279] Step 1930: Apply multiple adjustment methods to adjust the target mapping relationship of the reverse sequence to obtain corresponding multiple first mapping relationships;

[0280] Step 1940: Apply multiple adjustment methods to adjust the target mapping relationship of the inverse sequence to obtain corresponding multiple first mapping relationships, apply the multiple first mapping relationships to respectively map the multiple logical quantum bits in the inverse sequence to physical devices to obtain corresponding multiple third physical quantum bit sets, wherein each third physical quantum bit set includes multiple fourth physical quantum bits; for each first mapping relationship: for each candidate gate operator in the inverse sequence, detect whether the two logical quantum bits on which the candidate gate operator performs the gate operation are adjacent on the physical device based on the two fourth physical quantum bits corresponding to the first mapping relationship, and obtain a target detection result; based on the multiple target detection results obtained corresponding to the multiple candidate gate operators, determine the target fitness between the first mapping relationship and the inverse sequence; to obtain multiple target fitness corresponding to the multiple first mapping relationships, and based on the multiple target fitness, obtain a second mapping relationship that meets the preset fitness conditions from the multiple first mapping relationships.

[0281] Step 1950: Apply the second mapping relationship to map the multiple logical quantum bits in the inverse sequence to physical devices.

[0282] Steps 1910-1950 are described in detail below.

[0283] In step 1910, the inverse sequence of the gate operation sequence is determined.

[0284] The inverse sequence is a mirror image of the gate operation sequence. The gate operation that is executed first in the gate operation sequence is executed last in the inverse sequence; the gate operation that is executed last in the gate operation sequence is executed first in the inverse sequence.

[0285] When this embodiment is implemented, the multiple gate operation operators in the gate operation sequence are arranged in reverse order, and the obtained sequence is used as the reverse sequence of the gate operation sequence.

[0286] For example, for the gate operation sequence [g0, g1, g2, g3, g4] in Figure 4A , the reverse sequence is [g4, g3, g2, g1, g0]. In the reverse sequence, the first gate operation executed is g4. Next, g3 is executed, and so on. When g0 is completed, the reverse sequence is complete.

[0287] In step 1920, a target mapping relationship of the inverse sequence is obtained, wherein the target mapping relationship of the inverse sequence is used to map multiple logical quantum bits in the inverse sequence to physical devices to obtain multiple third physical quantum bits.

[0288] The third physical qubit is the physical qubit in the physical device to which each logical qubit in the inverse sequence is mapped under the target mapping relationship. The target mapping relationship is the target mapping relationship in step 340, which applies the target mapping relationship that enables all gate operations in the gate operation sequence to the inverse sequence of the gate operation sequence, that is, re-obtaining the target mapping relationship between the multiple logical qubits in the inverse sequence and the multiple third physical qubits in the physical device.

[0289] When this embodiment is implemented, the specific implementation process of step 1920 is similar to the specific implementation process of the above-mentioned step 320. To save space, it is not repeated here.

[0290] The specific implementation process of steps 1930-1950 is similar to the implementation process of steps 330-350 above, and will not be repeated here for the sake of space.

[0291] Among them, the fourth physical quantum bit in step 1940 is the physical carrier in the physical device to which each logical quantum bit is to be mapped under the first mapping relationship.

[0292] This embodiment utilizes the reversibility of quantum circuits and applies a target mapping relationship that enables all gate operations of a gate operation sequence to the inverse sequence of the gate operation sequence. Based on the execution status of each gate operation in the inverse sequence, the target mapping relationship is further optimized and adjusted to obtain a first mapping relationship. A second mapping relationship that enables all gate operations of the inverse sequence of the gate operation sequence to be executed is used as the final mapping relationship, thereby improving the accuracy of bit mapping and further reducing the number of swap gates that need to be added during the mapping process.

[0293] 20A-20B , the implementation details of the quantum bit mapping method according to the embodiment of the present disclosure are described in detail.

[0294] As shown in FIG20A , a schematic diagram of the implementation process of determining the final mapping relationship between multiple logical qubits of a gate operation sequence and the physical qubits of a given physical device according to an embodiment of the present disclosure is shown. First, according to a pre-set initial mapping relationship, the multiple logical qubits of the gate operation sequence are mapped to the physical device to obtain multiple first physical qubits. Based on the execution status of each gate operation in the gate operation sequence after the mapping is completed, the initial mapping relationship is optimized, and a target mapping relationship is obtained that enables all gate operations in the gate operation sequence to be executed. The specific implementation process is similar to steps 320-350 above. Next, the inverse sequence of the gate operation sequence is determined. According to the target mapping relationship, the multiple logical qubits of the inverse sequence of the gate operation sequence are mapped to the physical device to obtain multiple third physical qubits. Based on the execution status of each gate operation in the inverse sequence after the mapping is completed, the target mapping relationship is optimized, and a second mapping relationship is obtained that enables all gate operations in the inverse sequence to be executed. The second mapping relationship is used as the final mapping relationship corresponding to the gate operation sequence. The specific implementation process is similar to steps 1910-1950 above.

[0295] As shown in FIG. 20B , this is a specific implementation process of applying the initial mapping relationship to the gate operation sequence to obtain the target mapping relationship, and also a specific implementation process of applying the target mapping relationship to the inverse sequence of the gate operation sequence to obtain the second mapping relationship.

[0296] Step 1: Input gate operation sequence and initial mapping relationship.

[0297] In this process, first, according to a preset initial mapping relationship, multiple logical quantum bits of the gate operation sequence are mapped to physical devices to obtain multiple first physical quantum bits.

[0298] Step 2: Execute the executable gate operation set.

[0299] After completing mapping multiple logical quantum bits of the gate operation sequence to a physical device according to a pre-set initial mapping relationship to obtain a first physical quantum bit, an executable gate operation set is executed, wherein the executable gate operation set includes executable gate operations.

[0300] Step 3: Determine whether there is any gate operation that cannot be executed in the gate operation sequence.

[0301] After completing the mapping of multiple logical quantum bits of the gate operation sequence to physical devices according to the pre-set initial mapping relationship to obtain multiple first physical quantum bits, it is determined whether there are unexecutable gate operations in the gate operation sequence. The specific implementation process is similar to the above step 320.

[0302] Step 4: Enumerate all possible candidate mapping relationships.

[0303] When there are unexecutable gate operations in the gate operation sequence based on the initial mapping relationship, multiple candidate adjustment methods for the initial mapping relationship are generated, and the candidate mapping relationship corresponding to each candidate adjustment method is determined. The specific implementation process is similar to the above step 330.

[0304] Step 5: Determine whether the executable gate operation sets in all candidate mapping relationships are empty sets.

[0305] Determine whether there are any unexecutable gate operations in the gate operation sequence under each candidate mapping relationship. If at least one candidate mapping relationship among multiple candidate mapping relationships enables all gate operations in the gate operation sequence to be executed, then the executable gate operation sets in all candidate mapping relationships are not all empty sets. If at least one candidate mapping relationship among multiple candidate mapping relationships does not enable all gate operations in the gate operation sequence to be executed, then the executable gate operation sets in all candidate mapping relationships are all empty sets.

[0306] Step 6: Select the candidate mapping relationship with the greatest fitness.

[0307] When at least one candidate mapping relationship among multiple candidate mapping relationships enables all gate operations of the gate operation sequence to be executed, then one of the candidate mapping relationships that enables all gate operations of the gate operation sequence to be executed is selected as the target mapping relationship, and the specific implementation process is similar to the above steps 810-820. When at least one candidate mapping relationship among multiple candidate mapping relationships enables some gate operations of the gate operation sequence to be executed but not all gate operations to be executed, then the candidate mapping relationship with the greatest fitness is selected from the candidate mapping relationships that enable some gate operations of the gate operation sequence to be executed but not all gate operations to be executed to replace the initial mapping relationship, and the above process is repeated until a candidate mapping relationship that enables all gate operations of the gate operation sequence to be executed is found and used as the target mapping relationship, and the specific implementation process is similar to the above steps 910-920.

[0308] Step 7: Perform completeness operations.

[0309] When all candidate mapping relationships among multiple candidate mapping relationships make all gate operations of the gate operation sequence unable to be executed, a completeness operation is performed and the above process is repeated until a candidate mapping relationship that can execute all gate operations of the gate operation sequence is found as the target mapping relationship. The specific implementation process of the completeness operation is similar to the above steps 1110-1130.

[0310] Step 8: Generate target mapping relationship.

[0311] When there is no unexecutable gate operation in the gate operation sequence based on the initial mapping relationship, the initial mapping relationship is determined as the target mapping relationship.

[0312] For example, after obtaining the target mapping relationship, the multiple gate operations in the gate operation sequence are reversed to form an inverse sequence of the gate operation sequence. The above process is then repeated. Based on the execution of each gate operation in the inverse sequence according to the target mapping relationship, the target mapping relationship is optimized. The mapping relationship found so that all gate operations in the inverse sequence are executed is used as the final mapping relationship. The specific implementation process is similar to steps 1910-1950 above. To save space, this process is not further described.

[0313] It is to be understood that, although the steps in the above-mentioned flowcharts are shown in sequence according to the arrow representations, these steps are not necessarily performed in sequence according to the order represented by the arrows. Unless otherwise specified in the present embodiment, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the above-mentioned flowcharts may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0314] It should be noted that in each specific embodiment of the present application, when it comes to the need to perform relevant processing based on data related to the characteristics of the target object, such as the target object attribute information or attribute information set, the permission or consent of the target object will be obtained first, and the collection, use and processing of such data will comply with relevant laws, regulations and standards. In addition, when the embodiment of the present application needs to obtain the attribute information of the target object, the target object's separate permission or separate consent will be obtained through a pop-up window or by jumping to a confirmation page. After clearly obtaining the target object's separate permission or separate consent, the necessary target object-related data for the normal operation of the embodiment of the present application will be obtained.

[0315] FIG21 is a schematic diagram of the structure of a quantum bit mapping device 2100 provided in an embodiment of the present disclosure. The quantum bit mapping device 2100 includes:

[0316] an acquisition unit 2110 configured to acquire a gate operation sequence for performing a target quantum computation and a plurality of logical qubits, wherein each gate operator in the gate operation sequence is used to perform a gate operation on two of the plurality of logical qubits;

[0317] A first mapping unit 2120 is configured to obtain an initial mapping relationship, where the initial mapping relationship is used to map the plurality of logical qubits to a preset physical device to obtain a plurality of first physical qubits;

[0318] A generating unit 2130 is configured to apply multiple candidate adjustment methods to adjust the initial mapping relationship to obtain multiple corresponding candidate mapping relationships, where the multiple candidate mapping relationships are used to map the multiple logical qubits to the physical device, and the multiple candidate mapping relationships are different from the initial mapping relationship;

[0319] The determining unit 2140 is configured to apply the multiple candidate mapping relationships, respectively map the multiple logical qubits to the physical devices, and obtain a corresponding multiple second physical qubit sets, wherein each second physical qubit set includes multiple second physical qubits; for each candidate mapping relationship: for each gate operator, detect whether the two logical qubits of the gate operator performing the gate operation are adjacent to each other on the physical device based on the two second physical qubits corresponding to the candidate mapping relationship, and obtain a detection result; based on the multiple detection results corresponding to the multiple gate operators, determine the fitness between the candidate mapping relationship and the gate operation sequence; to obtain a multiple fitness corresponding to the multiple candidate mapping relationships; based on the multiple fitness, obtain a target mapping relationship that meets the preset fitness condition from the multiple candidate mapping relationships;

[0320] The second mapping unit 2150 is configured to apply the target mapping relationship to map the multiple logical quantum bits to the physical device to obtain multiple target physical quantum bits.

[0321] In some embodiments, the adaptability condition is reaching a first value, and the determination unit 2140 is configured to: determine that at least one adaptability corresponding to at least one candidate mapping relationship reaches the first value; and determine the target mapping relationship from at least one candidate mapping relationship.

[0322] In some embodiments, the determination unit 2140 is configured to: determine that the degree of fitness corresponding to each of the candidate mapping relationships has not reached the first value; replace the initial mapping relationship with the candidate mapping relationship with the largest degree of fitness, and return to the step of applying multiple candidate adjustment methods to adjust the initial mapping relationship until at least one degree of fitness corresponding to at least one of the candidate mapping relationships reaches the first value.

[0323] In some embodiments, the quantum bit mapping device also includes a processing unit, which is further configured to: for each of the candidate mapping relationships: for each of the gate operators, based on the detection results corresponding to the gate operators, determine that the gate operations corresponding to each of the gate operators cannot be executed; determine two physical quantum bits to be exchanged among the multiple first physical quantum bits in the initial mapping relationship, wherein the physical distance between the two physical quantum bits to be exchanged is the smallest and corresponds to one of the gate operators in the gate operation sequence; based on the two physical quantum bits to be exchanged, adjust the initial mapping relationship, and return to the step of applying multiple candidate adjustment methods to adjust the initial mapping relationship.

[0324] In some embodiments, adjusting the initial mapping relationship based on the two physical quantum bits to be exchanged includes: determining a connection path for the two physical quantum bits to be exchanged; determining a candidate adjustment exchange gate based on the connection path; determining a target adjustment exchange gate from the candidate adjustment exchange gates, and adjusting the initial mapping relationship based on the target adjustment exchange gate.

[0325] In some embodiments, the generation unit 2130 is further configured to: determine multiple candidate exchange gates in the physical device; combine the multiple candidate exchange gates based on the set search depth to obtain multiple bit position exchange methods; and determine multiple candidate adjustment methods for the initial mapping relationship based on the multiple bit position exchange methods.

[0326] In some embodiments, determining a plurality of candidate exchange gates in a physical device includes: determining a plurality of connection relationships of the first physical quantum bits in the physical device; and determining the plurality of candidate exchange gates based on the plurality of connection relationships.

[0327] In some embodiments, the qubit mapping device 2100 further includes a dependency graph determination unit (not shown), a gate operation division unit (not shown), a distance determination unit (not shown), and a fitness determination unit (not shown);

[0328] a dependency graph determining unit (not shown), configured to determine a gate operation dependency graph based on the execution order of each gate operation operator, wherein the gate operation dependency graph is a directed graph;

[0329] a gate operation division unit (not shown) configured to determine, in the gate operation sequence, a first gate operation operator capable of performing a gate operation and a second gate operation operator incapable of performing a gate operation based on the plurality of detection results corresponding to the plurality of gate operation operators, the gate operation dependency graph, and the candidate mapping relationship;

[0330] a distance determining unit (not shown), configured to determine a bit distance between two logical qubits of each of the second gate operators performing the gate operation;

[0331] A fitness determination unit (not shown) is configured to determine a fitness between the candidate mapping relationship and the gate operation sequence based on a first total number of the first gate operators and a bit distance corresponding to each of the second gate operators.

[0332] In some embodiments, the adaptability determination unit (not shown) is further configured to: determine a first adapter score based on the product of the first total number, the second total number of first physical quantum bits in the physical device, and a first setting parameter; determine a second adapter score based on the second total number, the second setting parameter, the third setting parameter, and the bit distance corresponding to each of the second gate operators; and determine the adaptability between the candidate mapping relationship and the gate operation sequence based on the first adapter score and the second adapter score.

[0333] In some embodiments, the two logical qubits on which the second gate operator performs the gate operation are a first logical bit and a second logical bit;

[0334] The distance determination unit (not shown) is further configured to: for each of the second gate operators, determine, based on the candidate mapping relationship, a first candidate physical quantum bit to which the first logical bit is mapped, and a second candidate physical quantum bit to which the second logical bit is mapped; and determine the physical distance between the first candidate physical quantum bit and the second candidate physical quantum bit as the bit distance.

[0335] In some embodiments, the quantum bit mapping device 2100 further includes an updating unit (not shown), which is configured to: determine the inverse sequence of the gate operation sequence; obtain the target mapping relationship of the inverse sequence, wherein the target mapping relationship of the inverse sequence is used to map the multiple logical quantum bits in the inverse sequence to the physical device to obtain multiple third physical quantum bits; apply multiple adjustment methods to adjust the target mapping relationship of the inverse sequence to obtain corresponding multiple first mapping relationships; apply the multiple first mapping relationships to respectively map the multiple logical quantum bits in the inverse sequence to the physical device to obtain corresponding multiple third physical quantum bit sets, wherein each third physical quantum bit set includes multiple fourth physical quantum bits; for For each of the first mapping relationships: for each candidate gate operator in the inverse sequence, detect whether the two logical quantum bits on which the candidate gate operator performs the gate operation are adjacent to each other on the physical device based on the two fourth physical quantum bits corresponding to the first mapping relationship, and obtain a target detection result; based on the multiple target detection results corresponding to the multiple candidate gate operators, determine the target fitness between the first mapping relationship and the inverse sequence; to obtain the multiple target fitnesses corresponding to the multiple first mapping relationships; based on the multiple target fitnesses, obtain a second mapping relationship that meets the preset fitness conditions from the multiple first mapping relationships; apply the second mapping relationship to map the multiple logical quantum bits in the inverse sequence to the physical device.

[0336] 22 , which is a block diagram of a portion of a terminal for implementing the quantum bit mapping method according to an embodiment of the present disclosure, includes components such as a radio frequency (RF) circuit 2210, a memory 2215, an input unit 2230, a display unit 2240, a sensor 2250, an audio circuit 2260, a wireless fidelity (WiFi) module 2270, a processor 2280, and a power supply 2290. Those skilled in the art will appreciate that the terminal structure shown in FIG22 does not limit the scope of a mobile phone or computer, and may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0337] The RF circuit 2210 may be used for receiving and sending signals during information transmission or calls. In particular, after receiving downlink information from the base station, it is sent to the processor 2280 for processing. In addition, the designed uplink data is sent to the base station.

[0338] The memory 2215 may be used to store software programs and modules. The processor 2280 executes various functional applications and data processing of the target terminal by running the software programs and modules stored in the memory 2215 .

[0339] The input unit 2230 may be configured to receive input digital or character information and generate key signal input related to the setting and function control of the target terminal. Specifically, the input unit 2230 may include a touch panel 2231 and other input devices 2232 .

[0340] The display unit 2240 may be configured to display input information or provided information and various menus of the target terminal. The display unit 2240 may include a display panel 2241.

[0341] The audio circuit 2260 , the speaker 2261 , and the microphone 2262 may provide an audio interface.

[0342] In this embodiment, the processor 2280 included in the terminal can execute the quantum bit mapping method of the previous embodiment.

[0343] The terminals of the embodiments of the present disclosure include but are not limited to mobile phones, computers, intelligent voice interaction devices, smart home appliances, vehicle-mounted terminals, aircraft, etc. The embodiments of the present invention can be applied to various scenarios, including but not limited to quantum computing, distributed quantum computing, superconducting quantum computing, etc.

[0344] Figure 23 is a block diagram of the structure of a portion of a server implementing the quantum bit mapping method of an embodiment of the present disclosure. The server may have relatively large differences due to different configurations or performances, and may include one or more central processing units (CPUs) 2322 (for example, one or more processors) and memory 2332, one or more storage media 2330 (for example, one or more mass storage devices) storing application programs 2342 or data 2344. Among them, the memory 2332 and the storage medium 2330 can be short-term storage or persistent storage. The program stored in the storage medium 2330 may include one or more modules (not shown in the figure), each module may include a series of instruction operations on the server. Furthermore, the central processing unit 2322 can be configured to communicate with the storage medium 2330 and execute a series of instruction operations in the storage medium 2330 on the server.

[0345] The server may also include one or more power supplies 2326, one or more wired or wireless network interfaces 2350, one or more input and output interfaces 2358, and / or one or more operating systems 2341, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0346] The central processor 2322 in the server can be used to execute the quantum bit mapping method of the embodiment of the present disclosure.

[0347] The embodiments of the present disclosure also provide a computer-readable storage medium, which is used to store program code, and the program code is used to execute the quantum bit mapping method of each of the aforementioned embodiments.

[0348] The present disclosure also provides a computer program product, which includes a computer program. A processor of a computer device reads and executes the computer program, so that the computer device implements the above-mentioned quantum bit mapping method.

[0349] The terms "first," "second," "third," "fourth," and the like (if any) in the specification of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein, for example, can be implemented in orders other than those illustrated or described herein. In addition, the terms "comprises" and "comprising," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0350] In the embodiments of the present disclosure, the term "module" or "unit" refers to a computer program or a part of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories) or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0351] It should be understood that in the present disclosure, "at least one (item)" refers to one or more, and "plurality" refers to two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0352] It should be understood that in the description of the embodiments of the present disclosure, the meaning of multiple (or multiple items) is more than two, greater than, less than, exceed, etc. are understood to exclude the number itself, and above, below, within, etc. are understood to include the number itself.

[0353] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0354] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0355] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0356] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0357] It should also be understood that the various implementations provided in the embodiments of the present disclosure can be combined arbitrarily to achieve different technical effects.

[0358] The above is a specific description of the implementation methods of the present disclosure, but the present disclosure is not limited to the above implementation methods. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present disclosure. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.

Claims

1. A quantum bit mapping method, applied to an electronic device, the method comprising: Obtaining a gate operation sequence for performing target quantum computing and a plurality of logical quantum bits, wherein each gate operation operator in the gate operation sequence is used to perform a gate operation on two of the plurality of logical quantum bits; Obtaining an initial mapping relationship, the initial mapping relationship being used to map the plurality of logical quantum bits to a preset physical device to obtain a plurality of first physical quantum bits; Applying a plurality of candidate adjustment methods to adjust the initial mapping relationship to obtain corresponding plurality of candidate mapping relationships, the plurality of candidate mapping relationships being used to map the plurality of logical quantum bits to the physical device, and the plurality of candidate mapping relationships being different from the initial mapping relationship; Applying the plurality of candidate mapping relationships to map the plurality of logical quantum bits to the physical device respectively to obtain corresponding plurality of second physical quantum bit sets, wherein each second physical quantum bit set includes a plurality of second physical quantum bits; For each of the candidate mapping relationships: - For each of the gate operation operators, detecting whether two second physical quantum bits corresponding to the two logical quantum bits on which the gate operation operator performs the gate operation are adjacent on the physical device based on the candidate mapping relationship, to obtain a detection result; - Based on the plurality of detection results respectively obtained by the plurality of gate operation operators, determining the fitness between the candidate mapping relationship and the gate operation sequence; To obtain the plurality of fitnesses corresponding to the plurality of candidate mapping relationships; Based on the plurality of fitnesses, obtaining a target mapping relationship that meets a preset fitness condition from the plurality of candidate mapping relationships; Applying the target mapping relationship to map the plurality of logical quantum bits to the physical device to obtain a plurality of target physical quantum bits.

2. The qubit mapping method according to claim 1, wherein The fitness condition is to reach a first value, and the obtaining a target mapping relationship that meets a preset fitness condition from the plurality of candidate mapping relationships based on the plurality of fitnesses includes: Determining that at least one fitness corresponding to at least one of the candidate mapping relationships reaches the first value; Determining the target mapping relationship from at least one of the candidate mapping relationships.

3. The quantum bit mapping method according to any one of claims 1-2, wherein, The fitness condition is to reach a first value, and the obtaining a target mapping relationship that meets a preset fitness condition from the plurality of candidate mapping relationships based on the plurality of fitnesses includes: Determining that the fitness corresponding to each of the candidate mapping relationships does not reach the first value; Replacing the initial mapping relationship with the candidate mapping relationship having the maximum fitness, and returning to the step of applying a plurality of candidate adjustment methods to adjust the initial mapping relationship until at least one fitness corresponding to at least one of the candidate mapping relationships reaches the first value.

4. The qubit mapping method according to claim 3, wherein After determining that the fitness corresponding to each of the candidate mapping relationships does not reach the first value, the method further includes: For each of the candidate mapping relationships: for each of the gate operation operators, based on the detection results respectively obtained by the gate operation operators, determine that none of the gate operations corresponding to each of the gate operation operators can be executed; Determine two physical qubits to be swapped among the multiple first physical qubits in the initial mapping relationship, where the physical distance between the two physical qubits to be swapped is the smallest and corresponds to one of the gate operation operators in the gate operation sequence; Based on the two physical qubits to be swapped, adjust the initial mapping relationship, and return to the step of adjusting the initial mapping relationship by applying multiple candidate adjustment methods; 5. The qubit mapping method according to claim 4, wherein, The adjusting the initial mapping relationship based on the two physical qubits to be swapped includes: Determine the connection path of the two physical qubits to be swapped; Based on the connection path, determine candidate adjustment swap gates; Determine a target adjustment swap gate from the candidate adjustment swap gates, and adjust the initial mapping relationship based on the target adjustment swap gate; 6. The qubit mapping method according to any one of claims 1-5, wherein, Before applying multiple candidate adjustment methods to adjust the initial mapping relationship, the method further includes: Determine multiple candidate swap gates in the physical device; Based on a set search depth, combine the multiple candidate swap gates to obtain multiple qubit position swapping methods; Based on the multiple qubit position swapping methods, determine multiple candidate adjustment methods for the initial mapping relationship; 7. The qubit mapping method according to claim 6, wherein, The determining multiple candidate swap gates in the physical device includes: Determine multiple connection relationships of the first physical qubit in the physical device; Based on the multiple connection relationships, determine the multiple candidate swap gates; 8. The qubit mapping method according to any one of claims 1-7, wherein, The determining the fitness between the candidate mapping relationship and the gate operation sequence based on the multiple detection results respectively obtained by multiple gate operation operators includes: Based on the execution order of each gate operation operator, determine a gate operation dependency graph, where the gate operation dependency graph is a directed graph; Based on the multiple detection results respectively obtained by multiple gate operation operators, the gate operation dependency graph, and the candidate mapping relationship, determine a first gate operation operator that can execute a gate operation and a second gate operation operator that cannot execute a gate operation in the gate operation sequence; Determine the qubit distance between the two logical qubits for which each of the second gate operation operators executes the gate operation; Based on the first total number of the first gate operation operators and the qubit distances corresponding to each of the second gate operation operators, determine the fitness between the candidate mapping relationship and the gate operation sequence; 9. The qubit mapping method according to claim 8, wherein, The determining the fitness between the candidate mapping relationship and the gate operation sequence based on the first total number of the first gate operation operators and the qubit distances corresponding to each of the second gate operation operators includes: Based on the product of the first total number, the second total number of the first physical qubits in the physical device, and a first set parameter, determine a first fitness sub - score; Based on the second total number, a second set parameter, a third set parameter, and the qubit distances corresponding to each of the second gate operation operators, determine a second fitness sub - score; Based on the first adaptor score and the second adaptor score, determine the fitness between the candidate mapping relationship and the gate operation sequence.

10. The method according to claim 8, wherein, The two logical qubits on which the second gate operation operator performs the gate operation are the first logical qubit and the second logical qubit; The determining the bit distance between the two logical qubits on which each of the second gate operation operators performs the gate operation includes: For each of the second gate operation operators, based on the candidate mapping relationship, determine the first candidate physical qubit to which the first logical qubit is mapped and the second candidate physical qubit to which the second logical qubit is mapped; Determine the physical distance between the first candidate physical qubit and the second candidate physical qubit as the bit distance.

11. The qubit mapping method according to any one of claims 1-10, wherein, After applying the target mapping relationship to map the multiple logical qubits to the physical device to obtain multiple target physical qubits, the method further includes: Determine the inverse sequence of the gate operation sequence; Obtain the target mapping relationship of the inverse sequence, where the target mapping relationship of the inverse sequence is used to map the multiple logical qubits in the inverse sequence to the physical device to obtain multiple third physical qubits; Apply a plurality of adjustment methods to adjust the target mapping relationship of the inverse sequence to obtain corresponding first mapping relationships; Apply the plurality of first mapping relationships to map the multiple logical qubits in the inverse sequence to the physical device respectively to obtain corresponding sets of multiple third physical qubits, where each set of third physical qubits includes multiple fourth physical qubits; For each of the first mapping relationships: - For each candidate gate operation operator in the inverse sequence, detect whether the two fourth physical qubits corresponding to the two logical qubits on which the candidate gate operation operator performs the gate operation based on the first mapping relationship are adjacent on the physical device to obtain a target detection result; - Based on the multiple target detection results respectively obtained by the multiple candidate gate operation operators, determine the target fitness between the first mapping relationship and the inverse sequence; To obtain the multiple target fitnesses corresponding to the multiple first mapping relationships; Based on the multiple target fitnesses, obtain a second mapping relationship that meets the preset fitness condition from the multiple first mapping relationships; Apply the second mapping relationship to map the multiple logical qubits in the inverse sequence to the physical device.

12. A quantum bit mapping device, the device includes: An acquisition unit, configured to acquire a gate operation sequence for performing target quantum computing and multiple logical qubits, where each gate operation operator in the gate operation sequence is used to perform a gate operation on two of the multiple logical qubits; A first mapping unit, configured to acquire an initial mapping relationship, where the initial mapping relationship is used to map the multiple logical qubits to a preset physical device to obtain multiple first physical qubits; A generating unit, configured to apply a plurality of candidate adjustment methods to adjust the initial mapping relationship to obtain a corresponding plurality of candidate mapping relationships, where the plurality of candidate mapping relationships are used to map the plurality of logical qubits to the physical device, and the plurality of candidate mapping relationships are different from the initial mapping relationship; A determining unit, configured to apply the plurality of candidate mapping relationships to map the plurality of logical qubits to the physical device respectively, to obtain a corresponding plurality of second physical qubit sets, where each second physical qubit set includes a plurality of second physical qubits; For each of the candidate mapping relationships: - For each of the gate operation operators, detect whether two second physical qubits corresponding to the two logical qubits on which the gate operation operator performs the gate operation are adjacent on the physical device based on the candidate mapping relationship, to obtain a detection result; - Based on the plurality of detection results respectively obtained by the plurality of gate operation operators, determine the fitness between the candidate mapping relationship and the gate operation sequence; to obtain the plurality of fitnesses corresponding to the plurality of candidate mapping relationships; Based on the plurality of fitnesses, obtain a target mapping relationship that meets a preset fitness condition from the plurality of candidate mapping relationships; A second mapping unit, configured to apply the target mapping relationship to map the plurality of logical qubits to the physical device, to obtain a plurality of target physical bit units.

13. An electronic device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, it implements the qubit mapping method according to any one of claims 1 to 11.

14. A computer-readable storage medium, where the storage medium stores a computer program, and when the computer program is executed by a processor, it implements the qubit mapping method according to any one of claims 1 to 11.

15. A computer program product, which includes a computer program, and the computer program is read and executed by a processor of a computer device, so that the computer device executes the qubit mapping method according to any one of claims 1 to 11.

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