Semiconductor device

Abstract

The present invention provides a semiconductor device that has a novel configuration. The present invention has a first memory cell, a sense amplifier, a second memory cell, and a computation block. The first memory cell, the sense amplifier, and the computation block are provided in a first element layer. The second memory cell is provided in a second element layer. The second element layer is provided in a layer above the first element layer. The second memory cell is electrically connected to the sense amplifier and the first memory cell via a first bit line. The first memory cell is electrically connected to the computation block via a second bit line. Data that is transferred to the computation block is data written in the first memory cell by making the sense amplifier activate data held in the second memory cell.

Description

Semiconductor Devices

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, efforts to combat global warming have become increasingly important. Energy consumption continues to increase, and carbon dioxide emissions, one of the causes of global warming, have yet to be reduced. Simply reducing energy consumption may actually result in a loss of convenience. To reduce energy consumption without sacrificing convenience, low-power consumption technologies are becoming extremely important.

[0004] In AI (Artificial Intelligence) technology, power consumption increases as performance improves, and technological development for reducing power consumption is being actively pursued. In AI technology, the following operations are repeated: sequentially reading data stored in a memory circuit, performing an operation using the data in an arithmetic circuit, and storing the data obtained by the operation in a memory. Therefore, the power consumption required for data transmission between the memory circuit and the arithmetic circuit becomes dominant. As a countermeasure, a technology known as in-memory computing or near-memory computing has been proposed (e.g., Patent Document 1), in which a memory circuit and an arithmetic circuit are integrated using a transistor including an oxide semiconductor (also referred to as an OS transistor).

[0005] US Patent Publication No. 2021 / 0024083

[0006] In an arithmetic circuit, when a series of arithmetic processes required for AI technology are executed, a memory circuit that can read or write a large amount of data at high speed is required. Although static random access memory (SRAM) memory cells are preferred as such memory circuits, they have disadvantages such as a large area per memory cell and high power consumption when retaining data. On the other hand, memory cells of a memory circuit using OS transistors have advantages such as low power consumption when retaining data, high flexibility in layout, and the ability to increase the number of memory cells per unit area by stacking them, but they read or write data slower than SRAM.

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed with low power consumption, can hold a large amount of data, and can execute a series of arithmetic operations required for AI technology.Another object of one embodiment of the present invention is to provide a miniaturized semiconductor device.Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0008] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0009] One aspect of the present invention is a semiconductor device including a first memory cell, a sense amplifier, a second memory cell, and an operation block, wherein the first memory cell, the sense amplifier, and the operation block are provided in a first element layer, the second memory cell is provided in a second element layer, and the second element layer is provided in an upper layer of the first element layer, the second memory cell is electrically connected to the sense amplifier and the first memory cell via a first bit line, and the first memory cell is electrically connected to the operation block via a second bit line, and data transferred to the operation block is data written to the first memory cell by activating data held in the second memory cell with the sense amplifier.

[0010] One aspect of the present invention is a semiconductor device including a first memory cell, a sense amplifier, a second memory cell, and an operation block, wherein the first memory cell, the sense amplifier, and the operation block are provided in a first element layer, the second memory cell is provided in a second element layer, and the second element layer is provided in an upper layer of the first element layer, the second memory cell is electrically connected to the sense amplifier and the first memory cell via a first bit line, and the first memory cell is electrically connected to the operation block via a second bit line, data transferred to the operation block is data written to the first memory cell by activating data held in the second memory cell with the sense amplifier, and the operation block includes a product-sum operation unit, an activation function operation unit, a data conversion unit, a load / store unit, and a controller unit.

[0011] In one embodiment of the present invention, the semiconductor device preferably includes a first memory cell having a first transistor, and the first transistor has a first semiconductor layer having silicon in a channel formation region.

[0012] In one embodiment of the present invention, the semiconductor device preferably includes a second transistor, and the second transistor includes a second semiconductor layer having an oxide semiconductor in a channel formation region.

[0013] In one aspect of the present invention, the semiconductor device is preferably such that the first memory cell is a memory cell of a static random access memory.

[0014] In one aspect of the present invention, a semiconductor device is preferred in which the first bit line has portions that are arranged parallel to a direction perpendicular to the substrate surface on which the first element layer is provided, between the second memory cell and the sense amplifier, and between the second memory cell and the first memory cell.

[0015] In one aspect of the present invention, the semiconductor device preferably has a product-sum calculation unit that includes an arithmetic circuit and an analog-to-digital conversion circuit, the arithmetic circuit including a cell array that performs product-sum calculations and an input circuit that converts input digital signals into analog signals and inputs the analog signals to the cell array, the analog-to-digital conversion circuit having a function of converting analog signals output by the arithmetic circuit into digital signals, and the input circuit and the analog-to-digital conversion circuit being provided in a first element layer, and the cell array being provided in a second element layer.

[0016] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0017] According to one embodiment of the present invention, a semiconductor device can be provided that operates at high speed, consumes low power, and can store a large amount of data and execute a series of arithmetic operations required for AI technology. Alternatively, according to one embodiment of the present invention, a miniaturized semiconductor device or a semiconductor device with a novel structure can be provided.

[0018] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification.

[0019] FIGS. 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. FIG. 2 is a diagram illustrating an operation example of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 4A and 4B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 5A and 5B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 6A to 6C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 7A to 7G are diagrams illustrating a configuration example of a semiconductor device. FIGS. 8A to 8C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 9A and 9B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 10A and 10B are diagrams illustrating a configuration example of a semiconductor device. FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. FIGS. 12A to 12C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 13A to 13D are diagrams illustrating a configuration example of a semiconductor device. FIG. 14 is a timing chart illustrating an operation example of a semiconductor device. FIG. 15 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 16A is a diagram illustrating a configuration example of a transistor included in the semiconductor device. FIG. 16B is a diagram illustrating an equivalent circuit of a memory cell. 17A to 17C are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 18A is a plan view illustrating an example of the configuration of a transistor included in a semiconductor device. FIGS. 18B to 18D are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 19A is a plan view illustrating an example of the configuration of a transistor included in a semiconductor device. FIGS. 19B to 19D are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 20 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 21A is a diagram illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 21B is a diagram illustrating an equivalent circuit of a memory cell. FIGS. 22A and 22B are plan views illustrating an example of the configuration of a transistor included in a semiconductor device, and FIG. 22C is a cross-sectional view illustrating an example of the configuration of a transistor included in a semiconductor device. FIGS. 23A and 23B are cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 24 is a cross-sectional view illustrating an example of the configuration of a transistor included in a semiconductor device.25A and 25B are schematic diagrams illustrating an example of a configuration of a transistor included in a semiconductor device. FIGS. 26A and 26B are plan views illustrating an example of a configuration of a transistor included in a semiconductor device, and FIGS. 26C and 26D are cross-sectional views illustrating an example of a configuration of a transistor included in a semiconductor device. FIGS. 27A to 27D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 28A to 28D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 29A and 29B are diagrams illustrating an example of an electronic component. FIGS. 30A to 30D are diagrams illustrating an example of an electronic component. FIGS. 31A and 31B are diagrams illustrating an example of an electronic device. FIGS. 32A to 32C are diagrams illustrating an example of an electronic device. FIG. 33 is a diagram illustrating an example of a mainframe computer.

[0020] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0021] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0022] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0023] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0024] Furthermore, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", or "[m, n]" may be added to the reference numeral. For example, the second wiring GL is described as wiring GL[2].

[0025] Embodiment 1 A structure, operation, and the like of a semiconductor device that is one embodiment of the present invention will be described.

[0026] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0027] (Configuration Example of Semiconductor Device 100) FIG. 1A is a schematic diagram illustrating a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 has a function of executing arithmetic processes such as product-sum operations used in AI technology. The semiconductor device 100 capable of executing a series of arithmetic processes required by AI technology is called an NPU (Neural-Network Processing Unit, or Neural Processing Unit). The semiconductor device 100 executes processing related to neural network arithmetic processes using data stored in a memory circuit unit. Specifically, the semiconductor device 100 performs parallel processing of product-sum operations, activation function operations, data conversion operations, and loading and storing of data associated with various arithmetic processes.

[0028] The semiconductor device 100 includes an element layer 10 and an element layer 40 stacked on the element layer 10. In the schematic diagram of Fig. 1A, the element layer 10 and the element layer 40 are shown separated from each other to make it easier to understand the arrangement of the elements that make up the semiconductor device 100. Note that the element layer is a layer in which elements such as transistors or capacitors are provided.

[0029] The element layer 10 has an interface unit 12, a memory circuit unit 11, and an operation block 14. The memory circuit unit 11 has a sense amplifier unit 20 and a memory circuit 30. The operation block 14 has a controller unit 15, a product-sum operation unit 16, an activation function operation unit 17, a data conversion unit 18, and a load / store unit 19.

[0030] 1A, in order to explain the arrangement of each component, the Z-axis direction is defined as a direction perpendicular or approximately perpendicular to the surface of the element layer 10 (e.g., a surface on which an interlayer insulating layer is provided). For ease of understanding, the Z-axis direction may be referred to as a direction perpendicular to the surface of the element layer 10 in the specification. Note that "approximately perpendicular" refers to a state in which the elements are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0031] In this specification and drawings, the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element. For example, in the schematic diagram shown in FIG. 1A, the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the semiconductor device 100. The X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other.

[0032] The element layer 10 has a transistor having silicon (Si transistor) in a semiconductor layer having a channel formation region. The element layer 10 is an element layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or an element layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.

[0033] Although the substrate provided in the element layer 10 is described as a silicon substrate, this embodiment is not limited to this. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a single-crystal silicon substrate. The substrate is not limited to silicon, and may be made of materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide).

[0034] The Si transistors included in the element layer 10 are made of highly crystalline silicon, such as monocrystalline silicon or polycrystalline silicon. The highly crystalline silicon in the element layer 10 allows for high field-effect mobility and faster operation. Therefore, the element layer 10 can integrate the interface unit 12, the sense amplifier unit 20 and the memory circuit 30 included in the memory circuit unit 11, and the controller unit 15, the product-sum operation unit 16, the activation function operation unit 17, the data conversion unit 18, and the load / store unit 19 included in the operation block 14.

[0035] The element layer 40 has a plurality of memory cells 41. Although the element layer 40 is illustrated only above the memory circuit portion 11 included in the element layer 10 in FIG. 1A, the element layer 40 can be provided in any position that overlaps with the element layer 10.

[0036] The memory cell 41 functions as a memory circuit that stores data. The memory cell 41 is connected to the sense amplifier unit 20 and the memory circuit 30 of the memory circuit unit 11. The memory cell 41 stores data used in the calculation block 14 via the sense amplifier unit 20 and the memory circuit 30. The data stored (stored) in the memory cell 41 is data (weight data) corresponding to weight parameters used in product-sum calculations of the neural network. By using digital data as the weight data, the semiconductor device can be made resistant to noise and capable of high-speed calculations. The weight data may also be analog data.

[0037] The element layer 40 includes a transistor including an oxide semiconductor (OS transistor) in a semiconductor layer having a channel formation region. The element layer 40 including the OS transistor can be stacked over the element layer 10. By providing the element layer 40 over the element layer 10, the transistor density per unit area can be increased. Therefore, the storage capacity of a memory circuit including the memory cell 41 provided in the element layer 40 can be increased.

[0038] Examples of metal oxides used in OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). Furthermore, an In—Zn oxide can be used as the metal oxide used in an OS transistor. The metal oxide preferably includes one or more elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0039] 1B is a block diagram illustrating the sense amplifier unit 20 and the memory circuit 30 included in the memory circuit unit 11. Also shown in FIG. 1B are a drive circuit 71 that outputs a signal WEN and a drive circuit 72 that outputs a signal REN. The signal WEN is a signal that controls writing of data to the sense amplifier unit 20 and the memory circuit 30 included in the memory circuit unit 11. The signal REN is a signal that controls reading of data from the sense amplifier unit 20 and the memory circuit 30 included in the memory circuit unit 11.

[0040] In the memory circuit section 11, the sense amplifier section 20 has a plurality of sense amplifiers 21. The memory circuit 30 has a plurality of memory cells 31. The memory cells 31 may be referred to as first memory cells. The memory cells 41 provided in the above-described element layer 40 may be referred to as second memory cells.

[0041] The interface unit 12 receives the input write data W ＤＡＴＡ The interface unit 12 amplifies the potential of the bit line OBL and outputs the read data R ＤＡＴＡ The write data W is output as ＤＡＴＡ In addition to the weight data, the input data input to the calculation block 14 and used for product-sum calculation processing with the weight data, etc. are included.

[0042] The bit line OBL is a wiring for bidirectionally inputting and outputting data between the interface unit 12 and the sense amplifier 21. For example, weight data can be written to the memory cell 41 by providing data from the interface unit 12 to the bit line OBL and activating a bit line pair (bit line BL) connecting the sense amplifier 21 and the memory cell 41. In addition, the bit line OBL can read the output data via the interface unit 12 by selecting the memory cell 31 that holds the output data obtained in the operation block 14.

[0043] The bit line SBL is a wiring for bidirectionally inputting and outputting data between the memory cell 31 and the operation block 14. For example, by selecting a memory cell 31 that holds weight data, data can be output to the operation block 14 via the bit line SBL. Furthermore, by selecting the selected memory cell 31, the output data obtained in the operation block 14 can be held in the memory cell.

[0044] When data input / output via the bit lines OBL and SBL is multi-bit, multiple wirings are also used. The bit line BL connected to the memory cell 41 may be referred to as the first bit line. The bit line OBL connected to the memory cell 31 may be referred to as the second bit line.

[0045] The sense amplifier 21 is connected to the memory cell 41 via a bit line pair (bit line BL and inverted bit line BLB) arranged in the Z direction. The sense amplifier 21 is arranged close to the memory cell 31. Data writing and reading of the sense amplifier 21 is controlled by a drive circuit 71 and a drive circuit 72. The bit line BL and inverted bit line BLB may be referred to as a bit line pair BL-BLB. Similarly, the bit line OBL and inverted bit line OBLB, and the bit line SBL and inverted bit line SBLB may be referred to as a bit line pair OBL-OBLB and a bit line pair SBL-SBLB, respectively.

[0046] The memory cell 31 can select weight data held in the memory cell 41 and update the held data. The memory cell 31 can also select output data obtained in the operation block 14 and update the held data. The memory cell 31 is connected to the memory cell 41 via a bit line pair BL-BLB provided in the Z direction (a direction parallel to the direction perpendicular to the substrate surface). The memory cell 31 is arranged in proximity to the sense amplifier 21. The memory cell 31 is connected to the sense amplifier 21. The memory cell 31 has data writing and reading controlled by a drive circuit 71 and a drive circuit 72.

[0047] The memory cells 31 are memory cells with a high access speed. For example, static random access memory (hereinafter, SRAM) memory cells are preferred as the memory cells 31. The memory cells 31 arranged near the operation block 14 are sometimes called scratch pad memories. Although the storage capacity of the storage circuit 30 having the memory cells 31 is smaller than that of the storage circuit having the memory cells 41, the access speed is high and therefore the memory is preferred as a memory for holding weight data in the operation block 14.

[0048] The controller unit 15 included in the calculation block 14 is a circuit for controlling the calculation processing performed in the calculation block 14. The product-sum calculation unit 16 included in the calculation block 14 is a circuit for performing product-sum calculation processing using weight data input to the calculation block 14. The activation function calculation unit 17 included in the calculation block 14 is a circuit for performing processing using an activation function such as a rectified linear function (ReLU) based on the calculation result obtained by the product-sum calculation unit 16 in the calculation block 14. The data conversion unit 18 included in the calculation block 14 is a circuit for performing data conversion for preprocessing based on the calculation result obtained by the activation function calculation unit 17 in the calculation block 14. The load-store unit 19 included in the calculation block 14 is a circuit for inputting or outputting data for the calculation processing performed in the calculation block 14.

[0049] In this way, in semiconductor device 100, operation block 14 is configured with circuits specialized for neural network operation processing. This configuration makes it possible to reduce the power consumption required for the operation processing compared to when similar operation processing is performed by general-purpose operation circuits such as a CPU and GPU.

[0050] 2 is a schematic diagram illustrating the operation of the semiconductor device 100 according to one embodiment of the present invention, which is described with reference to FIGS. 1A and 1B. FIG. 2 illustrates data held in the memory cell 41, which transitions according to a clock cycle, data held in the memory cell 31, arithmetic processing in the product-sum calculation unit 16, arithmetic processing in the activation function calculation unit 17, arithmetic processing in the data conversion unit 18, and data input or output processing in the load / store unit 19.

[0051] As described above, a memory circuit including the memory cell 41 has a large storage capacity. The memory cell 41 can store more data than the memory cell 31. FIG. 2 illustrates data OS_1 to OS_N (N is an integer equal to or greater than 2) as such data. The data OS_1 to OS_N are data that are stored in the memory cell 41 in advance before an operation is performed in the semiconductor device 100. The data stored in the memory cell 41 also functions as a cache for the data stored in the memory cell 31.

[0052] Data is transferred from memory cell 41 to memory cell 31 at time T01. In FIG. 2, data SR1 is shown as the data transferred to memory cell 31. Data SR1 corresponds to weight data used in calculation block 14. Then, product-sum calculation unit 16 performs calculation process MAC1, which performs product-sum calculation on input data input to calculation block 14 and data SR1. Then, activation function calculation unit 17 performs calculation process AF1 on the data obtained by calculation process MAC1. Then, data conversion unit 18 performs calculation process DC1 on the data obtained by calculation process AF1. Then, load / store unit 19 performs input or output process LS1 on the data obtained by calculation process DC1.

[0053] After time T01, data SR2 to SR9 required by the arithmetic block 14 are read from memory cell 41 to memory cell 31. Thereafter, as shown in FIG. 2, arithmetic operations MAC2 to MAC8, AF2 to AF7, DC2 to DC6, and LS2 to LS5 are executed by pipeline processing.

[0054] The memory cell 41 can store a large amount of data equivalent to the weight data. Therefore, the memory cell 41 can store data required by the memory cell 31. The memory cell 31 can update the data SR1 to SR9 required by the arithmetic block 14 based on the data stored in the memory cell 41 without accessing an external storage circuit. Therefore, it is possible to provide a semiconductor device that operates at high speed, consumes low power, and can store a large amount of data, and can execute a series of arithmetic processing required for AI technology.

[0055] The data held in memory cell 41 can be rewritten separately from the data held in memory cell 31. For example, as shown in Figure 2, the data held at time T02 can be rewritten from data OS_2 to data OS_2x. Also, as shown in Figure 2, the data held at time T03 can be rewritten from data OS_1 to data OS_1x. Also, as shown in Figure 2, for example, data OS_N can be held for a certain period of time without being rewritten.

[0056] A semiconductor device according to one embodiment of the present invention has a configuration in which a large number of sense amplifiers 21 and memory cells 31 are arranged directly under memory cells 41. Therefore, the memory cells 41, the sense amplifiers 21, and the memory cells 31 are arranged in close proximity to each other, and data held in the memory cells 31 can be updated at high speed without accessing an external storage circuit. In addition, the memory cells 31, which have excellent access speeds, are arranged near the processing block 14, and data can be input and output bidirectionally to and from the processing block 14. Therefore, near-memory computing can be realized, and power consumption required for data transmission between circuits can be reduced.

[0057] 3A is a schematic diagram for explaining a configuration example of memory cells 41, sense amplifiers 21, and memory cells 31. Fig. 3A illustrates a configuration in which an element layer 40 having memory cells 41 is provided above the region in which the sense amplifiers 21 and memory cells 31 are provided, as explained in Fig. 1B. Note that, for improved visibility, the memory cells 41 above the sense amplifiers 21 are omitted in Fig. 3A.

[0058] The memory cell 41 is connected to the sense amplifier 21 and the memory cell 31 via a bit line pair BL-BLB. The sense amplifier 21 is connected to the bit line OBL (bit line pair). The memory cell 31 is connected to the bit line SBL (bit line pair).

[0059] 3B is a schematic diagram for explaining a transistor 53 provided in the element layer 10 and a transistor 51 provided in the element layer 40 in the schematic diagram in which the element layer 10 and the element layer 40 are stacked as shown in FIG. 3B also illustrates a bit line pair BL-BLB connecting the memory cell 41 illustrated in FIG. 3A to the sense amplifier 21 and the memory cell 31.

[0060] When the semiconductor layer 52 of the transistor 51 is an oxide semiconductor (metal oxide), the memory cell 41 can be formed using the above-described OS transistor.

[0061] By using silicon for the semiconductor layer 54 of the transistor 53, the sense amplifier 21 and the memory cell 31 can be provided in the element layer 10 configured with the above-described Si transistor.

[0062] By locating the element layer 40 in which the memory cells 41 are provided on the element layer in which the sense amplifiers 21 and the memory cells 31 are provided, it is possible to increase the number of memory circuits per unit area, i.e., the memory capacity, compared to when the memory cells 41, the sense amplifiers 21, and the memory cells 31 are arranged on the same layer. Increasing the memory capacity reduces the number of times data required for arithmetic processing is transferred from an external storage device to the semiconductor device, thereby achieving lower power consumption.

[0063] When a memory circuit such as the memory cell 41 and a memory circuit such as the memory cell 31 are on separate chips, the bus width is limited according to the number of pins on the chip. On the other hand, in a configuration in which the memory cell 41 and the memory cell 31 are stacked as in one embodiment of the present invention, the number of parallel data required for arithmetic processing can be increased according to the opening where the bit line pair BL-BLB is provided, thereby enabling efficient arithmetic processing.

[0064] 4A illustrates sense amplifiers 21_P and 21_Q as the sense amplifier 21 in the schematic diagram shown in Fig. 3A, and memory cells 31_P and 31_Q as the memory cells 31 in the schematic diagram shown in Fig. 3A. Also, an element layer 40 having memory cells 41P and 41Q as the memory cells 41 in the schematic diagram shown in Fig. 3A is illustrated.

[0065] The sense amplifiers 21_P and 21_Q are connected to bit lines OBL_P and OBL_Q, respectively. By configuring the interface unit 12 and the sense amplifiers 21_P and 21_Q to be connected via a plurality of bit lines OBL_P and OBL_Q, it is possible to configure the device so that different data can be written or read at the same time.

[0066] Memory cells 31_P and 31_Q are connected to bit lines SBL_P and SBL_Q, respectively. By configuring the operation block 14 and memory cells 31_P and 31_Q to be connected via a plurality of bit lines SBL_P and SBL_Q, it is possible to configure the system so that different data can be written or read at the same time.

[0067] Memory cell 41P is connected to the bit line pair BL_P and BLB_P. Memory cell 41Q is connected to the bit line pair BL_Q and BLB_Q. It is preferable that the bit line pair BL_P and BLB_P and the bit line pair BL_Q and BLB_Q are not connected. With this configuration, it is possible to write and read different weight data between sense amplifier 21_P and sense amplifier 21_Q, and between memory cell 31_P and memory cell 31_Q, or to perform arithmetic processing using weight data.

[0068] 4B is a diagram illustrating bit lines BL_V connecting between sense amplifier 21_P and memory cell 31_P and memory cell 41P, and between sense amplifier 21_Q and memory cell 31_Q and memory cell 41Q, as shown in FIG. 4A. Bit lines BL_V are provided in the Z direction (a direction parallel to the direction perpendicular to the substrate surface) as shown in FIG. 4A and FIG. 4B.

[0069] 4B is a diagram showing bit lines BL_LD and BL_RD connected to bit line BL_V and provided in element layer 40. The lengths of bit lines BL_LD and BL_RD are preferably the same. In other words, the opening for providing bit line BL_V is preferably located near the center of bit line BL provided in element layer 40. This configuration makes it possible to equalize the distances between sense amplifier 21 and memory cell 31 and memory cell 41, and to equalize the parasitic capacitance between bit line pair BL-BLB.

[0070] The semiconductor device 100A shown in Fig. 5A is a modified example of the semiconductor device 100 shown in Fig. 3A. The schematic diagram shown in Fig. 5A illustrates a case where the element layer 40 in Fig. 3A is provided by stacking a plurality of element layers 40_1 and 40_2.

[0071] 5A includes element layers 40_1 and 40_2 in which a plurality of memory cells 41 are arranged. This configuration allows a manufacturing process using the same photomask to be employed for the plurality of element layers 40_1 and 40_2. Therefore, the memory cells 41 can be manufactured by repeatedly using the same manufacturing process in the vertical direction, thereby reducing manufacturing costs.

[0072] 5B is a schematic diagram illustrating element layers 40_1 to 40_n (n is an integer of 2 or greater) including element layers 40_1 and 40_2 shown in FIG. 5A . Also, FIG. 5B illustrates a bit line pair BL-BLB connecting the memory cell 41 illustrated in FIG. 5A to the sense amplifier 21 and the memory cell 31. As illustrated in FIG. 5B , in the semiconductor device 100A, multiple element layers 40_1 to 40_n are stacked in a vertical or approximately vertical direction relative to the surface of the element layer 10. This configuration allows the number of memory cells 41 arranged per unit area to be increased. This increases the storage capacity of the memory circuit configured with the memory cells 41.

[0073] 5B increases the number of memory cells 41 connected to the bit line pair BL-BLB, and shortens the bit line pair BL-BLB connecting the memory cells 41 to the sense amplifier 21 and the memory cells 31. The stacking of the element layer 40 shortens the wiring distance, reducing the parasitic capacitance generated between the bit line pair BL-BLB, and thus enabling low power consumption. Furthermore, weight data can be read from the memory cells 41 to the sense amplifier 21 at high speed, and the number of bits of weight data can be increased.

[0074] (Configuration Example of Memory Cell 41) A circuit configuration of a memory cell that can be applied to the memory cell 41 will be described. Note that the memory cell 41 is a memory cell that includes an OS transistor. A memory that includes a memory cell that includes an OS transistor may also be referred to as an "OS memory."

[0075] The OS transistor has an extremely low off-state current. Therefore, charge corresponding to data written to the memory cell 41 can be held for a long time. That is, data once written can be held for a long time in the memory cell 41. Therefore, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device of one embodiment of the present invention can be reduced.

[0076] 6A is a diagram illustrating a memory cell array 42 having a plurality of memory cells 41. In FIG. 6A, word lines WL_1 to WL_m and bit lines BL_1 to BL_n are illustrated, which are arranged in a matrix of m rows and n columns (m and n are natural numbers of 2 or greater). Also illustrated are memory cells 41 connected to each word line WL and bit line BL. Note that signals for driving the memory cells 41 and applied to the word lines and bit lines can be output from drive circuits 71 and 72 illustrated in FIG. 1B.

[0077] 6B is a circuit diagram illustrating an example of a circuit configuration applicable to the memory cell 41. The memory cell 41 has a transistor M1 and a capacitor C1 (also referred to as a capacitance element). The transistor M1 is connected to a word line WL, a bit line BL, and the capacitor C1. The capacitor C1 is connected to a wiring PL that functions as a capacitance line. For example, a ground potential GND (low-level power supply potential) is input to the wiring PL. FIG. 6C is a circuit block corresponding to the circuit diagram of FIG. 6B.

[0078] The memory cell 41 shown in FIG. 6B can be a 1T1C type DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) memory cell. DOSRAM refers to a RAM having a 1T (transistor) 1C (capacitor) type memory cell. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current of OS transistors. Because DOSRAM is a 1T1C type memory cell, a large storage capacity can be achieved in the memory cell array 42. Furthermore, by using OS transistors, the data retention period can be extended compared to DRAMs having Si transistors.

[0079] The circuit configuration applicable to the memory cell 41 is not limited to the 1T1C DOSRAM shown in FIG. 6B . For example, FIG. 7A shows another example configuration of a 1T1C memory cell applicable to a DOSRAM. The memory cell 41A shown in FIG. 7A differs from the memory cell 41 shown in FIG. 6B in that the transistor M1 is an OS transistor having a back gate, and the back gate is connected to a wiring BGL. The configuration including the wiring BGL allows the transistor M1 to have improved electrical characteristics.

[0080] The memory cell 41 having an OS transistor can be a nonvolatile oxide semiconductor random access memory (NOSRAM). The memory cell in an NOSRAM is a two-transistor (2T) or three-transistor (3T) gain cell. Since NOSRAM rewrites data by charging and discharging a capacitor, there is no theoretical limit to the number of rewrites and it requires low energy. Therefore, NOSRAM is a memory capable of high-speed operation, low power consumption, and high rewrite endurance. Furthermore, NOSRAM is suitable for long-term data retention because it can read written data nondestructively.

[0081] The memory cell 41B shown in FIG. 7B is a circuit equivalent to a 2T NOSRAM. The memory cell 41B includes a transistor M1, a transistor M2, and a capacitor C1. The transistors M1 and M2 are a write transistor and a read transistor, respectively. The transistors M1 and M2 may be OS transistors having semiconductor layers disposed in different layers or may be OS transistors having semiconductor layers disposed in the same layer. The memory cell 41B is illustrated as being connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, and a wiring SL.

[0082] The memory cell 41C shown in FIG. 7C is a circuit equivalent to a 3T NOSRAM. The memory cell 41C includes transistors M1, M2, and M3, and a capacitor C1. The transistors M1, M2, and M3 are a write transistor, a read transistor, and a select transistor, respectively. The inclusion of transistor M3 more reliably blocks current flowing between the source line and the read bit line RBL, regardless of the conduction state of transistor M2. The transistors M1, M2, and M3 may be OS transistors whose semiconductor layers are arranged in different layers or in the same layer.

[0083] Since the write transistor is an OS transistor, turning off the write transistor allows the memory cells 41B and 41C to continue to hold charge according to data. Therefore, the memory cells 41B and 41C do not consume power to hold data. Therefore, the memory cells 41B and 41C can function as low-power memory cells capable of holding data for a long period of time. The gate of the read transistor functions as a node that holds charge according to data. The read transistor is a transistor that has the function of passing a current according to the potential of the node that holds charge according to data. The select transistor is a transistor that controls the current flowing through the read transistor.

[0084] 7D shows another example of the configuration of a 2T gain cell. A memory cell 41D shown in FIG. 7D differs from the memory cell 41B shown in FIG. 7B in that the transistors M1 and M2 are OS transistors each having a back gate, and the back gates are connected to a wiring BGL. For example, a ground potential GND (low-level power supply potential) is input to the wiring BGL. The inclusion of the wiring BGL allows the transistors M1 and M2 to have improved electrical characteristics.

[0085] 7E shows another example of the configuration of a 3T gain cell. A memory cell 41E shown in FIG. 7E differs from the memory cell 41C shown in FIG. 7C in that the transistors M1, M2, and M3 are each OS transistors having back gates connected to a wiring BGL. A ground potential GND (low-level power supply potential), for example, is input to the wiring BGL. The inclusion of the wiring BGL allows the transistors M1, M2, and M3 to have improved electrical characteristics.

[0086] 7F shows another example of the configuration of a 2T-type gain cell. The memory cell 41F shown in FIG. 7F differs from the memory cell 41B shown in FIG. 7B in that the capacitor C1 is omitted by using the gate capacitance of the read transistor, and the line SL is omitted. By omitting the capacitor C1, it is possible to reduce the size of the semiconductor device.

[0087] The transistors M1 and M2 in the 2T gain cell shown in FIG. 7F are preferably vertical transistors in which the source electrode and the drain electrode are located at different heights. In a vertical transistor, current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.

[0088] In a vertical transistor, the source region, the channel formation region, and the drain region can be at least partially overlapped in a planar view, compared to a horizontal transistor (also called a planar transistor) in which the source electrode and the drain electrode are located at the same height. Therefore, the vertical transistor can have a smaller occupied area (also called a footprint). Furthermore, the vertical transistor has a structure in which the channel length can be made shorter and the channel width can be made larger, so that the on-resistance can be made smaller (the on-current can be made larger).

[0089] Fig. 7G shows another example of the configuration of a 3T gain cell. Memory cell 41G shown in Fig. 7G differs from memory cell 41C shown in Fig. 7C in that capacitor C1 is omitted by using the gate capacitance of the read transistor, and wiring PL is omitted. Transistors M1, M2, and M3 included in the 3T gain cell shown in Fig. 7G are vertical transistors in which the source electrode and drain electrode are located at different heights, thereby reducing the occupied area (also referred to as footprint) and reducing the on-resistance (increasing the on-current).

[0090] (Configuration Example of Sense Amplifier 21) An example of the circuit configuration of the sense amplifier 21 will be described. Fig. 8A is a circuit diagram of the sense amplifier 21. Fig. 8B shows a circuit block corresponding to the circuit diagram. Fig. 8C illustrates a configuration example that combines the circuit block of the memory cell 41 shown in Fig. 6C with the circuit block of the sense amplifier 21 shown in Fig. 8B.

[0091] 8A includes an amplifier circuit 61, a precharge circuit 62, a precharge circuit 63, and a switch circuit 64. The amplifier circuit 61, the precharge circuit 62, the precharge circuit 63, and the switch circuit 64 are each connected to the bit line pair BL-BLB. Note that signals for driving the sense amplifier 21 can be output from the drive circuits 71 and 72 shown in FIG. 1B.

[0092] The amplifier circuit 61 has a function of applying a predetermined potential to each of the wiring SAP and the wiring SAN to output a potential corresponding to one of the binary data values ​​to the bit line BL and output a potential corresponding to the other of the binary data values ​​to the inverted bit line BLB. The amplifier circuit 61 includes transistors 61_1, 61_2, 61_3, and 61_4. The transistors 61_1 and 61_2 are p-channel transistors. The transistors 61_3 and 61_4 are n-channel transistors. The transistors 61_1 and 61_3 form an inverter circuit that receives the inverted bit line BLB as an input, the bit line BL as an output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line. The transistors 61_2 and 61_4 form an inverter circuit that receives the bit line BL as an input, the inverted bit line BLB as an output, the wiring SAP as a high-potential power supply line, and the wiring SAN as a low-potential power supply line.

[0093] The precharge circuit 62 has a function of precharging the bit line pair BL-BLB to a potential VPRE in response to a signal EQB. Specifically, the precharge circuit 62 includes transistors 62_1, 62_2, and 62_3. Each of the transistors 62_1, 62_2, and 62_3 is a p-channel transistor. The transistor 62_1 has a function of turning on or off the bit line pair BL-BLB in response to the signal EQB. The transistor 62_2 has a function of precharging the bit line BL to a potential VPRE in response to the signal EQB. The transistor 62_3 has a function of precharging the inverted bit line BLB to a potential VPRE in response to the signal EQB.

[0094] The precharge circuit 63 has a function of precharging the bit line pair BL-BLB to a potential VPRE in response to a signal EQ. Specifically, the precharge circuit 63 includes transistors 63_1, 63_2, and 63_3. Each of the transistors 63_1, 63_2, and 63_3 is an n-channel transistor. The transistor 63_1 has a function of turning on or off the bit line pair BL-BLB in response to the signal EQ. The transistor 63_2 has a function of precharging the bit line BL to a potential VPRE in response to the signal EQ. The transistor 63_3 has a function of precharging the inverted bit line BLB to a potential VPRE in response to the signal EQ.

[0095] The switch circuit 64 has a function of bringing the bit line pair BL-BLB and the bit line OBL (bit line pair OBL-OBLB) into a conductive or non-conductive state in response to a column selection signal CSE. Specifically, the switch circuit 64 includes a transistor 64_1 and a transistor 64_2. Each of the transistors 64_1 and 64_2 is an n-channel transistor. The transistor 64_1 has a function of bringing the bit line pair BL-BLB and the bit line BL and the bit line OBL into a conductive or non-conductive state in response to the column selection signal CSE. The transistor 64_2 has a function of bringing the bit line pair BL-BLB and the bit line pair OBL-OBLB into a conductive or non-conductive state in response to the column selection signal CSE.

[0096] Fig. 8B shows a circuit block corresponding to the circuit diagram of the sense amplifier 21 described in Fig. 8A. Fig. 8C shows a configuration example in which the circuit block of the sense amplifier 21 shown in Fig. 8B is combined with the circuit block of the memory cell 41 shown in Fig. 6C.

[0097] 8A to 8C, the sense amplifier 21 can amplify the potential difference between the bit line BL and the inverted bit line BLB, which varies depending on the charge held in the memory cell 41 when data is read from the memory cell 41, and output the amplified potential difference to the bit line pair OBL-OBLB in response to the column selection signal CSE. Also, the sense amplifier 21 can apply the potential difference between the bit line pair OBL-OBLB to the bit line pair BL-BLB in response to the column selection signal CSE, and write data to the memory cell 41 connected to the bit line pair BL-BLB using the amplified potential difference.

[0098] (Configuration example of memory cell 31) A circuit configuration of a memory cell applicable to the memory cell 31 will be described. The memory cell 31 is a memory cell having a Si transistor. As described above, the memory cell 31 is a memory cell applicable to an SRAM with a high access speed. A multi-port SRAM memory cell is particularly preferable.

[0099] An example of a multi-port SRAM memory cell that can be applied to memory cell 31 is shown in FIG. 9A.

[0100] 9A shows a memory cell 31A having transistors M1A, M1B, M6A, and M6B, inverters INV1 and INV2, bit lines BL and SBL, inverted bit lines BLB and SBLB, and word lines WL1 and WL2. Note that signals for driving the memory cell 31A can be output from drive circuits 71 and 72 shown in FIG. 1B.

[0101] 9A correspond to the bit line pair BL-BLB connected to the memory cell 41 and sense amplifier 21. The bit lines SBL and SBLB correspond to the bit line pair SBL connected to the operation block 14. The word line WL1 is a word line for controlling the writing of data provided to the bit line pair BL-BLB to the memory cell 31A and the reading of data held in the memory cell 31A to the bit line pair BL-BLB. The word line WL2 is a word line for controlling the writing of data provided to the bit line pair of the bit line SBL connected to the operation block 14 to the memory cell 31A and the reading of data held in the memory cell 31A to the bit line pair of the bit line SBL connected to the operation block 14.

[0102] 9B shows an example of a multi-port SRAM memory cell that can be applied to memory cell 31. Note that signals for driving memory cell 31B can be output from drive circuits 71 and 72 shown in FIG.

[0103] FIG. 9B illustrates a memory cell 31B having transistors M1A, M6A, M7, and M8, inverters INV1 and INV2, bit line BL, inverted bit line BLB, bit line SBL, and word lines WL1 and WL2.

[0104] 9B correspond to the bit line pair BL-BLB connected to the memory cell 41 and sense amplifier 21. The bit line SBL corresponds to the bit line SBL connected to the operation block 14. The word line WL1 is a word line for controlling writing of data provided to the bit line pair BL-BLB to the memory cell 31B and reading of data held in the memory cell 31B to the bit line pair BL-BLB. The word line WL2 is a word line for controlling reading of data held in the memory cell 31B to the bit line SBL connected to the operation block 14.

[0105] 9A , it is preferable that the writing and reading of data to the memory cell 31 can be controlled separately. This configuration can improve the speed at which the processing block 14 accesses the data stored in the memory cell 31, while also enabling the rewriting of data in the memory cell 31 based on a large amount of data stored in the memory cell 41.

[0106] As described above, a semiconductor device according to one embodiment of the present invention has a configuration in which a large number of sense amplifiers 21 and memory cells 31 are arranged directly under the memory cells 41. Therefore, the memory cells 41, the sense amplifiers 21, and the memory cells 31 are arranged in close proximity to each other, and data held in the memory cells 31 can be updated at high speed. In addition, the memory cells 31 with excellent access speed are arranged near the operation block 14. Therefore, near-memory computing can be realized, and power consumption required for data transmission between circuits can be reduced.

[0107] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0108] Embodiment 2 In this embodiment, an example of a product-sum operation unit that can be used in a semiconductor device of one embodiment of the present invention will be described.

[0109] <Configuration Example of Product-Sum Calculation Unit> FIG. 10A is a block diagram illustrating a configuration example of a product-sum calculation unit 16A that can be applied to the product-sum calculation unit 16 included in the semiconductor device 100 described in FIG. 1A of the first embodiment.

[0110] The product-sum calculation unit 16A includes an arithmetic circuit MAC1 and an analog-to-digital conversion circuit 79.

[0111] The arithmetic circuit MAC1 receives the digital signal D ＩＮＤ is converted into an analog signal, a multiplication and accumulation operation is performed on the first data (e.g., weight data) and the second data (e.g., input data), and an analog signal D corresponding to the multiplication and accumulation operation is generated. ＭＡＣＡ It has the function of outputting.

[0112] The analog-to-digital converter 79 converts the analog signal D output from the arithmetic circuit MAC1 into ＭＡＣＡ is converted into a digital signal D ＭＡＣＤ and transmits and receives signals to and from the memory circuit unit 11 as well as other circuits in the operation block 14 (the controller unit 15, the activation function operation unit 17, the data conversion unit 18, and the load / store unit 19).

[0113] The arithmetic circuit MAC1 has an input circuit WCS, an input circuit XCS, a control circuit WSD, and a cell array CA.

[0114] The arithmetic circuit MAC1 is a circuit that performs a product-sum operation on first data (weight data) corresponding to the potential held in each cell and input second data (input data). Note that the first data and second data may be, for example, analog data or multi-valued data (discrete data).

[0115] The input circuit WCS and the input circuit XCS have the function of converting the first data and the second data of the digital signal supplied from the outside into the first data and the second data of the analog signal and providing them to the cells for performing the sum-of-products operation in the arithmetic circuit MAC1. The control circuit WSD has the function of outputting signals for controlling the cells for performing the sum-of-products operation in the arithmetic circuit MAC1.

[0116] FIG. 10B is a block diagram of a semiconductor device 100A in which the product-sum operation unit 16 in the configuration of the semiconductor device 100 described in FIG. 1A of the first embodiment is replaced with the product-sum operation unit 16A described in FIG. 10A.

[0117] The analog-to-digital conversion circuit 79 , the input circuit WCS, the input circuit XCS, and the control circuit WSD are circuits provided in the element layer 10 .

[0118] The cell array CA is a circuit that can be provided in the same element layer (shown as element layer 40A in the figure) as the element layer 40 having the memory cells 41 described in the first embodiment. That is, the transistors included in the plurality of cells included in the cell array CA can be OS transistors. Therefore, the cell array CA can be provided above the region where the analog-to-digital conversion circuit 79, the input circuit WCS, the input circuit XCS, and the control circuit WSD included in the element layer 10 are provided. As a result, the cell array CA can be arranged in close proximity to the analog-to-digital conversion circuit 79, the input circuit WCS, the input circuit XCS, and the control circuit WSD, thereby reducing the power consumption required for signal input / output.

[0119] OS transistors have extremely low off-state current. Therefore, a cell using an OS transistor can be used as a cell that stores first analog data. The cell array CA can store multi-bit digital data as analog values. Furthermore, the cell array CA can achieve low power consumption by performing a product-sum operation using a subthreshold current.

[0120] 11 shows an example of the configuration of the arithmetic circuit MAC1 that performs a product-sum operation on first data and second data. The arithmetic circuit MAC1 includes the input circuit WCS, input circuit XCS, control circuit WSD, and cell array CA described above, as well as a circuit SWS1 and a circuit SWS2.

[0121] <<Cell Array CA>> Here, a specific example of the cell array CA will be described.

[0122] The cell array CA includes cells 91_1,1 through 91_m,n and cells 81_1 through 81_m. For example, each of cells 91_1,1 through 91_m,n includes a transistor 92, a transistor 93, a transistor 94, and a capacitor 95. For example, each of cells 81_1 through 81_m includes a transistor 82, a transistor 83, a transistor 84, and a capacitor 85. In the following description, "one of the source or the drain" may be referred to as a "first terminal," and "the other of the source or the drain" may be referred to as a "second terminal." In the following description, "one electrode" of a capacitor may be referred to as a "first terminal," and "the other electrode" may be referred to as a "second terminal."

[0123] As shown in FIG. 11, the transistors and capacitances of cells 91_1,1 to 91_m,n and cells 81_1 to 81_m are connected to at least one of wirings WSL_1 to WSL_m (wirings WSL), wirings XCL_1 to XCL_m (wirings XCL), wiring VBL, wirings WCL_1 to WCL_n (wirings WCL), and wirings that apply ground potential.

[0124] 11 , in cell 91_1,1, the connection point between the first terminal of transistor 92, the gate of transistor 94, and the first terminal of capacitor 95 is designated as node NN_11. Similarly, in FIG. 11 , in cells 91_1,n, 91_m,1, and 91_m,n, similar connection points are designated as nodes NN_1n, NN_m1, and NN_mn. Similarly, in FIG. 11 , in cells 81_1 and 81_m, similar connection points are designated as nodes NN_ref1 and NNref_m. Note that nodes NN_11 to NN_mn and nodes NNref_1 to NNref_m function as the retention nodes (node ​​NN, node NNref) of the respective cells.

[0125] The cells 81 (cells 81_1,1 to 81_m) have the function of causing a set current to flow when writing data and when reading data, thereby executing an arithmetic operation in the cells 91 (cells 91_1,1 to 91_m,n). Specifically, when writing data, the cells 81 have a function of causing a reference current to flow to hold a reference voltage within the cells 81, and then, when reading data, have a function of causing a current corresponding to input data (X) to be given to the cells 91 to flow through the cells 81, thereby controlling the current flowing through the cells 91.

[0126] The connections within the cell 81 will now be described.

[0127] The gate of the transistor 82 is connected to the wiring WSL. One of the source or the drain of the transistor 82 is connected to one of the source or the drain of the transistor 83 and the wiring XCL. The other of the source or the drain of the transistor 82 is connected to the gate of the transistor 84 and one electrode of the capacitor 85. When writing data, the transistor 82 is turned on to write a reference voltage to a holding node (the gate of the transistor 84) in the cell 81, and is turned off to hold the reference voltage in the cell 81.

[0128] A gate of the transistor 83 is connected to the wiring VBL. A back gate of the transistor 83 is connected to the other of the source and the drain of the transistor 84. One of the source and the drain of the transistor 83 is connected to one of the source and the drain of the transistor 82 and the wiring XCL. The other of the source and the drain of the transistor 83 is connected to one of the source and the drain of the transistor 84. The transistor 83 sets the potential of the one of the source and the drain of the transistor 84 to a potential corresponding to the potential of the gate of the transistor 83.

[0129] The gate of the transistor 84 is connected to the other of the source or drain of the transistor 82 and one electrode of the capacitor 85. A holding node to which the gate of the transistor 84, the other of the source or drain of the transistor 82, and one electrode of the capacitor 85 are connected can be set to a potential corresponding to the current flowing through the transistor 84. The back gate of the transistor 84 is connected to the other of the source or drain of the transistor 84. The other of the source or drain of the transistor 84 is connected to a wiring that applies a low power supply potential (e.g., ground potential). The wiring that applies the ground potential functions as a wiring for flowing current between the source and drain of the transistor 84. The other of the source or drain of the transistor 84 is connected to the back gate of the transistor 83 and the back gate of the transistor 84. A fixed potential is applied to the back gate of the transistor 83 and the back gate of the transistor 84, thereby stabilizing the transistor characteristics of the transistors 83 and 84. The transistor 84 flows an output current corresponding to the potential of the gate of the transistor 84 to the other of the source or drain.

[0130] One electrode of the capacitor 85 is connected to the other of the source and the drain of the transistor 82 and the gate of the transistor 84. The other electrode of the capacitor 85 is connected to the wiring XCL. The capacitor 85 has a function of changing the potential of one electrode in response to a change in the potential of the other electrode when the other electrode is in a floating state.

[0131] When writing data, the cell 91 has a function of flowing a current corresponding to the weight data (W) stored in the cell 91, thereby storing a voltage corresponding to the current. When reading data, the cell 91 has a function of flowing a current corresponding to an operation performed on the weight data and input data, by boosting the voltage stored when writing data according to the current flowing through the cell 91. The weight data may be referred to as first data, and the input data may be referred to as second data. The weight data may be, for example, data (weight data) corresponding to weight parameters used in a product-sum operation of an artificial neural network.

[0132] The connections within the cell 91 will now be described.

[0133] The gate of transistor 92 is connected to wiring WSL. One of the source or drain of transistor 92 is connected to one of the source or drain of transistor 93 and wiring WCL. The other of the source or drain of transistor 92 is connected to the gate of transistor 94 and one electrode of capacitor 95. When writing data, transistor 92 is turned on to write a voltage corresponding to weight data into cell 91, and by turning off transistor 92, the voltage corresponding to the weight data can be held in cell 91.

[0134] The gate of the transistor 93 is connected to the wiring VBL. The back gate of the transistor 93 is connected to the other of the source and the drain of the transistor 94. The one of the source and the drain of the transistor 93 is connected to the one of the source and the drain of the transistor 92 and the wiring WCL. The other of the source and the drain of the transistor 93 is connected to the one of the source and the drain of the transistor 94. The transistor 93 sets the potential of the one of the source and the drain of the transistor 94 to a potential corresponding to the potential of the gate of the transistor 93.

[0135] The gate of the transistor 94 is connected to the other of the source or drain of the transistor 92 and one electrode of the capacitor 95. The back gate of the transistor 94 is connected to the other of the source or drain of the transistor 94. The other of the source or drain of the transistor 94 is connected to a wiring that applies a low power supply potential (e.g., ground potential). The wiring that applies the ground potential functions as a wiring for flowing a current between the source and drain of the transistor 94. The other of the source or drain of the transistor 94 is connected to the back gate of the transistor 93 and the back gate of the transistor 94. A fixed potential is applied to the back gate of the transistor 93 and the back gate of the transistor 94, thereby stabilizing the transistor characteristics of the transistors 93 and 94. The transistor 94 flows an output current corresponding to the potential of the gate of the transistor 94 to the other of the source or drain.

[0136] One electrode of the capacitor 95 is connected to the other of the source or the drain of the transistor 92 and the gate of the transistor 94. The other electrode of the capacitor 95 is connected to the wiring XCL. When one electrode of the capacitor 95 is in a floating state, the potential of one electrode of the capacitor 95 changes in response to a change in the potential of the other electrode.

[0137] Next, the transistors included in the cells 81 and 91 will be described.

[0138] Unless otherwise specified, the transistors 84 and 94 operate in the subthreshold region. The drain current Id of a transistor operating in the subthreshold region can be expressed by the following equation (1).

[0139]

[0140] In formula (1), I ０ is V ｇ =V ｔｈ The drain current when ｇ is the gate voltage, V ｔｈ is the threshold voltage, η is a coefficient determined by the device structure, etc., and k Ｂis the Boltzmann constant, and T is temperature. As shown in equation (1), the drain current Id of a transistor operating in the subthreshold region does not depend on the drain voltage. The current flowing through transistor 84 and transistor 94 is the current that flows when they operate in the subthreshold region. The current in the subthreshold region of transistor 84 and transistor 94 can reduce the influence of variations in the drain voltage. This can improve the accuracy of the data obtained by calculation.

[0141] In this specification and elsewhere, the subthreshold region refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes the regions that can be considered as the regions described above.

[0142] The drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with gate voltage, regardless of drain voltage. Circuit operation using the subthreshold current can reduce the effect of drain voltage variations.

[0143] When turned off, the transistors 92 and 82 have a function of holding potentials of the gates of the transistors 84 and 94. Specifically, they have a function of holding potentials according to data applied to the gate of the transistor 94 through the transistor 92. As an example, the transistors 92 and 82 are preferably OS transistors.

[0144] An OS transistor has an extremely small current flowing between its source and drain in an off state, that is, a small leakage current. By using an OS transistor as the transistor 92 and / or the transistor 82, the leakage current of the transistor 92 and / or the transistor 82 can be suppressed, thereby reducing the power consumption of the semiconductor device 100. Specifically, fluctuations in the potentials held at the gates of the transistors 84 and 94 can be significantly reduced, thereby reducing the number of refresh operations for the potentials. Furthermore, reducing the number of refresh operations can reduce the power consumption of the semiconductor device 100. Furthermore, by significantly reducing the leakage current from the retention node to the wiring WCL or XCL, the cell can retain the potential of the retention node for a long time.

[0145] When the gate voltage of an OS transistor is lower than the threshold voltage of the transistor, −２０ Less than A, 1 x 10 −２２ Less than A or 1 x 10 −２４ An extremely small drain current per 1 μm of channel width, such as less than 1.0×10 A, can flow. −８ A or less, 1.0×10 −１２ A or less, or 1.0 x 10 −１５ A or less per 1 μm of channel width can flow. Therefore, the OS transistor can flow subthreshold currents of different magnitudes in the range of gate voltages in which it operates in the subthreshold region. That is, the OS transistor can operate in a wide range of gate voltages in the subthreshold region. Specifically, when the threshold voltage of the OS transistor is V ｔｈ In the subthreshold region, (V ｔｈ -1.0V) or more V ｔｈ Below, or (V ｔｈ -0.5V) or more V ｔｈ The circuit can operate using gate voltages in the following voltage ranges:

[0146] On the other hand, Si transistors have a large off-state current and operate in a narrow range of gate voltages in the subthreshold region. When using a subthreshold current, an OS transistor can operate in a circuit over a wider range of gate voltages than a Si transistor.

[0147] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. Therefore, the OS transistor is less susceptible to drain-induced barrier lowering (DIBL), which is one of the short-channel effects, compared to an inversion-type transistor having a pn junction. That is, an OS transistor has higher resistance to the short-channel effect than a Si transistor.

[0148] Furthermore, by using OS transistors for the transistors 93, 94, and the transistors 83, 84, the transistors can operate over a wide current range in the subthreshold region, thereby reducing current consumption. Furthermore, by using OS transistors for the transistors 93, 94, and the transistors 83, 84, the transistors can be manufactured simultaneously with the transistors 82 and 92, which may shorten the manufacturing process of the arithmetic circuit. The transistors 93, 94, and the transistors 83, 84 can be Si transistors containing silicon in their channel formation regions, other than OS transistors. Examples of silicon that can be used include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and single crystal silicon.

[0149] When the transistors 93, 94 and the transistors 83, 84 are Si transistors, it is preferable to provide a configuration that functions as a back gate of the transistor, for example, a configuration in which an electrode or a body electrode is provided, and the potential applied to the back gate is the ground potential applied to the other of the source or drain of the transistors 94, 84. By using such a configuration, the electrical characteristics of the transistors 93, 94 and the transistors 83, 84 can be stabilized.

[0150] Next, the wiring WSL, the wiring XCL, the wiring VBL, and the wiring WCL connected to the cell 81 and the cell 91 will be described.

[0151] The wiring WSL receives a signal that controls the on / off of the transistors 82 and 92, which function as switches. The wiring WSL functions as a write word line when writing data to the cells 81 and 91. Data is written to the cells 81 and 91 by applying a current or voltage corresponding to the data to be written to the wiring XCL or the wiring WCL. The data is written by turning on the transistors 82 and 92. In this case, the wiring WCL is set to an H level (high-level potential). Furthermore, in the cells 81 and 91, the transistors 82 and 92 are controlled to be turned off, thereby retaining the data in the cells 81 and 91. In this case, the wiring WCL is set to an L level (low-level potential).

[0152] The wiring WCL supplies a current (weight current or constant current I Ｗｕｔ ) or a function of applying a drain voltage Vd for causing a current to flow in accordance with the potential held in the processing cell.

[0153] The wiring XCL supplies a current (reference current or constant current I) corresponding to the reference data to the cells 81 and 91. Ｘｕｔ ), or a current (input current or current I Ｘ ) has the function of flowing.

[0154] The wiring VBL is a wiring to which a constant potential Vb is applied. The constant potential Vb is a potential for fixing the potentials of the drain terminals of the transistors 84 and 94 in the cells 81 and 91. By applying the constant potential Vb to the gates of the transistors 83 and 93, it is possible to stabilize the transistor characteristics, such as the threshold voltages of the transistors 84 and 94, in response to fluctuations in the potential of the wiring WCL.

[0155] In particular, when transistor 94 and transistor 84 are short-channel transistors with short channel lengths, DIBL reduces the threshold voltage, causing the drain current Id to depend on the drain voltage Vd. Therefore, it is effective to apply a constant potential Vb to the gates of transistors 83 and 93, thereby reducing the change in the drain voltage of transistors 84 and 94. This configuration can improve the accuracy of data obtained by calculation.

[0156] 11 have back gates, other structures are also possible. For example, the transistors 82 and 92 shown in FIG. 11 may have a structure without a back gate, that is, may have a single-gate structure. The potential or signal applied to the back gate may be a fixed potential such as ground potential, or a signal applied to the gate.

[0157] 11 are n-channel transistors, other configurations are also possible. For example, some or all of the transistors 92 to 94 and the transistors 82 to 84 can be replaced with p-channel transistors. Note that when some or all of the transistors 92 to 94 and the transistors 82 to 84 are replaced with p-channel transistors, the voltages applied to the wirings may be changed as necessary so that the transistors 92 to 94 and the transistors 82 to 84 operate as desired.

[0158] It is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors included in each cell of the cell array CA are equal to each other. For example, it is preferable that the sizes of transistors 82 and 92 are equal to each other. For example, it is preferable that the sizes of transistors 83 and 93 are equal to each other. For example, it is preferable that the sizes of transistors 84 and 94 are equal to each other.

[0159] By making the transistors equal in size, the electrical characteristics of the respective transistors can be made substantially equal. Therefore, by making the size of the transistor 92 included in each of the cells 91_1,1 through 91_m,n equal, making the size of the transistor 93 included in each of the cells 91_1,1 through 91_m,n equal, and making the size of the transistor 94 included in each of the cells 91_1,1 through 91_m,n equal, the cells 91_1,1 through 91_m,n can perform substantially the same operation under the same conditions. Here, the same conditions refer to, for example, input potentials to the source, drain, gate, etc. of the transistor 92, input potentials to the source, drain, gate, etc. of the transistor 93, input potentials to the source, drain, gate, etc. of the transistor 94, and voltages held in each of the cells 91_1,1 through 91_m,n. Furthermore, by making the sizes of the transistors 82 included in each of the cells 81_1 to 81_m equal, making the sizes of the transistors 83 included in each of the cells 81_1 to 81_m equal, and making the sizes of the transistors 84 included in each of the cells 81_1 to 81_m equal, for example, the cells 81_1 to 81_m can perform substantially the same operations and achieve substantially the same results. The cells 81_1 to 81_m can perform substantially the same operations under the same conditions. The same conditions here refer to, for example, input potentials to the source, drain, gate, etc. of the transistor 82, input potentials to the source, drain, gate, etc. of the transistor 83, input potentials to the source, drain, gate, etc. of the transistor 84, and voltages held in each of the cells 81_1 to 81_m.

[0160] <<Circuit SWS1, Circuit SWS2>> Here, specific examples of the circuit SWS1 and the circuit SWS2 will be described.

[0161] The circuit SWS1 includes, for example, transistors F3_1 to F3_n. A first terminal of the transistor F3_1 is connected to the wiring WCL_1, a second terminal of the transistor F3_1 is connected to the input circuit WCS, and a gate of the transistor F3_1 is connected to the wiring SWL1. A first terminal of the transistor F3_n is connected to the wiring WCL_n, a second terminal of the transistor F3_n is connected to the input circuit WCS, and a gate of the transistor F3_n is connected to the wiring SWL1.

[0162] For example, a transistor applicable to the transistors included in the cell array CA can be used as each of the transistors F3_1 to F3_n. In particular, it is preferable to use an OS transistor as each of the transistors F3_1 to F3_n.

[0163] The circuit SWS1 functions as a circuit that turns on or off the connection between the input circuit WCS and each of the wirings WCL_1 to WCL_n.

[0164] The circuit SWS2 includes, for example, transistors F4_1 to F4_n. A first terminal of the transistor F4_1 is connected to the wiring WCL_1, a second terminal of the transistor F4_1 is connected to the wiring OL_1, and a gate of the transistor F4_1 is connected to the wiring SWL2. A first terminal of the transistor F4_n is connected to the wiring WCL_n, a second terminal of the transistor F4_n is connected to the wiring OL_n, and a gate of the transistor F4_n is connected to the wiring SWL2.

[0165] For example, a transistor applicable to the transistors included in the cell array CA can be used as each of the transistors F4_1 to F4_n. In particular, it is preferable to use an OS transistor as each of the transistors F4_1 to F4_n.

[0166] The circuit SWS2 has a function of turning on or off the wirings between the wiring WCL_1 and the wiring OL_1 and between the wiring WCL_n and the wiring OL_n.

[0167] The input circuit WCS has a function of supplying data to be stored in each cell of the cell array CA.

[0168] The input circuit XCS is connected to the wirings XCL_1 to XCL_m. The input circuit XCS has a function of supplying a current corresponding to reference data or second data, which will be described later, to each of the cells 81_1 to 81_m included in the cell array CA.

[0169] The control circuit WSD is connected to the wirings WSL_1 to WSL_m. When writing first data to the cells 91_1,1 to 91_m,n, the control circuit WSD has a function of selecting a row of the cell array CA to which the first data is to be written by supplying a predetermined signal to the wirings WSL_1 to WSL_m. In other words, the wirings WSL_1 to WSL_m function as write word lines.

[0170] The control circuit WSD is connected to, for example, a wiring SWL1 and a wiring SWL2. The control circuit WSD has a function of turning on or off the connection between the input circuit WCS and the cell array CA by supplying a predetermined signal to the wiring SWL1, and a function of turning on or off the connection between the wirings OL_1 to OL_n and the cell array CA by supplying a predetermined signal to the wiring SWL2.

[0171] <<Input Circuit WCS, Input Circuit XCS>> Here, specific examples of the input circuit WCS and the input circuit XCS will be described.

[0172] First, the input circuit WCS will be described. Fig. 12A is a block diagram showing an example of the input circuit WCS. Note that Fig. 12A also illustrates a circuit SWS1, a transistor F3, a wiring SWL1, and a wiring WCL in order to show electrical connections between the input circuit WCS and peripheral circuits. The transistor F3 is any one of the transistors F3_1 to F3_n included in the arithmetic circuit MAC1 of Fig. 11, and the wiring WCL is any one of the wirings WCL_1 to WCL_n included in the arithmetic circuit MAC1 of Fig. 11.

[0173] 12A includes a switch SWW, as an example. A first terminal of the switch SWW is connected to a second terminal of the transistor F3, and the second terminal of the switch SWW is connected to a wiring VINIL1. The wiring VINIL1 functions as a wiring that applies an initialization potential to the wiring WCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCL, and is turned off otherwise.

[0174] The switch SWW may be, for example, an electrical switch such as an analog switch or a transistor. When a transistor is used as the switch SWW, the transistor may be, for example, a transistor that can be used in the cell array CA. In addition to an electrical switch, a mechanical switch may also be used.

[0175] 12A has a plurality of current sources CS. Ｋ In this case, the input circuit WCS has a function of outputting the first data of 2 Ｋ The input circuit WCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the K-th bit as a current. Ｋ−１ There are individual ones.

[0176] 12A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is connected to the second terminal of the transistor F3 of the circuit SWS1. The terminal T2 of one current source CS is connected to the wiring DW_1, and the terminals T2 of the two current sources CS are connected to the wiring DW_2. Ｋ−１ Each of the terminals T2 of the current sources CS is connected to the wiring DW_K.

[0177] The multiple current sources CS of the input circuit WCS each have the same constant current I Ｗｕｔ The constant current I Ｗｕｔ is the normalized current I Ｗｕｔ In reality, during the manufacturing stage of the arithmetic circuit MAC1, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant current I output from each of the terminals T1 of the multiple current sources CS may be Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of the plurality of current sources CS included in the input circuit WCS is Ｗｕｔ The following explanation will be given assuming that there is no error.

[0178] The wirings DW_1 to DW_K are connected to a current source CS and supplied with a constant current I Ｗｕｔ Specifically, for example, when a high-level potential is applied to the wiring DW_1, the current source CS connected to the wiring DW_1 outputs a constant current I Ｗｕｔ flows to the second terminal of the transistor F3, and when a low-level potential is applied to the wiring DW_1, the current source CS connected to the wiring DW_1 flows as follows: Ｗｕｔ Do not output.

[0179] The current flowing from one current source CS connected to wiring DW_1 corresponds to the value of the first bit, the current flowing from two current sources CS connected to wiring DW_2 corresponds to the value of the second bit, and the current flowing from K current sources CS connected to wiring DW_K corresponds to the value of the Kth bit.

[0180] 12A illustrates the input circuit WCS when K is an integer equal to or greater than 3, but when K is 1, the input circuit WCS in FIG. 12A may be configured without the current source CS connected to the wirings DW_2 to DW_K. When K is 2, the input circuit WCS in FIG. 12A may be configured without the current source CS connected to the wirings DW_3 to DW_K.

[0181] Next, a specific example of the configuration of the current source CS will be described.

[0182] The current source CS1 shown in FIG. 13A is a circuit that can be applied to the current source CS included in the input circuit WCS in FIG. 12A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0183] A first terminal of the transistor Tr1 is connected to the wiring VDDL, and a second terminal of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is connected to the terminal T1, and a gate of the transistor Tr2 is connected to the terminal T2. The terminal T2 is also connected to the wiring DW.

[0184] The wiring DW is any one of the wirings DW_1 to DW_K in FIG. 12A.

[0185] The wiring VDDL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential.

[0186] When the constant voltage applied by the wiring VDDL is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. In this case, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold region flows between the first terminal and the second terminal of the transistor Tr1. The amount of this current is, for example, 1.0×10 −８ A or less, and 1.0 × 10 −１２ A or less is more preferable, and 1.0 × 10 −１５It is more preferable that the current is equal to or less than 1 A. Furthermore, for example, it is more preferable that the current is in a range that increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the current range when operating in the subthreshold region. Note that the current is the above-mentioned I Ｗｕｔ , or I described below Ｘｕｔ is equivalent to

[0187] The transistor Tr2 functions as a switching element. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 functions as a drain, and the second terminal of the transistor Tr2 functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are connected, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on when a high-level potential is input to the gate of the transistor Tr2, and is turned off when a low-level potential is input to the gate of the transistor Tr2. Specifically, when the transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of the transistor Tr1 to the terminal T1. When the transistor Tr2 is off, the current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

[0188] Note that a circuit applicable to the current source CS included in the input circuit WCS of FIG. 12A is not limited to the current source CS1 of FIG. 13A. For example, while the current source CS1 is configured such that the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2, the back gate of transistor Tr2 may be connected to a separate wiring. An example of such a configuration is shown in FIG. 13B. In the current source CS2 shown in FIG. 13B, the back gate of transistor Tr2 is connected to wiring VTHL. By connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0189] Further, for example, the current source CS1 is configured such that the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected, but the voltage may be held by a capacitor between the back gate and the second terminal of the transistor Tr2. Such a configuration example is shown in FIG. 13C. The current source CS3 shown in FIG. 13C includes a transistor Tr3 and a capacitor C6 in addition to the transistor Tr1 and the transistor Tr2. The current source CS3 is different from the current source CS1 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are connected via the capacitor C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are connected. Also, the current source CS3 is configured such that the second terminal of the transistor Tr3 is connected to the wiring VTL and the gate of the transistor Tr3 is connected to the wiring VWL. The current source CS3 can turn on the connection between the wiring VTL and the back gate of the transistor Tr1 by applying a high-level potential to the wiring VWL to turn on the transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be held by the capacitor C6. That is, by determining the voltage that the wiring VTL applies to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C6.

[0190] Further, for example, as a circuit applicable to the current source CS included in the input circuit WCS of FIG. 12A, it may be the current source CS4 shown in FIG. 13D. The current source CS4 is configured such that in the current source CS3 of FIG. 13C, the back gate of the transistor Tr2 is connected to the wiring VTHL instead of the second terminal of the transistor Tr2. That is, similar to the current source CS2 in FIG. 13B, the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential applied by the wiring VTHL.

[0191] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0192] 12A includes the current source CS1 to the current source CS4 shown in Figures 13A to 13D, so that the input circuit WCS can output a current corresponding to the K-bit first data. The amount of the current can be, for example, a current flowing between the first terminal and the second terminal within a range in which the transistor 94 operates in the subthreshold region.

[0193] 12B may be used as the input circuit WCS in FIG. 12A. The input circuit WCS in FIG. 12B has a configuration in which the current source CS in FIG. 13A is connected to each of the wirings DW_1 to DW_K. When the channel width of the transistor Tr1_1 is w_1, the channel width of the transistor Tr1_2 is w_2, and the channel width of the transistor Tr1_K is w_K, the ratio of the channel widths is w_1:w_2:w_K=1:2:2. Ｋ−１ Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the input circuit WCS shown in Fig. 12B can output a current corresponding to the K-bit first data, similar to the input circuit WCS in Fig. 12A.

[0194] Note that the transistors Tr1 (including transistors Tr1_1 to Tr1_K), Tr2 (including transistors Tr2_1 to Tr2_K), and Tr3 can be, for example, transistors that can be used for the transistors included in the cell array CA. In particular, OS transistors are preferably used for the transistors Tr1 (including transistors Tr1_1 to Tr1_K), Tr2 (including transistors Tr2_1 to Tr2_K), and Tr3.

[0195] Next, a specific example of the input circuit XCS will be described.

[0196] 12C is a block diagram showing an example of an input circuit XCS. Note that in order to show electrical connection between the input circuit XCS and peripheral circuits, a wiring XCL is also shown in FIG. 12C. The wiring XCL is any one of the wirings XCL_1 to XCL_m included in the arithmetic circuit MAC1 in FIG. 11.

[0197] The input circuit XCS shown in FIG. 12C includes, as an example, a switch SWX. A first terminal of the switch SWX is connected to the wiring XCL and a plurality of current sources CS, and a second terminal of the switch SWX is connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL. The initialization potential may be a ground potential (GND), a low-level potential, a high-level potential, or the like. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0198] The switch SWX may be, for example, a switch applicable to the switch SWW.

[0199] The circuit configuration of the input circuit XCS in FIG. 12C can be substantially the same as that of the input circuit WCS in FIG. 12A. Specifically, the input circuit XCS has a function of outputting reference data as a current and a function of outputting L bits (2 Ｌand a function of outputting second data of a value (L is an integer of 1 or more) as a current. In this case, the input circuit XCS has a function of outputting second data of a value (L is an integer of 1 or more) as a current. Ｌ The input circuit XCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the Lth bit as a current. Ｌ−１ There are individual ones.

[0200] Incidentally, the reference data output as a current by the input circuit XCS can be, for example, information in which the value of the first bit is "1" and the values ​​of the second and subsequent bits are "0".

[0201] In FIG. 12C, the terminal T2 of one current source CS is connected to the wiring DX_1, and the terminals T2 of two current sources CS are each connected to the wiring DX_2. Ｌ−１ The terminals T2 of the current sources CS are each connected to the line DX_L.

[0202] The multiple current sources CS of the input circuit XCS are each supplied with the same constant current I Ｘｕｔ from the terminal T1. The wirings DX_1 to DX_L are connected to the current source CS and output I Ｘｕｔ That is, the input circuit XCS has a function of causing a current corresponding to L-bit information transmitted from the wirings DX_1 to DX_L to flow to the wiring XCL.

[0203] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the input circuit XCS, the constant current I output from each of the terminals T1 of the multiple current sources CS may be Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the input circuit XCS is Ｘｕｔ The following explanation will be given assuming that there is no error.

[0204] 13A to 13D can be applied as the current source CS of the input circuit XCS, similar to the current source CS of the input circuit WCS. In this case, the wiring DW shown in FIGS. 13A to 13D can be replaced with the wiring DX. This allows the input circuit XCS to pass a current in the subthreshold current range through the wiring XCL as reference data or L-bit second data.

[0205] 12C can be configured similarly to the input circuit WCS shown in Fig. 12B. In this case, the input circuit WCS shown in Fig. 12B can be replaced with the input circuit XCS, the wiring DW_1 with the wiring DX_1, the wiring DW_2 with the wiring DX_2, the wiring DW_K with the wiring DX_L, the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0206] <Example of Operation of Arithmetic Circuit> Next, an example of operation of the arithmetic circuit MAC1 will be described.

[0207] 14 shows a timing chart of an operation example of the arithmetic circuit MAC1. The timing chart of FIG. 14 shows fluctuations in the potentials of the wiring SWL1, the wiring SWL2, the wiring WSL_i (i is an integer of 1 to m-1), the wiring WSL_i+1, the wiring XCL_i, the wiring XCL_i+1, the node NN_i,j (j is an integer of 1 to n-1), the node NN_i+1,j, the node NNref_i, and the node NNref_i+1 between time T11 and time T23 and in the vicinity thereof. Furthermore, the timing chart of FIG. 14 shows fluctuations in the potentials of the wiring SWL1, the wiring SWL2, the wiring WSL_i (i is an integer of 1 to m-1), the wiring WSL_i+1, the wiring XCL_i, the wiring XCL_i+1, the node NN_i,j (j is an integer of 1 to n-1), the node NN_i+1,j, the node NNref_i, and the node NNref_i+1 between time T11 and time T23 and in the vicinity thereof. ９４ _i,j and a current I flowing between the first terminal and the second terminal of the transistors 83 and 84 included in the cell 81_i. ８４ _i and a current I flowing between the first terminal and the second terminal of the transistors 93 and 94 included in the cell 91_i+1,j. ９４ _i+1,j and a current I flowing between the first terminal and the second terminal of the transistors 83 and 84 included in the cell 81_i+1. ８４_i+1 and the respective variations are also shown.

[0208] The input circuit WCS of the arithmetic circuit MAC1 is the input circuit WCS of FIG. 12A, and the input circuit XCS of the arithmetic circuit MAC1 is the input circuit XCS of FIG. 12C.

[0209] In this operation example, the source potentials of transistors 84 and 94 are set to ground potential GND. Before time T11, the potentials of nodes NN_i,j, NN_i+1,j, NNref_i, and NNref_i+1 are set to ground potential GND as an initial setting. Specifically, for example, by setting the initialization potential of wiring VINIL1 in FIG. 12A to ground potential GND and turning on switch SWW, transistor F3, and the transistors 92 included in cells 91_i,j and 91_i+1,j, the potentials of nodes NN_i,j and NN_i+1,j can be set to ground potential GND. Furthermore, for example, by setting the initialization potential of the wiring VINIL2 in Figure 12C to the ground potential GND and turning on the switch SWX and the respective transistors 82 included in the cells 91_i,j and 91_i+1,j, the potentials of the nodes NNref_i,j and NNref_i+1,j can be set to the ground potential GND.

[0210] In this operation example, the gate potential of the transistors 83 and 93 is set to a constant potential Vb. By setting the gate potential of the transistors 83 and 93 to the constant potential Vb, the first terminals of the transistors 83 and 93 can be set to a voltage Vb-Vth, which is lower than the constant potential Vb by the threshold voltage. This makes it possible to suppress an increase in the second terminals (drain sides) of the transistors 84 and 94.

[0211] <<From Time T11 to Time T12>> From time T11 to time T12, a high-level potential (denoted as High in FIG. 14) is applied to the wiring SWL1, and a low-level potential (denoted as Low in FIG. 14) is applied to the wiring SWL2. As a result, the high-level potential is applied to the gates of the transistors F3_1 to F3_n, turning on the transistors F3_1 to F3_n, and the low-level potential is applied to the gates of the transistors F4_1 to F4_n, turning off the transistors F4_1 to F4_n.

[0212] Furthermore, between time T11 and time T12, a low-level potential is applied to the wiring WSL_i and the wiring WSL_i+1. As a result, a low-level potential is applied to the gate of the transistor 92 included in the cells 91_i,1 to 91_i,n in the i-th row of the cell array CA and the gate of the transistor 82 included in the cell 81_i, turning off the transistors 92 and 82. Furthermore, a low-level potential is applied to the gate of the transistor 92 included in the cells 91_i+1,1 to 91_i+1,n in the i+1-th row of the cell array CA and the gate of the transistor 82 included in the cell 81_i+1, turning off the transistors 92 and 82.

[0213] 12C corresponds to the wiring XCL_i and the wiring XCL_i+1, the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0214] 12A corresponds to the wirings WCL_1 to WCL_K, the first data is not input to the wirings DW_1 to DW_K. Also, between time T11 and time T12, when the wiring WCL in FIG. 12A corresponds to the wirings WCL_1 to WCL_K, the first data is not input to the wirings DW_1 to DW_K. Also, when the wiring XCL in FIG. 12C corresponds to the wirings XCL_1 to XCL_K, the second data is not input to the wirings DX_1 to DX_L. Here, in the input circuit WCS in FIG. 12A , a low-level potential is input to the wirings DW_1 to DW_K, and in the input circuit XCS in FIG. 12C , a low-level potential is input to the wirings DX_1 to DX_L.

[0215] Furthermore, between time T11 and time T12, no current flows through the wiring WCL_j, the wiring XCL_i, and the wiring XCL_i+1. ９４ _i, j, I ８４ _i, I ９４ _i+1, j, I ８４ _i+1 becomes 0.

[0216] <<From Time T12 to Time T13>> Between time T12 and time T13, a high-level potential is applied to the wiring WSL_i. As a result, a high-level potential is applied to the gate of the transistor 92 included in cells 91_i,1 to 91_i,n in the i-th row of the cell array CA and to the gate of the transistor 82 included in cell 81_i, turning on the transistors 92 and 82. Between time T12 and time T13, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i. As a result, the transistors 92 included in cells 91_1,1 to 91_m,n other than those in the i-th row of the cell array CA and the transistors 82 included in cells 81_1 to 81_m other than those in the i-th row of the cell array CA are turned off.

[0217] Furthermore, the ground potential GND continues to be applied to the wirings XCL_1 to XCL_m from before time T12.

[0218] <<From time T13 to time T14>> During the period from time T13 to time T14, current I ０＿ i,j flows from the input circuit WCS to the cell array CA via the transistor F3_j. Specifically, when the wiring WCL shown in FIG. 12A is the wiring WCL_j, signals corresponding to the first data are input to each of the wirings DW_1 to DW_K, whereby current I ０＿ i,j flows from the input circuit WCS to the second terminal of the transistor F3_j. That is, when the value of the K-bit signal input as the first data is w_i,j (let w_i,j be an integer of 0 or more and 2 Ｋ −1 or less), I ０ _i,j = w_i,j × I Ｗｕｔ is obtained.

[0219] When w_i,j is 0, I ０ _i,j = 0. Therefore, strictly speaking, no current flows from the input circuit WCS to the cell array CA via the transistor F3_j. However, in this specification and the like, there may be a description such as "a current of I ０ _i,j = 0 flows".

[0220] During the period from time T13 to time T14, the transistor 92 included in the cell 91_i,j in the i-th row of the cell array CA is in the on state, and the transistors 92 included in the cells 91_1,j to 91_m,j other than the i-th row of the cell array CA are in the off state. Therefore, current I ０ _i,j flows from the wiring WCL_j to the cell 91_i,j.

[0221] When the transistor 92 included in the cell 91_i,j is in the on state, current I ０ _i,j flows through the transistor ninety-four. As the current flowing between the first terminal and the second terminal of the transistor ninety-four, current I ０ _i,j is set. The voltage between the gate and the source of the transistor ninety-four becomes V ０ _i,j - GND so that current I ｇ _i,j flows.

[0222] In addition, during the period from time T13 to time T14, a current I ｒｅｆ０ Specifically, when the wiring XCL in FIG. 12C is the wiring XCL_i, a high-level potential is input to the wiring DX_1 and a low-level potential is input to each of the wirings DX_2 to DX_K, and a current I flows from the input circuit XCS to the wiring XCL_i. ｒｅｆ０ =I Ｘｕｔ is playing.

[0223] Between time T13 and time T14, the transistor 82 included in the cell 81_i is in an on state, and therefore, a current I flows from the wiring XCL_i to the cell 81_i. ｒｅｆ０ is playing. ８４ _i is I ｒｅｆ０ It becomes. ｒｅｆ０ =I Ｘｕｔ Therefore, I ９４ _i, j is I ０ _i,j=w_i,j×I ｒｅｆ０ ("j x I" in the specification) ｒｅｆ０ " is "j*I ｒｅｆ０ " is shown in the diagram).

[0224] As in the case of the cell 91_i,j, when the transistor 82 included in the cell 81_i is in an on state, a current I flows through the transistor 84. ｒｅｆ０ As a current flowing between the first terminal and the second terminal of the transistor 84, a current I ｒｅｆ０ is set. Current I ｒｅｆ０ The gate-source voltage of transistor 84 is V ｇｍ _i-GND.

[0225] <<From Time T14 to Time T15>> A low-level potential is applied to the wiring WSL_i from time T14 to time T15. As a result, a low-level potential is applied to the gates of the transistors 92 included in the cells 91_i,1 to 91_i,n in the i-th row of the cell array CA and the gates of the transistors 82 included in the cell 81_i, turning off the transistors 92 and 82.

[0226] When the transistor 92 included in the cell 91_i,j is turned off, the capacitor 95 is charged with V ｇ _i, j-V ｇｍ In addition, when the transistor 92 included in the cell 91_i is turned off, the capacitor 95 holds 0, which is the difference between the potential of the gate of the transistor 84 (node ​​NNref_i) and the potential of the wiring XCL_i.

[0227] 12C is the wiring XCL_i, the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0228] Therefore, the potentials of nodes NN_i,1 to NN_i,n change due to capacitive coupling by capacitors 95 included in each of cells 91_i,1 to 91_i,n in the i-th row, and the potential of node NNref_i changes due to capacitive coupling by capacitor 85 included in cell 81_i.

[0229] The amount of change in the potential of the nodes NN_i,1 to NN_i,n is the potential obtained by multiplying the amount of change in the potential of the wiring XCL_i by a capacitive coupling coefficient determined by the configuration of each of the cells 91_i,1 to 91_i,n included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor 95, the gate capacitance of the transistor 94, the parasitic capacitance, etc. In each of the cells 91_i,1 to 91_i,n, when the capacitive coupling coefficient of the capacitor 95 is p, the potential of the node NN_i,j of the cell 91_i,j is calculated by multiplying the potential at the time point between time T14 and time T15 by p(V ｇｍ _i-GND) decreases.

[0230] Similarly, when the potential of the wiring XCL_i changes, the potential of the node NNref_i also changes due to the capacitive coupling by the capacitor 85 included in the cell 81_i. When the capacitive coupling coefficient of the capacitor 85 is p, like the capacitor 95, the potential of the node NNref_i of the cell 81_i changes from the potential between time T14 and time T15 to p(V ｇｍ 14, p=1 is set as an example. Therefore, the potential of the node NNref_i becomes GND between time T15 and time T16.

[0231] As a result, the potential of the node NN_i,j of the cell 91_i,j drops, turning off the transistor 94. Similarly, the potential of the node NNref_i of the cell 81_i drops, turning off the transistor 84. Therefore, between time T15 and time T16, I ９４ _i, j, I ８４ Each of the _i's will be 0.

[0232] <<From Time T16 to Time T17>> Between time T16 and time T17, a high-level potential is applied to the wiring WSL_i+1. As a result, a high-level potential is applied to the gates of the transistors 92 included in cells 91_i+1,1 to 91_i+1,n in the i+1th row of the cell array CA and the gates of the transistors 82 included in cell 81_i+1, turning on the transistors 92 and 82. Between time T16 and time T17, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i+1. As a result, the transistors 92 included in cells 91_1,1 to 91_m,n other than those in the i+1th row of the cell array CA and the transistors 82 included in cells 81_1 to 81_m other than those in the i+1th row of the cell array CA are turned off.

[0233] Furthermore, the ground potential GND continues to be applied to the wirings XCL_1 to XCL_m from before time T16.

[0234] <<From Time T17 to Time T18>> During the period from time T17 to time T18, a current I is supplied as first data from the input circuit WCS to the cell array CA via the transistor F3_j. ０ Specifically, when the wiring WCL illustrated in FIG. 12A is the wiring WCL_j+1, signals corresponding to the first data are input to the wirings DW_1 to DW_K, and a current I flows from the input circuit WCS to the second terminal of the transistor F3_j. ０ That is, the value of the K-bit signal input as the first data is w_i+1,j (w_i+1,j is 0 to 2). Ｋ -1 or less.) ０ _i+1,j=w_i+1,j×I Ｗｕｔ This becomes:

[0235] When w_i+1,j is 0, I ０ Since _i+1, j=0, strictly speaking, no current flows from the input circuit WCS to the cell array CA via the transistor F3_j. However, in this specification, I ０ As in the case of i, j = 0, "I ０ _i+1, j=0 current flows."

[0236] At this time, the transistor 92 included in the cell 91_i+1,j in the i+1th row of the cell array CA is in an on state, and the transistors 92 included in the cells 91_1,j to 91_m,j other than the i+1th row of the cell array CA are in an off state. Therefore, a current I flows from the wiring WCL_j to the cell 91_i+1,j. ０ _i+1, j flows.

[0237] When the transistor 92 included in the cell 91_i+1,j is in an on state, a current I ０ A current I flows between the first terminal and the second terminal of the transistor 94. ０ _i+1, j is set. Current I ０ _i+1, j flows, the gate-source voltage of the transistor 94 is V ｇ _i+1, j-GND.

[0238] In addition, between time T17 and time T18, the input circuit XCS supplies a current I ｒｅｆ０ Specifically, similarly to the period from time T13 to time T14, when the wiring XCL in FIG. 12C is the wiring XCL_i+1, a high-level potential is input to the wiring DX_1 and a low-level potential is input to each of the wirings DX_2 to DX_K, and a current I flows from the input circuit XCS to the wiring XCL_i+1. ｒｅｆ０ =I Ｘｕｔ is playing.

[0239] Between time T17 and time T18, the transistor 82 included in the cell 81_i+1 is turned on, and therefore, a current I flows from the wiring XCL_i+1 to the cell 81_i+1. ｒｅｆ０ is playing. ８４ _i+1 is I ｒｅｆ０ It becomes. ｒｅｆ０ =I Ｘｕｔ Therefore, I ９４ _i+1, j is I ０ _i+1,j=w_i+1,j×I ｒｅｆ０ (In the figure, "x" is shown as "*").

[0240] Similarly to the cell 91_i+1,j, when the transistor 82 included in the cell 81_i+1 is in an on state, a current I flows through the transistor 84. ｒｅｆ０ As a current flowing between the first terminal and the second terminal of the transistor 84, a current I ｒｅｆ０ is set. Current I ｒｅｆ０ The gate-source voltage of transistor 84 is V ｇｍ _i+1-GND.

[0241] <<From Time T18 to Time T19>> A low-level potential is applied to the wiring WSL_i+1 from time T18 to time T19. As a result, a low-level potential is applied to the gates of the transistors 92 included in cells 91_i+1,1 to 91_i+1,n in the i+1th row of the cell array CA and the gate of the transistor 82 included in cell 81_i+1, turning off the transistors 92 and 82.

[0242] When the transistor 92 included in the cell 91_i+1,j is turned off, the capacitor 95 is charged with V ｇ _i+1,j-V ｇｍ _i+1 is held in the capacitor 85. Furthermore, because the transistor 92 included in the cell 81_i+1 is turned off, the capacitor 85 holds 0, which is the difference between the potential of the gate of the transistor 84 (node ​​NNref_i+1) and the potential of the wiring XCL_i+1. Note that the voltage held in the capacitor 85 is a non-zero voltage (here, for example, V ｄｓ In this case, the potential of the node NNref_i+1 is V ｄｓ This can be thought of as the sum of the potentials.

[0243] 12C is the wiring XCL_i+1, the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0244] Therefore, the potentials of nodes NN_i,1 to NN_i+1,n change due to capacitive coupling by capacitors 95 included in each of cells 91_i+1,1 to 91_i+1,n in the i+1th row, and the potential of node NNref_i+1 changes due to capacitive coupling by capacitor 85 included in cell 81_i+1.

[0245] The amount of change in the potential of the nodes NN_i+1,1 to NN_i+1,n is equal to the amount of change in the potential of the wiring XCL_i+1 multiplied by a capacitive coupling coefficient determined by the configuration of each of the cells 91_i+1,1 to 91_i+1,n included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor 95, the gate capacitance of the transistor 94, the parasitic capacitance, and the like. When the capacitive coupling coefficient of the capacitor 95 in each of the cells 91_i+1,1 to 91_i+1,n is set to p, which is the same as the capacitive coupling coefficient of the capacitor 95 in each of the cells 91_i,1 to 91_i,n, the potential of the node NN_i+1,j of the cell 91_i+1,j is calculated by multiplying the amount of change in the potential of the wiring XCL_i+1 by p(V ｇｍ _i+1-GND) decreases.

[0246] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to the capacitive coupling by the capacitor 85 included in the cell 81_i+1. When the capacitive coupling coefficient of the capacitor 85 is p, the same as that of the capacitor 95, the potential of the node NNref_i+1 of the cell 81_i+1 changes from the potential between time T18 and time T19 to p(V ｇｍ 14, p=1 is set as an example. Therefore, the potential of the node NNref_i+1 becomes GND between time T20 and time T21.

[0247] As a result, the potential of the node NN_i+1,j of the cell 91_i+1,j drops, turning off the transistor 94. Similarly, the potential of the node NNref_i+1 of the cell 81_i+1 drops, turning off the transistor 84. Therefore, between time T19 and time T20, I ９４ _i+1, j, I ８４ Each of _i+1 is 0.

[0248] <<From Time T20 to Time T21>> A low-level potential is applied to the wiring SWL1 from time T20 to time T21. As a result, the low-level potential is applied to the gates of the transistors F3_1 to F3_n, and the transistors F3_1 to F3_n are turned off.

[0249] <<From Time T21 to Time T22>> A high-level potential is applied to the wiring SWL2 from time T21 to time T22. As a result, the high-level potential is applied to the gates of the transistors F4_1 to F4_n, and the transistors F4_1 to F4_n are turned on.

[0250] <<From Time T22 to Time T23>> During the period from time T22 to time T23, a current I is supplied as second data from the input circuit XCS to the wiring XCL_i. ｒｅｆ０ x_i times x_iI ｒｅｆ０ Specifically, for example, when the wiring XCL in FIG. 12C is a wiring XCL_i, a high-level potential or a low-level potential is input to each of the wirings DX_1 to DX_K depending on the value of x_i, and a current of x_iI flows from the input circuit XCS to the wiring XCL_i. ｒｅｆ０ = x_iI Ｘｕｔ In this operation example, x_i corresponds to the value of the second data. At this time, the potential of the wiring XCL_i is changed from 0 to V ｇｍ _i+ΔV_i.

[0251] When the potential of the wiring XCL_i changes, the potentials of the nodes NN_i,1 to NN_i,n also change due to capacitive coupling by the capacitors 95 included in the cells 91_i,1 to 91_i,n in the i-th row of the cell array CA. Therefore, the potential of the node NN_i,j of the cell 91_i,j is V ｇ _i,j+pΔV_i.

[0252] Similarly, when the potential of the wiring XCL_i changes, the potential of the node NNref_i also changes due to capacitive coupling by the capacitor 85 included in the cell 81_i. Therefore, the potential of the node NNref_i of the cell 81_i is V ｇｍ _i+pΔV_i.

[0253] Therefore, the current flowing between the first terminal and the second terminal of the transistor 94 included in the cell 91_i,j is proportional to the product of the first data w_i,j and the second data x_i.

[0254] In addition, during the period from time T22 to time T23, a current I is supplied as second data from the input circuit XCS to the wiring XCL_i+1. ｒｅｆ０ x_i+1I, which is x_i+1 times ｒｅｆ０ Specifically, for example, when the wiring XCL in FIG. 12C is a wiring XCL_i+1, a high-level potential or a low-level potential is input to each of the wirings DX_1 to DX_K depending on the value of x_i+1, and a current of x_i+1I flows from the input circuit XCS to the wiring XCL_i+1. ｒｅｆ０ = x_i + 1I Ｘｕｔ In this operation example, x_i+1 corresponds to the value of the second data. At this time, the potential of the wiring XCL_i+1 changes from 0 to V ｇｍ _i+1+ΔV_i+1.

[0255] When the potential of the wiring XCL_i+1 changes, the potentials of the nodes NN_i+1,1 to NN_i+1,n also change due to capacitive coupling by the capacitors 95 included in each of the cells 91_i+1,1 to 91_i+1,n in the i+1th row of the cell array CA. Therefore, the potential of the node NN_i+1,j of the cell 91_i+1,j is V ｇ _i+1,j+pΔV_i+1.

[0256] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to capacitive coupling by the capacitor 85 included in the cell 81_i+1. Therefore, the potential of the node NNref_i+1 of the cell 81_i+1 is V ｇｍ_i+1+pΔV_i+1.

[0257] Therefore, the current flowing between the first terminal and the second terminal of transistor 94 included in cell 91_i+1,j is proportional to the product of the first data w_i+1,j and the second data x_i+1.

[0258] Therefore, the current output from the wiring OL_j can be a current proportional to the sum of the products of the weighting coefficients w_i,j and w_i+1,j, which are the first data, and the values ​​x_i and x_i+1,j of the input signal, which are the second data. The current can be converted into an analog signal D having an analog voltage value by a current-voltage conversion circuit or the like. ＭＡＣＡ and can be output to the analog-to-digital conversion circuit 79.

[0259] Therefore, even in the case of an arithmetic circuit MAC1 having three or more rows and two or more columns of cell arrays CA, it is possible to perform a product-sum operation as described above. In this case, the arithmetic circuit MAC1 selects one of the multiple columns as a current I ｒｅｆ０ , and xI ｒｅｆ０ By using a cell that holds a signal, it is possible to simultaneously perform product-sum calculations for the remaining number of columns among the multiple columns. In other words, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that achieves high-speed product-sum calculations. Therefore, it is possible to provide a product-sum calculation unit with excellent calculation processing capacity per unit power.

[0260] Although this embodiment describes the case where the transistor included in the arithmetic circuit MAC1 is an OS transistor or a Si transistor, one embodiment of the present invention is not limited thereto. The transistor included in the arithmetic circuit MAC1 may be, for example, a transistor including Ge or the like in a channel formation region, a transistor including a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region.

[0261] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0262] In this embodiment, a cross-sectional structure example of an element layer including stacked OS transistors that can be applied to a semiconductor device or the like will be described. In this embodiment, an example of a cross-sectional schematic diagram that can be applied to a circuit configuration such as a NOSRAM or a DOSRAM will be described.

[0263] <Configuration Example 1 of NOSRAM> Figure 15 shows a cross-sectional configuration example when a three-transistor NOSRAM circuit configuration is used. Figure 15 illustrates a case where element layers UF[1] to UF[3] are stacked on element layer LF. Figure 16A shows an example of the cross-sectional structure of element layer UF[k]. Figure 16B shows an equivalent circuit diagram of Figure 16A.

[0264] The element layer LF is the element layer 10 described in the above-described embodiment 1. An element such as a Si transistor is provided in the element layer LF. The element layer UF is the element layer 40 described in the above-described embodiment 1. An element such as an OS transistor is provided in the element layer UF.

[0265] 15 illustrates a transistor 550 included in the element layer LF. The transistor 550 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314 a and 314 b functioning as source and drain regions.

[0266] The transistor 550 may be either a p-channel type or an n-channel type.

[0267] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0268] Note that the transistor 550 illustrated in FIG. 15 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0269] A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the element layer LF and the element layer UF, or between the kth element layer UF and the k+1th element layer UF. In the present embodiment and the like, the kth element layer UF may be referred to as element layer UF[k], and the k+1th element layer UF may be referred to as element layer UF[k+1]. Here, k is an integer of 1 or more and N or less. In the present embodiment and the like, when "k+α (α is an integer of 1 or more)" or "k-α" is used, the solutions of "k+α" and "k-α" are integers of 1 or more and N or less.

[0270] In addition, multiple wiring layers can be provided depending on the design. In addition, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0271] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 550. A conductive layer 328 or the like is embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 or the like is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0272] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in FIG. 15 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order on the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0273] An insulating layer 514 included in the element layer UF is provided over the insulating layer 354. A conductive layer 358 is embedded in the insulating layer 514 and the insulating layer 354. The conductive layer 358 functions as a contact plug or a wiring. For example, a wiring functioning as a bit line and the transistor 550 are connected via the conductive layer 358, the conductive layer 356, the conductive layer 330, or the like.

[0274] The memory cell 41E shown in FIG. 15 has a transistor M2, a transistor M3, and a transistor M1 on an insulating layer 514 as shown in FIG. 16A.

[0275] 15 and 16A share a single island-shaped semiconductor layer 530. In other words, a portion of the island-shaped semiconductor layer 530 functions as a channel formation region for the transistor M2, and another portion functions as a channel formation region for the transistor M3. The source of the transistor M2 and the drain of the transistor M3, or the drain of the transistor M2 and the source of the transistor M3, are shared. Therefore, the area occupied by the transistors M2 and M3 is smaller than when the transistors M2 and M3 are provided independently.

[0276] 15 and 16A, the memory cell 41E may be configured without the transistor M1. The memory cell 41E without the transistor M1 may be a two-transistor NOSRAM, and corresponds to the memory cell 41D shown in FIG. 7D.

[0277] 17A to 17C, an OS transistor will be described. 17A and 17B are schematic cross-sectional views of a transistor 500 that can be used for the transistors M1 to M3.

[0278] 17A and 17B , an insulating layer 516 is disposed over an insulating layer 514. The transistor 500 includes a conductive layer 503 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed over the insulating layer 516 and the conductive layer 503, an insulating layer 524 disposed over the insulating layer 522, a semiconductor layer 530 disposed over the insulating layer 524, conductive layers 542a and 542b disposed apart from each other on the semiconductor layer 530, an insulating layer 580 disposed over the conductive layers 542a and 542b and having an opening formed therebetween to overlap the conductive layers 542a and 542b, an insulating layer 545 disposed on a bottom surface and a side surface of the opening, and a conductive layer 560 disposed on the insulating layer 545. The conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 545 and a conductive layer 560b provided on the conductive layer 560a so as to be embedded in the opening.

[0279] 17A and 17B , an insulating layer 544 is disposed between the semiconductor layer 530, the conductive layers 542a and 542b, and the insulating layer 580. An insulating layer 574 is disposed on the insulating layer 580, the conductive layer 560, and the insulating layer 545, and an insulating layer 581 is disposed on the insulating layer 574.

[0280] In the transistor 500, the conductive layer 560 functions as a gate electrode, the insulating layer 545 functions as a gate insulating film, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. The conductive layer 560 may function as a first gate electrode. The conductive layer 503 may function as a second gate electrode. The insulating layers 522 and 524 function as second gate insulating films.

[0281] 17A and 17B , the insulating layer 522 and the insulating layer 524 are illustrated as the second gate insulating film having a two-layer stacked structure, but the second gate insulating film may have a single-layer structure or a stacked structure of three or more layers. In this case, the second gate insulating film is not limited to a stacked structure made of the same material and may have a stacked structure made of different materials.

[0282] In the transistor 500, an oxide semiconductor layer is preferably used as the semiconductor layer 530 including a channel formation region. An oxide semiconductor layer that can be used as the semiconductor layer 530 will be described in Embodiment 4 below.

[0283] The channel formation region of a transistor using an oxide semiconductor for a semiconductor layer has a higher oxygen vacancy (V Ｏ It is preferable that the concentration of impurities such as hydrogen, nitrogen, and metal elements is low. In addition, hydrogen in the vicinity of the oxygen vacancy is replaced by a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that become carriers. Therefore, in the channel formation region, V Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0284] In addition, the source and drain regions of a transistor using an oxide semiconductor for a semiconductor layer have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of a transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, and metal elements.

[0285] The band gap of the oxide semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using an oxide semiconductor with a wide band gap for a semiconductor layer, the off-state current of a transistor can be reduced. By using a transistor with a low off-state current for a memory cell, stored data can be retained for a long period of time. In other words, a refresh operation is not required or is performed very infrequently, and therefore the power consumption of the semiconductor device can be sufficiently reduced.

[0286] 17A and 17B, the semiconductor layer 530 is shown as a single layer, but the present invention is not limited to this. For example, the semiconductor layer 530 may have a stacked structure of two or more layers.

[0287] 17A , when an oxide semiconductor is used for the semiconductor layer 530, a region 543a may be formed as a low-resistance region at the interface with the conductive layer 542a of the semiconductor layer 530 or in its vicinity. Similarly, a region 543b may be formed as a low-resistance region at the interface with the conductive layer 542b of the semiconductor layer 530 or in its vicinity. In this case, the region 543a and the region 543b function as a source region and a drain region, respectively. Furthermore, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0288] Note that the semiconductor material that can be used for the semiconductor layer 530 is not limited to an oxide semiconductor. A semiconductor material other than an oxide semiconductor may be used for the semiconductor layer 530. Other semiconductor materials that can be used for the semiconductor layer 530 will be described in the section "Other Semiconductor Materials" below.

[0289] 17A, the conductive layers 542a and 542b each have a single-layer structure, but the present invention is not limited to this. For example, the conductive layers 542a and 542b each may have a stacked structure of two or more layers.

[0290] 17A and 17B, the conductive layer 560 and the conductive layer 503 each have a two-layer stacked structure, but the present invention is not limited to this. For example, the conductive layer 560 and the conductive layer 503 each may have a single-layer structure or a stacked structure of three or more layers.

[0291] The insulating layer 580 is provided over the conductive layers 542a and 542b with the insulating layer 544 interposed therebetween. The opening of the insulating layer 580 is formed to overlap the region between the conductive layers 542a and 542b. As a result, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b.

[0292] When an oxide semiconductor is used for the semiconductor layer 530, the insulating layer 580 is preferably an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). By performing heat treatment on the insulating layer 580 containing excess oxygen, oxygen is supplied from the insulating layer 580 to a channel formation region of the semiconductor layer 530, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor 500 and improve its reliability.

[0293] 17A and 17B, the insulating layer 545 is shown as a single layer, but the present invention is not limited to this. For example, the insulating layer 545 may have a stacked structure of two or more layers.

[0294] The insulating layer 544 is provided to cover the conductive layers 542a and 542b. The insulating layer 544 preferably has a barrier property against oxygen. With such a structure, the conductive layers 542a and 542b can be prevented from being oxidized.

[0295] An insulating layer 571a is disposed over the conductive layer 542a, and an insulating layer 571b is disposed over the conductive layer 542b. By providing the insulating layers 571a and 571b, it is possible to prevent the end portions of the conductive layers 542a and 542b from being excessively etched when the semiconductor film that becomes the semiconductor layer 530 and the conductive films that become the conductive layers 542a and 542b are collectively processed into island shapes. Therefore, it is possible to process minute transistors with high precision.

[0296] The insulating layer 574 preferably has a function of suppressing diffusion of impurities such as hydrogen. The insulating layer 574 also preferably has a function of capturing or fixing impurities such as hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 530 can be suppressed. Furthermore, the hydrogen concentration in the semiconductor layer 530 can be reduced.

[0297] A conductive layer 540a is disposed in openings formed in the insulating layers 581, 574, 580, 544, and 571a, and a conductive layer 540b is disposed in openings formed in the insulating layers 581, 574, 580, 544, and 571b. The conductive layers 540a and 540b are disposed opposite each other with the conductive layer 560 interposed therebetween. The conductive layers 540a and 540b function as vias, contact plugs, or wiring.

[0298] 17A, the conductive layer 540a and the conductive layer 540b each have a two-layer structure, but the present invention is not limited to this. For example, the conductive layer 540a and the conductive layer 540b each may have a single-layer structure or a stacked structure of three or more layers.

[0299] The transistor 500 shown in FIGS. 17A and 17B is just an example, and the present invention is not limited to this configuration. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0300] 17A and 17B . For example, a transistor 500 having a structure shown in Fig. 17C may be used. The transistor 500 shown in Fig. 17C differs from the transistor 500 shown in Fig. 17A and 17B in that the conductive layers 542a and 542b each have a stacked structure and that an insulating layer 520 and an insulating layer 555 are provided.

[0301] 17C , the conductive layer 542a has a stacked structure of a conductive layer 542a1 and a conductive layer 542a2 over the conductive layer 542a1, and the conductive layer 542b has a stacked structure of a conductive layer 542b1 and a conductive layer 542b2 over the conductive layer 542b1. The conductive layers 542a1 and 542b1 in contact with the semiconductor layer 530 are preferably made of a conductor that is resistant to oxidation, such as a metal nitride. This can prevent the conductive layers 542a and 542b from being excessively oxidized by oxygen contained in the semiconductor layer 530. Furthermore, the conductive layers 542a2 and 542b2 are preferably made of a conductor having higher conductivity than the conductive layers 542a1 and 542b1. This allows the conductive layers 542a and 542b to function as highly conductive wirings or electrodes. In this manner, a semiconductor device in which the conductive layers 542a and 542b functioning as wirings or electrodes are provided in contact with the top surface of the semiconductor layer 530 can be provided.

[0302] As shown in FIG. 17C , in a cross-sectional view of the transistor 500 in the channel length direction, the distance between the conductive layer 542a1 and the conductive layer 542b1 is smaller than the distance between the conductive layer 542a2 and the conductive layer 542b2. This structure shortens the source-drain distance and accordingly shortens the channel length. Furthermore, by using a stacked structure of the conductive layer 542a2 and the conductive layer 542a2 and a stacked structure of the conductive layer 542b1 and the conductive layer 542b2, variations in the manufacturing process of the transistor 500 can be reduced. More specifically, by processing the conductive layer 542a1 and the conductive layer 542b1 after processing the conductive layer 542a2 and the conductive layer 542b2, variations in the manufacturing process of the transistor 500 can be reduced. Therefore, the frequency characteristics of the transistor 500 can be improved, and a semiconductor device with a high yield can be realized. In this way, miniaturization of the semiconductor device can provide a semiconductor device with improved operating speed.

[0303] The insulating layer 555 is provided in contact with the side surfaces of the conductive layer 542a2 and the conductive layer 542b2. The insulating layer 555 preferably has a function of suppressing oxygen diffusion. With such a structure, oxidation of the side surfaces of the conductive layer 542a2 and the conductive layer 542b2 can be suppressed.

[0304] The insulating layer 520 preferably has a barrier property against hydrogen, which can suppress diffusion of hydrogen into the semiconductor layer 530 and reduce the hydrogen concentration in the semiconductor layer 530.

[0305] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0306] Note that the transistor that can be used in the present invention is not limited to the transistor 500 shown in Figures 17A and 17C. Figures 18A to 18D describe structures different from those of the transistors shown in Figures 17A to 17C. Figure 18A is a plan view of a transistor 500A that can be used for the transistors M1 to M3. Figures 18B to 18D are cross-sectional views of the transistor 500A.

[0307] 18B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 18A , which is also a cross-sectional view of the transistor 500A in the channel width direction. FIG. 18C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 18A , which is also a cross-sectional view of the transistor 500A in the channel width direction. FIG. 18D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 18A , which is also a cross-sectional view of the transistor 500A in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 18A , some elements are omitted and some elements are shown transparently for clarity.

[0308] The transistor 500A includes an insulating layer 516 over a substrate (not shown), an insulator 521 over the insulating layer 516, an insulating layer 522 over the insulator 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 545 over the semiconductor layer 530, and a conductive layer 560 (conductive layers 560a and 560b) over the insulating layer 545. Note that hereinafter, the conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0309] An insulator 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulator 575. The insulating layer 545 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulator 575. The openings reach the semiconductor layer 530, and the insulating layer 545 is in contact with the semiconductor layer 530 within the openings. An insulating layer 574 is provided over the insulating layer 580 and the conductive layer 560. An insulator 583 is provided over the insulating layer 574. An insulator 515 is provided under the insulating layer 516.

[0310] An insulator 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulator 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulator 541b is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulator 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulators 541a and 541b may be collectively referred to as the insulator 541.

[0311] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500A. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500A. The insulating layer 545 has a region that functions as a first gate insulator of the transistor 500A.

[0312] The conductive layer 542a has a region functioning as one of the source electrode and the drain electrode of the transistor 500A. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and the drain electrode of the transistor 500A. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0313] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. The semiconductor layer 530 has a shape with a high aspect ratio (a shape in which the length in the height direction (H) is equal to or greater than the length of the base side (W) (H≧W)) in a cross-sectional view in the channel width direction. The semiconductor layer 530 having a shape with a high aspect ratio is sometimes referred to as having a fin-like shape.

[0314] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the width L of the semiconductor layer 530 to the height H of the semiconductor layer 530. The aspect ratio of the semiconductor layer 530 is preferably as large as possible without causing the semiconductor layer 530 to collapse during the manufacturing process of the transistor 500A. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 may be greater than 1 time and less than 400 times, preferably 2 times to 100 times, more preferably 5 times to 40 times, and even more preferably 10 times to 20 times the width L of the semiconductor layer 530. Alternatively, for example, the height H may be 2 times to 10 times the width L. For example, the width L may be 5 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 10 nm to 30 nm. For example, the height H may be 50 nm or more and 2000 nm or less, and preferably 100 nm or more and 1000 nm or less.

[0315] In addition, in a cross-sectional view in the channel width direction, the angle formed between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably a right angle or a substantially right angle. For example, the angle formed between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably 80° to 100°, more preferably 85° to 95°.

[0316] An insulating layer 545, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 having such a high aspect ratio. In the transistor 500A, the insulating layer 545 and a part of the conductive layer 560 are provided so as to sandwich the semiconductor layer 530 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 545 sandwiched between the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 each function as a channel formation region. Therefore, compared to when the semiconductor layer 530 is formed in a planar shape, the channel width of the transistor 500A is larger by the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0317] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 500A can be improved. This makes it possible to provide a transistor with high operating speed. Furthermore, the operating speed of a memory device using the transistor can be increased. Furthermore, in the above structure, by providing the semiconductor layer 530, the channel width can be increased without increasing the area occupied by the transistor 500A. This enables miniaturization or high integration of the transistor. Furthermore, by using the above structure, the area where the side surfaces of the conductive layer 560 and the semiconductor layer 530 face each other is increased, so that the threshold voltage can be controlled to make the transistor 500A normally off.

[0318] The upper portion of the semiconductor layer 530 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulating layer 545 and the conductive layer 542 near the upper portion of the semiconductor layer 530.

[0319] Because the semiconductor layer 530 has a high aspect ratio, it is preferably formed in the shape of a sidewall on the side surface of a pillar made of an insulator. Therefore, it is preferable to form the semiconductor layer 530 using the ALD method, which has good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to form at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0320] 18A , by forming the semiconductor layers 530 in a sidewall shape in contact with the side surfaces of the pillars, the plurality of semiconductor layers 530 can be formed simultaneously. By forming the plurality of semiconductor layers 530 in this manner, the distance between the semiconductor layers 530 can be set in accordance with the size and shape of the pillars. Therefore, the distance between the semiconductor layers 530 can be reduced, the area occupied by the transistor 500A can be reduced, and high integration of the transistors can be achieved.

[0321] Since the semiconductor layer 530 is formed in a sidewall shape in contact with the pillar, as shown in FIG. 18A , the top surface shape of the semiconductor layer 530 is a circumferential shape with both ends coinciding (which can also be called a frame shape, annular shape, doughnut shape, or closed curve shape). The semiconductor layer 530 can also be said to have a shape with an opening in the center. Note that in FIG. 18A , the top surface shape of the semiconductor layer 530 is line-symmetrical about A1-A2, but the present invention is not limited to this. For example, the top surface shape of the semiconductor layer 530 may be asymmetrical.

[0322] The structure shown in FIG. 18A has two pillars arranged in the A1-A2 direction, and a circumferential semiconductor layer 530 formed in contact with the side surface of each pillar. As shown in FIG. 18A , the semiconductor layer 530 preferably overlaps with the conductive layer 560 at two or more locations in a plan view. That is, the semiconductor layer 530 has two or more overlapping regions with the conductive layer 560. With this structure, as shown in FIG. 18B , multiple fin-shaped semiconductor layers 530 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped semiconductor layers 530 functions as a channel formation region. That is, the transistor 500A functions as a multi-channel transistor. Therefore, the channel width of the transistor 500A can be further increased.

[0323] 18A to 18D, the structure of the transistor 500A applicable to the transistors M1 to M3 may be changed to a structure in which a conductive layer 503 is provided under an insulator 521, as illustrated in a transistor 500B shown in FIGS. 19A to 19D. The conductive layer 503 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 500B. The insulating layer 522 and the insulator 521 each have a region that functions as a second gate insulator of the transistor 500B. Here, FIGS. 19A to 19D correspond to FIGS. 18A to 18D, and therefore the above description can be referred to for detailed structures.

[0324] In the transistor 500B, the conductive layer 503 is arranged to overlap with the semiconductor layer 530 and the conductive layer 560. Here, the conductive layer 503 is preferably provided so as to be embedded in an opening formed in the insulating layer 516. Furthermore, the conductive layer 503 is preferably provided to extend in the channel width direction as shown in FIGS. 19A and 19B. With this structure, when a plurality of transistors are provided, the conductive layer 503 functions as a wiring.

[0325] 19B and 19D, the conductive layer 503 preferably includes a conductive layer 503a and a conductive layer 503b. The conductive layer 503a is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 503b is provided so as to fill a recess in the conductive layer 503a formed along the opening. Here, the height of the upper surface of the conductive layer 503 coincides with or approximately coincides with the height of the upper surface of the insulating layer 516.

[0326] Here, the conductive layer 503a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0327] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 503a, impurities such as hydrogen contained in the conductive layer 503b can be prevented from diffusing into the semiconductor layer 530 through the insulating layer 516 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 503a, oxidation of the conductive layer 503b and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 503a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 503a preferably contains titanium nitride.

[0328] The conductive layer 503b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0329] The conductive layer 503 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500B can be controlled by changing the potential applied to the conductive layer 503 independently of the potential applied to the conductive layer 560. In particular, applying a negative potential to the conductive layer 503 can increase the Vth of the transistor 500B and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 503 can reduce the drain current when the potential applied to the conductive layer 560 is 0 V compared to when a negative potential is not applied.

[0330] The electrical resistivity of the conductive layer 503 is designed in consideration of the potential applied to the conductive layer 503, and the film thickness of the conductive layer 503 is set to match the electrical resistivity. The film thickness of the insulating layer 516 is approximately the same as that of the conductive layer 503. Here, it is preferable to make the film thicknesses of the conductive layer 503 and the insulating layer 516 thin within the range permitted by the design of the conductive layer 503. By making the film thickness of the insulating layer 516 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 516 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 530 can be suppressed.

[0331] Although the above describes a stacked structure of the conductive layer 503a and the conductive layer 503b, the present invention is not limited to this, and the conductive layer 503 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 503 has a three-layer stacked structure, a conductor made of the same material as the conductive layer 503a can be provided on the conductive layer 503b in the stacked structure of the conductive layer 503a and the conductive layer 503b. In this case, the conductor may be formed so that the top surface of the conductive layer 503b is lower than the top of the conductive layer 503a and fills the recess formed by the conductive layer 503a and the conductive layer 503b.

[0332] <Configuration Example of DOSRAM> Fig. 20 shows a cross-sectional configuration example when a DOSRAM circuit configuration is used. Fig. 20 illustrates a case where element layers UF[1] to UF[3] are stacked on an element layer LF. Fig. 21A shows an example of the cross-sectional structure of element layer UF[k]. Fig. 21B shows an equivalent circuit diagram of Fig. 21A.

[0333] 20 , each of the multiple element layers UF has multiple memory cells 41. In each of the element layers UF[1] to UF[3] illustrated in FIG. 20 , an example is shown in which two memory cells 41 are connected to one bit line BL. The memory cell 41 illustrated in FIG. 20 has a transistor M1 and a capacitor C1. In the memory cell 41 illustrated in FIG. 20 , the capacitor C1 is provided below the transistor M1. An OS transistor can be used as the transistor M1.

[0334] Furthermore, conductive layers 363a, 363b, and 363c are embedded in the interlayer film between the element layer LF and the element layer UF[1]. Furthermore, in each of the multiple element layers UF, a conductive layer 365 is embedded in the insulating layer 180, which will be described later. Furthermore, in each of the multiple element layers UF, a conductive layer 366 is embedded in the insulating layer 180 and the insulating layer 280, which will be described later. Furthermore, in each of the multiple element layers UF, a conductive layer 367 is embedded in the semiconductor layer 270, the insulating layer 250, and the insulating layer 285, which will be described later. The conductive layers 363a, 363b, 363c, 365, 366, and 367 function as vias, contact plugs, or wiring.

[0335] Next, a configuration example of the memory cells 41 included in the plurality of element layers UF shown in FIG. 20 will be described.

[0336] Fig. 22A is a plan view showing an example of the configuration of a memory cell 41 and its periphery included in each of multiple element layers UF. Fig. 22B is a plan view in which some of the components shown in Fig. 22A are omitted. Fig. 22C is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 22A. Note that in Fig. 22A, some of the components of the transistor VM1, such as the insulating layer 250, are omitted. Furthermore, some of the components, such as the insulating layer, are omitted in the plan views of subsequent transistors as well.

[0337] 22A to 22C, the transistor VM1 corresponds to the transistor M1 in FIG. 20, and the capacitor VC1 corresponds to the capacitor C1 in FIG.

[0338] In FIG. 22C, insulating layer 160 is disposed on a substrate (not shown), insulating layer 180 is disposed on insulating layer 160, insulating layer 280 is disposed on insulating layer 180, and insulating layer 285 is disposed on insulating layer 280.

[0339] A conductive layer 110 is provided on the insulating layer 160. As an example, the conductive layer 110 can be a wiring PL extending in the Y direction.

[0340] An opening 601 is provided in a region of the insulating layer 180 that overlaps with the conductive layer 110. The conductive layer 115 is provided so as to be in contact with the bottom surface and sidewall of the opening 601. That is, the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 and a region in contact with the side surface of the insulating layer 180 in the opening 601. Note that in FIG. 22C , the conductive layer 115 has a region in contact with the top surface of the insulating layer 180.

[0341] An insulating layer 130 is provided on the insulating layer 180 and the conductive layer 115. A conductive layer 220 is provided on the insulating layer 130. The conductive layer 220 is provided so as to fill the opening 601.

[0342] The capacitor VC1 includes a conductive layer 115, a conductive layer 220, and an insulating layer 130.

[0343] In the capacitor VC1, the conductive layer 115 functions as one of a pair of electrodes, the conductive layer 220 functions as the other of the pair of electrodes, and the insulating layer 130 functions as a dielectric sandwiched between the pair of electrodes.

[0344] The transistor VM1 is provided above the capacitor VC1. The transistor VM1 includes a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0345] In the transistor VM1, the conductive layer 260 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating film. The conductive layer 220 and the conductive layer 240 function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 220 also functions as the other of the pair of electrodes of the capacitor VC1.

[0346] The entire region of the semiconductor layer 270 that faces the gate electrode via the gate insulating film between the source electrode and the drain electrode functions as a channel formation region. The region of the semiconductor layer 270 that contacts the source electrode functions as a source region, and the region that contacts the drain electrode functions as a drain region.

[0347] The insulating layer 280 can function as an interlayer insulating layer. The interlayer insulating layer here can be an interlayer film for separating the source electrode and the drain electrode of the transistor VM1.

[0348] The conductive layer 240 is provided on the insulating layer 280. The insulating layer 280 has an opening 602 that reaches the conductive layer 220. The conductive layer 240 has an opening 603 that reaches the opening 602. That is, the opening 603 has a region that overlaps with the opening 602.

[0349] Fig. 22A shows conductive layer 220, conductive layer 240, conductive layer 260, opening 602, and opening 603. Here, Fig. 22B shows a configuration example in which conductive layer 260 is omitted from the components shown in Fig. 22A. That is, Fig. 22B shows conductive layer 220, conductive layer 240, opening 602, and opening 603.

[0350] 22A and 22B show an example in which the shapes of the openings 602 and 603 are each circular in a plan view. By making the planar shapes of the openings 602 and 603 (the shape and outline of the object in a planar view) circular, the processing accuracy when forming the openings 602 and 603 can be improved, and the openings 602 and 603 can be formed in microscopic sizes. This allows for miniaturization or high integration of memory cells. Note that in this specification, a circle is not limited to a perfect circle. For example, the planar shapes of the openings 602 and 603 may be elliptical or may include curves. Alternatively, they may be polygonal, or may be polygonal with rounded corners.

[0351] The description of the shapes of the openings 602 and 603 can also be applied to the opening 601 .

[0352] The conductive layer 240 is preferably not provided inside the opening 602. In other words, the conductive layer 240 is preferably not in contact with the side surface of the insulating layer 280 on the opening 602 side. With this structure, the opening 603 and the opening 602 can be formed at the same time, thereby simplifying the process.

[0353] 22C shows an example in which the bottom edge of conductive layer 240 in opening 603 coincides with or roughly coincides with the top edge of insulating layer 280 in opening 602. In this specification and the like, the bottom surface of conductive layer 240 refers to the surface on the insulating layer 280 side. The top surface of insulating layer 280 refers to the surface on the conductive layer 240 side.

[0354] Incidentally, "the edges are aligned or approximately aligned" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, it is also said that the edges are approximately aligned or the planar shapes are approximately aligned.

[0355] Hereinafter, an opening including openings 602 and 603 may be referred to as opening 290. That is, opening 290 reaching conductive layer 220 is provided in insulating layer 280 and conductive layer 240. Opening 602 is a part of opening 290, and opening 603 is another part of opening 290.

[0356] At least a portion of the semiconductor layer 270 is disposed in the opening 290. In the opening 290, the semiconductor layer 270 has a region in contact with a side surface of the conductive layer 240, a region in contact with a side surface of the insulating layer 280, and a region in contact with the top surface of the conductive layer 220. The semiconductor layer 270 has a region in contact with the top surface of the conductive layer 240.

[0357] At least a portion of the insulating layer 250 is disposed in the opening 290. The insulating layer 250 is provided on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region in contact with the top surface of the semiconductor layer 270, a region in contact with the side surface of the semiconductor layer 270, a region in contact with the side surface of the conductive layer 240, and a region in contact with the top surface of the insulating layer 280.

[0358] The conductive layer 260 is provided on the insulating layer 250, and has a region in contact with the upper surface of the insulating layer 250. The conductive layer 260 is provided so as to fill the opening 290. The conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270, with the insulating layer 250 interposed therebetween.

[0359] 22C shows an example in which the conductive layer 260 has a region overlapping with the conductive layer 240 with the insulating layer 250 and the semiconductor layer 270 interposed therebetween, but the present invention is not limited to this. For example, the conductive layer 260 may be provided so as not to overlap with the conductive layer 240. With such a structure, parasitic capacitance occurring between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operating speed of the memory cell can be improved.

[0360] The transistor VM1 is configured such that the direction of the channel length is not substantially parallel to the substrate (not shown) but is along the sidewall of an opening 602 provided in the insulating layer 280. Therefore, the transistor VM1 is a vertical transistor.

[0361] FIG. 22A shows an example in which the conductive layer 240 extends in a direction perpendicular to the conductive layers 110 and 260 .

[0362] Here, an enlarged view of the semiconductor layer 270 and its vicinity in Fig. 22C is shown in Fig. 23A, and a cross-sectional view in the XY plane including the conductive layer 240 is shown in Fig. 23B.

[0363] As shown in FIG. 23A, the semiconductor layer 270 has a region 270i, and regions 270na and 270nb that are provided so as to sandwich the region 270i.

[0364] Region 270na is a region of semiconductor layer 270 that contacts conductive layer 220. Region 270nb is a region of semiconductor layer 270 that contacts conductive layer 240. Region 270na and region 270nb each function as a source region or a drain region of transistor VM1. As shown in FIG. 23B , conductive layer 240 contacts the entire periphery of semiconductor layer 270. Therefore, the source region or drain region of transistor VM1 can be formed around the entire periphery of a portion of semiconductor layer 270 that is formed in the same layer as conductive layer 240.

[0365] Region 270i is a region in the semiconductor layer 270 that is sandwiched between regions 270na and 270nb. Region 270i functions as a channel formation region of transistor VM1. That is, the channel formation region of transistor VM1 is formed in a part of the semiconductor layer 270 that is located in a region between the conductive layer 220 and the conductive layer 240. It can also be said that the channel formation region of transistor VM1 is located in a region in contact with the insulating layer 280 or in a region in the vicinity of the insulating layer 280 in the semiconductor layer 270.

[0366] The channel length of the transistor VM1 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor VM1 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 23A, the channel length L of the transistor VM1 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the semiconductor layer 270 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 270 and the conductive layer 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 602 side in a cross-sectional view.

[0367] In a planar transistor, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor VM1 can be made an extremely fine structure below the exposure limit of photolithography. This increases the on-state current of the transistor VM1, thereby improving the frequency characteristics. Therefore, a semiconductor device with high operating speed can be provided.

[0368] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This allows the area occupied by the transistor VM1 to be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for a higher integration of the semiconductor device, thereby increasing the storage capacity per unit area.

[0369] Furthermore, in the XY plane including the channel formation region of the semiconductor layer 270, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged concentrically, as in FIG. 23B . Therefore, the side surface of the centrally located conductive layer 260 faces the side surface of the semiconductor layer 270 via the insulating layer 250. In other words, in a planar view, the entire periphery of the semiconductor layer 270 forms the channel formation region. In this case, for example, the channel width of the transistor VM1 is determined by the outer periphery of the semiconductor layer 270. In other words, the channel width of the transistor VM1 can be determined by the maximum width of the opening 602. In FIGS. 23A and 23B, the maximum width D of the opening 602 is indicated by a double-headed, dashed arrow. In FIG. 23B, the channel width W of the transistor VM1 is indicated by a double-headed, dashed arrow. Increasing the maximum width D of the opening 602 increases the channel width per unit area, thereby increasing the on-current.

[0370] When the opening 602 is formed using photolithography, the maximum width D of the opening 602 is set by the exposure limit of photolithography. The maximum width D of the opening 602 is also set by the film thicknesses of the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 provided in the opening 602. When the opening 602 is circular in plan view, the maximum width D of the opening 602 corresponds to the diameter of the opening 602, and the channel width W can be calculated as "D × π".

[0371] The maximum width D of the opening 602 may be calculated appropriately according to the shape of the opening 602 in a planar view. For example, if the opening 602 is rectangular in a planar view, the maximum width of the opening 602 may be the length of the diagonal of the rectangle. Alternatively, for example, if the opening 602 is elliptical, polygonal, or polygonal with rounded corners in a planar view, the maximum width of the opening 602 may be the diameter of the smallest circle (also referred to as the minimum encompassing circle) that encompasses the shape of the opening 602 in a planar view.

[0372] In the semiconductor device of one embodiment of the present invention, the channel length L of the transistor VM1 is preferably smaller than at least the channel width W of the transistor VM1. The channel length L of the transistor VM1 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor VM1. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0373] Furthermore, by forming the opening 602 so as to have a substantially circular shape in a plan view, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the semiconductor layer 270 substantially uniform, allowing a gate electric field to be applied to the semiconductor layer 270 substantially uniformly.

[0374] 23A and other drawings, the opening 602 is provided so that the side surface of the opening 602 is perpendicular to the upper surface of the conductive layer 220, but the present invention is not limited to this. For example, the side surface of the opening 602 may be tapered.

[0375] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0376] 22C , a portion of insulating layer 250 is located outside opening 603, i.e., on insulating layer 280. In this case, insulating layer 250 preferably covers the side edges of conductive layer 240. This can prevent conductive layer 260 and conductive layer 240 from shorting out.

[0377] The semiconductor layer 270 can be a single layer or a stack of semiconductors that can be used for the semiconductor layer 530. For the structure of the semiconductor layer 270, the structure of the semiconductor layer 530 can also be referred to.

[0378] The semiconductor layer 270 preferably has layered crystals that are approximately parallel to the side surface of the insulating layer 280 in the opening 602. With this configuration, the layered crystals of the semiconductor layer 270 are formed approximately parallel to the channel length direction of the transistor VM1, thereby increasing the on-state current of the transistor.

[0379] When the semiconductor layer 270 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the resistance of a region 270na of the semiconductor layer 270 decreases. When the semiconductor layer 270 comes into contact with the conductive layer 220, the resistance of the semiconductor layer 270 and the conductive layer 220 decreases, thereby reducing the contact resistance between the semiconductor layer 270 and the conductive layer 220. Similarly, when the semiconductor layer 270 and the conductive layer 240 come into contact with each other, the resistance of a region 270nb of the semiconductor layer 270 decreases. Therefore, the contact resistance between the semiconductor layer 270 and the conductive layer 240 can be reduced.

[0380] The conductive layer 240 can have a stacked structure of a first conductive layer and a second conductive layer over the first conductive layer. In this case, the first conductive layer can be formed using a conductive material with high conductivity, and the second conductive layer can be formed using a conductive material containing oxygen. When an oxide semiconductor is used for the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced by using a conductive material containing oxygen for the second conductive layer of the conductive layer 240 that is in contact with the semiconductor layer 270, thereby suppressing a decrease in the on-state current of the transistor VM1 due to the contact resistance. For example, tungsten can be used for the first conductive layer of the conductive layer 240, and indium tin oxide containing silicon can be used for the second conductive layer of the conductive layer 240.

[0381] The conductive layer 220 has a recessed portion at a position overlapping with the opening 602. The semiconductor layer 270 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220. Note that the recessed portion of the conductive layer 220 may be regarded as part of the opening 290.

[0382] By providing a recess in the position where the conductive layer 220 overlaps with the opening 602, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be made lower than the height of the top surface of the conductive layer 220 that is in contact with the insulating layer 280, with the top surface of the insulating layer 160 as the reference, compared to when the recess is not provided. Here, the height of each surface can be determined with the surface on which the memory cell or transistor is formed as the reference. Here, the top surface of the insulating layer 160 is used as the reference. The surface used as the reference is not particularly limited, and may be, for example, the top surface of a substrate on which the memory cell or transistor is provided as the reference.

[0383] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby reducing the contact resistance between the conductive layer 220 and the semiconductor layer 270. Therefore, a decrease in the on-state current of the transistor VM1 due to the contact resistance between the conductive layer 220 and the semiconductor layer 270 can be suppressed. Furthermore, a gate electric field is more easily applied to the channel formation region of the semiconductor layer 270, thereby improving the electrical characteristics of the transistor VM1. Furthermore, a gate electric field is more easily applied to the region of the semiconductor layer 270 that is in contact with the conductive layer 220, thereby increasing the on-state current of the transistor VM1. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor VM1 can be improved.

[0384] A conductive material containing oxygen is preferably used for the conductive layer 220. When an oxide semiconductor is used for the semiconductor layer 270, the use of a conductive material containing oxygen for the conductive layer 220 can reduce contact resistance between the semiconductor layer 270 and the conductive layer 220.

[0385] Alternatively, the conductive layer 220 may have a structure in which tungsten is stacked under a conductive material containing oxygen. By providing tungsten in this manner, the conductivity of the conductive layer 220 can be improved.

[0386] The insulating layers 280 and 285 preferably have a low dielectric constant because they function as interlayer films. By using a material with a low dielectric constant as the interlayer film, the capacitance value of parasitic capacitance generated between wirings can be reduced.

[0387] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 270.

[0388] An insulator containing excess oxygen is preferably used for the insulating layer 280. By performing heat treatment on the insulating layer 280 containing excess oxygen, oxygen is supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor VM1 and improve reliability.

[0389] Note that the transistor that can be used in the present invention is not limited to the transistor VM1 shown in Fig. 22C. For example, a transistor VM2 having a structure shown in Fig. 24 may be used. The transistor VM2 shown in Fig. 24 differs from the transistor VM1 shown in Fig. 22C in that a conductive layer 215 and an insulating layer 225 are provided.

[0390] The configuration shown in Fig. 24 corresponds to the memory cell 41A shown in Fig. 7A. In the memory cell 41A shown in Fig. 24, a transistor VM2 is provided above a capacitor VC1.

[0391] 24 , a conductive layer 215 is provided on an insulating layer 280. An insulating layer 281 is disposed on the insulating layer 280 and the conductive layer 215. A conductive layer 240 is provided on the insulating layer 281.

[0392] An opening 604 reaching the conductive layer 220 is provided in the insulating layer 280, the conductive layer 215, the insulating layer 281, and the conductive layer 240. The opening 604 includes an opening in the insulating layer 280, an opening in the conductive layer 215, an opening in the insulating layer 281, and an opening in the conductive layer 240. The sidewalls of the opening 604 include the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 215, the side surfaces of the insulating layer 281, and the side surfaces of the conductive layer 240.

[0393] The insulating layer 225, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are each provided so that at least a portion thereof is located in the opening 604. Specifically, the insulating layer 225 is provided so as to cover a portion of the bottom and the sidewall of the opening 604, the semiconductor layer 270 is provided so as to cover another portion of the bottom of the opening 604 and the insulating layer 225, and the insulating layer 250 is provided so as to cover the semiconductor layer 270. Then, the conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 604.

[0394] Insulating layer 225 contacts part of the top surface of conductive layer 220 , the side surfaces of insulating layer 280 , conductive layer 215 , insulating layer 281 , and conductive layer 240 in opening 604 .

[0395] In the transistor VM2 shown in FIG. 24, the semiconductor layer 270 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating film, the conductive layer 215 functions as a second gate electrode, the insulating layer 225 functions as a second gate insulating film, and the conductive layer 220 and the conductive layer 240 function as a source electrode or a drain electrode, respectively.

[0396] The potential applied to the conductive layer 215 is changed independently of the potential applied to the conductive layer 260, and the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 215, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 215, the drain current when the potential applied to the conductive layer 260 is 0 V can be made smaller than when a negative potential is not applied. Note that the conductive layer 260 may function as a second gate electrode, and the conductive layer 215 may function as a first gate electrode.

[0397] Alternatively, the conductive layer 215 may be connected to the conductive layer 260. Connecting the conductive layer 215 and the conductive layer 260 and applying the same potential to them makes it possible to increase the on-current, reduce variations in initial characteristics, suppress deterioration of electrical characteristics in a negative GBT (Gate Bias-Temperature) stress test, and suppress fluctuations in the on-current rise voltage at different drain voltages.

[0398] As described above, the transistor VM2 illustrated in FIG. 24 includes the first gate electrode and the second gate electrode, and therefore the electrical characteristics of the transistor included in the semiconductor device can be improved.

[0399] <Configuration Example 2 of NOSRAM> Figures 25A and 25B show an example of a transistor configuration applicable to a two-transistor NOSRAM circuit configuration. Figure 25A is an example of a perspective view of a semiconductor device in which multiple memory cells 41F, each having a stacked transistor VT1 and a transistor VT2, are arranged side by side. Transistors VT1 and VT2 are vertical transistors. Memory cell 41F is connected to conductive layer 220a, conductive layer 240a, conductive layer 240b, and conductive layer 210. Note that, for clarity, insulating layers such as interlayer films are not shown in Figure 25A, and the uppermost conductive layer 210 is indicated by a dashed line.

[0400] The conductive layer 220a shown in Fig. 25A functions as the read bit line RBL shown in Fig. 7F etc. The conductive layer 240a shown in Fig. 25A functions as the read word line RWL shown in Fig. 7F etc. The conductive layer 240b shown in Fig. 25A functions as the write bit line WBL shown in Fig. 7F etc. The conductive layer 210 shown in Fig. 25A functions as the write word line WWL shown in Fig. 7F etc.

[0401] In the memory cell 41F shown in Fig. 25A, a transistor VT2 is provided above a transistor VT1. The transistor VT2 shown in Fig. 25A corresponds to the transistor M1 of the memory cell 41F shown in Fig. 7F. The transistor VT1 shown in Fig. 25A corresponds to the transistor M2 of the memory cell 41F shown in Fig. 7F.

[0402] Although FIG. 25A shows an example in which the memory cells 41F are arranged at equal intervals in the X and Y directions, the memory cells 41F may be arranged in a staggered fashion, with each memory cell 41F being shifted alternately.

[0403] The transistor VT1 includes a conductive layer 220a, a conductive layer 240a, and a conductive layer 260a as its components, and the transistor VT2 includes a conductive layer 260a, a conductive layer 240b, and a conductive layer 260b as its components.

[0404] Next, a configuration example of memory cell 41F will be described. Fig. 25B is a perspective view illustrating the configuration example of memory cell 41F. For clarity, insulating layers such as interlayer films are not shown, and conductive layer 220a, parts of conductive layer 240a and conductive layer 240b, and conductive layer 210 are shown by dashed lines.

[0405] The memory cell 41F shown in FIG. 25B has a configuration in which, in the transistor VT1, a semiconductor layer 270a is provided in an opening provided in a conductive layer 240a, and the side surface of the conductive layer 240a in the opening contacts the semiconductor layer 270a.

[0406] 26A is a plan view illustrating the transistor VT1, and FIG. 26B is a plan view illustrating the transistor VT2. Note that in the plan views, some elements are omitted for clarity.

[0407] Fig. 26C is a diagram corresponding to a cross section taken along line A1-A2 in Fig. 26A and Fig. 26B. Fig. 26D is a diagram corresponding to a cross section taken along line B1-B2 in Fig. 26A and Fig. 26B.

[0408] The memory cell 41F includes an insulating layer 160 on a substrate (not shown), a transistor VT1 provided on the insulating layer 160, and a transistor VT2 provided on the transistor VT1. Note that insulating layers 280a, 280b, 285, and the like that function as interlayer films can be provided between the transistors and between various wirings.

[0409] The transistor VT1 includes a conductive layer 220a, a conductive layer 240a, a semiconductor layer 270a, an insulating layer 250a, and a conductive layer 260a. In the transistor VT1, the semiconductor layer 270a functions as a semiconductor layer, the conductive layer 260a functions as a gate electrode, and the insulating layer 250a functions as a gate insulating film. The conductive layer 220a and the conductive layer 240a function as a source electrode and a drain electrode, respectively.

[0410] That is, the transistor VT1 has a structure corresponding to the structure of the transistor VM1 shown in FIG. 22C. Therefore, in the figure, the corresponding components in the transistor VM1 and the transistor VT1 are basically designated by the same three-digit numeral. In the following, unless otherwise specified, the description of the transistor VM1 can be referred to for the transistor VT1.

[0411] The transistor VT2 includes a conductive layer 260a, a conductive layer 240b, a semiconductor layer 270b, an insulating layer 250b, and a conductive layer 260b. In the transistor VT2, the semiconductor layer 270b functions as a semiconductor layer, the conductive layer 260b functions as a gate electrode, and the insulating layer 250b functions as a gate insulating film. The conductive layer 260a and the conductive layer 240b function as source and drain electrodes.

[0412] That is, the transistor VT2 has a structure corresponding to the structure of the transistor VM1 shown in FIG. 22C. Therefore, in the figure, the corresponding components in the transistors VM1 and VT2 are basically designated by the same three-digit numeral. Also, hereinafter, unless otherwise specified, the description of the transistor VM1 can be referred to for the transistor VT2. The conductive layer 260a corresponds to the conductive layer 220 in the transistor VM1. Therefore, the description of the conductive layer 220 described above can be referred to for the conductive layer 260a.

[0413] The transistor VM2 shown in FIG. 24 may be applied to one or both of the transistors VT1 and VT2.

[0414] In other words, the conductive layer 260a has a region that shares the gate electrode of the transistor VT1 and one of the source electrode and drain electrode of the transistor VT2.

[0415] The conductive layer 260b is connected to the conductive layer 210 formed on the conductive layer 260b. The conductive layer 260b and the conductive layer 210 may be formed as the same element.

[0416] The conductive layers 260a and 260b preferably have a substantially circular top surface shape. Such a structure can increase the integration degree of the memory cell 41F. Note that the above description of the shape of the opening 602 and the like can be referred to for the top surface shapes of the conductive layers 260a and 260b.

[0417] In order to increase the overlapping area of ​​the transistors VT2 and VT1, it is preferable that the top surface shape of the opening 290b and the top surface shape of the opening 290a in which the transistor VT1 is formed are the same or similar.

[0418] <Constituent Materials of Semiconductor Device> Constituent materials that can be used in the semiconductor device will be described below.

[0419] [Substrate] Substrates that can be used in semiconductor devices include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements provided thereon may be used, such as a capacitor, a resistor, a switch, a light-emitting element, a memory element, and the like.

[0420] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0421] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the capacitance value of the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function. Note that materials with a low dielectric constant also have high dielectric strength.

[0422] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0423] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0424] Furthermore, a transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0425] An insulating layer, such as a gate insulating film, that is in contact with a semiconductor layer or that is provided near the semiconductor layer preferably has a region containing excess oxygen. For example, by providing an insulating layer having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0426] Examples of insulators having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0427] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0428] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0429] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0430] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., which are difficult to diffuse.

[0431] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As the alloy containing the above metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0432] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and elsewhere, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0433] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0434] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0435] When an oxide semiconductor is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0436] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed. Alternatively, the above-mentioned conductive materials containing the metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0437] [Other Semiconductor Materials] The semiconductor material that can be used for the semiconductor layer is not limited to an oxide semiconductor. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also called an atomic layer material, a two-dimensional material, or the like) as the semiconductor material.

[0438] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0439] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0440] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0441] Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0442] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a semiconductor device with a large on-current can be provided.

[0443] According to one embodiment of the present invention, a novel transistor and a novel semiconductor device can be provided. Alternatively, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with favorable frequency characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided. Alternatively, a semiconductor device with favorable reliability can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, a semiconductor device with favorable electrical characteristics can be provided.

[0444] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0445] Embodiment 4 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0446] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0447] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0448] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0449] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0450] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0451] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium Examples of usable materials include aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITO), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0452] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0453] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0454] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0455] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0456] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0457] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0458] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0459] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using at least two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed using at least two kinds of film formation methods may be referred to as a hybrid OS.

[0460] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by a first deposition method and then forming a metal oxide as a second layer on the first layer by a second deposition method. In this case, it is preferable to use a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the second deposition method as the first deposition method. By using a deposition method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, thereby increasing the crystallinity of the oxide semiconductor layer.

[0461] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. Compared to the sputtering method described below, the ALD and CVD methods are suitable as the first film formation method because they can suppress damage to the surface to be formed.

[0462] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0463] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs a high substrate temperature during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0464] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0465] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0466] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0467] Note that the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased using the second layer as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0468] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0469] For example, the oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer by a first deposition method, forming a metal oxide as a second layer by a second deposition method, and forming a metal oxide as a third layer by the first deposition method. Specifically, an ALD method can be used as the first deposition method, and a sputtering method can be used as the second deposition method. The ALD method has better coverage than the sputtering method, and the use of the ALD method as the deposition method for the first layer and the third layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0470] [Method for Manufacturing Oxide Semiconductor Layer] The oxide semiconductor 230, which is an oxide semiconductor layer, can be manufactured by, for example, forming an oxide semiconductor 230a over the layer 229, which is a surface to be formed, by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor 230. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process may be used.

[0471] The oxide semiconductor 230 can be used for the semiconductor layer 530, the semiconductor layer 270, or the like described in the above embodiment. The layer 229 corresponds to the insulating layer 524, the insulating layer 280, the insulating layer 225, the conductive layer 220, or the like described in the above embodiment.

[0472] The layer 229 does not need to be crystalline. When the layer 229 is crystalline, the layer 229 may have a crystal structure with low lattice matching with a metal oxide included in the oxide semiconductor 230.

[0473] An example of a method for manufacturing the oxide semiconductor 230 will be described with reference to FIGS. 27A to 28D.

[0474] First, an oxide semiconductor 230a is formed on the layer 229 by ALD (FIG. 27A). Then, an oxide semiconductor 230b is formed on the oxide semiconductor 230a by sputtering (FIG. 27B).

[0475] When a metal oxide film is formed by sputtering, damage to the surface on which the film is to be formed may cause alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed.

[0476] In the method for forming the oxide semiconductor layer of one embodiment of the present invention, the oxide semiconductor 230a is formed between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is formed. This prevents alloying of components contained in the oxide semiconductor 230 and components contained in the layer 229, thereby enabling the crystallinity of the oxide semiconductor 230 to be further improved.

[0477] By using the above structure, the thickness of the alloyed region can be reduced, or the thickness can be reduced to such an extent that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 27A and 27B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0478] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0479] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0480] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0481] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0482] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0483] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor 230 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0484] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0485] When the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 27A , the oxide semiconductor 230a may have a region having lower crystallinity than the oxide semiconductor 230b.

[0486] The oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0487] When the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, sputtering particles or energy imparted to the substrate by the sputtering particles or the like during the formation of the oxide semiconductor 230b may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor 230a to crystallize.

[0488] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, a metal oxide with high crystallinity can be formed in some cases.

[0489] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b by ALD (FIG. 27C). The formation of the oxide semiconductor 230c by ALD can be performed by referring to the method for forming the oxide semiconductor 230a.

[0490] When the oxide semiconductor 230c is formed on the oxide semiconductor 230b having the CAAC structure by the ALD method, the oxide semiconductor 230c may grow epitaxially around the oxide semiconductor 230b as a nucleus. Therefore, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0491] Next, a heat treatment step may be performed. This heat treatment step may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. Furthermore, if the region is formed only below the oxide semiconductor 230c after film formation by the ALD method, this heat treatment step may cause the region to expand upward ( FIG. 27D ). That is, this heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 230c.

[0492] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a is converted into CAAC by the heat treatment ( FIG. 27D ). It is expected that the CAAC conversion is facilitated by the mixed layer 231 formed in the oxide semiconductor 230a during the formation of the oxide semiconductor 230b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 229.

[0493] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 230a, the CAAC can be formed up to the vicinity of the layer 229 regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0494] 27A to 27D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 27A to 27D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide film according to one embodiment of the present invention. As shown in FIGS. 27A to 27D , the crystallinity of the oxide semiconductor 230a and the oxide semiconductor 230c increases with the oxide semiconductor 230b, which has high crystallinity, serving as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor 230a may be increased by heat treatment during the formation of the oxide semiconductor 230b or after the formation of the oxide semiconductor 230c. The crystallinity of the oxide semiconductor 230c may be increased by heat treatment during the formation of the oxide semiconductor 230c or after the formation of the oxide semiconductor 230c. The heat treatment assists in increasing the crystallinity.

[0495] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor 230a and the oxide semiconductor 230c here) can be increased by using the oxide semiconductor 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown by solid-phase growth using the oxide semiconductor 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC).

[0496] In the oxide semiconductor 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. FIG. 28A shows the oxide semiconductors 230a, 230b, and 230c each being crystallized. In this case, the boundary between the oxide semiconductors 230a and 230b may not be observed. The boundary between the oxide semiconductors 230b and 230c may not be observed. The oxide semiconductor 230 may be expressed as a single layer with no clearly observable interface. The oxide semiconductor 230 may be expressed as a single layer. Note that FIG. 27D illustrates the oxide semiconductor 230 having a three-layer stacked structure of the oxide semiconductors 230a, 230b, and 230c, but this is not limiting. For example, the oxide semiconductor 230 may have a two-layer stacked structure of the oxide semiconductors 230b and 230c.

[0497] Furthermore, there are cases where a portion of the oxide semiconductor 230a or the oxide semiconductor 230c is not crystallized. The example shown in Figure 28B illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a is not crystallized. Figure 28C illustrates a state in which the vicinity of the surface in the oxide semiconductor 230c is not crystallized. Figure 28D illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a and the vicinity of the surface of the oxide semiconductor 230c are not crystallized.

[0498] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0499] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 230, the boundaries between the stacked films of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0500] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductors 230a and 230c, crystals that reflect the crystal orientation of the oxide semiconductor 230b are formed, thereby suppressing polycrystallization.

[0501] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small. This allows the oxide semiconductor 230a or the oxide semiconductor 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 230b. In this case, for example, when a cross section of the oxide semiconductor 230 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0502] The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c is not particularly limited as long as the lattice mismatch between the crystal of the oxide semiconductor 230b and the crystal of the oxide semiconductor 230a or the oxide semiconductor 230c is small. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0503] [Composition of Oxide Semiconductor Layer] As described above, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed by, for example, a sputtering method. The oxide semiconductor 230b preferably contains, for example, zinc. The inclusion of zinc results in a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 230b preferably contains the element M in addition to zinc. The inclusion of the element M in the oxide semiconductor 230b can, for example, prevent oxygen vacancies from being formed in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the oxide semiconductor 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:3:4 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0504] The oxide semiconductor 230b may not contain the element M. For example, it may be an In—Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0505] The oxide semiconductor 230a and the oxide semiconductor 230c can be metal oxides having a high proportion of In. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current and frequency characteristics can be increased.

[0506] Alternatively, the oxide semiconductors 230a and 230c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, a composition of In:Zn=2:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound. Alternatively, indium oxide may be used. The oxide semiconductors 230a and 230c may contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0507] The oxide semiconductors 230a and 230c can be metal oxides containing a higher proportion of In than the oxide semiconductor 230b.

[0508] Alternatively, for example, metal oxides having a higher Ga content than the oxide semiconductor 230b may be used for the oxide semiconductors 230a and 230c. For example, the oxide semiconductors 230a and 230c may preferably be metal oxides having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout, metal oxides having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, or metal oxides having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereabout. Increasing the Ga content may result in the band gaps of the oxide semiconductors 230a and 230c being larger than those of the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductors 230a and 230c, which have larger band gaps, and the oxide semiconductor 230b mainly functions as a current path (channel). The oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c, whereby trap states at the interface of the oxide semiconductor 230b and in the vicinity thereof can be reduced, thereby realizing a buried-channel transistor in which the channel is separated from the insulating layer interface, and thereby increasing field-effect mobility.

[0509] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 230a and 230c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the oxide semiconductor 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor 230a and the oxide semiconductor 230c and the oxide semiconductor 230b.

[0510] In particular, even when the oxide semiconductor 230 a and the oxide semiconductor 230 c have a high In content, the oxide semiconductor layer can have suitable crystallinity for a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0511] The oxide semiconductor 230a and the oxide semiconductor 230c may have different compositions.

[0512] The oxide semiconductor 230a and the oxide semiconductor 230c may be made of a metal oxide having the same composition as the oxide semiconductor 230b.

[0513] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0514] The composition of the metal oxide used in the oxide semiconductor 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0515] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0516] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0517] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0518] The c-axis orientation rate can be calculated by calculating the percentage of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0519] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0520] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0521] The c-axis orientation rates of the region where the oxide semiconductor 230a is formed, the region where the oxide semiconductor 230b is formed, and the region where the oxide semiconductor 230c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0522] After the oxide semiconductor 230 is formed, the boundaries between the oxide semiconductors 230a, 230b, and 230c may not be clearly observed.

[0523] The oxide semiconductor 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0524] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0525] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor 230 .

[0526] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0527] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0528] In this embodiment, electronic components, electronic devices, and large scale computers that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, and large scale computers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0529] [Electronic Component] FIG. 29A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted. The electronic component 709 shown in FIG. 29A has a semiconductor device 710 inside a mold 711. FIG. 29A omits some parts in order to show the interior of the electronic component 709. The electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are connected to electrode pads 713, and the electrode pads 713 are connected to the semiconductor device 710 via wires 714. The electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on the printed circuit board 702 to complete the mounting substrate 704.

[0530] The semiconductor device 710 also includes a layer 715 having an arithmetic core and a layer 716 having a memory. The layer 716 having the memory is configured by stacking multiple memory cell arrays. The stacked configuration of the layer 715 having the arithmetic core and the layer 716 having the memory can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the layer 715 having the arithmetic core and the layer 716 having the memory as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0531] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0532] Furthermore, it is preferable that the memory cell arrays included in the memory-containing layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used in the memory-containing layer 716, it is more difficult to achieve a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0533] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0534] 29B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

[0535] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0536] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0537] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0538] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0539] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0540] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0541] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 29B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0542] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0543] 30A to 30D are diagrams illustrating configuration examples different from those of electronic components 709 and 730 described above in Fig. 29A and Fig. 29B. Electronic components 730A to 730D illustrated in Fig. 30A to 30D have a configuration in which a layer 715 having an arithmetic core and a layer 716 having a memory are provided in a mold 711 on an interposer 731 provided with the above-described electrodes 733.

[0544] In the configuration of electronic component 730A shown in FIG. 30A , layer 715 having processor cores is provided on interposer 731 and connected to electrode pads (not shown) via wires 714. Layer 716 having memory formed on layer 715 having processor cores has the monolithic stack configuration described above. In the monolithic stack configuration, layer 716 having memory and layer 715 having processor cores are connected. Therefore, wires 714 between interposer 731 and layer 715 having processor cores can also serve as wiring between each layer having memory 716 and interposer 731, thereby reducing the number of wires.

[0545] While the configuration example of FIG. 30A illustrates a single monolithic stacked structure, a configuration in which an electronic component having a monolithic stacked structure is stacked with other electronic components is also possible. For example, as shown in FIG. 30B , a configuration in which a monolithic stacked structure is formed by stacking a layer 716A having memory and a layer 715A having an arithmetic core, and a layer 716B having memory and a layer 715B having an arithmetic core, are stacked together. The monolithic stacked structure stacked with other electronic components is fixed to a resin sheet 744 by an adhesive layer 743. This configuration allows for stacking multiple memory cell arrays with different circuit configurations. Having different circuit configurations allows for a semiconductor device with different memory bandwidths and memory access latencies, making it suitable for use in a hierarchical structure such as a cache memory.

[0546] The configuration example of FIG. 30A can also be stacked with other electronic components. For example, as shown in FIG. 30C , an electronic component having a layer 715C with an operational core such as a processor provided in a mold 711 between interposers 731A and 731B, and the above-described electronic component 730A can be stacked to form electronic component 730C. The circuit layers can be connected via conductors such as electrodes 733. This configuration enables the processor and memory interface to operate at high speed. Furthermore, a gap (space) can be provided between the mold including the operational core layer 715C and the electronic component 730A, thereby making it difficult for heat generated in the operational core layer 715C to be transmitted to the electronic component 730A.

[0547] 30C , a memory layer having an OS transistor may be provided on a layer 715C having an arithmetic core such as a processor. For example, as shown in FIG. 30D , a memory layer 716C may be provided on the arithmetic core layer 715C, and stacked with electronic components 730A. This configuration enables the high-speed operation of the interface between the so-called on-chip memory configuration in which memory is formed directly on a processor and the semiconductor device configuration having stacked memory layers.

[0548] [Electronic Device] Fig. 31A is an external view showing an example of a portable electronic device. Fig. 31B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0549] In the portable electronic device 595, the electronic component 709 can be provided on the printed circuit board 596. The portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by the speaker 597, the camera 598, the microphone 599, etc. using the electronic component 709. The portable electronic device 595 can also be used in systems that perform voice guidance, image search, etc.

[0550] The electronic component 709 performs arithmetic processing of the obtained image data using a neural network or the like, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0551] The portable game console 1100 shown in FIG. 32A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The electronic component 709 can be incorporated into chips or the like provided on the substrates of the housings 1102 and 1103.

[0552] 32B shows a stick-shaped electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The electronic component 709 can be incorporated into the controller chip 1126 of the board 1124, etc.

[0553] 32C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the electronic component 709 described above.

[0554] [Mainframe] The electronic component 709 can be used in a system 3000 including a mainframe that communicates with the electronic device, instead of being built into the electronic device. In this case, the electronic device and the mainframe constitute a computing system. Fig. 33 shows an example of the configuration of the system 3000.

[0555] The system 3000 is configured by an electronic device 3001 and a mainframe computer 3002. Communication between the electronic device 3001 and the mainframe computer 3002 can be performed via an internet line 3003.

[0556] The mainframe 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided on the racks, and the electronic components 709 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in the mainframe 3002. The mainframe 3002 can then perform neural network calculations using data input from the electronic device 3001 via the Internet line 3003. The results of calculations by the mainframe 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as necessary. This reduces the calculation load on the electronic device 3001.

[0557] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0558] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0559] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0560] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0561] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0562] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0563] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0564] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0565] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0566] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0567] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0568] In this specification and the like, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0569] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0570] In this specification, the channel length of a planar transistor refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a plan view of the transistor, or a distance between a source and a drain in a region where a channel is formed.

[0571] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0572] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0573] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0574] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0575] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0576] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0577] In this specification, "connection" includes, as an example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, as examples, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0578] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0579] Specific examples of "indirect connection" are given below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, it is assumed that there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where there is a time when one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0580] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0581] Another example of a case in which it cannot be said that "A and B are indirectly connected" is when there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. For example, a path from A to B may have multiple transistors connected via their sources and drains, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." Note that if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply, GND, or the like, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and C are indirectly connected" or "B and C are indirectly connected."

[0582] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0583] Next, specific examples of "direct connection" are shown. An example of "A and B are directly connected" is when A and B are connected without any circuit element between them. Note that when A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Note that even when A (or B) is connected to a constant potential V via the source and drain of a transistor, it can still be said that "A and B are directly connected." Note that because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0584] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0585] 10: Element layer, 11: Memory circuit section, 12: Interface section, 14: Operation block, 15: Controller section, 16: Product-sum operation section, 17: Activation function operation section, 18: Data conversion section, 19: Load store section, 20: Sense amplifier section, 21: Sense amplifier, 30: Memory circuit, 31: Memory cell, 40: Element layer, 41: Memory cell, 42: Memory cell array, 51: Transistor, 52: Semiconductor layer, 53: Transistor

Claims

a first memory cell, a sense amplifier, a second memory cell, and an arithmetic block, wherein the first memory cell, the sense amplifier, and the arithmetic block are provided in a first device layer, the second memory cell is provided in a second device layer, the second device layer is provided above the first device layer, the second memory cell is electrically connected to the sense amplifier and the first memory cell via a first bit line, the first memory cell is electrically connected to the arithmetic block via a second bit line, data transferred to the arithmetic block is data written to the first memory cell by activating, in the sense amplifier, data held in the second memory cell, a semiconductor device. 　 In claim 1, the first memory cell includes a first transistor, the first transistor includes a first semiconductor layer having silicon in a channel formation region, a semiconductor device. 　 In claim 1 or 2, the second memory cell includes a second transistor, the second transistor includes a second semiconductor layer having an oxide semiconductor in a channel formation region, a semiconductor device. 　 In claim 1, the first memory cell is a memory cell of a static random access memory, a semiconductor device. 　 In claim 1, the first bit line has a portion provided parallel to a direction perpendicular to the surface of the substrate on which the first device layer is provided, between the second memory cell and the sense amplifier and between the second memory cell and the first memory cell, a semiconductor device. 　 a first memory cell, a sense amplifier, a second memory cell, and an arithmetic block, wherein the first memory cell, the sense amplifier, and the arithmetic block are provided in a first device layer, the second memory cell is provided in a second device layer, the second device layer is provided above the first device layer, the second memory cell is electrically connected to the sense amplifier and the first memory cell via a first bit line, the first memory cell is electrically connected to the arithmetic block via a second bit line, data transferred to the arithmetic block is data written to the first memory cell by activating, in the sense amplifier, data held in the second memory cell, the arithmetic block includes a multiply-accumulate unit, an activation function calculation unit, a data conversion unit, a load / store unit, and a controller unit, a semiconductor device. 　 In claim 6, The first memory cell has a first transistor, The first transistor has a first semiconductor layer having silicon in a channel formation region, A semiconductor device. 　 In claim 6 or 7, The second memory cell has a second transistor, The second transistor has a second semiconductor layer having an oxide semiconductor in a channel formation region, A semiconductor device. 　 In claim 6, The first memory cell is a memory cell of a static random access memory, A semiconductor device. 　 In claim 6, The first bit line has a portion provided in parallel with a direction perpendicular to the substrate surface on which the first element layer is provided, between the second memory cell and the sense amplifier, and between the second memory cell and the first memory cell, A semiconductor device. 　 In claim 6, The sum-of-products calculation unit has an arithmetic circuit and an analog-to-digital conversion circuit, The arithmetic circuit has a cell array that performs a sum-of-products calculation, and an input circuit that converts an input digital signal into an analog signal and inputs it to the cell array, The analog-to-digital conversion circuit has a function of converting the analog signal output by the arithmetic circuit into a digital signal, The input circuit and the analog-to-digital conversion circuit are provided in the first element layer, The cell array is provided in the second element layer, A semiconductor device.

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