Substrate for semiconductor package, method for manufacturing same, wiring board, and semiconductor package

Abstract

This substrate for a semiconductor package has a side surface having an arithmetic average roughness Ra of 450 nm or less. The side surface may be a polished surface. A substrate body part including an insulating resin layer and an inorganic fiber base arranged in the insulating resin layer may be provided.

Description

Substrate for semiconductor package and manufacturing method thereof, wiring board, and semiconductor package

[0001] The present disclosure relates to a substrate for a semiconductor package, a manufacturing method thereof, a wiring board, and a semiconductor package.

[0002] In a semiconductor package, a semiconductor chip may be mounted on a wiring board having a core board formed from a substrate material and a multilayer wiring layer formed on the core board (see, for example, Patent Document 1).

[0003] JP 2017-11156 A

[0004] In semiconductor packages in which electronic components including semiconductor chips are mounted on a wiring board, cracks may occur in the substrate that constitutes the wiring board due to internal stress caused by differences in thermal expansion coefficients due to thermal shock, physical shock due to contact with other objects, etc.

[0005] The present disclosure relates to a substrate for a semiconductor package that is less susceptible to cracking.

[0006] The present disclosure includes the following: [1] A semiconductor package substrate having a side surface with an arithmetic mean roughness Ra of 450 nm or less. [2] The semiconductor package substrate according to [1], wherein the side surface is a polished surface. [3] The semiconductor package substrate according to [1] or [2], which has an insulating substrate including an insulating resin layer and an inorganic fiber base material disposed in the insulating resin layer. [4] The semiconductor package substrate according to [3], further having a protective resin portion provided around the insulating substrate, which forms the side surface with an arithmetic mean roughness Ra of 450 nm or less. [5] The semiconductor package substrate according to any one of [1] to [4], which has curved corners. [6] A method for manufacturing a semiconductor package substrate, comprising: cutting out a plurality of semiconductor package substrates from a sheet-like substrate material; and smoothing the side surface of the semiconductor package substrate to form the side surface with an arithmetic mean roughness Ra of 450 nm or less. [7] A wiring board including the semiconductor package substrate according to any one of [1] to [5]. [8] A semiconductor package comprising: the wiring board according to [7]; and an electronic component including a semiconductor chip mounted on the wiring board.

[0007] The occurrence of cracks in the semiconductor package substrate can be suppressed, and the suppression of crack occurrence can improve the reliability of the semiconductor package.

[0008] During the process of mounting a semiconductor package on a device such as an electronic device, the package may be subjected to physical shocks, such as contact with other objects. For example, the package may come into contact with manufacturing equipment or other substrate materials during transportation, or may be dropped from its designated position on the manufacturing line and come into contact with the floor. Smoothing the side surfaces of the substrate can prevent cracks from occurring due to these physical shocks.

[0009] During the process of mounting a semiconductor package on a device, the package may be subjected to thermal shock, for example, due to heating for curing a resin layer laminated on the substrate and heating for mounting a semiconductor chip. Furthermore, after the semiconductor package is mounted on various devices, the package may be heated by the heat generated when the device is operating and by the ambient air. The substrate, wiring, resin materials such as build-up film and solder resist, and semiconductor chip that make up the semiconductor package all have different thermal expansion coefficients. In particular, because the substrate is sandwiched between the wiring, resin material, and semiconductor chip, internal stress from both sides makes it prone to cracking, especially at corners. Smoothing the side surfaces of the substrate can also prevent cracking of the substrate due to thermal shock.

[0010] 1 is a plan view showing an example of a method for manufacturing a substrate for a semiconductor package; 2 is a cross-sectional view showing an example of a method for manufacturing a substrate for a semiconductor package; 3 is a cross-sectional view showing an example of a method for manufacturing a substrate for a semiconductor package; 4 is a cross-sectional view showing an example of a method for manufacturing a substrate for a semiconductor package; 5 is a plan view showing an example of a semiconductor package; 6 is a cross-sectional view showing an example of a semiconductor package; 7 is a cross-sectional view showing an example of a method for manufacturing a substrate material; 8 is a cross-sectional view showing an example of a method for manufacturing a substrate material;

[0011] The present invention is not limited to the following examples: In this specification, the term "thickness direction" refers to a direction perpendicular to the two main faces of a sheet-like material that have the largest areas.

[0012] 1, 2, and 3 are plan views or cross-sectional views schematically illustrating an example of a method for manufacturing a semiconductor package substrate. As shown in the plan view of FIG. 1, a sheet-like substrate material 100 for forming a semiconductor package substrate is prepared. The substrate material 100 may be an insulating substrate including an insulating resin layer and an inorganic fiber base material disposed within the insulating resin layer. The substrate material 100 may further include a metal foil provided on one or both sides of the insulating substrate.

[0013] The width of the substrate material 100 may be 200 to 2650 mm, and the thickness of the substrate material 100 may be 200 to 2000 μm.

[0014] A plurality of semiconductor package substrates 20 are cut out from a sheet-like substrate material 100. An example of one cut semiconductor package substrate 20 is shown in FIG. 2. The semiconductor package substrate 20 has a first surface S1, which is a rectangular main surface, a second surface S2 on the back side thereof, and a side surface S3 between the first surface S1 and the second surface S2. The side surface S3 of the semiconductor package substrate 20 has a certain degree of roughness as a result of cutting using a blade or the like. Next, as shown in FIG. 3, the side surface S3 is smoothed. The smoothed side surface S3 has an arithmetic mean roughness Ra of 450 nm or less. The semiconductor package substrate 20 having the smoothed side surface S3 is less susceptible to stress concentration and therefore less susceptible to cracking due to thermal shock or physical impact. From a similar perspective, the arithmetic mean roughness Ra of the smoothed side surface S3 may be 420 nm or less, 400 nm or less, 380 nm or less, 360 nm or less, 340 nm or less, or 320 nm or less. The arithmetic mean roughness Ra of the smoothed side surface S3 may be 100 nm or more, 150 nm or more, 200 nm or more, or 250 nm or more. When the substrate material 100 has an insulating substrate and a metal foil, the side surface of the semiconductor package substrate including the metal foil or the side surface of the semiconductor package substrate that is an insulating substrate from which the metal foil has been removed can have an arithmetic mean roughness Ra of 450 μm or less.

[0015] The arithmetic mean roughness Ra is a value determined in accordance with JIS B 0601. The arithmetic mean roughness Ra is measured in the thickness direction of the semiconductor package substrate 20 using a contact profilometer under conditions of, for example, a measurement distance of 0.5 mm, a measurement speed of 100 μm, and a measurement load of 0.2 mg.

[0016] The method for smoothing the side surface S3 may be, for example, a method using a chemical reaction or a method using polishing. The method using a chemical reaction may include, for example, immersing the side surface S3 in a chemical solution that dissolves the material that constitutes the substrate. Immersion in the chemical solution removes irregularities and fine cracks on the side surface S3, thereby smoothing the side surface S3. The chemical solution may be, for example, a desmear solution. The polishing method may be, for example, contact with abrasive paper or a metal file, irradiation with laser light, or ion milling.

[0017] The entire side surface S3 of the semiconductor package substrate 20 may be smoothed. Only the portion of the side surface S3 where large irregularities are formed due to irregularities and fine cracks may be smoothed. For example, only the side surface S3 near the corner of the substrate may be smoothed. Typically, the side surface S3 is smoothed so that the entire side surface S3 has an arithmetic mean roughness of 450 nm or less. The side surface of the substrate material 100 before the semiconductor package substrate 20 is cut out may be smoothed.

[0018] 4 is a cross-sectional view showing another example of a semiconductor package substrate having a smoothed side surface S3. The semiconductor package substrate 20 shown in FIG. 4 includes an insulating substrate 10 cut out from a substrate material 100 and a protective resin portion 22 provided around the periphery of the insulating substrate 10, the protective resin portion 22 forming a side surface S3 having an arithmetic mean roughness Ra of 450 nm or less. The insulating substrate 10 may include an insulating resin layer and an inorganic fiber substrate disposed within the insulating resin layer. Metal foil may be provided on one or both sides of the insulating substrate 10, and the side surface including the insulating substrate and the metal foil may be covered with the protective resin portion 22.

[0019] The protective resin portion 22 may be a cured product of a thermosetting or ultraviolet-curing resin composition. The protective resin portion 22 may contain a thermoplastic resin. The thermosetting resin may have one or more reactive functional groups at the molecular end or in the molecular chain. Examples of the reactive functional group include an epoxy group, a hydroxyl group, a carboxyl group, an amino group, an amide group, an isocyanato group, an acryloyl group, a methacryloyl group, a vinyl group, and a maleic anhydride group. The thermoplastic resin may be, for example, at least one selected from an acrylic resin, a polyamide resin, a polyimide resin, and a polyurethane resin.

[0020] The protective resin portion 22 is formed by a method including, for example, applying a thermosetting or ultraviolet-curable resin composition to the side surface of the substrate main body portion 21 and curing the applied resin composition. The method for applying the resin composition to the side surface of the substrate main body portion 21 may be, for example, dispensing, laminating, spraying, or immersion in the resin composition.

[0021] An individual semiconductor package substrate obtained from the substrate material 100 is used to form a wiring substrate on which a semiconductor package is mounted. When the substrate material 100 has an insulating substrate and a metal foil, for example, a wiring substrate for a semiconductor package having fine wiring can be manufactured by using the metal foil of the substrate material 100 or by forming wiring on the insulating substrate by a build-up method or the like after removing the metal foil. The semiconductor package substrate may also be used as a core material for forming a wiring substrate for a semiconductor package.

[0022] FIG. 5 is a plan view showing an example of a semiconductor package, and FIG. 6 is an end view taken along line VI-VI in FIG. 5 . The semiconductor package 50 shown in FIGS. 5 and 6 includes a wiring substrate 30, an electronic component 40 including a semiconductor chip mounted on the wiring substrate 30, and bumps 35 provided on the side of the wiring substrate 30 opposite the electronic component 40. The wiring substrate 30 includes a semiconductor package substrate 20 obtained from a substrate material as a core material, and build-up layers 25 including wiring provided on the first surface S1 and second surface S2 of the semiconductor package substrate 20. The electronic component 40 is flip-chip connected to the wiring substrate 30 via connection terminals 41 on the first surface S1 of the semiconductor package substrate 20. An underfill 42 may be filled between the electronic component 40 (semiconductor chip) and the wiring substrate 30.

[0023] FIG. 7 is a plan view showing another example of a semiconductor package. In the semiconductor package shown in FIG. 7, the wiring substrate 30 and the semiconductor package substrate 20 forming it have four curved corners C. The curved corners can also contribute to suppressing crack formation. A curved corner refers to a curved surface shape with a radius of curvature greater than 0 mm. From the viewpoint of ensuring a wide area for forming wiring, the radius of curvature of the curved corner C may be equal to or less than the length of the short side of the rectangular first surface S1, or equal to or less than ¼ of the length of the short side of the rectangular first surface S1. From the viewpoint of more effective internal stress distribution, the radius of curvature of the curved corner C may be equal to or greater than 1 / 10 of the length of the short side of the rectangular first surface S1. The short sides of the rectangular first surface S1 are two of the four straight lines surrounding the first surface S1. If the four straight lines surrounding the first surface S1 are equal, the length of any one of the straight lines is considered to be the length of the short side.

[0024] The curved corners C of the semiconductor package substrate 20 can be formed by applying an external force, such as grinding or cutting. Examples of grinding include grinding the corners using abrasive paper or a metal file. Examples of cutting include using a diamond cutter, a cutting saw, a router, a laser, a press cutter, or a dicer.

[0025] The curved corner C of the semiconductor package substrate 20 may be formed by a method of removing the corner portion of the semiconductor package substrate 20 by a chemical reaction, such as by immersing the corner portion in a chemical solution. The chemical solution may be, for example, a desmear solution.

[0026] 8, 9, and 10 are cross-sectional views showing an example of a method for producing the substrate material exemplified in FIG. 1. The method shown in FIGS. 8 to 10 includes preparing a sheet-like inorganic fiber substrate 11 and a plurality of prepregs 1 containing a thermosetting resin composition 12 impregnated into the inorganic fiber substrate 11, and forming an insulating substrate 10 by heating and pressurizing a laminate 5 containing the plurality of prepregs 1. The laminate 5 shown in FIG. 9 further includes two metal foils 3 arranged to sandwich the stacked plurality of prepregs 1 from both sides. A molding process including increasing the temperature of the stacked laminate 5 while applying pressure to the laminate 5 forms an insulating substrate 10 formed by integrating two or more prepregs 1, as shown in FIG. 10, and a substrate material 100 having metal foils 3 provided on both sides of the insulating substrate 10. An insulating resin layer may be provided between the metal foils 3 and the laminate 5. Heating the laminate 5 cures the thermosetting resin composition 12, forming an insulating resin layer 12A of the substrate material 100.

[0027] The inorganic fiber substrate 11 can be, for example, a woven or nonwoven fabric containing inorganic fibers. The inorganic fibers constituting the inorganic fiber substrate 11 may be glass fibers, carbon fibers, or a combination thereof. The inorganic fiber substrate 11 may also be a glass cloth made of glass fibers. The proportion of glass fibers among the inorganic fibers constituting the inorganic fiber substrate may be 80 to 100 mass%, 90 to 100 mass%, 95 to 100 mass%, or 99 to 100 mass%. The glass fibers may be, for example, E-glass, S-glass, or quartz glass. The thickness of the inorganic fiber substrate 11 may be 0.01 to 0.20 μm.

[0028] The thermosetting resin composition 12 includes a thermosetting resin component. The thermosetting resin composition 12 may further include an inorganic filler. When the thermosetting resin composition 12 includes an inorganic filler, the portion of the thermosetting resin composition 12 excluding the inorganic filler may be considered as the resin component.

[0029] The thermosetting resin component is a component that forms a cured product upon heating and may include, for example, a thermosetting resin and a curing accelerator. The thermosetting resin is a compound that forms a crosslinked polymer upon heating and typically has a reactive functional group that undergoes a crosslinking reaction. The reactive functional group may be, for example, an epoxy group, a hydroxyl group, a carboxyl group, an amino group, an amide group, an isocyanato group, an acryloyl group, a methacryloyl group, a vinyl group, a maleic anhydride group, or a combination thereof. The thermosetting resin may include an epoxy resin having two or more epoxy groups, an acrylate compound having two or more (meth)acryloyl groups, or a combination thereof. The content of the thermosetting resin may be, for example, 20 to 80% by mass based on the total mass of the components of the thermosetting resin composition 12 other than the inorganic filler.

[0030] The thermosetting resin may include a thermosetting elastomer having a reactive functional group. Examples of thermosetting elastomers include styrene-based elastomers, olefin-based elastomers, urethane-based elastomers, polyester-based elastomers, polyamide-based elastomers, acrylic-based elastomers, and silicone-based elastomers. The content of the thermosetting elastomer may be, for example, 10 to 70 mass % or 20 to 60 mass % based on the total mass of components other than the inorganic filler in the thermosetting resin composition.

[0031] Examples of the curing accelerator include peroxides, imidazole compounds, organic phosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. These may be used alone or in combination of two or more. When the thermosetting resin is an epoxy resin, the curing accelerator may be, for example, an imidazole compound. The content of the curing accelerator may be, for example, 0.1 to 10% by mass, 0.5 to 5% by mass, or 0.75 to 3% by mass, based on the total mass of the components of the thermosetting resin composition other than the inorganic filler.

[0032] The thermosetting resin composition 12 may further include a thermoplastic resin as a resin component. The content of the thermoplastic resin may be, for example, 20 to 80 mass % based on the total mass of the components of the thermosetting resin composition 12 other than the inorganic filler.

[0033] The thermoplastic resin may be, for example, at least one selected from an acrylic resin, a polyamide resin, a polyimide resin, and a polyurethane resin. The thermoplastic resin may have a siloxane group. For example, an acrylic resin, a polyamide resin, a polyimide resin, or a polyurethane resin may have a siloxane group. The resin having a siloxane group may be a silicone resin. The polyimide resin having a siloxane group may be, for example, a polymer produced by the reaction of a siloxane diamine with a tetracarboxylic dianhydride, or a polymer produced by the reaction of a siloxane diamine with a bismaleimide.

[0034] The thermoplastic resin may have one or more reactive functional groups at the molecular end or in the molecular chain, examples of which include an epoxy group, a hydroxyl group, a carboxyl group, an amino group, an amide group, an isocyanato group, an acryloyl group, a methacryloyl group, a vinyl group, and a maleic anhydride group.

[0035] The proportion of the thermosetting resin component in the thermosetting resin composition 12 may be 20% by mass or more, 30% by mass or more, or 40% by mass or more, relative to the mass of the thermosetting resin composition 12, and may be 100% by mass or less, or 80% by mass or less.

[0036] Examples of inorganic fillers include alumina, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, crystalline silica, amorphous silica, boron nitride, titania, glass, iron oxide, ceramic, and carbon.

[0037] The content of the inorganic filler may be, for example, 40 to 300 mass % based on the total mass of the components of the thermosetting resin composition 12 other than the inorganic filler.

[0038] The average particle size of the inorganic filler may be 10 μm or less or 5 μm or less, or may be 0.001 μm or more. The maximum particle size of the filler may be 30 μm or less or 20 μm or less, or may be 0.001 μm or more. The average particle size and maximum particle size of the inorganic filler may be the average value and maximum value of the maximum width in a two-dimensional image of the inorganic filler observed with a scanning electron microscope (SEM), for example.

[0039] The thermosetting resin composition may further contain other components as necessary. Examples of the other components include an adhesion aid, a silane coupling agent, a triazole compound, a tetrazole compound, an ion scavenger, an antioxidant, and an organic filler.

[0040] The content of the thermosetting resin composition 12 in the prepreg 1 may be 40 to 80 mass % based on the mass of the prepreg 1 .

[0041] The width of the prepreg 1 may be, for example, 200 to 1300 mm. The thickness of the prepreg 1 may be, for example, 15 to 300 μm. If the thickness of the prepreg 1 is less than 15 μm, the flatness of the substrate tends to decrease relatively due to unevenness caused by the inorganic fiber substrate 11. If the thickness of the prepreg 1 is large, the warpage of the substrate tends to increase.

[0042] The prepreg 1 can be obtained, for example, by a method including impregnating an inorganic fiber substrate 11 with a resin varnish containing a thermosetting resin composition 12 and a solvent, and removing the solvent from the resin varnish.

[0043] From the viewpoint of electrical conductivity, the metal foil 3 may contain copper, gold, silver, nickel, platinum, molybdenum, ruthenium, aluminum, tungsten, iron, titanium, chromium, or an alloy containing at least one of these metal elements. The metal foil 3 may be a copper foil, an aluminum foil, or a copper foil. An insulating resin layer may be provided on the surface of the metal foil 3 facing the prepreg 1.

[0044] The heating conditions for forming the substrate material 100 may include increasing the temperature of the laminate 5 to a molding temperature at a predetermined temperature increase rate, and maintaining the temperature of the laminate 5 at the molding temperature. In this case, the molding temperature may be, for example, 100 to 300° C. or 150 to 250° C. The heating and pressurizing time at the molding temperature may be, for example, 0.1 to 5 hours.

[0045] Typically, pressure is continuously applied to the laminate 5 while the laminate 5 is being heated. The pressure applied to the laminate 5 may be, for example, 0.2 to 10 MPa.

[0046] The device for heating and pressurizing the laminate 5 can be a heat press device. The heat press device may be, for example, a multi-stage press, a multi-stage vacuum press, a continuous molding machine, or an autoclave molding machine. When the device for heating and pressurizing the laminate 5 is a heat press device, a metal plate may be placed on the surface of the metal foil 3 opposite to the prepreg 1.

[0047] The insulating resin layer 12A, which is a cured thermosetting resin composition, may have a dielectric constant of 3.0 or less, or 2.8 or less, at 10 GHz. The insulating resin layer 12A may have a dielectric loss tangent of 0.005 or less at 10 GHz. The dielectric constant can be measured using a test piece of the cured thermosetting resin composition, which is 60 mm long, 2 mm wide, and 300 μm thick. The test piece may be vacuum dried at 30°C for 6 hours before measurement. The dielectric loss tangent can be calculated from the resonant frequency and unloaded Q value obtained at 10 GHz. The measurement device may be a Keysight Technologies vector network analyzer E8364B, a Kanto Electronics Application Development CP531 (10 GHz resonator), and a CPMAV2 (program). The measurement temperature may be 25°C.

[0048] The insulating resin layer 12A, which is a cured thermosetting resin composition, may have a glass transition temperature of 120° C. or higher, or 140° C. or higher. The insulating resin layer 12A may have a glass transition temperature of 240° C. or lower, or 220° C. or lower.

[0049] The wiring board for a semiconductor package can be obtained, for example, by a method including forming wiring by a subtractive method on the metal foil 3 of the semiconductor package substrate 20 obtained from the substrate material 100, or by a method including forming wiring by a semi-additive method after removing the metal foil 3 as necessary. If necessary, a through hole penetrating the insulating substrate 10 may be formed, and a conductive via filling the through hole may be formed.

[0050] A build-up layer may be formed on the semiconductor package substrate 20 as a core material. In this case, wiring connected to the semiconductor chip may be formed on the build-up layer. The build-up layer may be formed by, for example, a subtractive method, a full-additive method, a semi-additive method (SAP: Semi-Additive Process), a modified semi-additive method (m-SAP: Modified Semi-Additive Process), or a trench method.

[0051] The trench method is a method that includes forming a build-up material or a photosensitive insulating material layer having a pattern including grooves on a semiconductor package substrate 20 as a core material, and filling the grooves with a conductive material. The conductive material formed outside the grooves is removed by a method such as CMP or flycutting.

[0052] A semiconductor package is manufactured by mounting electronic components including a semiconductor chip at predetermined positions on a wiring board prepared using the semiconductor package substrate 20.

[0053] 1...prepreg, 5...laminate, 10...insulating substrate, 11...inorganic fiber base material, 12...thermosetting resin composition, 20...substrate for semiconductor package, 22...protective resin part, 30...wiring board, 40...electronic component (semiconductor chip), 50...semiconductor package, C...curved corner, S1...first surface, S2...second surface, S3...side surface.

Claims

1. A substrate for a semiconductor package having a side surface with an arithmetic mean roughness Ra of 450 nm or less.

2. The substrate for a semiconductor package according to claim 1, wherein the side surface is a polished surface.

3. The substrate for a semiconductor package according to claim 1, having an insulating substrate including an insulating resin layer and an inorganic fiber base material disposed in the insulating resin layer.

4. The substrate for a semiconductor package according to claim 3, further having a protective resin portion provided around the insulating substrate and forming the side surface having an arithmetic mean roughness Ra of 450 nm or less.

5. The substrate for a semiconductor package according to claim 1, having a curved corner.

6. A method for manufacturing a substrate for a semiconductor package, including cutting out a plurality of substrates for semiconductor packages from a sheet-like substrate material, and forming the side surface having an arithmetic mean roughness Ra of 450 nm or less by smoothing the side surface of the substrate for a semiconductor package.

7. A wiring board including the substrate for a semiconductor package according to claim 1.

8. A semiconductor package including the wiring board according to claim 7 and an electronic component including a semiconductor chip mounted on the wiring board.

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