Light detection device and electronic apparatus

Abstract

Provided is a light detection device in which the influence of dark current is suppressed. The light detection device comprises: a semiconductor layer having a back surface on one side and an element formation surface on the other side, the semiconductor layer including a plurality of cell regions that are arranged in a matrix and include a photoelectric conversion region, namely, a semiconductor region of a first conductivity type; separator walls that are provided in a groove extending between the back surface and the element formation surface of the semiconductor layer and separate the cell regions from each other; and a first transistor and a second transistor provided on the element formation surface side of the cell regions. The first transistor is a transistor having a transfer path that is a semiconductor region of the first conductivity type directly connected to the photoelectric conversion regions, the second transistor is a transistor other than the first transistor, the first transistor is provided at a position closer to a first separator wall among the separator walls than the centers of the cell regions in a plan view, the transfer path is provided spaced apart from the first separator wall, and the semiconductor region of the second transistor is in contact with the separator walls.

Description

Photodetector and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to a photodetector device and an electronic device, and in particular to a photodetector device and an electronic device in which pixels are separated by a trench isolation structure.

[0002] CMOS solid-state imaging devices (hereafter referred to as CMOS image sensors) are known as solid-state imaging devices that can be manufactured using the same process as CMOS integrated circuits. CMOS image sensors can easily form active structures with amplification functions for each pixel thanks to the miniaturization technology associated with the CMOS process. CMOS image sensors also have the advantage of being able to integrate peripheral circuitry, such as signal processing circuits that process signals output from each pixel in the pixel array, on the same chip (substrate) as the pixel array. For this reason, CMOS image sensors have attracted attention, and much research and development is being conducted on them.

[0003] Furthermore, there is a technology for forming a P-type diffusion region on the sidewall of the through-trench to increase the saturated charge amount of the photodiode. However, in order to ensure the length L and width W of the pixel transistor, the P-type diffusion region may not be formed in the semiconductor region where the pixel transistor is located. This makes it possible to use the sidewall of the through-trench as the pixel transistor region, thereby improving area efficiency (see, for example, Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2020-13817

[0005] In the case of a pixel transistor having a function of directly transferring signal charges from a photodiode, electrons generated on the sidewall of the through-trench may flow into the photodiode, causing deterioration of dark characteristics.

[0006] The present technology aims to provide a photodetector and electronic device in which the influence of dark current is suppressed.

[0007] a semiconductor layer having a back surface and an element formation surface on one surface thereof, the semiconductor layer including a matrix of cell regions each including a photoelectric conversion region that is a semiconductor region of a first conductivity type; a separation wall disposed in a groove extending between the back surface and the element formation surface of the semiconductor layer and separating the cell regions from each other; and a first transistor and a second transistor disposed on the element formation surface side of the cell region, the first transistor having a transfer path that is a semiconductor region of the first conductivity type directly connected to the photoelectric conversion region; the second transistor being a transistor other than the first transistor, the first transistor being disposed at a position closer to the first separation wall than a center of the cell region in a planar view; the transfer path being disposed at a distance from the first separation wall; and the semiconductor region of the second transistor being in contact with the separation wall.

[0008] An electronic device according to an aspect of the present technology includes the light detection device and an optical system that forms an image light from a subject on the light detection device.

[0009] 11 is a chip layout diagram showing a configuration example of a photodetector according to a first embodiment of the present technology. FIG. 12 is a block diagram showing a configuration example of a photodetector according to a first embodiment of the present technology. FIG. 13 is an equivalent circuit diagram of a pixel of the photodetector according to the first embodiment of the present technology. FIG. 14 is a plan view showing an example of an arrangement of pixel transistors included in the photodetector according to the first embodiment of the present technology. FIG. 15 is a longitudinal sectional view showing a cross-sectional configuration when viewed in a plane along the A-A cutting line of FIG. 4. FIG. 16 is a plan view showing an example of an arrangement of pixel transistors included in a photodetector according to a first modified example of the first embodiment of the present technology. FIG. 17 is a longitudinal sectional view showing a cross-sectional configuration when viewed in a plane along the A-A cutting line of FIG. 6. FIG. 18 is a longitudinal sectional view showing a cross-sectional configuration when viewed in a plane along the B-B cutting line of FIG. 6. FIG. 19 is a plan view showing an example of an arrangement of pixel transistors included in a photodetector according to a second modified example of the present technology. FIG. 19 is a plan view showing an example of an arrangement of pixel transistors included in a photodetector according to a third modified example of the first embodiment of the present technology. FIG. 19 is a longitudinal sectional view showing a cross-sectional configuration when viewed in a plane along the A-A cutting line of FIG. 16 is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in a plane along the B-B cutting line of FIG. 11. FIG. 17 is a plan view showing an example of an arrangement of pixel transistors included in a photodetector according to a first modified example of the second embodiment of the present technology. FIG. 18 is a plan view showing an example of an arrangement of pixel transistors included in a photodetector according to a second modified example of the second embodiment of the present technology. FIG. 19 is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in a plane along the A-A cutting line of FIG. 16. FIG. 19 is a longitudinal cross-sectional view showing a cross-sectional configuration when viewed in a plane along the A-A cutting line of FIG. 16. FIG. 20 is a plan view showing an example of an arrangement of pixel transistors included in a photodetector according to a fifth modified example of the second embodiment of the present technology. FIG. 21 is a block diagram showing an example of a schematic configuration of an electronic device. FIG. 22 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 23 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0010] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0011] In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings include parts with different dimensional relationships and ratios. Furthermore, since drawings suitable for explaining the present technology are used, there may be differences in configuration between the drawings.

[0012] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] The description will be given in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment Application example to electronic devices Application example to mobile devices

[0015] First Embodiment In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0016] <Overall Configuration of Photodetection Device> First, the overall configuration of the photodetection device 1 will be described. As shown in Fig. 1 , the photodetection device 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape in a plan view. That is, the photodetection device 1 is mounted on the semiconductor chip 2. As shown in Fig. 21 , the photodetection device 1 captures image light (incident light 106) from a subject via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0017] As shown in FIG. 1, the semiconductor chip 2 on which the photodetector 1 is mounted includes, in a two-dimensional plane including an X direction and a Y direction that intersect with each other, a square-shaped pixel region 2A provided in the center, and a peripheral region 2B provided outside the pixel region 2A so as to surround the pixel region 2A.

[0018] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 21 . In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that intersect with each other within the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. Furthermore, the direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction, depth direction). Furthermore, the direction perpendicular to the Z direction is the horizontal direction.

[0019] 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0020] 2, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0021] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0022] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0023] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0024] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0025] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0026] <Pixel> Fig. 3 is an equivalent circuit diagram showing an example of the configuration of a pixel 3. In the equivalent circuit diagram shown in Fig. 3, the charge overflowing from the photodiode is configured to flow to the MIM capacitance element side rather than the FD section side, and two vertically arranged pixels 3 (pixels 3a and 3b) share a reset transistor and the like (hereinafter referred to as two-pixel sharing, as appropriate).

[0027] The pixel 3a includes a photoelectric conversion unit 151-1, a transfer transistor 152-1, a first FD unit 153, a conversion efficiency switching transistor 154, a second FD unit 155, a conversion efficiency switching transistor 156-1, a third FD unit 157-1, an MIM (Metal-Insulator-Metal) capacitance element 158-1, a reset transistor 159, an amplification transistor 160, a selection transistor 161, and an overflow transistor 162-1. The pixel 3b includes a photoelectric conversion unit 151-2, a transfer transistor 152-2, a conversion efficiency switching transistor 156-2, a third FD unit 157-2, an MIM capacitance element 158-2, and an overflow transistor 162-2. In the following description, for example, when it is not necessary to individually distinguish between the photoelectric conversion unit 151-1 and the photoelectric conversion unit 151-2, they will simply be referred to as the photoelectric conversion unit 151. The other parts are described in the same manner.

[0028] The first FD section 153, the conversion efficiency switching transistor 154, the second FD section 155, the reset transistor 159, the amplification transistor 160, and the selection transistor 161 are configured to be shared by the pixels 3a and 3b. For example, a plurality of drive lines are wired for each pixel row as pixel drive lines 10 for the pixels 3. Then, drive signals TG1, TG2, drive signals FDG, drive signals FCG1, FCG2, drive signals RST, drive signals SEL, drive signals OFG1, and drive signals OFG2 are supplied from the vertical drive circuit 4 via a plurality of drive lines to the transfer transistor 152-1, transfer transistor 152-2, conversion efficiency switching transistor 154, conversion efficiency switching transistor 156-1, conversion efficiency switching transistor 156-2, reset transistor 159, selection transistor 161, overflow transistor 162-1, and overflow transistor 162-2, respectively.

[0029] The photoelectric conversion unit 151 is made up of, for example, a PN junction photodiode, and receives incident light, performs photoelectric conversion, and accumulates the resulting electric charge.

[0030] The transfer transistor 152-1 constituting the pixel 3a is provided between the photoelectric conversion unit 151-1 and the first FD unit 153, and a drive signal TG1 is supplied to the gate electrode of the transfer transistor 152-1. Similarly, the transfer transistor 152-2 constituting the pixel 3b is provided between the photoelectric conversion unit 151-2 and the first FD unit 153, and a drive signal TG2 is supplied to the gate electrode of the transfer transistor 152-2.

[0031] When the drive signal TG goes high, the transfer transistor 152 is turned on, and the charge stored in the photoelectric conversion unit 151 is transferred to the first FD unit 153 via the transfer transistor 152 .

[0032] The first FD section 153, the second FD section 155, and the third FD section 157 are each a floating diffusion region called a floating diffusion, which accumulates transferred charges. The third FD section 157 is connected to an MIM capacitance element 158, which is configured to function as the third FD section 157. The conversion efficiency switching transistor 154 is provided between the first FD section 153 and the second FD section 155, and a drive signal FDG is supplied to the gate electrode of the conversion efficiency switching transistor 154. When this drive signal FDG becomes high level, the conversion efficiency switching transistor 154 is turned on, and charges from the first FD section 153 are transferred to the second FD section 155 via the conversion efficiency switching transistor 154.

[0033] The conversion efficiency switching transistor 156-1 constituting pixel 3a is provided between the second FD section 155 and the third FD section 157-1, and a drive signal FCG1 is supplied to the gate electrode of the conversion efficiency switching transistor 156-1. The conversion efficiency switching transistor 156-2 constituting pixel 3b is provided between the second FD section 155 and the third FD section 157-2, and a drive signal FCG2 is supplied to the gate electrode of the conversion efficiency switching transistor 156-2. When this drive signal FCG becomes high level, the conversion efficiency switching transistor 156 is turned on, and the charge accumulated in the third FD section 157 is read out. The third FD section 157-1 is connected to an MIM capacitance element 158-1, and the third FD section 157-2 is connected to an MIM capacitance element 158-2.

[0034] The overflow transistor 162-1 provided in pixel 3a is provided between the photoelectric conversion unit 151-1 and the third FD unit 157-1 (MIM capacitance element 158-1), and a drive signal OFG1 is supplied to the gate electrode of the overflow transistor 162-1. The overflow transistor 162-2 provided in pixel 3b is provided between the photoelectric conversion unit 151-2 and the third FD unit 157-2 (MIM capacitance element 158-2), and a drive signal OFG2 is supplied to the gate electrode of the overflow transistor 162-2.

[0035] The reset transistor 159 is connected between the power supply voltage VDD and the second FD section 155, and a drive signal RST is supplied to the gate electrode of the reset transistor 159. When the drive signal RST is set to a high level, the reset transistor 159 is turned on and the potential of the second FD section 155 is reset to the level of the power supply voltage VDD.

[0036] The amplification transistor 160 has a gate electrode connected to the first FD section 153 and a drain connected to a power supply voltage VDD, and serves as an input section of a readout circuit (a so-called source follower circuit) that reads out a signal corresponding to the charge held in the first FD section 153. The selection transistor 161 is connected between the source of the amplification transistor 160 and the vertical signal line 11, and a drive signal SEL is supplied to the gate electrode of the selection transistor 161. When the drive signal SEL is set to a high level, the selection transistor 161 is turned on, and pixel 3 a or pixel 3 b is placed in a selected state. As a result, the pixel signal output from the amplification transistor 160 is output to the vertical signal line 11 via the selection transistor 161.

[0037] In the pixel 3 shown in FIG. 3, an overflow transistor 162-1 is connected to the photoelectric conversion section 151-1 in addition to the transfer transistor 152-1 that transfers to the first FD section 153, and the charge that overflows the overflow transistor 162-1 is stored in the third FD section 157-1 (MIM capacitance element 158-1).

[0038] Similarly, an overflow transistor 162-2 is connected to the photoelectric conversion section 151-2 in addition to the transfer transistor 152-2 that transfers to the first FD section 153, and the charge that overflows the overflow transistor 162-2 is stored in the third FD section 157-2 (MIM capacitance element 158-2).

[0039] The overflow transistor 162 functions as an overflow gate (OFG) from the photoelectric conversion unit 151 .

[0040] Of the charges photoelectrically converted by the photoelectric conversion unit 151-1, the charges that do not overflow the overflow transistor 162-1 and are accumulated in the photoelectric conversion unit 151-1 are read out by the transfer transistor 152-1 to the first FD unit 153, just as in the case of two-pixel sharing in a normal CIS (CMOS Image Sensor). Similarly, of the charges photoelectrically converted by the photoelectric conversion unit 151-2, the charges that do not overflow the overflow transistor 162-2 and are accumulated in the photoelectric conversion unit 151-2 are read out by the transfer transistor 152-2 to the first FD unit 153.

[0041] The charge that has overflowed the overflow transistor 162 and accumulated in the MIM capacitance element 158 ​​is added to the charge in the first FD section 153 and the second FD section 155 and then read out. To read out the charge accumulated in the MIM capacitance element 158-1, first the conversion efficiency switching transistor 156-1 is turned off and the transfer transistor 152-1 is turned on, the charge in the photoelectric conversion section 151-1 is read out to the first FD section 153-1 and output to the vertical signal line 11 (VSL) via the amplification transistor 160. Thereafter, the conversion efficiency switching transistor 154 is turned on, and the charge accumulated in the first FD section 153 and the second FD section 155 is output to the vertical signal line 11 (VSL) via the amplification transistor 160.

[0042] Thereafter, the conversion efficiency switching transistor 156-1 is turned on, and the charge accumulated in the MIM capacitance element 158-1 is added to the first FD section 153 and the second FD section 155, and is output to the vertical signal line 11 (VSL) via the amplification transistor 160. The charge accumulated in the MIM capacitance element 158-2 is also read out by performing an operation similar to that described above.

[0043] <<Specific Configuration of Photodetector>> Next, a specific configuration of the photodetector 1 according to the first embodiment of the present technology will be described with reference to FIGS. 4 and 5 . FIG.

[0044] <<Layer Structure of the Photodetector>> Figure 5 is a longitudinal cross-sectional view showing the cross-sectional configuration when viewed in a plane along the A-A cutting line in Figure 4. As shown in Figure 5, the photodetector 1 has a semiconductor layer 20, for example, one surface of which is a first surface S1 and the other surface of which is a second surface S2. The first surface S1 may be referred to as the element formation surface or main surface, and the second surface S2 may be referred to as the light incidence surface or back surface. A multilayer wiring layer, in which wiring and gate electrodes of transistors are provided via an insulating film, is provided on the first surface S1 of the semiconductor layer 20, but is not shown in the figure. The second surface S2 is provided with, for example, a microlens LZ or the like.

[0045] The semiconductor layer 20 is made of a semiconductor substrate. The semiconductor layer 20 is made of, for example, a single-crystal silicon substrate, but is not limited thereto. The semiconductor layer 20 includes a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type. In this embodiment, a case will be described in which the first conductivity type is n-type and the second conductivity type is p-type. In the following description, a semiconductor region described as n-type corresponds to a semiconductor region of the first conductivity type, and a semiconductor region described as p-type corresponds to a semiconductor region of the second conductivity type. However, the present technology is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0046] In the portion of the semiconductor layer 20 corresponding to the pixel region 2A, a plurality of island-shaped cell regions 20a partitioned by isolation regions 20b are provided in a matrix. For example, one cell region 20a is provided for each pixel 3. The isolation region 20b is provided with an isolation wall 32 that separates the cell regions 20a from each other. The isolation wall 32 is formed by filling an isolation material into a groove 31 provided in the isolation region 20b across the second surface S2 and the first surface S1. The isolation wall 32 separates the cell regions 20a from each other. For example, silicon oxide (SiO ２ Examples of the isolation material include insulating materials such as silicon dioxide, silicon dioxide, and silicon dioxide. Examples of the isolation material include conductive materials such as polysilicon and metal. When the isolation material is made of a conductive material, the inner wall of the trench is first covered with an insulating film and then the conductive material is filled in.

[0047] The cell region 20a includes a photoelectric conversion region 21, a well region 22, a diffusion region 23, an FD portion (not shown), and the like. A plurality of transistors are configured on the first surface S1 side of the cell region 20a. The photoelectric conversion region 21 is an n-type semiconductor region. In the depth direction, the photoelectric conversion region 21 is located closer to the second surface S2, and an end portion 21a of the photoelectric conversion region 21 closer to the first surface S1 does not reach the first surface S1. The photodiode PD configured in the cell region 20a includes the photoelectric conversion region 21.

[0048] The well region 22 is a p-type semiconductor region, and is provided between an end 21a of the photoelectric conversion region 21 and the plurality of transistors in the depth direction.

[0049] The diffusion region 23 is a p++ type semiconductor region that is provided along the side surface of the isolation wall 32 and covers the side surface of the isolation wall 32. The diffusion region 23 is provided in the depth direction from the second surface S2 to the end 21a of the photoelectric conversion region 21, but does not reach the first surface S1. The diffusion region 23 is an example of a first diffusion region. The diffusion region 23 is formed by solid-phase diffusion or plasma doping.

[0050] 4 shows an example of the arrangement of multiple transistors provided on the first surface S1 side of the cell region 20a. Note that the FD section and other components are omitted in Fig. 4. The cell region 20a includes a transfer transistor 152, conversion efficiency switching transistors 154 and 156, a reset transistor 159, an amplifier transistor 160, a selection transistor 161, and an overflow transistor 162.

[0051] The cell region 20a is partitioned on the first surface S1 side by an isolation 40. The semiconductor region partitioned by the isolation 40 in a plan view is called an active region (device formation region) 24. The above-mentioned multiple transistors are provided in the active region 24. As shown in FIG. 5 , the isolation 40 is a shallow trench isolation (STI) formed by forming a trench 41 in the cell region 20a from the first surface S1 side and filling the trench 41 with an insulating material such as silicon oxide. The region in which the isolation 40 is provided in a plan view may also be called a field region. The dimension of the isolation 40 in the depth direction is smaller than the dimension of the isolation wall 32 in the depth direction.

[0052] The overflow transistor 162 is a first transistor having a transfer path 25, which is an n-type semiconductor region directly connected to the photoelectric conversion region 21. The transfer transistor 152 also has a transfer path 25, but this is not shown. The transfer path 25 extends in the depth direction from the first surface S1, and its end on the second surface S2 side is directly connected to the photoelectric conversion region 21. The transfer path 25 is used when extracting signal charges directly from the photoelectric conversion region 21. The transfer transistor 152 and the overflow transistor 162 are transistors having a transfer function of sending signal charges directly extracted from the photoelectric conversion region 21 via the transfer path 25 to a subsequent stage.

[0053] The transfer path 25 of the transfer transistor 152 is provided at a position overlapping the gate electrode TGL of the transfer transistor 152 in a planar view. The transfer path 25 of the overflow transistor 162 is provided at a position overlapping the gate electrode OFG of the overflow transistor 162 in a planar view. As shown in FIG. 5 , the transfer transistor 152 is provided in the center of the cell region 20a in a planar view, and the overflow transistor 162 is provided at a position closer to the isolation wall 32 than the center of the cell region 20a. More specifically, the overflow transistor 162 is provided at a position closer to one of the four isolation walls 32 (on the four sides) surrounding the cell region 20a. The isolation wall 32 adjacent to the overflow transistor 162 is referred to as the first isolation wall 32a to distinguish it from the other isolation walls 32. When the first isolation wall 32a is not distinguished from the other isolation walls 32, it is simply referred to as the isolation wall 32.

[0054] As shown in FIG. 5 , the transfer path 25 of the overflow transistor 162 is spaced apart from the first isolation wall 32a. Between the transfer path 25 and the first isolation wall 32a, an isolation 40 is interposed, extending from the first surface S1 in the depth direction. In the depth direction, the end of the isolation 40 closer to the second surface S2 is closer to the first surface S1 than the end of the transfer path 25 closer to the second surface S2. More specifically, between the transfer path 25 and the first isolation wall 32a, the isolation 40 and a well region 22 contacting the end of the isolation 40 closer to the second surface S2 are interposed. The diffusion region 23 contacts the end of the well region 22 closer to the second surface S2. The transfer path 25 of the transfer transistor 152 is located in the center of the cell region 20a in a plan view, and is therefore spaced apart from the isolation walls 32 on all four sides.

[0055] Transistors other than the transfer transistor 152 and the overflow transistor 162 do not have a transfer path 25 and do not extract signal charges directly from the photoelectric conversion region 21. Such transistors are referred to as second transistors. As shown in FIG. 4 , the second transistors include, for example, the conversion efficiency switching transistors 154 and 156, the reset transistor 159, the amplification transistor 160, and the selection transistor 161. Hereinafter, the selection transistor 161 will be described as an example of the second transistor. As shown in FIG. 5 , a well region 22 is provided between the selection transistor 161 and the photoelectric conversion region 21. More specifically, the well region 22 is provided between the semiconductor region 26 of the selection transistor 161 and the photoelectric conversion region 21. The semiconductor region 26 of the selection transistor 161 is a region of the semiconductor layer 20 occupied by the selection transistor 161. More specifically, it is a semiconductor region of the semiconductor layer 20 in which a pair of main electrode regions (source region and drain region) and a channel formation region of the selection transistor 161 are configured. The semiconductor region of the select transistor 161 being in contact with the isolation wall 32 means that at least one of the source region, drain region, and channel formation region is in contact with the isolation wall 32. In the depth direction, the end of the semiconductor region 26 closer to the second surface S2 is closer to the first surface S1 than the end of the element isolation 40 closer to the second surface S2. The semiconductor region 26 of the select transistor 161 is in contact with the isolation wall 32. The semiconductor regions 26 of all the second transistors are in contact with the isolation wall 32. The second transistors are reset immediately before use to remove electrons generated on the processed surface of the semiconductor layer 20, so that they are less susceptible to the effects of dark current even when in contact with the isolation wall 32.

[0056] The isolation wall 32 functions as an element isolation wall in addition to functioning as an inter-pixel isolation wall. The isolation wall 32 may be referred to as a first element isolation 32, and the element isolation 40 may be referred to as a second element isolation 40. As shown in FIG. 4 , the transfer transistor 152 and the overflow transistor 162 are defined only by the second element isolation 40 of the first element isolation 32 and the second element isolation 40. The conversion efficiency switching transistors 154 and 156, the reset transistor 159, the amplification transistor 160, and the selection transistor 161 are defined by both the first element isolation 32 and the second element isolation 40.

[0057] Main Effects of the First Embodiment The main effects of the first embodiment are described below. In the photodetector 1 according to the first embodiment of the present technology, the first transistor (overflow transistor 162) is a transistor having a transfer path 25, which is a semiconductor region of a first conductivity type directly connected to the photoelectric conversion region 21. The first transistor is located closer to the first isolation wall 32a of the isolation wall 32 than the center of the cell region 20a in a plan view. The transfer path 25 is located at a distance from the first isolation wall 32a. The semiconductor region of a second transistor, which is a transistor other than the first transistor, is in contact with the isolation wall 32. Because the transfer path 25 is not in contact with the isolation wall 32, electrons generated at the interface between the semiconductor layer 20 and the isolation wall 32 are less likely to flow into the transfer path 25. This makes it possible to prevent electrons generated at the interface between the semiconductor layer 20 and the isolation wall 32 from flowing along the transfer path 25 to the photoelectric conversion region 21. Furthermore, the semiconductor region of the second transistor that does not have the transfer path 25 is in contact with the separation wall 32, with no gap between it and the separation wall 32. This makes it possible to install the second transistor right up to the edge of the separation wall 32, and the second transistor can be provided while effectively utilizing the area on the first surface S1 side of the cell region 20a.

[0058] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the semiconductor regions of all the second transistors are in contact with the separation wall 32. This allows the second transistors to be provided while effectively utilizing the area on the first surface S1 side of the cell region 20 a.

[0059] Furthermore, the photodetector 1 according to the first embodiment of the present technology has a diffusion region 23 provided so as to cover the side surface of the separation wall 32, and the diffusion region 23 is provided in the depth direction from the second surface S2 to an end 21a of the photoelectric conversion region 21 closer to the first surface S1. In the depth direction, a p-type well region 22 is interposed between the diffusion region 23 and an active region 24 in which a second transistor such as the conversion efficiency switching transistor 156 is provided. Therefore, the semiconductor region occupied by the second transistor such as the conversion efficiency switching transistor 156 is not in contact with the diffusion region 23. This makes it possible to suppress the generation of a strong electric field between the n-type semiconductor region of the transistor and the p++-type diffusion region 23, thereby suppressing deterioration of the transistor characteristics.

[0060] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, an element isolation 40 made of an insulating material is interposed between the transfer path 25 and the first separation wall 32a, extending from the first surface S1 side along the depth direction, and in the depth direction, the end of the element isolation 40 closer to the second surface S2 is closer to the first surface S1 than the end of the transfer path 25 closer to the second surface S2. In this way, since the element isolation 40 is provided between the transfer path 25 and the first separation wall 32a, the transfer path 25 and the first separation wall 32a can be more reliably separated from each other. Furthermore, since only a portion of the side surface of the transfer path 25 on the first separation wall 32a side comes into contact with the element isolation 40, the area in contact with the processed surface of the semiconductor can be reduced, and the influence of dark current can be suppressed.

[0061] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, when the area of ​​the pixel 3 is reduced through miniaturization, it may be difficult in terms of layout to provide both the transfer transistor 152 and the overflow transistor 162 in the center of the cell region 20 a in plan view. Even in such cases, dark current can be suppressed.

[0062] <Modification of First Embodiment> Modifications of the first embodiment will be described below.

[0063] <Modification 1> In a photodetector 1 according to Modification 1 of the first embodiment, the transfer transistor 152 is the first transistor, as shown in Fig. 6 to Fig. 8. Fig. 7 is a longitudinal sectional view showing the cross-sectional configuration when viewed in a plane along the A-A cutting line in Fig. 6. Fig. 8 is a longitudinal sectional view showing the cross-sectional configuration when viewed in a plane along the B-B cutting line in Fig. 6.

[0064] As shown in Figure 6, the cell region 20a is divided into multiple regions by separation walls 32b. Of the divided regions, the larger region is called region X and the smaller region is called region Y. In a plan view, the cell region 20a is quadrangular (square or rectangular) and has a first corner 33 and a second corner 34 that are diagonally opposite each other. Region X is the region closer to the first corner 33. Region Y is the region closer to the second corner 34.

[0065] The photoelectric conversion region 21 includes, for each cell region 20a, a first photoelectric conversion region 211 and a second photoelectric conversion region 212 that can photoelectrically convert a smaller amount of signal charge per unit time than the first photoelectric conversion region 211. When the first photoelectric conversion region 211 and the second photoelectric conversion region 212 are not distinguished from each other, they are simply referred to as photoelectric conversion regions 21. The first photoelectric conversion region 211 is provided in region X and is located closer to the first corner 33 of the first corner 33 and the second corner 34 in a planar view. The second photoelectric conversion region 212 is provided in region Y and is located closer to the second corner 34 of the first corner 33 and the second corner 34 in a planar view.

[0066] The first separation wall 32a is two sides of the separation wall 32 that intersect at the first corner 33 in a plan view. The transfer transistor 152 is provided at a position closer to the first corner 33. As shown in FIGS. 7 and 8 , the transfer path 25 of the transfer transistor 152 is directly connected to the first photoelectric conversion region 211. The transfer path 25 of the transfer transistor 152 is provided at a distance from the first separation wall 32a that constitutes the first corner 33 in a plan view. An element isolation 40 is interposed between the transfer path 25 and the first separation wall 32a.

[0067] The photodetector 1 according to the first modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0068] 9 , in the photodetector 1 according to the second modification of the first embodiment, the element isolation 40 interposed between the transfer path 25 and the first isolation wall 32a is provided along the first isolation wall 32a over the entire extension direction of the first isolation wall 32a in a plan view. Some of the second transistors are provided closer to the first isolation wall 32a in a plan view, and the element isolation 40 is provided between the first isolation wall 32a and the semiconductor region of the second transistor provided closer to the first isolation wall 32a. In this embodiment, the second transistor provided closer to the first isolation wall 32a is a conversion efficiency switching transistor 156.

[0069] The photodetector 1 according to the second modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0070] Furthermore, in the photodetector 1 according to the second modification of the first embodiment, the element isolation 40 interposed between the transfer path 25 and the first separation wall 32a is provided along the first separation wall 32a over the entire extension direction of the first separation wall 32a in a plan view. Forming the element isolation 40 in this manner facilitates the manufacturing method of the element isolation 40. More specifically, compared to when there are regions along the first separation wall 32a where the element isolation 40 is provided and regions where it is not provided, providing the element isolation 40 over the entire extension direction of the first separation wall 32a can reduce the burden of lithography technology, etching technology, and the like, and can also accommodate miniaturization of the pixels 3.

[0071] <Modification 3> In the photodetector 1 according to Modification 3 of the first embodiment, as shown in FIG. 10 , the semiconductor regions of all the transfer paths 25 and all the second transistors are provided with an element isolation 40 between them and the isolation wall 32.

[0072] In the photodetector 1 according to the third modification of the first embodiment, all the transistors are provided with the isolation 40 between them and the isolation wall 32, so that the influence of dark current can be suppressed.

[0073] 11 to 13, a second embodiment of the present technology will be described below. The photodetector 1 according to the second embodiment differs from the photodetector 1 according to the first embodiment in that an isolation diffusion region 50 is interposed between the transfer path 25 and the first isolation wall 32a. In this embodiment, no element isolation 40 is interposed between the transfer path 25 and the first isolation wall 32a.

[0074] As shown in FIG. 12 , an isolation diffusion region 50 extending from the first surface S1 side along the depth direction is interposed between the transfer path 25 and the first isolation wall 32a. The isolation diffusion region 50 is provided along the depth direction over the entire area between the transfer path 25 and the first isolation wall 32a. The isolation diffusion region 50 is a p-type semiconductor region and is formed by ion implanting impurities into the region R1 shown in FIG. 11 . In this embodiment, the isolation diffusion region 50 is formed by ion implanting a known impurity that converts the semiconductor to p-type into the region R1. The region R1 corresponds to an opening in a mask pattern for ion implantation. The concentration of the impurity that converts the semiconductor to p-type is higher in the isolation diffusion region 50 than in the well region 22. The concentration of the impurity that converts the semiconductor to p-type may be the same or different between the isolation diffusion region 50 and the diffusion region 23.

[0075] 12, it is desirable that the width (horizontal dimension) of the isolation diffusion region 50 be equal to or smaller than the width of the diffusion region 23. This is because the larger the width of the isolation diffusion region 50, the smaller the region in which the transistor is provided.

[0076] As shown in FIGS. 12 and 13, the second transistors such as the selection transistor 161, the amplification transistor 160, and the conversion efficiency switching transistor 156 do not have the transfer path 25.

[0077] <<Main Effects of Second Embodiment>> The main effects of the second embodiment will be described below. The photodetector 1 according to the second embodiment also provides the same effects as the photodetector 1 according to the first embodiment.

[0078] Furthermore, in the photodetector 1 according to the second embodiment of the present technology, the isolation diffusion region 50 is provided so as to cover as much of the side surface of the transfer path 25 on the first isolation wall 32a side as possible, thereby suppressing the influence of dark current.

[0079] <Modification of Second Embodiment> A modification of the second embodiment will now be described.

[0080] <Modification 1> In a photodetector 1 according to Modification 1 of the second embodiment shown in Figure 14, the isolation diffusion region 50 is provided along the first separation wall 32a in the entire extension direction of the first separation wall 32a in plan view. The isolation diffusion region 50 is formed by ion implanting impurities into region R2 shown in Figure 14. Some of the second transistors are provided closer to the first separation wall 32a in plan view, and the isolation diffusion region 50 is interposed between the first separation wall 32a and the semiconductor region of the second transistor provided closer to the first separation wall 32a. In this embodiment, the second transistor provided closer to the first separation wall 32a is a conversion efficiency switching transistor 156.

[0081] The photodetector 1 according to the first modified example of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0082] Furthermore, in the photo-detecting device 1 according to the first modification of the second embodiment, the isolation diffusion region 50 interposed between the transfer path 25 and the first separation wall 32a is provided along the first separation wall 32a over the entire extension direction of the first separation wall 32a in a plan view. Forming the isolation diffusion region 50 in this manner facilitates the manufacturing method of the isolation diffusion region 50. More specifically, compared to when there are regions along the first separation wall 32a where the isolation diffusion region 50 is provided and regions where it is not provided, providing the isolation diffusion region 50 over the entire extension direction of the first separation wall 32a can reduce the burden of lithography techniques for forming a mask pattern for ion implantation and can also accommodate miniaturization of the pixels 3.

[0083] <Modification 2> In a photodetector 1 according to Modification 2 of the second embodiment, as shown in FIG. 15 , two adjacent cell regions 20a share a first isolation wall 32a. More specifically, the two cell regions 20a are adjacent to each other across the first isolation wall 32a to form a pair. The first and second transistors included in one of the pair of adjacent cell regions 20a are arranged symmetrically with respect to the first isolation wall 32a with respect to the other cell region 20a. As a result, the first transistors are arranged on both sides of the first isolation wall 32a. In this embodiment, the overflow transistors 162, which are the first transistors, are located on both sides of the first isolation wall 32a in a plan view, so that the isolation diffusion regions 50 are formed by simultaneously implanting impurities into both sides. More specifically, the isolation diffusion regions 50 are formed by implanting impurities into region R3. Region R3 corresponds to an opening in a mask pattern for ion implantation. The region R3 straddles the first separation wall 32a, extends on both sides of the first separation wall 32a, and extends over the entire extension direction of the first separation wall 32a.

[0084] Even with the photodetector 1 according to variant 2 of the second embodiment, the same effects as those of the photodetector 1 according to the second embodiment described above and the photodetector 1 according to variant 1 of the second embodiment described above can be obtained.

[0085] Furthermore, in the photodetector 1 according to the second modification of the second embodiment, the width of the isolation diffusion region 50 can be changed by adjusting the overlapping area between the region R3 and the cell region 20a. More specifically, because the region R3 straddles the first isolation wall 32a, it is possible to reduce the overlapping area between the region R3 and the cell region 20a while maintaining a relatively large width. This reduces the burden of reducing the dimensions of the region R3, which is the opening of the mask pattern. This allows the width of the isolation diffusion region 50 to be reduced even when the pixel 3 is further miniaturized.

[0086] <Modification 3> In a photodetector 1 according to Modification 3 of the second embodiment, two overflow transistors 162 on both sides of a first separation wall 32 a share one gate electrode, as shown in Figures 16 and 17. Note that the shared gate electrode may be partially embedded in the first separation wall 32 a, as shown in Figure 18.

[0087] The photodetector 1 according to this modified example 3 of the second embodiment can also achieve the same effects as the photodetector 1 according to the second embodiment described above and the photodetector 1 according to modified example 2 of the second embodiment.

[0088] 19 , a photodetector 1 according to a fourth modification of the second embodiment has a set of four cell regions 20 a arranged in two rows and two columns, with the first isolation wall 32 a arranged so as to pass through the center of the set and extend continuously along the row or column direction, and the first transistor and the second transistor are arranged point-symmetrically with respect to the center of each set of cell regions 20 a. The overflow transistor, which is the first transistor, is located toward the center of each set of cell regions 20 a. The isolation diffusion region 50 is formed by ion implanting impurities into region R4.

[0089] The photodetector 1 according to the fourth modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0090] <Modification 5> In a photodetector 1 according to Modification 5 of the second embodiment, as shown in FIG. 20, an isolation 40 is provided between the isolation diffusion region 50 and the first isolation wall 32a.

[0091] The photodetector 1 according to the fifth modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0092] [Third Embodiment] <1. Application Example to Electronic Device> Next, an electronic device 100 according to a third embodiment of the present technology shown in Fig. 21 will be described. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-described photodetector device 1 as the solid-state imaging device 101.

[0093] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transfer from the solid-state imaging device 101 is performed in accordance with the drive signal (timing signal) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0094] With this configuration, the electronic device 100 can suppress the influence of dark current in the solid-state imaging device 101, thereby improving the image quality of the video signal.

[0095] The electronic device 100 is not limited to a camera, but may be other electronic devices, such as an imaging device such as a camera module for a mobile device such as a mobile phone.

[0096] Furthermore, the electronic device 100 can be provided with, as the solid-state imaging device 101, a photodetector 1 relating to any of the first embodiment to the second embodiment and modified versions of those embodiments, or a photodetector 1 relating to a combination of at least two of the first embodiment to the second embodiment and modified versions of those embodiments.

[0097] 2. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0098] FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0099] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 22, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0100] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0101] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0102] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0103] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0104] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0105] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0106] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0107] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0108] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 22, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0109] FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031.

[0110] In FIG. 23, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0111] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0112] 23 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0113] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0114] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0115] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0116] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0117] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, the above-described light detection device 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0118] [Other Embodiments] As described above, the present technology has been described by the first to third embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0119] For example, it is possible to combine the technical ideas described in the first to third embodiments.

[0120] Furthermore, the present technology can be applied to a general photodetection device, including not only the solid-state imaging device as the image sensor described above but also a distance measurement sensor that measures distance, also known as a ToF (Time of Flight) sensor. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until when the reflected light is received. The structure of the pixel 3 described above can be adopted as the structure of this distance measurement sensor.

[0121] Furthermore, for example, the materials cited as constituting the above-mentioned components may contain additives, impurities, and the like.

[0122] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0123] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0124] Note that the present technology may be configured as follows: (1) A photodetector comprising: a semiconductor layer having one surface serving as a back surface and the other surface serving as an element formation surface, the semiconductor layer including a plurality of cell regions arranged in a matrix, the cell regions including photoelectric conversion regions that are semiconductor regions of a first conductivity type; a separation wall provided in a groove extending between the back surface and the element formation surface of the semiconductor layer and separating the cell regions; and a first transistor and a second transistor provided on the element formation surface side of the cell region, wherein the first transistor is a transistor having a transfer path that is a semiconductor region of the first conductivity type directly connected to the photoelectric conversion region, the second transistor is a transistor other than the first transistor, the first transistor is provided at a position closer to the first separation wall than a center of the cell region in a plan view, the transfer path is provided with a gap between the first separation wall and the first transistor, and the semiconductor region of the second transistor is in contact with the separation wall. (2) The photodetector according to (1), wherein the semiconductor regions of all of the second transistors are in contact with the separation wall. (3) The photodetector according to (1) or (2), wherein the transfer path is provided at a position overlapping with the gate electrode of the first transistor in a plan view. (4) The photodetector according to any of (1) to (3), wherein the first transistor is also provided in the central part of the cell region, the first transistor provided in the central part is a transfer transistor, and the first transistor provided at a position closer to the first isolation wall is an overflow transistor. (5) The photodetector according to any of (1) to (3), wherein the cell region is a rectangle having four corners in a plan view, the first isolation wall is the isolation wall that intersects with the first isolation wall at a first corner that is one of the four corners, and the first transistor is a transfer transistor. (6) A photodetector device described in any one of (1) to (5), wherein an element isolation made of an insulating material is interposed between the transfer path and the first isolation wall, extending in a depth direction from the element formation surface side, and in the depth direction, an end of the element isolation closer to the back surface is closer to the element formation surface than an end of the transfer path closer to the back surface.(7) The photodetector according to (6), wherein the element isolation is provided over the entire extension direction of the first isolation wall in plan view. (8) The photodetector according to (7), wherein some of the second transistors are provided closer to the first isolation wall in plan view, and the element isolation is interposed between the first isolation wall and a semiconductor region of the second transistor provided closer to the first isolation wall. (9) The photodetector according to (8), wherein the second transistor provided closer to the first isolation wall is a conversion efficiency switching transistor. (10) The photodetector according to any of (6) to (9), wherein the element isolation and a well region in contact with an end of the element isolation closer to the back surface are interposed between the transfer path and the first isolation wall, and the well region is a semiconductor region of a second conductivity type. (11) The photodetector according to any one of (6) to (10), wherein the isolation wall functions as a first element isolation and the element isolation is a second element isolation, wherein the first transistor is defined by only the second element isolation of the first element isolation and the second element isolation, and wherein the second transistor is defined by both the first element isolation and the second element isolation. (12) The photodetector according to any one of (6) to (11), wherein a dimension of the element isolation along the depth direction is smaller than a dimension of the isolation wall along the depth direction. (13) The photodetector according to (1), wherein an isolation diffusion region that is a semiconductor region of a second conductivity type extending along the depth direction from the element formation surface side is interposed between the transfer path and the first isolation wall. (14) The photodetector according to (13), wherein the isolation diffusion region is provided along the depth direction over the entire area between the transfer path and the first isolation wall. (15) The photodetector according to (13) or (14), wherein the isolation diffusion region is provided over the entire extension direction of the first isolation wall in a plan view. (16) The photodetector according to (15), wherein some of the second transistors are provided closer to the first isolation wall in a plan view, and the isolation diffusion region is interposed between the first isolation wall and a semiconductor region of the second transistor provided closer to the first isolation wall.(17) The photodetector according to (15), comprising two sets of the cell regions adjacent to each other with the first separation wall in between, wherein the first transistor and the second transistor included in one of the cell regions of the set are arranged in line symmetry with the first transistor and the second transistor included in the other cell region with respect to the first separation wall. (18) The photodetector according to any of (13) to (16), comprising sets of four of the cell regions arranged in two rows and two columns, wherein the first separation wall is arranged so as to pass through the center of the set and to be continuous in an extending direction along the row direction or the column direction, wherein the first transistor and the second transistor are arranged so as to be point symmetric with respect to the center of the set for each of the cell regions, and wherein the first transistor is located closer to the center of the set for each of the cell regions. (19) The photodetector according to any of (13) to (18), wherein an element isolation made of an insulating material is provided between the isolation diffusion region and the first separation wall. (20) The photodetector according to any one of (13) to (19), wherein a well region that is a semiconductor region of a second conductivity type is provided between the semiconductor region of the second transistor and the photoelectric conversion region in the depth direction, and the concentration of an impurity that converts the semiconductor to the second conductivity type is higher in the isolation diffusion region than in the well region. (21) The photodetector according to any one of (1) to (20), wherein the first transistor is a transfer transistor or an overflow transistor. (22) The photodetector according to any one of (1) to (21), wherein the second transistor is an amplification transistor, a reset transistor, a conversion efficiency switching transistor, or a selection transistor. (23) The photodetector according to any one of (1) to (23), wherein the photodetector has a first diffusion region that is a semiconductor region of the second conductivity type and is provided along a side surface of the isolation wall in the depth direction from the back surface to an end of the photoelectric conversion region closer to the element formation surface. (24) The photodetector according to (23), wherein the first diffusion region is formed by solid-phase diffusion or plasma doping.(25) A photodetector comprising: a semiconductor layer having one surface serving as a back surface and the other surface serving as an element formation surface, the semiconductor layer having a plurality of cell regions arranged in a matrix, the cell regions including photoelectric conversion regions which are semiconductor regions of a first conductivity type; an isolation wall provided in a groove extending between the back surface of the semiconductor layer and the element formation surface and separating the cell regions; a first transistor and a second transistor provided on the element formation surface side of the cell region; and an isolation made of an insulating material extending from the element formation surface side along a depth direction, wherein the first transistor is a transistor having a transfer path which is a diffusion region of the first conductivity type directly connected to the photoelectric conversion region, the second transistor is a transistor other than the first transistor, and the semiconductor regions of all the transfer paths and all the second transistors are provided between them and the isolation wall via the isolation. (26) The photodetector according to (25), wherein a dimension along the depth direction of the isolation is smaller than a dimension along the depth direction of the isolation wall. (27) The photodetector according to (25) or (26), wherein the first transistor is a transfer transistor or an overflow transistor. (28) The photodetector according to any one of (25) to (27), wherein the second transistor is an amplification transistor, a reset transistor, a conversion efficiency switching transistor, or a selection transistor. (29) The photodetector according to any one of (25) to (28), wherein the photodetector has a first diffusion region that is a semiconductor region of a second conductivity type and is provided along a side surface of the separation wall in a depth direction from the back surface to an end of the photoelectric conversion region closer to the element formation surface. (30) The photodetector according to (29), wherein the first diffusion region is formed by solid-phase diffusion or plasma doping.(31) An electronic device comprising: a photodetector; and an optical system that forms an image light from a subject on the photodetector; wherein the photodetector comprises: a semiconductor layer having one surface that is a back surface and the other surface that is an element formation surface, and having a plurality of cell regions arranged in a matrix, each cell region including a photoelectric conversion region that is a semiconductor region of a first conductivity type; a separation wall that is provided in a groove extending between the back surface and the element formation surface of the semiconductor layer and separates the cell regions; and a first transistor and a second transistor that are provided on the element formation surface side of the cell region, wherein the first transistor is a transistor having a transfer path that is a semiconductor region of the first conductivity type directly connected to the photoelectric conversion region; the second transistor is a transistor other than the first transistor; the first transistor is provided at a position closer to the first separation wall than a center of the cell region in a plan view, and the transfer path is provided with a gap between it and the first separation wall; and the semiconductor region of the second transistor is in contact with the separation wall.

[0125] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0126] REFERENCE SIGNS LIST 1 Photodetector 20 Semiconductor layer 20a Cell region 21 Photoelectric conversion region 21a End 22 Well region 23 Diffusion region 25 Transfer path 26 Semiconductor region 31 Groove 32 Isolation wall (first element isolation) 32a First isolation wall 33 First corner 40 Element isolation (second element isolation) 41 Groove 50 Isolation diffusion region 102 Optical system 152 Transfer transistor (first transistor) 154, 156 Conversion efficiency switching transistor (second transistor) 159 Reset transistor (second transistor) 160 Amplification transistor (second transistor) 161 Selection transistor (second transistor) 162 Overflow transistor (first transistor)

Claims

1. A photodetector comprising: a semiconductor layer having a plurality of cell regions including a photoelectric conversion region which is a semiconductor region of a first conductivity type with one surface being a back surface and the other surface being an element formation surface, arranged in a matrix; a separation wall provided in a groove extending between the back surface and the element formation surface of the semiconductor layer and separating between the cell regions; a first transistor and a second transistor provided on the element formation surface side of the cell region, wherein the first transistor is a transistor having a transfer path which is a semiconductor region of a first conductivity type directly connected to the photoelectric conversion region, the second transistor is a transistor other than the first transistor, the first transistor is provided at a position closer to a first separation wall among the separation walls than the central part of the cell region in plan view, the transfer path is provided with a space from the first separation wall, and the semiconductor region of the second transistor is in contact with the separation wall.

2. The photodetector according to claim 1, wherein semiconductor regions of all the second transistors are in contact with the separation wall.

3. The photodetector according to claim 1, wherein the transfer path is provided at a position overlapping the gate electrode of the first transistor in plan view.

4. The first transistor is also provided at the central part of the cell region, the first transistor provided at the central part is a transfer transistor, and the first transistor provided at a position closer to the first separation wall is an overflow transistor. The photodetector according to claim 1.

5. In plan view, the cell region is square having four corners, the first separation wall is the separation wall intersecting at a first corner which is one of the four corners of the separation walls, and the first transistor is a transfer transistor. The photodetector according to claim 1.

6. An element isolation made of an insulating material extending along the depth direction from the element formation surface side is interposed between the transfer path and the first separation wall, and in the depth direction, an end portion of the element isolation closer to the back surface is closer to the element formation surface than an end portion of the transfer path closer to the back surface. The photodetector according to claim 1.

7. The photodetector according to claim 6, wherein the element isolation is provided over the entire extending direction of the first separation wall in plan view.

8. Some of the second transistors are provided at positions closer to the first isolation wall in a plan view, and element isolation is interposed between the semiconductor region of the second transistor provided at the position closer to the first isolation wall and the first isolation wall. The photodetection device according to claim 7.

9. The second transistor provided at the position closer to the first isolation wall is a conversion efficiency switching transistor. The photodetection device according to claim 8.

10. Element isolation and a well region in contact with an end portion closer to the back surface of the element isolation are interposed between the transfer path and the first isolation wall. The well region is a semiconductor region of a second conductivity type. The photodetection device according to claim 6.

11. The isolation wall functions as a first element isolation, the element isolation is a second element isolation, the first transistor is defined only by the second element isolation of the first element isolation and the second element isolation, and the second transistor is defined by both the first element isolation and the second element isolation. The photodetection device according to claim 6.

12. The dimension along the depth direction of the element isolation is smaller than the dimension along the depth direction of the isolation wall. The photodetection device according to claim 6.

13. A separation diffusion region, which is a semiconductor region of a second conductivity type extending along the depth direction from the element formation surface side, is interposed between the transfer path and the first isolation wall. The photodetection device according to claim 1.

14. The separation diffusion region is provided over the entire area between the transfer path and the first isolation wall along the depth direction. The photodetection device according to claim 13.

15. The separation diffusion region is provided over the entire extending direction of the first isolation wall in a plan view. The photodetection device according to claim 13.

16. Some of the second transistors are provided at positions closer to the first isolation wall in a plan view, and the separation diffusion region is interposed between the semiconductor region of the second transistor provided at the position closer to the first isolation wall and the first isolation wall. The photodetection device according to claim 15.

17. Having a pair of two adjacent cell regions separated by the first separation wall, the first transistor and the second transistor included in one of the cell regions in the pair are arranged symmetrically with respect to the first separation wall with the first transistor and the second transistor included in the other cell region in the pair, the photodetection device according to claim 15.

18. Having a set of four cell regions arranged in two rows and two columns, the first separation wall is arranged so as to pass through the center of the set and be continuous in the extending direction along the row direction or the column direction, the first transistor and the second transistor are arranged so as to be point-symmetric with respect to the center of the set for each cell region, and the first transistor is located closer to the center of the set for each cell region, the photodetection device according to claim 13.

19. An element isolation made of an insulating material is provided between the separation diffusion region and the first separation wall, the photodetection device according to claim 13.

20. In the depth direction, a well region which is a semiconductor region of a second conductivity type is provided between the semiconductor region of the second transistor and the photoelectric conversion region, and the concentration of the impurity for making the semiconductor of the second conductivity type is higher in the separation diffusion region than in the well region, the photodetection device according to claim 13.

21. The first transistor is a transfer transistor or an overflow transistor, the photodetection device according to claim 1.

22. The second transistor is an amplification transistor, a reset transistor, a conversion efficiency switching transistor, or a selection transistor, the photodetection device according to claim 1.

23. Having a first diffusion region which is a semiconductor region of a second conductivity type and is provided along the side surface of the separation wall from the back surface in the depth direction to an end portion closer to the element formation surface of the photoelectric conversion region, the photodetection device according to claim 1.

24. The first diffusion region is formed by solid-phase diffusion or plasma doping, the photodetection device according to claim 23.

25. A semiconductor layer having a plurality of cell regions including a photoelectric conversion region which is a semiconductor region of a first conductivity type, one surface thereof being a back surface and the other surface being an element formation surface, arranged in a matrix; a separation wall provided in a groove extending between the back surface and the element formation surface of the semiconductor layer and separating between the cell regions; a first transistor and a second transistor provided on the element formation surface side of the cell region; and an element isolation made of an insulating material extending along the depth direction from the element formation surface side. The first transistor is a transistor having a transfer path which is a diffusion region of the first conductivity type directly connected to the photoelectric conversion region. The second transistor is a transistor other than the first transistor. All the transfer paths and the semiconductor regions of all the second transistors are provided via the element isolation with respect to the separation wall. A photodetector device.

26. The photodetector device according to claim 25, wherein a dimension along the depth direction of the element isolation is smaller than a dimension along the depth direction of the separation wall.

27. The photodetector device according to claim 25, wherein the first transistor is a transfer transistor or an overflow transistor.

28. The photodetector device according to claim 25, wherein the second transistor is an amplification transistor, a reset transistor, a conversion efficiency switching transistor, or a selection transistor.

29. The photodetector device according to claim 25, having a first diffusion region which is a semiconductor region of a second conductivity type and is provided along the side surface of the separation wall from the back surface to an end portion near the element formation surface of the photoelectric conversion region in the depth direction.

30. The photodetector device according to claim 29, wherein the first diffusion region is formed by solid-phase diffusion or plasma doping.

31. An electronic device includes an optical detection device and an optical system that forms an image of subject light on the optical detection device. The optical detection device includes a semiconductor layer having a plurality of cell regions including a photoelectric conversion region, which is a semiconductor region of a first conductivity type, arranged in a matrix, with one surface being a back surface and the other surface being an element formation surface; a separation wall provided in a groove extending between the back surface and the element formation surface of the semiconductor layer and separating between the cell regions; a first transistor and a second transistor provided on the element formation surface side of the cell regions. The first transistor is a transistor having a transfer path, which is a semiconductor region of the first conductivity type directly connected to the photoelectric conversion region. The second transistor is a transistor other than the first transistor. The first transistor is provided, in a plan view, at a position closer to a first separation wall among the separation walls than the central portion of the cell region, and the transfer path is provided with a gap from the first separation wall. The semiconductor region of the second transistor is in contact with the separation wall.

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