Light detection device and electronic apparatus

Abstract

The present invention improves image quality. This light detection device is provided with: a semiconductor layer having a first surface part and a second surface part positioned on mutually opposite sides in one direction; a separation region including a dug part extending from the first surface part side toward the second surface part side of the semiconductor layer; a photoelectric conversion region demarcated by the separation region and provided in the semiconductor layer; a photoelectric conversion part including a first conductivity type first semiconductor region separated from the separation region and the first surface part of the semiconductor layer and provided in the photoelectric conversion region; a first conductivity type second semiconductor region provided on the photoelectric conversion region side between the separation region and the first semiconductor region; and a second conductivity type third semiconductor region provided in the photoelectric conversion region between the first semiconductor region and the second semiconductor region. The second semiconductor region is connected to a conductor to which a potential is applied.

Description

Photodetector and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to a photodetector and an electronic device, and in particular to a technology that is effective when applied to a photodetector and an electronic device having a photoelectric conversion region partitioned by a recessed isolation region.

[0002] In photodetection devices such as distance measuring devices and solid-state imaging devices, a photoelectric conversion region in a semiconductor layer is partitioned by an isolation region. Patent Document 1 discloses an example of such an isolation region, a recessed isolation region in which a recessed portion is formed in a semiconductor layer to partition the photoelectric conversion region. The same document also discloses a technology for strengthening pinning by providing a p-type semiconductor region at the interface between the recessed isolation region and the photoelectric conversion region, thereby reducing the generation of dark current.

[0003] Japanese Patent Application Laid-Open No. 2018-148116

[0004] However, with the technology of providing a p-type semiconductor region at the interface between the recessed isolation region and the photoelectric conversion region, it is difficult to completely eliminate dark current, and there is a possibility that dark current may be mixed into the photoelectric conversion portion of the photoelectric conversion region. This dark current mixing causes deterioration of image quality in dimly lit scenes, so there is room for improvement.

[0005] An object of the present technology is to provide a technology that can achieve high image quality.

[0006] (1) A photodetector according to one aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction; an isolation region including a recessed portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a photoelectric conversion region provided in the semiconductor layer and partitioned by the isolation region. The photoelectric conversion region includes: a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided spaced apart from the isolation region and the first surface portion of the semiconductor layer; a second semiconductor region of the first conductivity type provided between the isolation region and the first semiconductor region; and a third semiconductor region of a second conductivity type provided between the second semiconductor region and the first semiconductor region. (2) A photodetector according to another aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a separation region including a recessed portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; a photoelectric conversion region provided in the semiconductor layer and partitioned by the separation region; and a charge discharge layer provided on a side portion of the semiconductor layer inside the recessed portion.

[0007] (3) An electronic device according to another aspect of the present technology includes the above-mentioned photodetector; an optical lens that focuses image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device.

[0008] 6A is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a5-a5 cutting line of FIG. 5; FIG. 6B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the b5-b5 cutting line of FIG. 5; FIG. 6C is a longitudinal sectional view schematically showing a cross-sectional pattern of a conductor in a cross section perpendicular to the thickness direction of a semiconductor layer in the pixel block of FIG. 5; FIG. 6D is a longitudinal sectional view schematically showing a process of a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology; FIG. 9A is a longitudinal sectional view schematically showing a process subsequent to the process of FIG. 9B; FIG. 9C is a longitudinal sectional view schematically showing a process subsequent to the process of FIG. 9D. 9B. A longitudinal sectional view schematically showing a step subsequent to the step of FIG. 9E. A longitudinal sectional view schematically showing a step subsequent to the step of FIG. 9F. A longitudinal sectional view schematically showing a step subsequent to the step of FIG. 9G. A longitudinal sectional view schematically showing a step subsequent to the step of FIG. 9H. A longitudinal sectional view schematically showing a step subsequent to the step of FIG. 9I. It is a plan view schematically showing a part of a pixel array section, which is a modified example 1-1 of the first embodiment of the present technology. It is a plan view schematically showing a part of a pixel array section, which is a modified example 1-2 of the first embodiment of the present technology. It is a plan view schematically showing a part of a pixel array section, which is a modified example 1-3 of the first embodiment of the present technology. It is a schematic cross-sectional view of a cross-sectional pattern of a conductor in a cross section orthogonal to the thickness direction of a semiconductor layer, which is a modified example 1-5 of the first embodiment of the present technology. It is a schematic cross-sectional view of a cross-sectional pattern of a conductor in a cross section orthogonal to the thickness direction of a semiconductor layer, which is a modified example 1-6 of the first embodiment of the present technology. 1-7 is a cross-sectional view schematically illustrating a cross-sectional pattern of a conductor in a cross section perpendicular to a thickness direction of a semiconductor layer according to a modification of the first embodiment of the present technology. 1-8 is a cross-sectional view schematically illustrating a vertical cross-sectional structure according to a modification of the first embodiment of the present technology.25A and 25B are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a modified example 1-9 of the first embodiment of the present technology; FIG. 25B are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a modified example 1-10 of the first embodiment of the present technology; FIG. 25C are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a modified example 1-11 of the first embodiment of the present technology; FIG. 25C are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a modified example 1-12 of the first embodiment of the present technology; FIG. 25D are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a modified example 1-13 of the first embodiment of the present technology; FIG. 25C are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a modified example 1-14 of the first embodiment of the present technology; FIG. 25D are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a modified example 1-15 of the first embodiment of the present technology; FIG. 25C are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure of a solid-state imaging device according to a second embodiment of the present technology; 34A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a26-a26 cutting line of FIG. 26. FIG. 34B is a plan view schematically showing a configuration example of one pixel block in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 34C is a cross-sectional view schematically showing a cross-sectional pattern of a conductor in a cross section perpendicular to the thickness direction of a semiconductor layer in the pixel block of FIG. 28. FIG. 34B is an equivalent circuit diagram showing an example of a circuit included in a pixel in a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 34C is a plan view schematically showing a plane pattern of a pixel in a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 34B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a31-a31 cutting line of FIG. 31. FIG. 34C is a cross-sectional view schematically showing a cross-sectional structure taken along the a32-a32 cutting line of FIG. 32. FIG. 34D is a cross-sectional view schematically showing a cross-sectional structure taken along the b32-b32 cutting line of FIG. 32. FIG. 34D is a longitudinal cross-sectional view schematically showing a process of a method for manufacturing a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 34B is a longitudinal cross-sectional view schematically showing a process subsequent to the process of FIG. 34B. FIG. 34C. FIG. 34D. FIG. 34E. FIG. 34F.39A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a solid-state imaging device according to a sixth embodiment of the present technology. FIG. 39B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a solid-state imaging device according to a seventh embodiment of the present technology. FIG. 39C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a solid-state imaging device according to an eighth embodiment of the present technology. FIG. 39D is a plan view schematically showing a plane pattern of a pixel in a solid-state imaging device according to a ninth embodiment of the present technology. FIG. 39C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a38-a38 cutting line of FIG. 38. FIG. 39D is a cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b38-b38 cutting line of FIG. 38. FIG. 39A is a cross-sectional view schematically showing a cross-sectional structure taken along the a39-a39 cutting line of FIG. 39A. FIG. 39C is a plan view schematically showing a plane pattern of a pixel in a solid-state imaging device according to a tenth embodiment of the present technology. FIG. 41C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a41-a41 cutting line of FIG. 41. FIG. 42C is a cross-sectional view schematically showing a cross-sectional structure taken along the a42-a42 cutting line of FIG. 42. 47A and 47B are cross-sectional views schematically showing a cross-sectional structure of a pixel according to a modified example 10-1 of the tenth embodiment of the present technology; FIG. 47C are plan views schematically showing a plane pattern of a pixel according to a modified example 10-2 of the tenth embodiment of the present technology; FIG. 47D are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure taken along the a45-a45 cutting line of FIG. 45; FIG. 47E are plan views schematically showing a plane pattern of a pixel according to a solid-state imaging device according to an eleventh embodiment of the present technology; FIG. 47F are longitudinal cross-sectional views schematically showing a longitudinal cross-sectional structure taken along the a47-a471 cutting line of FIG. 47; and FIG. 47G are diagrams showing a schematic configuration of an electronic device according to a twelfth embodiment of the present technology.

[0009] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0010] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0011] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0012] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0013] In addition, in the following embodiments, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type as the conductivity type of the semiconductor, but the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type.

[0014] In the following embodiments, among the three directions orthogonal to each other in space, a first direction and a second direction orthogonal to each other in the same plane are referred to as the X direction and the Y direction, respectively, and a third direction orthogonal to each of the first direction and the second direction is referred to as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 21 (described later) will be described as the Z direction. In the following embodiments, the Z direction will be described as "one direction" of the present technology.

[0015] In addition, in the following embodiments, the thickness of the semiconductor layer 21 is the distance between the first surface portion S1 and the second surface portion S2, which are located on opposite sides in the Z direction, and the thickness direction of the semiconductor layer 21 is the direction representing the thickness of the semiconductor layer 21.

[0016] In the following embodiments, a plan view refers to a case where the semiconductor layer 21 is viewed from the Z direction (one direction). A cross-sectional view refers to a case where a cross section along the Z direction (one direction) is viewed from a direction (Z direction) perpendicular to the cross section.

[0017] First Embodiment In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. Also, in this first embodiment, a pixel in which one photoelectric conversion unit is provided in a photoelectric conversion region will be described.

[0018] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1A will be described. As shown in Fig. 1 , the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in Fig. 49 , this solid-state imaging device 1A (101) captures image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0019] As shown in FIG. 1 , a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including mutually orthogonal X and Y directions, a rectangular pixel array section 2A provided in the center and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The semiconductor chip 2 is formed in a manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (described below) into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in a wafer state before the semiconductor wafer is diced. In other words, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0020] The pixel array unit 2A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in Fig. 49. The pixel array unit 2A has a plurality of pixels (sensor pixels) 3 arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0021] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides of the semiconductor chip 2 in a two-dimensional plane. Each of the plurality of bonding pads 14 functions as an input / output terminal (external connection terminal) that electrically connects the semiconductor chip 2 to an external device. Although not shown, a connecting member such as a bonding wire or a bump electrode is connected to the bonding pad 14.

[0022] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0023] 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via vertical signal lines 11.

[0024] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0025] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0026] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0027] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0028] <Pixel Block> The semiconductor chip 2 includes a pixel block 15 and a pixel circuit (readout circuit) 16 shown in FIG.

[0029] As shown in Figures 3 and 5, the pixel block 15 includes a plurality of pixels 3. The pixel block 15 of the first embodiment includes, for example, a 2x2 arrangement of four pixels 3 (3a, 3b, 3c, 3d) arranged two by two adjacent to each other in each of the X and Y directions in a plan view, although this is not limited thereto. Although Figures 3 and 5 mainly illustrate one pixel block 15, the pixel blocks 15 are repeatedly arranged in each of the X and Y directions as shown in Figure 4, constituting the pixel array unit 2A shown in Figure 1.

[0030] As shown in FIG. 3 , the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 each have common components. Specifically, each of the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 includes a photoelectric conversion unit 25, a floating diffusion region FD serving as a charge storage unit for storing (accumulating) signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR for transferring the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Each of the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 also includes a photoelectric conversion region 22 of the semiconductor layer 21 shown in FIGS. 6A , 6B , and 7 . The photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR are each provided in the photoelectric conversion region 22, as shown in FIGS. 5 to 7 . 6A and 6B show two pixels, 3a and 3d, out of four pixels, 3a, 3b, 3c, and 3d, included in one pixel block 15. Also, in Fig. 7, two pixels, 3a and 3c, out of four pixels, 3a, 3b, 3c, and 3d, included in one pixel block 15 are shown.

[0031] 3 is configured, for example, by a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge. The cathode side of the photoelectric conversion unit 25 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).

[0032] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0033] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0034] <Pixel Circuit> The pixel circuit (readout circuit) 16 shown in FIG. 3 has its input side electrically connected to the floating diffusion region FD of the pixel 3. In this first embodiment, the pixel circuit 16 is provided for each pixel block 15, for example. Here, in this first embodiment, as an example, a circuit configuration is used in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes four pixels 3. However, the assignment of the pixel circuits 16 is not limited to this first embodiment. For example, a circuit configuration in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes two or more pixels 3, may also be used. Alternatively, a circuit configuration in which one pixel circuit 16 is assigned to multiple pixel blocks 15, each unit of which includes multiple pixels 3, may also be used. Furthermore, a circuit configuration in which one pixel circuit 16 is assigned to one pixel 3 may also be used.

[0035] 3 reads out the signal charges held in the floating diffusion region FD of the pixel 3 and outputs a pixel signal based on the read-out signal charges. In other words, the pixel circuit 16 converts the signal charges photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charges and outputs the pixel signal.

[0036] 3, the pixel circuit 16 includes, but is not limited to, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG as pixel transistors Q. These pixel transistors Q (AMP, SEL, RST, FDG) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２ The pixel transistors and the transfer transistors TR are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0037] Of the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0038] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) and the source region of the switching transistor FDG.

[0039] 3, the source region of the select transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the select transistor SEL is electrically connected to the select transistor drive line of the pixel drive lines 10 shown in FIG.

[0040] 3, the source region of the reset transistor RST is electrically connected to the drain of the switching transistor FDG, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0041] 3, the drain region of the switching transistor FDG is electrically connected to the source region of the reset transistor RST, and the source region is electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion regions FD of each of the four pixels 3 (3 a, 3 b, 3 c, 3 d). The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line among the pixel drive lines 10 shown in FIG.

[0042] The selection transistor SEL and the switching transistor FDG may be omitted as necessary. When the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL). When the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode and floating diffusion region FD of the amplification transistor AMP.

[0043] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0044] When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd.

[0045] The selection transistor SEL shown in FIG. 3 controls the output timing of the pixel signal from the pixel circuit 16 .

[0046] 3 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifier transistor AMP constitutes a source-follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0047] The switching transistor FDG shown in FIG. 3 controls charge retention by the floating diffusion region FD, and adjusts the multiplication factor of the voltage according to the potential amplified by the amplifier transistor AMP.

[0048] During operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of the pixel 3 (photoelectric conversion region 22) are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 16 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 16. A horizontal line selection control signal is applied to the gate electrode of the select transistor SEL of the pixel circuit 16 from the vertical shift register. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 16 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0049] 3 are mounted on a semiconductor layer 21 (see FIG. 7 ) described later. In addition, although not limited thereto, in the first embodiment, the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16 of FIG. 3 are also mounted on the semiconductor layer 21 (see FIGS. 5 and 6A ), for example.

[0050] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the solid-state imaging device 1A (semiconductor chip 2) will be described with reference to Fig. 4 to Fig. 7. In Fig. 4 and Fig. 5, in order to make the drawings easier to see, a multilayer wiring layer 51, which will be described later, is omitted from illustration, and in Fig. 6A, Fig. 6B, and Fig. 7, layers above a first wiring layer 54 included in the multilayer wiring layer 51 are omitted from illustration. In addition, Fig. 1 is a plan view of the semiconductor chip 2 as viewed from its light incident surface side, while Fig. 4 and Fig. 5 are plan views as viewed from the opposite side of the light incident surface side of the semiconductor chip 2 (the multilayer wiring layer side).

[0051] 6A, the solid-state imaging device 1A according to the first embodiment includes a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located on opposite sides in a thickness direction (Z direction) that is one direction, an inter-pixel isolation region 31 provided in the semiconductor layer 21 and extending along the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 provided in the semiconductor layer 21 and partitioned by the inter-pixel isolation region 31. The photoelectric conversion region 22 includes the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21.

[0052] The solid-state imaging device 1A according to the first embodiment further includes a field isolation region 32 provided in a surface layer portion of the first surface S1 of the semiconductor layer 21, and a multilayer wiring layer 51 provided on the first surface S1 side of the semiconductor layer 21. The solid-state imaging device 1A according to the first embodiment further includes, on the second surface S2 side of the semiconductor layer 21, a planarization film 61, a light-shielding film 62, an optical filter layer 63, and a lens layer 64, which are provided in this order from the second surface S2 side.

[0053] Here, the first surface S1 of the semiconductor layer 21 may be referred to as a main surface or an element forming surface, and the second surface S2 may be referred to as a back surface. The solid-state imaging device 1A according to the first embodiment is a back-illuminated image sensor that photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 using a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 may be referred to as a light incident surface. In the first embodiment, the inter-pixel isolation region 31 corresponds to a specific example of an "isolation region" of the present technology.

[0054] 6A , the planarization film 61 is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21, and planarizes the second surface S2 side of the semiconductor layer 21. As the planarization film 61, for example, a light-transmitting silicon oxide film can be used.

[0055] 6A , the light-shielding film 62 is provided on the side of the planarization film 61 opposite to the semiconductor layer 21 side. The light-shielding film 62 has a lattice-like planar pattern in plan view that opens on the light-receiving surface side of each of the multiple photoelectric conversion regions 22 so that light incident on a given photoelectric conversion region 22 does not leak into an adjacent photoelectric conversion region 22. The light-shielding film 62 has the same lattice-like planar pattern as the inter-pixel isolation region 31 described below, and is arranged in a position that overlaps the inter-pixel isolation region 31 in plan view. For example, a tungsten (W) film having light-shielding properties can be used as this light-shielding film 62.

[0056] 6A , the optical filter layer 63 is provided on the side of the light-shielding film 62 opposite to the semiconductor layer 21. This optical filter layer 63 separates the color of incident light that is incident from the light incident surface side (second surface portion S2 side) of the solid-state imaging device 1A. This optical filter layer 63 includes an optical filter portion 63 a for each pixel 3 (for each photoelectric conversion region 22) that transmits light of a specific wavelength, such as, but not limited to, red (R), green (G), or blue (B).

[0057] 6A , the lens layer 64 is provided on the side of the optical filter layer 63 opposite to the planarization film 61. The lens layer 64 includes a microlens (on-chip lens) 64 a for each pixel 3 (for each photoelectric conversion region 22) that collects irradiated light and allows the collected light to efficiently enter the photoelectric conversion region 22.

[0058] That is, the pixel 3 of this first embodiment includes a photoelectric conversion region 22, and a planarization film 61, a light-shielding film 62, an optical filter portion 63a, and a microlens 64a each provided on the second surface portion S2 side of this photoelectric conversion region 22.

[0059] 6A and 7 , the semiconductor layer 21 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21 and a photoelectric conversion region 22 defined by the inter-pixel isolation region 31. The semiconductor layer 21 further includes a field isolation region 32 provided in a surface layer portion of the first surface portion S1 of the semiconductor layer 21 and element formation regions 43 a and 43 b defined by the field isolation region 32. As shown in FIG. 5 , the photoelectric conversion region 22 and the element formation regions 43 a and 43 b are each provided for each pixel 3. The semiconductor layer 21 may be formed of a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, the semiconductor layer 21 is formed of, but is not limited to, a p-type semiconductor substrate made of single crystal silicon, for example.

[0060] 5 , 6A and 7 , the field isolation region 32 is provided on the first surface S1 of the semiconductor layer 21 across a plurality of photoelectric conversion regions 22. The field isolation region 32 includes a shallow recess 35 provided on the first surface S1 side of the semiconductor layer 21, and an isolation insulating film 42 provided inside the shallow recess 35 so as to bury the shallow recess 35.

[0061] 5 and 8 , the inter-pixel isolation region 31 includes a first planar extending portion 31x extending in the X direction in a plan view and a second planar extending portion 31y extending in the Y direction. The inter-pixel isolation region 31 further includes an intersection portion (intersection portion) 31xy where the first planar extending portion 31x and the second planar extending portion 31y intersect with each other on the same plane. In this first embodiment, the first planar extending portion 31x and the second planar extending portion 31y are, for example, perpendicular to each other.

[0062] The first planar extending portions 31x are repeatedly arranged at predetermined intervals in the Y direction, and the second planar extending portions 31y are repeatedly arranged at predetermined intervals in the X direction. That is, the inter-pixel isolation region 31 has a grid-like planar pattern in plan view.

[0063] 5 and 8 , the inter-pixel isolation region 31 corresponding to one photoelectric conversion region 22 has an annular planar pattern (ring-shaped planar pattern) having a square planar shape in a plan view, and surrounds the periphery of one photoelectric conversion region 22. On the other hand, as shown in Fig. 5 and 8 , the inter-pixel isolation region 31 corresponding to one pixel block 15 has a composite planar pattern having a cross-shaped planar pattern in which a first planar extension portion 31x and a second planar extension portion 31y are arranged orthogonal to each other within the square annular planar pattern.

[0064] 5 and 8 , in the inter-pixel isolation region 31 corresponding to one pixel block 15, an intersection (intersection) 31xy between a first planar extension 31x and a second planar extension 31y is located in the center of the pixel block 15. The photoelectric conversion regions 22 of four pixels 3 (3a, 3b, 3c, 3d) are arranged in a matrix (2 × 2) so as to surround this intersection 31xy. That is, the photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15 are adjacent to each other via the inter-pixel isolation region 31 in each of the X and Y directions in a planar view.

[0065] 6A and 7 , the inter-pixel isolation region 31 extends in one direction, that is, the thickness direction (Z direction) of the semiconductor layer 21, and electrically and optically isolates two adjacent photoelectric conversion regions 22 in a planar view. The inter-pixel isolation region 31 is configured, for example, as an engraved, i.e., trench, type region in which deep engraved portions 36 are formed in the semiconductor layer 21 to partition and isolate the photoelectric conversion regions 22. The inter-pixel isolation region 31 overlaps a portion of the field isolation region 32 in a planar view, and is provided from the bottom of the field isolation region 32 to the second surface portion of the semiconductor layer.

[0066] The inter-pixel isolation region 31 includes, but is not limited to, for example, a deep recess 36 extending from the bottom of the field isolation region 32 toward the second surface S1 side of the semiconductor layer 21, and an isolation insulating film 39 provided inside the deep recess 36 so as to bury the deep recess 36.

[0067] 5 , 6A , 7 , and 8 , the photoelectric conversion region 22 is surrounded by the inter-pixel isolation region 31 in a plan view and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first planar extensions 31x that extend in the X direction and are spaced apart in the Y direction, and two second planar extensions 31y that extend in the Y direction and are spaced apart in the X direction. The photoelectric conversion region 22 is partitioned by the first planar extensions 31x and the second planar extensions 31y, and is separated from adjacent photoelectric conversion regions 22.

[0068] As shown in Figures 6A and 7, the photoelectric conversion region 22 has a p-type well region 23 provided on the first surface portion S1 side of the semiconductor layer 21, and a photoelectric conversion unit 25 including an n-type semiconductor region 24 that overlaps the p-type well region 23 in a planar view and is provided in the semiconductor layer 21 at a distance from each of the inter-pixel isolation region 31 and the first surface portion S1 of the semiconductor layer 21.

[0069] In addition, the photoelectric conversion region 22 further has an n-type semiconductor region 38 provided between the inter-pixel isolation region 31 and the n-type semiconductor region 24, and a p-type semiconductor region 37 provided between this n-type semiconductor region 38 and the n-type semiconductor region 24.

[0070] As shown in FIG. 7 , the photoelectric conversion region 22 further includes an n-type floating diffusion region FD provided on the first surface S1 side of the semiconductor layer 21 and serving as a charge holding section for holding (accumulating) signal charges photoelectrically converted by the photoelectric conversion section 25, and a transfer transistor TR provided on the first surface S1 side of the semiconductor layer 21 and for transferring the signal charges photoelectrically converted by the photoelectric conversion section 25 to the floating diffusion region FD.

[0071] 5, 6A, and 7, the photoelectric conversion region 22 further includes element formation regions 43a and 43b partitioned by a field isolation region 32, and a pixel transistor Q included in the pixel circuit 16. 5 and 7, the photoelectric conversion region 22 further includes a p-type power supply contact region WC provided on the first surface S1 side of the semiconductor layer 21 in contact with the p-type well region 23.

[0072] 5, 6A, and 7, each of the element formation regions 43a and 43b is provided on the first surface S1 of the semiconductor layer 21 in the photoelectric conversion region 22. Each of the element formation regions 43a and 43b is surrounded by a field isolation region 32, partitioned into islands, and insulated and isolated from each other. A p-type well region 23 is provided in each of the element formation regions 43a and 43b.

[0073] 6A and 7, the p-type well region 23 is provided over the entire photoelectric conversion region 22 on the first surface portion S1 side of the semiconductor layer 21. The p-type well region 23 is composed of a p-type semiconductor region.

[0074] 6A and 7 , the n-type semiconductor region 24 has a three-dimensional structure, with its top surface side in contact with the p-type well region 23, its side surface side in contact with the p-type semiconductor region 37, and the side opposite to the top surface side in contact with the planarization film 61. That is, the n-type semiconductor region 24 forms a pn junction with the p-type well region 23 and the p-type semiconductor region 37.

[0075] 6A , the photoelectric conversion unit 25 is provided in the photoelectric conversion region 22. In the photoelectric conversion region 22, the photoelectric conversion unit 25 includes an n-type semiconductor region 24, and further includes a p-type well region 23 and a p-type semiconductor region 37. The photoelectric conversion unit 25 is configured as a pn junction photodiode (PD) including a pn junction between the p-type well region 23, the p-type semiconductor region 37, and the n-type semiconductor region 24.

[0076] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at a pn junction between the p-type well region 23 and the p-type semiconductor region 37 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is provided in the semiconductor layer 21, spaced apart from the first surface S1 of the semiconductor layer 21. The photoelectric conversion unit 25 is provided for each photoelectric conversion region 22 (pixel 3).

[0077] 5 and 7 , the n-type floating diffusion region FD is provided in the p-type well region 23 in the element formation region 43 a of the photoelectric conversion region 22. The n-type floating diffusion region FD overlaps with the n-type semiconductor region 24 in a plan view, and is spaced apart from the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21. That is, the p-type well region 23 is provided between the n-type floating diffusion region FD and the n-type semiconductor region 24. The n-type floating diffusion region FD is composed of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24.

[0078] 5 and 7 , the transfer transistor TR is provided in the element formation region 43a of the photoelectric conversion region 22. The transfer transistor TR has a gate electrode 46 provided on the first surface portion S1 side of the semiconductor layer 21, and a gate insulating film 45 provided between the gate electrode 46 and the semiconductor layer 21. The transfer transistor TR also has an n-type semiconductor region 24 and an n-type floating diffusion region FD functioning as a source region and a drain region, and a p-type well region 23 functioning as a channel formation region. Although not limited thereto, the transfer transistor TR has a vertical type configuration in which the gate electrode 46 extends through the semiconductor layer 21 in its thickness direction (Z direction).

[0079] 7, the gate electrode 46 of the transfer transistor TR has a head 46a provided outside the first surface S1 of the semiconductor layer 21 with the gate insulating film 45 interposed therebetween, and a body 46b that protrudes from the head 46a into the semiconductor layer 21 and is adjacent to the semiconductor layer 21 with the gate insulating film 45 interposed therebetween. The gate electrode 46 of the first embodiment is not limited to this, but for example, the body 46b is narrower than the head 46a.

[0080] The body portion 46b of the gate electrode 46 is provided in the gate recessed portion 44 of the semiconductor layer 21 with a gate insulating film 45 interposed therebetween, and reaches the n-type semiconductor region 24. The gate recessed portion 44 extends from the first surface S1 toward the second surface S2 of the semiconductor layer 21. The gate insulating film 45 is made of, for example, a silicon oxide film. The gate electrode 46 is made of, for example, a polycrystalline silicon film (doped polysilicon film) into which impurities that reduce resistance have been introduced.

[0081] 7, when a gate voltage is applied to the gate electrode 46 to turn on the transfer transistor TR, a charge transfer path (channel) electrically connecting the n-type semiconductor region 24 and the n-type floating diffusion region FD is formed in the p-type well region 23. Then, signal charges photoelectrically converted in the n-type semiconductor region 24 of the photoelectric conversion unit 25 are transferred from the n-type semiconductor region 24 to the n-type floating diffusion region FD through the charge transfer path.

[0082] 5 and 7 , the p-type power supply contact region WC is provided in the p-type well region 23 in the element formation region 43 a of the photoelectric conversion region 22, and is electrically connected to the p-type well region 23. The p-type power supply contact region WC is made of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23.

[0083] A first reference potential (Vss potential), for example, 0 V, is applied to the p-type power supply contact region WC when the solid-state imaging device 1A is in operation, and the p-type well region 23 is fixed at this first reference potential while the solid-state imaging device 1A is in operation.

[0084] 5, the photoelectric conversion region 22 of each of the four pixels 3 (3a, 3b, 3c, and 3d) included in one pixel block 15 includes a pixel transistor Q included in one pixel circuit 16, as described above. In the first embodiment, although not limited thereto, for example, as shown in FIG. 5, among the four pixels 3 (3a, 3b, 3c, and 3d) included in one pixel block 15, the photoelectric conversion region 22 of pixel 3a includes an amplification transistor AMP provided in the element formation region 53a as the pixel transistor Q, and the photoelectric conversion region 22 of pixel 3b includes a selection transistor SEL provided in the element formation region 53a as the pixel transistor Q. Furthermore, among the four pixels 3 (3a, 3b, 3c, and 3d) included in one pixel block 15, the photoelectric conversion region 22 of pixel 3c includes a switching transistor FDG provided in the element formation region 53a as the pixel transistor Q, and the photoelectric conversion region 22 of pixel 3d includes a reset transistor RST provided in the element formation region 53a as the pixel transistor Q.

[0085] 6A , in the pixel transistor Q included in the pixel circuit 16, the amplification transistor AMP has a gate electrode 47 provided on the outside of the first surface portion S1 of the semiconductor layer 21, and a gate insulating film 45 provided between the gate electrode 47 and the first surface portion S1 of the semiconductor layer 21. The amplification transistor AMP also has a pair of main electrode regions 48a that are provided in the semiconductor layer 21 on both sides of the gate electrode 47 in the gate length direction (the direction of the gate length Lg) and function as a source region and a drain region. １ and 48a ２ and the pair of main electrode regions 48a １ and 48a ２ and a channel forming portion provided between the

[0086] A pair of main electrode regions 48a １ and 48a ２Each of these is made up of, for example, an n-type semiconductor region provided in a p-type well region 23. The channel formation portion is made up of, for example, the p-type well region 23. The gate insulating film 45 is made up of, for example, a silicon oxide film. The gate electrode 47 is made up of, for example, a polycrystalline silicon film (doped polysilicon film) into which impurities that reduce the resistance value are introduced.

[0087] In addition, as the pixel transistors Q included in the pixel circuit 16, the selection transistor SEL, the switching transistor FDG, and the reset transistor RST other than the amplification transistor AMP also have the same configuration as the amplification transistor AMP, so a description of these pixel transistors Q (SEL, FDG, RST) will be omitted.

[0088] In addition, in the first embodiment, as an example, a case where one pixel transistor Q is arranged in one photoelectric conversion region 22 is described, but a plurality of pixel transistors Q with the same function may be arranged in one photoelectric conversion region 22, or a plurality of pixel transistors Q with different functions may be arranged in one photoelectric conversion region 22. Also, there is a case where no pixel transistor Q is arranged in the photoelectric conversion region 22. In this case, the pixel transistor Q is arranged in another semiconductor layer provided so as to overlap the semiconductor layer 21 in a planar view.

[0089] (n-type semiconductor region and p-type semiconductor region) As described above, the photoelectric conversion region 22 shown in Figures 6A and 7 includes a photoelectric conversion section 25 including an n-type semiconductor region 24 provided at a distance from each of the inter-pixel isolation region 31 and the first surface portion S1 of the semiconductor layer 21, an n-type semiconductor region 38 provided between the inter-pixel isolation region 31 and the n-type semiconductor region 24, and a p-type semiconductor region 37 provided between the n-type semiconductor region 38 and the n-type semiconductor region 24.

[0090] Here, in this first embodiment, the n-type semiconductor region 24 corresponds to a specific example of a "first semiconductor region of a first conductivity type" in the present technology, the n-type semiconductor region 38 corresponds to a specific example of a "second semiconductor region of a first conductivity type" in the present technology, and the p-type semiconductor region 37 corresponds to a specific example of a "third semiconductor region of a second conductivity type" in the present technology.

[0091] 6A , 7 , and 8 , the n-type semiconductor region 38 and the p-type semiconductor region 37 are disposed in this order from the inter-pixel isolation region 31 side toward the n-type semiconductor region 24 side, and extend along the inter-pixel isolation region 31 in the thickness direction (Z direction) of the semiconductor layer 21. As shown in FIG. 8 , the n-type semiconductor region 38 and the p-type semiconductor region 37 extend along the inter-pixel isolation region 31 that surrounds the photoelectric conversion region 22 in a planar view, and have an annular (ring-shaped) planar pattern in a planar view. The n-type semiconductor region 38 and the p-type semiconductor region 37 extend across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21.

[0092] The n-type semiconductor region 38 is provided in contact with the inter-pixel isolation region 31 on the photoelectric conversion region 22 side of the interface between the inter-pixel isolation region 31 and the photoelectric conversion region 22. The p-type semiconductor region 37 is provided between the n-type semiconductor region 38 and the n-type semiconductor region 24 in contact with each of the n-type semiconductor regions 38 and 24.

[0093] Each of the n-type semiconductor region 38 and the p-type semiconductor region 37 is formed in the manufacturing process of the solid-state imaging device 1A by introducing impurities from inside the deep recessed portion 36 formed in the semiconductor layer 21 into the semiconductor layer 21 (photoelectric conversion region 22) around the deep recessed portion 36. Therefore, each of the n-type semiconductor region 38 and the p-type semiconductor region 37 is provided in alignment with the inter-pixel isolation region 31.

[0094] 6A , 6B and 7 , the n-type semiconductor region 38 is electrically and mechanically connected to a conductor 41 to which a potential is applied. The conductor 41 in this first embodiment is provided in the deep recess 36 of the inter-pixel isolation region 31 on the first surface S1 side of the semiconductor layer 21. The conductor 41 is electrically and mechanically connected to the n-type semiconductor region 38 on the side surface of the photoelectric conversion region 22.

[0095] As shown in FIGS. 6A and 7 , the conductor 41 is provided between the isolation insulating film 39 of the inter-pixel isolation region 31 and the isolation insulating film 42 of the field isolation region 32. As shown in FIG. 8 , the conductor 41 has a planar shape in a planar view that is the same as the planar pattern of the inter-pixel isolation region. That is, the conductor 41 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a planar view, surrounding the periphery of one photoelectric conversion region 22. On the other hand, as shown in FIG. 8 , the conductor 41 corresponding to one pixel block 15 has a planar shape in a planar view that is a composite planar pattern having a cross-shaped planar pattern in which a first portion extending in the X direction and a second portion extending in the Y direction are arranged orthogonal to each other within the rectangular annular planar pattern. The conductor 41 can be, for example, a polycrystalline silicon film (doped polysilicon film) doped with impurities that reduce resistance.

[0096] 6A and 7, the multilayer wiring layer 51 is provided on the first surface S1 side of the semiconductor layer 21. The multilayer wiring layer 51 includes an interlayer insulating film 52 provided on the first surface S1 side of the semiconductor layer 21 so as to cover the field isolation region 32 and the element formation regions 43a, 43b, and a first-layer wiring layer 54 provided on the side of the interlayer insulating film 52 opposite to the semiconductor layer 21 side. The multilayer wiring layer 51 also includes a contact electrode 53a provided in the interlayer insulating film 52. １ , 53a ２ , 53f, 53r １ , 53r ２ , 53w, and a contact electrode 53x provided across the interlayer insulating film 52 and the isolation insulating film 42. １ , 54a ２ , 54f, 54r １ , 54r ２ , 54w, 54x.

[0097] Contact electrode 53a １ , 53a ２ , 53f, 53r １ , 53r ２, 53w may be made of, for example, tungsten (W), a high-melting-point metal. The first wiring layer 54 may be made of, for example, a metal material such as aluminum (Al) or copper (Cu), or an alloy material mainly containing Al or Cu. The interlayer insulating film 52 may be, for example, a silicon oxide film. The gate electrode 47t of the transfer transistor TR and each of the gate electrodes 47 of the plurality of pixel transistors Q (AMP, SEL, RST, FDG) are covered with an interlayer insulating film 56.

[0098] <Contact Electrode and Wiring> As shown in FIG. 6A, the main electrode region 48a of the amplifier transistor AMP １ , 48a ２ The contact electrode 53a provided on the interlayer insulating film 52 １ , 53a ２ The wiring 54a provided in the wiring layer 54 on the interlayer insulating film 52 is １ , 54a ２ Although not shown in detail, the gate electrode 47 of the amplification transistor AMP is electrically connected to a wiring provided in a wiring layer on the interlayer insulating film 52 via a contact electrode provided in the interlayer insulating film 52.

[0099] As shown in FIG. 6A, the n-type semiconductor region 48r of the reset transistor RST １ , 48r ２ is a contact electrode 53r provided in the interlayer insulating film 52. １ , 53r ２ The wiring 54r provided in the wiring layer 54 on the interlayer insulating film 52 is １ , 54r ２ Although not shown in detail, the gate electrode 47 of the reset transistor RST is electrically connected to a wiring provided in a wiring layer on the interlayer insulating film 52 via a contact electrode provided in the interlayer insulating film 52.

[0100] Although not shown, each of the selection transistor SEL and the switching transistor FDG is electrically connected to the wiring on the interlayer insulating film 52 via a contact electrode of the interlayer insulating film 52, similar to the amplification transistor AMP and the reset transistor RST.

[0101] As shown in FIG. 6A, the conductor 41 is electrically connected to a wiring 54x provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 53x provided across the interlayer insulating film 52 and the isolation insulating film 42.

[0102] As shown in FIG. 7, the gate electrode 46 of the transfer transistor TR is electrically connected to a wiring 54t provided in a wiring layer 58 on the interlayer insulating film 56 via a contact electrode 53t provided in the interlayer insulating film 52.

[0103] As shown in FIG. 7, the n-type floating diffusion region FD is electrically connected to a wiring 54f provided in the wiring layer 54 on the interlayer insulating film 52 via a contact electrode 53f provided in the interlayer insulating film 52.

[0104] 7, the p-type power supply contact region WC is electrically connected to a wiring 54w provided in the wiring layer 54 on the interlayer insulating film 52 via a contact electrode 53w provided in the interlayer insulating film 52. A potential is supplied to this wiring 54w.

[0105] 6A and 6B , the conductor 41 is electrically connected to a wiring 54x provided in the wiring layer 54 on the interlayer insulating film 52 via a contact electrode 53x provided across the interlayer insulating film 52 and the field isolation region 32. A potential is applied to this wiring 54x. That is, the conductor 41 is electrically connected to the wiring 54x to which a potential is applied, and the potential of this wiring 54x is applied (supplied) to the conductor 41, and the potential of the wiring 54x is also applied (supplied) to the n-type semiconductor region 38 connected to this conductor 41.

[0106] The potentials include a power supply potential supplied from a power generation circuit provided inside the solid-state imaging device 1A and a power supply potential supplied from outside the solid-state imaging device 1A via the bonding pad 14. These power supply potentials include, for example, a first reference potential of "0 V," a second reference potential that is a positive potential higher than the first reference potential, and a third reference potential that is a negative potential lower than the first reference potential. In this first embodiment, since the semiconductor region 38 is configured as an n-type semiconductor, a positive potential of, for example, 2.8 V is applied to the conductor 41 as the second reference potential. The potential application to the wiring 54x is maintained during operation of the solid-state imaging device 1A.

[0107] A first reference potential of, for example, "0 V" is applied to the wiring 54w as a power supply potential, and the p-type well region 23 is fixed at the first reference potential during operation of the solid-state imaging device 1A.

[0108] <Location of Contact Electrode> As shown in FIGS. 6A and 6B , the contact electrode 53x extends from the wiring 54x through the interlayer insulating film 52 and the isolation insulating film 42 of the field isolation region 32 to reach the conductor 41, electrically connecting the wiring 54x and the conductor 41. Although not limited to the first embodiment, the contact electrode 53x is provided for each pixel block 15 including four pixels 3 in the pixel array section 2A, as shown in FIGS. 1 and 8 , for example. The contact electrode 53x is disposed at the intersection 31xy of the inter-pixel isolation region 31 in the center of each pixel block 15 in a plan view. That is, the conductor 41 is electrically connected to the wiring 54x of the multilayer wiring layer 51 for each pixel block 15, and receives a second reference potential from the wiring 54x of the multilayer wiring layer 51 and is fixed at this second reference potential. The contact electrode 53x can be made of, for example, tungsten (W), a high-melting-point metal.

[0109] 6A to 7 functions as a drain region that sweeps away dark current that has welled up at the interface between the inter-pixel isolation region 31 and the photoelectric conversion region 22 when a second reference potential is applied to the conductor 41. On the other hand, the p-type semiconductor region 37 functions as a depletion layer expansion suppression region that suppresses expansion of a depletion layer from the n-type semiconductor region 38 to the n-type semiconductor region 24.

[0110] 9A to 9J , a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present technology will be described. In this first embodiment, the description will be focused on the manufacture of the p-type semiconductor region 37 and the n-type semiconductor region 38, which are included in the method for manufacturing the solid-state imaging device 1A.

[0111] First, as shown in FIG. 9A , a p-type well region 23 and an n-type semiconductor region 24 are formed in the semiconductor layer 21. The p-type well region 23 and the n-type semiconductor region 24 are each formed over the entire semiconductor layer 21, including the photoelectric conversion region 22 and the recessed portion formation region 34. The p-type well region 23 is formed closer to the first surface S1 of the semiconductor layer 21 than the n-type semiconductor region 24. The n-type semiconductor region 24 overlaps the p-type semiconductor region 37 in a planar view and is formed closer to the second surface S2 of the semiconductor layer 21 than the p-type semiconductor region 37. The p-type well region 23 and the n-type semiconductor region 24 can be formed using well-known photolithography techniques and impurity ion implantation methods. FIG. 9A illustrates a photoelectric conversion region 22 that has not yet been partitioned by an inter-pixel isolation region 31.

[0112] Here, in the manufacture of the solid-state imaging device 1A of the first embodiment, a thinning step (see FIG. 9J) is carried out to thin the thickness of the semiconductor layer 21 in the Z direction. In this thinning step, the semiconductor layer 21 is thinned to the thinning line S2a shown in FIG. 9A.

[0113] Next, the recessed portion formation region 34 on the first surface S1 side of the semiconductor layer 21 is selectively etched to form a shallow recessed portion 35 recessed from the first surface S1 toward the second surface S2 side of the semiconductor layer 21, as shown in FIG. 9B , and an island-shaped element formation region partitioned by this shallow recessed portion 35 is formed. In FIGS. 9B to 9J, the island-shaped element formation region 43b is shown as an example, and the island-shaped element formation region 43a is not shown. The shallow recessed portion 35 can be formed by selectively etching the recessed portion formation region 34 of the semiconductor layer 21 using, for example, well-known photolithography and anisotropic dry etching techniques.

[0114] Next, as shown in FIG. 9C , an etching mask M1 is formed on the first surface S1 side of the semiconductor layer 21. The etching mask M1 includes openings M1a in a grid-like planar pattern and mask portions M1b that are partitioned by the openings M1a and cover the first surface S1 side of the semiconductor layer 21 and the side surfaces of the semiconductor layer 21 (side surfaces of the photoelectric conversion regions 22) inside the shallow recessed portions 35 for each photoelectric conversion region 22. The etching mask M1 is formed of a material that ensures an etching ratio with respect to the semiconductor layer 21. The openings M1a of the etching mask M1 are located in the shallow recessed portions 35, and the width of the openings M1a is formed to be narrower than the width of the shallow recessed portions 35. The width of the openings M1a defines the width of the deep recessed portions 36, which will be described later. The openings M1a of the etching mask M1 are formed in a grid-like planar pattern that surrounds each of the multiple photoelectric conversion regions 22 in a plan view.

[0115] Next, the semiconductor layer 21 exposed through the openings M1a of the etching mask M1 is selectively etched using, for example, an anisotropic dry etching technique to form deep recessed portions 36 that are continuous with the shallow recessed portions 35, extend from the shallow recessed portions 35 toward the second surface portion S2 of the semiconductor layer 21, and are narrower than the width of the shallow recessed portions 35, as shown in FIG. 9D . The deep recessed portions 36 are formed deeper than the thinning lines S2a of the semiconductor layer 21 that will be formed in the subsequent thinning step. In this step, the deep recessed portions 36 are formed so that their planar shape in a grid-like plane pattern in plan view. Also, in this step, each photoelectric conversion region 22 is surrounded by the deep recessed portions 36, and is partitioned and separated into individual regions by the deep recessed portions 36.

[0116] Next, as shown in FIG. 9E , a p-type semiconductor region 37 is formed on the side surface of the semiconductor layer 21 (the side surface of the photoelectric conversion region 22) inside the deep recess 36. The p-type semiconductor region 37 can be formed by introducing an impurity into the side surface of the semiconductor layer 21 (the side surface of the photoelectric conversion region 22) from inside the deep recess 36 while the first surface S1 side of the semiconductor layer 21 and the side surface of the semiconductor layer 21 inside the shallow recess 35 (the side surface of the photoelectric conversion region 22) are covered with an etching mask M1. The introduction of the impurity can be performed by ion implantation, solid-phase diffusion, plasma doping, or the like. The impurity can be, for example, boron (B) or boron fluoride (BF), which exhibits p-type conductivity when introduced into silicon (Si).

[0117] In the case of ion implantation or plasma doping, p-type impurities are introduced into the side surfaces of the semiconductor layer 21 (side surfaces of the photoelectric conversion region 22) from inside the deep recess 36 to form the p-type semiconductor region 37, and then heat treatment is performed to activate the introduced impurities. The heat treatment may be performed in the step of forming the n-type semiconductor region 38, which will be described later, or may be performed before the step of forming the n-type semiconductor region 38. The introduction of the impurities is performed in a state in which the first surface S1 side of the semiconductor layer 21 and the side surfaces of the semiconductor layer 21 inside the shallow recess 35 (side surfaces of the photoelectric conversion region 22) are covered (masked) with an etching mask M1.

[0118] In the case of the solid-phase diffusion method, a solid-phase diffusion medium film doped (introduced) with p-type impurities is formed in the deep recess 36, and then heat treatment is performed to diffuse and introduce the impurities from the solid-phase diffusion medium film from the inside of the deep recess 36 into the side surfaces of the semiconductor layer 21 (side surfaces of the photoelectric conversion region 22), thereby forming the p-type semiconductor region 37. The solid-phase diffusion medium film is formed, for example, in a state where the side surfaces of the semiconductor layer 21 (side surfaces of the photoelectric conversion region 22) inside the deep recess 36 are selectively covered with a mask such as a silicon oxide film or a silicon nitride film. The solid-phase diffusion medium film can be, for example, a polycrystalline silicon film doped with impurities.

[0119] In any of the ion implantation method, the plasma doping method, and the solid-phase diffusion method, the p-type semiconductor region 37 is formed in alignment with the deep recessed portion 36. The p-type semiconductor region 37 is formed along the deep recessed portion 36 in the thickness direction (Z direction) of the semiconductor layer 21. In the first embodiment, the p-type semiconductor region 37 is formed by, for example, the plasma doping method.

[0120] The p-type semiconductor region 37 is formed so that its thickness, measured from the inside of the deep recess 36 toward the semiconductor layer 21 (the photoelectric conversion region 22) in a plan view, is thicker than the thickness of an n-type semiconductor region 38 (described later). The p-type semiconductor region 37 is formed with an impurity concentration higher than the impurity concentration of the p-type well region 23.

[0121] Next, as shown in FIG. 9F , an n-type semiconductor region 38 is formed on the side surface of the semiconductor layer 21 (the side surface of the photoelectric conversion region 22) inside the deep recess 36. The n-type semiconductor region 38 can be formed, similar to the p-type semiconductor region 37 described above, by introducing impurities into the side surface of the semiconductor layer 21 (the side surface of the photoelectric conversion region 22) from inside the deep recess 36 while covering the first surface S1 side of the semiconductor layer 21 and the side surface of the semiconductor layer 21 inside the shallow recess 35 (the side surface of the photoelectric conversion region 22) with an etching mask M1. The introduction of the impurities can be performed by ion implantation, solid-phase diffusion, plasma doping, or the like, similar to the formation of the p-type semiconductor region 37 described above. The impurities can be, for example, phosphorus (P) or arsenic (As), which exhibit n-type conductivity when introduced into silicon (Si).

[0122] In the case of ion implantation or plasma doping, n-type impurities are introduced from inside the deep recess 36 into the side surface of the semiconductor layer 21 (the side surface of the photoelectric conversion region 22) to form the n-type semiconductor region 38, and then a heat treatment is performed to activate the introduced impurities. The heat treatment may be performed together with the heat treatment for the p-type semiconductor region 37 described above, or may be performed separately from the heat treatment for the p-type semiconductor region 37. This introduction of impurities is also performed with the first surface S1 side of the semiconductor layer 21 and the side surface of the semiconductor layer 21 inside the shallow recess 35 (the side surface of the photoelectric conversion region 22) covered with the etching mask M1 (masked state).

[0123] In the case of the solid-phase diffusion method, a solid-phase diffusion medium film doped (introduced) with n-type impurities is formed in the deep recess 36, and then heat treatment is performed to diffuse and introduce the impurities from the solid-phase diffusion medium film from the inside of the deep recess 36 into the side surfaces of the semiconductor layer 21 (side surfaces of the photoelectric conversion region 22), thereby forming the n-type semiconductor region 38. The solid-phase diffusion medium film is formed, for example, in a state where the side surfaces of the semiconductor layer 21 (side surfaces of the photoelectric conversion region 22) inside the deep recess 36 are selectively covered with a mask such as a silicon oxide film or a silicon nitride film. The solid-phase diffusion medium film can be, for example, a polycrystalline silicon film doped with impurities.

[0124] In any of the ion implantation method, the plasma doping method, and the solid-phase diffusion method, the n-type semiconductor region 38 is formed in alignment with the deep recessed portion 36. The n-type semiconductor region 38 is formed along the deep recessed portion 36 in the thickness direction (Z direction) of the semiconductor layer 21. In the first embodiment, the n-type semiconductor region 38 is formed by, for example, the plasma doping method.

[0125] The n-type semiconductor region 38 is formed so that its thickness, measured from the inside of the deep recess 36 toward the semiconductor layer 21 (photoelectric conversion region 22) in a plan view, is thinner than the thickness of the above-mentioned p-type semiconductor region 37. Furthermore, the n-type semiconductor region 38 is formed to have a higher impurity concentration than the impurity concentration of the n-type semiconductor region 24.

[0126] By this process, the photoelectric conversion region 22 is formed in this order from the deep recess 36 toward the n-type semiconductor region 24 in plan view.

[0127] In addition, boron (B) and boron fluoride (BF), which exhibit p-type conductivity, have a lighter mass and are more easily diffused than phosphorus (P) and arsenic (As), which exhibit n-type conductivity. Therefore, it is preferable to form an n-type semiconductor region after forming a p-type semiconductor region, as in this first embodiment.

[0128] 9G , an isolation insulating film 39 and a conductor 41 are formed in this order inside the deep carved portion 36 from the second surface S2 side of the semiconductor layer 21. The isolation insulating film 39 is formed so as to fill the deep carved portion 36 from a position one step lower than the shallow carved portion 35 toward the second surface S2 side of the semiconductor layer 21 and extend toward the second surface S2 side of the semiconductor layer 21. The conductor 41 is formed on the first surface S1 side of the semiconductor layer so as to contact the n-type semiconductor region 38 on the side surface of the semiconductor layer 21 inside the deep carved portion 36 (the side surface of the photoelectric conversion region 22).

[0129] The isolation insulating film 39 inside the deep recessed portion 36 can be formed, for example, by depositing an insulating film over the entire surface of the first surface S1 side of the semiconductor layer 21 including the inside of the deep recessed portion 36, and then selectively removing the insulating film outside the first surface S1 of the semiconductor layer 21 by a CMP method, an etch-back method, or the like, so that the insulating film selectively remains inside the deep recessed portion 36. For example, a silicon oxide film can be used as the insulating film.

[0130] The conductor 41 inside the deep recess 36 can be formed, for example, by depositing a conductive film over the entire surface of the first surface S1 of the semiconductor layer 21, including the inside of the deep recess 36, and then selectively removing the conductive film outside the first surface S1 of the semiconductor layer 21 by a CMP method, an etch-back method, or the like, so that the conductive film selectively remains inside the deep recess 36. As the conductive film, for example, a polycrystalline silicon film (doped polysilicon film) doped with impurities that reduce the resistivity can be used.

[0131] In this step, the inter-pixel isolation region 31, which includes the deep recess 36, the isolation insulating film 39, and the conductor 41 and which separates the photoelectric conversion region 22, is formed.

[0132] 9H , an isolation insulating film 42 is formed inside the shallow recessed portion 35. The isolation insulating film 42 is formed so as to fill the shallow recessed portion 35. The isolation insulating film 42 inside the shallow recessed portion 35 can be formed, for example, by depositing an insulating film over the entire surface of the first surface S1 of the semiconductor layer 21, including the inside of the shallow recessed portion 35, and then selectively removing the insulating film outside the first surface S1 of the semiconductor layer 21 by a CMP method, an etch-back method, or the like, so that the insulating film selectively remains inside the shallow recessed portion 35. The insulating film can be, for example, a silicon oxide film.

[0133] In this step, the field isolation region 32 is formed, which includes the shallow recess 35 and the isolation insulating film 42 and separates the element forming regions 43b and 43a. Also in this step, the conductor 41 is covered with the isolation insulating film 42.

[0134] Next, as shown in FIG. 9I, a pixel transistor Q is formed in the element formation region 43b of the photoelectric conversion region 22, and although not shown in FIG. 9I, as will be explained with reference to FIG. 7, a transfer transistor TR, an n-type floating diffusion region FD, and a p-type power supply contact region WC are each formed in the element formation region 43a of the photoelectric conversion region 22.

[0135] Next, as shown in FIG. 9I, an interlayer insulating film 52 and a contact electrode 53a are formed on the first surface S1 side of the semiconductor layer 21. １ , 53a ２ , 53f, 53r １ , 53r ２ , 53w and a first wiring layer 54, and a contact electrode 53x is formed.

[0136] 9J , after the multilayer wiring layer 51 and the contact electrodes 53x are formed, a thinning step is performed in which the second surface S2 side of the semiconductor layer 21 is cut up to the thinning line S2a by, for example, a CMP method to thin the thickness of the semiconductor layer 21. In this step, an inter-pixel isolation region 31 is formed, which extends from the first surface S1 side of the semiconductor layer 21 along the thickness direction (Z direction) of the semiconductor layer 21 and reaches the second surface S2 of the semiconductor layer 21.

[0137] Thereafter, a planarization film 61, an optical filter layer 63, and a lens layer 64 are formed in this order on the second surface S2 side of the semiconductor layer 21, resulting in the states shown in FIGS. 6A to 8.

[0138] <Major Effects of First Embodiment> Next, major effects of the first embodiment will be described. The solid-state imaging device 1A according to the first embodiment includes a photoelectric conversion region 22 that is partitioned by an inter-pixel isolation region 31 and provided in a semiconductor layer 21. The photoelectric conversion region 22 includes a photoelectric conversion unit 25 including an n-type semiconductor region 24 that is provided spaced apart from the inter-pixel isolation region 31 and the first surface portion S1 of the semiconductor layer 21, an n-type semiconductor region 38 that is provided between the inter-pixel isolation region 31 and the n-type semiconductor region 24, and a p-type semiconductor region 37 that is provided between the n-type semiconductor region 38 and the n-type semiconductor region 24. The n-type semiconductor region 38 is connected to a conductor 41 to which a potential is applied.

[0139] In the solid-state imaging device 1A having such a configuration, by applying the second reference potential to the conductor 41, the n-type semiconductor region 38 functions as a drain region, and dark current that has welled up at the interface between the inter-pixel isolation region 31 and the photoelectric conversion region 22 can be swept away in the n-type semiconductor region 38. This makes it possible to further suppress the intrusion of dark current into the photoelectric conversion unit 25 of the photoelectric conversion region 22, compared to the conventional technology in which a p-type semiconductor region is provided as a pinning layer at the interface between a recessed isolation region and the photoelectric conversion region. Therefore, the solid-state imaging device 1A according to the first embodiment can achieve even higher image quality.

[0140] Furthermore, since the p-type semiconductor region 37 is provided between the n-type semiconductor region 38 and the n-type semiconductor region 24, the expansion of the depletion layer from the n-type semiconductor region 38 to the n-type semiconductor region 24 can be suppressed by the p-type semiconductor region 37, and the decrease in the saturation signal amount Qs due to the expansion of the depletion layer can be suppressed.

[0141] Modification of First Embodiment Modification 1-1 FIG. 10 is a plan view schematically showing a part of a pixel array unit, showing Modification 1-1 according to the first embodiment of the present technology.

[0142] In the above-described embodiment, as shown in Figures 1 and 6A, a contact electrode 53x is provided for each pixel block 15, and electrical connection between the wiring 54x of the multilayer wiring layer 51 and the conductor 41 is made for each pixel block 15.

[0143] In contrast, in this variant 1-1, as shown in Figure 10, contact electrodes 53x are provided around the periphery of the pixel array section 2A, and electrical connection between the wiring 54x of the multilayer wiring layer 51 and the conductor 41 is made around the periphery of the pixel array section 2A.

[0144] The present technology can also be applied to this modified example 1-1, and the same effects as those of the first embodiment described above can be obtained.

[0145] <Modification 1-2> FIG. 11 is a plan view schematically showing a part of a pixel array unit according to Modification 1-2 of the first embodiment of the present technology.

[0146] 11 , in this modification 1-2, a contact electrode 53x is provided for each pixel block group 18, with four pixel blocks 15 arranged two by two in each of the X and Y directions, and electrical connection is made between the wiring 54x of the multilayer wiring layer 51 and the conductor 41 for each pixel block group 18. The contact electrode 53x is then disposed in the center of the pixel block group 18 in plan view, specifically in the center surrounded by the four pixel blocks 15.

[0147] The present technology can also be applied to this modified example 1-2, and the same effects as those of the first embodiment described above can be obtained.

[0148] <Modification 1-3> FIG. 12 is a plan view schematically showing a part of a pixel array unit according to Modification 1-3 of the first embodiment of the present technology.

[0149] As shown in Figure 12, in this variant 1-3, as in the first embodiment described above, a contact electrode 53x is provided for each pixel block 15, and contact electrodes 53x are also provided between pixel blocks 15 adjacent to each other in a planar view, so that electrical connection between the wiring 54x of the multilayer wiring layer 51 and the conductor 41 is made by more contact electrodes 53x.

[0150] The present technology can also be applied to this modified example 1-3, and the same effects as those of the first embodiment can be obtained. Furthermore, in this modified example 1-3, since a larger number of contact electrodes 53x are provided compared to the first embodiment, the connection resistance between the wiring 54x of the multilayer wiring layer 51 and the conductor 41 can be reduced.

[0151] <Modification 1-4> In the above-described first embodiment and modifications 1-1 to 1-3, the case where the first-layer wiring of the multilayer wiring layer 51 and the conductor 41 are electrically connected by the contact electrode 53x has been described. However, the present technology can also be applied to the case where the second-layer wiring or the third-layer wiring of the multilayer wiring layer 51 is connected to the conductor 41.

[0152] <Modification 1-5> FIG. 13 is a modification 1-5 according to the first embodiment of the present technology, and is a schematic cross-sectional view of a cross-sectional pattern of a conductor in a cross section perpendicular to the thickness direction of a semiconductor layer.

[0153] In the first embodiment described above, the conductor 41 is configured in a grid-like planar pattern as shown in FIG.

[0154] 13, in this modified example 1-5, stripe-shaped (linear) conductors 41 extending in the X direction are repeatedly arranged in the Y direction in a planar pattern. The conductors 41 in this modified example 2-5 are provided for each first planar extending portion 31x of the inter-pixel isolation region 31 in a planar view. Although not shown in detail, the conductors 41 in this modified example 1-5 are also electrically and mechanically connected to the n-type semiconductor region 38 at the side portions of the photoelectric conversion region 22.

[0155] The present technology can also be applied to this modified example 1-5, and the same effects as those of the first embodiment described above can be obtained.

[0156] <Modification 1-6> FIG. 14 is a modification 1-6 according to the first embodiment of the present technology, and is a schematic cross-sectional view of a cross-sectional pattern of a conductor in a cross section perpendicular to the thickness direction of the semiconductor layer.

[0157] 14, in this modified example 1-6, stripe-shaped (linear) conductors 41 extending in the Y direction are configured in a planar pattern repeatedly arranged in the X direction. The conductors 41 in this modified example 1-6 are provided for each second planar extending portion 31y of the inter-pixel isolation region 31 in plan view. Although not shown in detail, the conductors 41 in this modified example 1-6 are also electrically and mechanically connected to the n-type semiconductor region 38 at the side portions of the photoelectric conversion region 22.

[0158] The present technology can also be applied to this modified example 1-6, and the same effects as those of the first embodiment described above can be obtained.

[0159] <Modification 1-7> FIG. 15 is a modification 1-7 according to the first embodiment of the present technology, and is a schematic cross-sectional view of a cross-sectional pattern of a conductor in a cross section perpendicular to the thickness direction of the semiconductor layer.

[0160] 15, this modified example 1-7 has a configuration in which a plurality of conductors 41 are scattered. The conductors 41 of this modified example 1-7 are provided in each region surrounded by the corners of four photoelectric conversion regions 22 that are adjacent to each other in a plan view. Although not shown in detail, the conductors 41 of this modified example 1-7 are also electrically and mechanically connected to the n-type semiconductor region 38 at the side portions of the photoelectric conversion regions 22.

[0161] The present technology can also be applied to this modified example 1-7, and the same effects as those of the first embodiment described above can be obtained.

[0162] The conductors 41 may be interspersed between two photoelectric conversion regions 22 (pixels 3) that are adjacent to each other in a plan view.

[0163] <Modification 1-8> FIG. 16 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-8 of the first embodiment of the present technology.

[0164] In the first embodiment described above, the conductor 41 is provided on the first surface S1 side of the semiconductor layer 21, as shown in FIG. 6A . In contrast, in Modification 1-8, as shown in FIG. 16 , the conductor 41 extends from the first surface S1 side to the second surface S2 side of the semiconductor layer 21. That is, the conductor 41 in Modification 1-8 is provided from the first surface S1 side to the second surface S2 side of the semiconductor layer 21. In Modification 1-8, in a vertical cross section along the thickness direction (Z direction) of the semiconductor layer 21, one end of the conductor 41 on the first surface S1 side of the semiconductor layer 21 is separated from the first surface S1 of the semiconductor layer 21, and the other end on the second surface S2 side of the semiconductor layer 21 reaches the planarization film 61. The conductor 41 of this variant 1-8 is electrically and mechanically connected to the n-type semiconductor region 38 on the side of the photoelectric conversion region 22 across the first surface S1 side and the second surface S2 side of the semiconductor layer 21.

[0165] The present technology can also be applied to this modified example 1-8, and the same effects as those of the first embodiment described above can be obtained.

[0166] Furthermore, since the conductor 41 of this modified example 1-8 is provided across the first surface S1 side and the second surface S2 side of the semiconductor layer 21, the potential difference between the first surface S1 side and the second surface S2 side of the semiconductor layer 21 in the n-type semiconductor region 38 can be reduced, and the discharge of dark current into the n-type semiconductor region 38 can be made more uniform than in the first embodiment described above.

[0167] <Modification 1-9> FIG. 17 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-9 of the first embodiment of the present technology.

[0168] 17, in Modification 1-9, a light-shielding film 62 is electrically connected to the conductor 41 of Modification 1-8 via a back surface contact electrode 62a. The conductor 41 of Modification 1-9 is electrically connected to the wiring 54x of the multilayer wiring layer 51 via a contact electrode 53x on the first surface S1 side of the semiconductor layer 21, and is electrically connected to the light-shielding film 62 via a back surface contact electrode 62a on the second surface S2 side of the semiconductor layer 21. A potential similar to that of the wiring 54x is applied (supplied) to the light-shielding film 62 of Modification 1-9 without going through the conductor 41. That is, a potential is applied (supplied) to the conductor 41 of Modification 1-9 from both the first surface S1 side and the second surface S2 side of the semiconductor layer 21.

[0169] The back surface contact electrode 62a is provided in the planarization film 61 and penetrates the planarization film 61 in the thickness direction thereof. As the back surface contact electrode 62a, a film containing a high-melting point metal material such as tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), or tantalum (Ta), or a film containing a metal material such as aluminum (Al) or copper (Cu) can be used.

[0170] The present technology can also be applied to this modified example 1-9, and the same effects as those of the first embodiment described above can be obtained.

[0171] Furthermore, since a potential is applied to the conductor 41 of this modification 1-9 from both the first surface S1 side and the second surface S2 side of the semiconductor layer 21, the potential difference between the first surface S1 side and the second surface S2 side of the semiconductor layer 21 in the n-type semiconductor region 38 can be made smaller than in the above-mentioned modification 1-8, and the dark current can be swept away more uniformly into the n-type semiconductor region 38.

[0172] As shown in FIG. 17, in this modification 1-9, for example, the back contact electrode 62a is arranged at a position overlapping the contact electrode 53x in a planar view, but the back contact electrode 62a may be arranged in the same manner as the contact electrode 53x shown in each of the above-mentioned modifications 1-1 to 1-3.

[0173] <Modification 1-10> FIG. 18 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-10 of the first embodiment of the present technology.

[0174] 18, in this modification 1-10, a conductor 41 is provided on the second surface S2 side of the semiconductor layer 21. In addition, in this modification 1-10, a light-shielding film 62 is electrically connected to the conductor 41 on the second surface S2 side of the semiconductor layer 21 via a back surface contact electrode 62a. A potential similar to that of the wiring 54x in the first embodiment is applied (supplied) to the light-shielding film 62 in this modification 1-9. That is, unlike in the first embodiment, a potential is applied (supplied) to the conductor 41 in this modification 1-10 from the second surface S2 side of the semiconductor layer 21.

[0175] The inter-pixel isolation region 31 of this modified example 1-10 includes a deep carved portion 36 and an isolation insulating film 42 provided inside this deep carved portion 36. The isolation insulating film 42 of this modified example 1-10 is provided so as to fill the inside of both the shallow carved portion 35 and the deep carved portion 36.

[0176] The conductor 41 of this modification 1-8 is electrically and mechanically connected to the n-type semiconductor region 38 at the side surface of the photoelectric conversion region 22 on the second surface S2 side of the semiconductor layer 21.

[0177] The present technology can also be applied to this modified example 1-10, and the same effects as those of the first embodiment described above can be obtained.

[0178] As in the first embodiment, different isolation insulating films may be used for the deep recessed portion 36 and the shallow recessed portion 35 .

[0179] <Modification 1-11> FIG. 19 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-11 of the first embodiment of the present technology.

[0180] As shown in FIG. 19, this modification 1-11 differs from the above-described modification 1-10 in the connection form between the conductor 41 and the light-shielding film 62.

[0181] 19, in this modified example 1-11, the light-shielding film 62 is directly connected to the conductor 41. The light-shielding film 62 reaches the conductor 41 from the optical filter layer 63 side of the planarization film 61 through the connection hole of the planarization film 61, and is electrically and mechanically connected to the conductor 41.

[0182] The present technology can also be applied to this modified example 1-11, and the same effects as those of the first embodiment described above can be obtained.

[0183] <Modification 1-12> FIG. 20 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-12 of the first embodiment of the present technology.

[0184] 20, in this modification 1-12, the material of the conductor 41 is changed from the doped polysilicon film to a metal film 41a. As the metal film 41a, it is preferable to use a metal film having a refractive index smaller than that of the semiconductor layer 21.

[0185] The present technology can also be applied to this modified example 1-12, and the same effects as those of the first embodiment described above can be obtained.

[0186] <Modification 1-13> FIG. 21 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-11 of the first embodiment of the present technology.

[0187] 21 , in this modification 1-14, a contact electrode 53x serving as a conductor is directly connected to the n-type semiconductor region 38. The contact electrode 53x penetrates the interlayer insulating film 52 and the isolation insulating film 42, and reaches the inside of the deep recess 36 of the inter-pixel isolation region 31. One end of the contact electrode 53x is electrically and mechanically connected to the wiring 54x, and the other end is electrically and mechanically connected to the n-type semiconductor region 38 on the side surface of the photoelectric conversion region 22.

[0188] Similar to the above-described modification 1-10, the inter-pixel isolation region 31 of this modification 1-13 includes a deep carved portion 36 and an isolation insulating film 42 provided inside this deep carved portion 36. The isolation insulating film 42 of this modification 1-13 is provided so as to fill the insides of both the shallow carved portion 35 and the deep carved portion 36.

[0189] In this modification 1-13, the contact electrode 53x corresponds to a specific but not limitative example of "electrical conductor" of the present technology.

[0190] The present technology can also be applied to this modified example 1-13, and the same effects as those of the first embodiment described above can be obtained.

[0191] As in the first embodiment, different isolation insulating films may be used for the deep recessed portion 36 and the shallow recessed portion 35 .

[0192] <Modification 1-14> FIG. 22 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-11 of the first embodiment of the present technology.

[0193] As shown in FIG. 22, this modification 1-14 has the contact electrode 53x of the above-described modification 1-13 and a conductor 65 provided on the second surface S2 side of the semiconductor layer 21.

[0194] The conductor 65 penetrates the planarization film 61 in its film thickness direction (Z direction) and enters the deep recessed portion 36 of the inter-pixel isolation region 31. One end of the conductor 65 (the light-shielding film 62 side) is electrically and mechanically connected to the light-shielding film 62, and the other end (the deep recessed portion 36 side) is electrically and mechanically connected to the n-type semiconductor region 38 on the side surface of the photoelectric conversion region 22. A potential similar to that of the wiring 54x is applied (supplied) to the conductor 65 via the light-shielding film 62. That is, a potential is applied (supplied) to the n-type semiconductor region 38 of this modification 1-14 from both the first surface S1 side and the second surface S2 side of the semiconductor layer 21.

[0195] The inter-pixel isolation region 31 of this modified example 1-14 includes a deep carved portion 36 and an isolation insulating film 42 provided inside this deep carved portion 36. The isolation insulating film 42 of this modified example 1-14 is provided so as to fill the insides of both the shallow carved portion 35 and the deep carved portion 36.

[0196] The present technology can also be applied to this modified example 1-14, and the same effects as those of the first embodiment described above can be obtained.

[0197] Furthermore, since a potential is applied to the n-type semiconductor region 38 of this modified example 1-9 from both the first surface S1 side and the second surface S2 side of the semiconductor layer 21, similarly to the above-described modified example 1-9, the potential difference between the first surface S1 side and the second surface S2 side of the semiconductor layer 21 in the n-type semiconductor region 38 can be made smaller than in the above-described modified example 1-8, and the discharge of dark current into the n-type semiconductor region 38 can be made more uniform.

[0198] <Modification 1-15> FIG. 23 is a plan view schematically showing one pixel block, illustrating Modification 1-15 according to the first embodiment of the present technology.

[0199] As shown in FIG. 8, the inter-pixel isolation region 31 of the first embodiment described above is configured in a ring shape that continuously surrounds the photoelectric conversion region 22 in a plan view.

[0200] In contrast, as shown in Fig. 23, the inter-pixel isolation region 31 of Modification 1-15 is configured to surround the photoelectric conversion region 22 in a plan view and to have discontinuities 33 provided in places. In other words, the inter-pixel isolation region 31 of Modification 1-15 is configured such that the continuity surrounding the photoelectric conversion region 22 in a plan view is interrupted by the discontinuities 33. In Fig. 23, as an example, two discontinuities 33 are provided per pixel 3, but the number of discontinuities 33 is not limited to two.

[0201] The present technology can also be applied to this modified example 1-15, and the same effects as those of the first embodiment described above can be obtained.

[0202] <Modification 1-16> In the above-described first embodiment, the case where the n-type semiconductor region 24 and the p-type semiconductor region 37 are in contact with each other has been described, but the present technology can also be applied to a case where a p-type well region 23 is provided between the p-type semiconductor region 37 and the n-type semiconductor region 24.

[0203] [Second Embodiment] Fig. 24 is a plan view schematically showing a configuration example of one pixel block in a solid-state imaging device according to a second embodiment of the present technology. Fig. 25 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a24-a24 cutting line in Fig. 24. A solid-state imaging device 1B according to the second embodiment of the present technology is basically configured similarly to the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration. That is, as shown in Figs. 24 and 25, a pair of main electrode regions 48a of a pixel transistor Q １ and 48a ２ The main electrode region 48a ２ is electrically and physically (structurally) connected to the n-type semiconductor region 38. In Fig. 25, as an example, the amplification transistor AMP and the reset transistor RST of the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16 are illustrated. Each of the amplification transistor AMP and the reset transistor RST is connected to a pair of main electrode regions 48a １ and 48a ２ Among these, the main electrode region 48a functions as a drain region. ２ The n-type semiconductor region 38 is fixed at the Vdd potential as the second reference potential.

[0204] In the second embodiment, the main electrode regions 48a of the amplifier transistor AMP and the reset transistor RST are ２ corresponds to a specific example of "a conductor to which a potential is applied" in the present technology.

[0205] In the solid-state imaging device 1B according to the second embodiment, the main electrode regions 48a of the amplification transistor AMP and the reset transistor RST are ２By applying a Vdd potential as the second reference potential to the n-type semiconductor region 38, dark current that has welled up at the interface between the inter-pixel isolation region 31 and the photoelectric conversion region 22 can be swept away into the n-type semiconductor region 38, and therefore, compared to the conventional technology in which a p-type semiconductor region is provided as a pinning layer at the interface between the recessed isolation region and the photoelectric conversion region, it is possible to further suppress the intrusion of dark current into the photoelectric conversion unit 25 of the photoelectric conversion region 22. Therefore, in the solid-state imaging device 1B according to the second embodiment, it is possible to achieve even higher image quality, as with the solid-state imaging device 1A according to the first embodiment described above.

[0206] [Third Embodiment] In this third embodiment, an example of applying the present technology to a stacked-type photodetector device in which semiconductor layers are stacked in multiple stages, for example, a two-stage stacked-type solid-state imaging device in which two semiconductor layers are stacked in two stages, will be described.

[0207] Fig. 26 is a plan view schematically showing a configuration example of one pixel block in a solid-state imaging device according to a third embodiment of the present technology. Fig. 27 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a26-a26 cutting line in Fig. 26. Note that Fig. 26 omits illustration of layers above the gate electrode shown in Fig. 27.

[0208] As shown in Figures 26 and 27, the solid-state imaging device 1C of the third embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A of the first embodiment described above, with the following differences in configuration.

[0209] 26 and 27 , the solid-state imaging device 1C according to the third embodiment further includes a semiconductor layer 81 provided on the first surface S1 side of the semiconductor layer 21 with an insulating layer 71 interposed therebetween, and an insulating layer 91 provided on the side of the semiconductor layer 81 opposite the insulating layer 71 side. Unlike the first embodiment described above, the solid-state imaging device 1C according to the third embodiment includes a pixel transistor Q included in the pixel circuit 16 (see FIG. 3 ) provided in the semiconductor layer 81. In FIG. 27 , an amplification transistor AMP and a switching transistor FDG are illustrated as examples of the pixel transistor Q.

[0210] 26 and 27 , the photoelectric conversion unit 25, the transfer transistor TR, and the floating diffusion region FD are each provided on a side of the semiconductor layer 21 that is different from the semiconductor layer 81. The solid-state imaging device 1C of the third embodiment has the semiconductor layer 21 and the semiconductor layer 81 stacked with an insulating layer 71 interposed therebetween in the thickness direction (Z direction) of the semiconductor layer 21, which is one direction.

[0211] In the third embodiment, the semiconductor layer 21 corresponds to a specific example of a "first semiconductor layer" in the present technology, and the semiconductor layer 81 corresponds to a specific example of a "second semiconductor layer" in the present technology.

[0212] 27 , the solid-state imaging device 1C according to the third embodiment further includes a conductive path 96 that electrically connects the floating diffusion region FD provided on the semiconductor layer 21 side to the amplification transistor AMP and the reset transistor RST provided in the semiconductor layer 81. The solid-state imaging device 1C according to the third embodiment further includes a relay conductive pad 49 that is provided on the first surface portion S1 side of the semiconductor layer 21 across the photoelectric conversion region 22 and the inter-pixel isolation region 31 and is electrically connected to the floating diffusion region FD of the photoelectric conversion region 22.

[0213] The conductive path 96 includes a relay conductive pad 49 that is provided across the photoelectric conversion region 22 and the inter-pixel isolation region 31 on the first surface portion S1 side of the semiconductor layer 21 and is electrically connected to the floating diffusion region FD of the photoelectric conversion region 22, and a through-contact electrode 92 that extends from the insulating layer 91 to the relay conductive pad 49 in the stacking direction (Z direction) of the semiconductor layer 21 and the semiconductor layer 81 and is connected to the relay conductive pad 49. The conductive path 96 also includes a contact electrode 93 that is embedded in the insulating layer 91 and is connected to the gate electrode 47 of the amplifier transistor AMP, and a main electrode region 48a that is embedded in the insulating layer 91 and functions as the source region of the reset transistor RST. １ and a wiring 95 provided on the side of the insulating layer 91 opposite the semiconductor layer 81 side and electrically and mechanically connected to each of the through contact electrode 92 and the contact electrodes 93 and 94.

[0214] The wiring 95 may be formed of, for example, a metal film such as aluminum (Al) or copper (Cu), or an alloy film mainly containing Al or Cu. The insulating layer 91 may be formed of, for example, a silicon oxide film. The insulating layer 71 includes, for example, two insulating films 73 and 75. These two insulating films 73 and 75 may be formed of, for example, silicon oxide films. The semiconductor layer 81 may be formed of, for example, a Si substrate, a SiGe substrate, or an InGaAs substrate. In the second embodiment, the semiconductor layer 81 is formed of, for example, a p-type semiconductor substrate made of single crystal silicon, although this is not limited thereto.

[0215] The through contact electrode 92 is electrically insulated and separated from the semiconductor layer 81. A high-melting point metal film such as titanium (Ti) or tungsten (W) can be used for each of the through contact electrode 92 and the contact electrodes 93 and 94. A polycrystalline silicon film doped with impurities that reduce resistance can be used for the relay conductive pad 49.

[0216] The solid-state imaging device 1C according to the third embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above. That is, the present technology can also be applied to a two-stage stacked solid-state imaging device 1C in which two semiconductor layers 21 and 81 are stacked in two stages.

[0217] Although not shown, the present technology can also be applied to a multi-layer stacked solid-state imaging device in which three or more semiconductor layers are stacked in multiple stages.

[0218] [Fourth Embodiment] In this fourth embodiment, an example in which the present technology is applied to a solid-state imaging device including phase difference pixels will be described. Fig. 28 is a plan view schematically showing a configuration example of one pixel block in a solid-state imaging device according to the fourth embodiment of the present technology. Fig. 29 is a cross-sectional view schematically showing a cross-sectional pattern of a conductor in a cross section orthogonal to the thickness direction of a semiconductor layer in the pixel block of Fig. 28.

[0219] A solid-state imaging device 1D according to the fourth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the pixel 3. The other configurations are generally the same as those of the first embodiment described above.

[0220] That is, as shown in FIGS. 5 and 8, the pixel 3 of the first embodiment described above has a configuration in which one photoelectric conversion section 25 (PD) is provided in one photoelectric conversion region 22.

[0221] 28 and 29 , the pixel 3 of the fourth embodiment is configured as a phase difference pixel that detects a phase difference between two photoelectric conversion units 25 provided in one photoelectric conversion region 22. The present technology can also be applied to a solid-state imaging device 1D that includes such a phase difference pixel.

[0222] 28 and 29 , the photoelectric conversion region 22 of the fourth embodiment includes a first photoelectric conversion cell 22L and a second photoelectric conversion cell 22R that are adjacent to each other in the X direction in a plan view and are provided in the semiconductor layer 21. The photoelectric conversion region 22 of the fourth embodiment further includes a separation barrier 66 that is provided between the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R in a plan view and that extends in the thickness direction of the semiconductor layer 21.

[0223] Each of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R is partitioned by an inter-pixel isolation region 31 and an isolation barrier 66, and includes a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion unit 25, a transfer transistor TR, an n-type floating diffusion region FD, a p-type power supply contact region WC, and a pixel transistor Q. Each of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R further includes an n-type semiconductor region 38 and a p-type semiconductor region 37.

[0224] 28 and 29 , the separation barriers 66 protrude inward from the middle of each of the two first planar extending portions 31x that extend in the X direction across the photoelectric conversion region 22 in a plan view, and are spaced apart from each other in the Y direction. That is, in the photoelectric conversion region 22 of the fourth embodiment, the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R that are adjacent to each other in the X direction are selectively separated by the two separation barriers 66 that protrude inward from the middle of each of the two first planar extending portions 31x that extend in the X direction.

[0225] Although not limited to this, each of the two isolation barriers 66 includes, for example, a deep recessed portion 36 and an isolation insulating film 39 provided inside this deep recessed portion 36, similar to the inter-pixel isolation region 31, and is integrated with and connected to the inter-pixel isolation region 31. Therefore, on the side surface of each of the two isolation barriers 66, an n-type semiconductor region 38 and a p-type semiconductor region 37 are provided in this order from the side surface side.

[0226] <Autofocus> In an electronic device equipped with the solid-state imaging device 1D of this fourth embodiment, the signal charges of the two photoelectric conversion units 25, 25 provided in one photoelectric conversion region 22 are read out for each pixel 3, and the phase difference therebetween is detected.

[0227] When the focus is correct, there is no difference in the amount of signal charge accumulated in the two photoelectric conversion units 25 included in one photoelectric conversion region 22. In contrast, when the focus is not correct, there is a difference between the amount of signal charge Q1 accumulated in one of the two photoelectric conversion units 25 and the amount of signal charge Q2 accumulated in the other photoelectric conversion unit 25. When the focus is not correct, the electronic device performs an operation such as moving the objective lens so that Q1 and Q2 coincide with each other. This is autofocus.

[0228] <Flow of Signal Charges> In the photoelectric conversion region 22 of the fourth embodiment, the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R are partially separated from each other except for the area between the two isolation barriers 66. The p-type well regions 23 of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R are connected between the two isolation barriers 66. Therefore, the p-type well regions 23 between the isolation barriers 66 function as an overflow path.

[0229] A first potential barrier can be formed in the well region 23 between the two isolation barriers 66. The transfer transistor TR of the first photoelectric conversion cell 22L can form a second potential barrier higher than the first potential barrier when not transferring signal charges from the photoelectric conversion unit 25 to the floating diffusion region FD. Furthermore, the transfer transistor TR of the second photoelectric conversion cell 22R can form a second potential barrier higher than the first potential barrier when not transferring signal charges from the photoelectric conversion unit 25 to the floating diffusion region FD.

[0230] The photoelectric conversion units 25, 25 of each of the first and second photoelectric conversion cells 22L, 22R can independently accumulate signal charges up to the height of the first potential barrier. When the amount of accumulated signal charges exceeds the height of the first potential barrier, the signal charges flow from one of the photoelectric conversion units 25 of each of the first and second photoelectric conversion cells 26L, 22R to the other via the overflow path between the two separation barriers 48.

[0231] The present technology can also be applied to the solid-state imaging device 1D according to the fourth embodiment, and the same effects as those of the solid-state imaging device 1A according to the first embodiment described above can be obtained.

[0232] [Fifth Embodiment] Fig. 30 is an equivalent circuit diagram showing an example of a circuit included in a pixel of a solid-state imaging device according to a fifth embodiment of the present technology. Fig. 31 is a plan view schematically showing a plane pattern of a pixel of a solid-state imaging device according to the fifth embodiment of the present technology. Fig. 32 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a31-a31 cutting line in Fig. 31. Fig. 33 is a transverse sectional view schematically showing a transverse sectional structure taken along the a32-a32 cutting line in Fig. 32.

[0233] 5 of the first embodiment described above, Fig. 31 is a plan view seen from the multilayer wiring layer side opposite to the light incident surface side of the semiconductor chip 2. In Fig. 32, for ease of viewing, layers above the first wiring layer 54 included in the multilayer wiring layer 51 are omitted from the illustration, similar to Fig. 6A of the first embodiment described above.

[0234] As shown in Figures 30 to 33 , a solid-state imaging device 1E according to a fifth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, with the following differences. That is, the solid-state imaging device 1E according to the fifth embodiment mainly includes a pixel 3E and an inter-pixel isolation region 110 shown in Figures 30 to 33 instead of the pixel 3 and inter-pixel isolation region 31 shown in Figures 3 to 8 of the first embodiment described above. The solid-state imaging device 1E according to the fifth embodiment also includes an n-type epitaxial layer 112 as a charge discharge layer instead of the n-type semiconductor region 38 shown in Figure 6B of the first embodiment described above. In this fifth embodiment, the n-type epitaxial layer 112 corresponds to a specific example of a "charge discharge layer" according to the present technology. The other configurations are generally similar to those of the first embodiment described above. The solid-state imaging device 1E according to the fifth embodiment will be specifically described below.

[0235] <<Specific Configuration of Photoelectric Conversion Device>> <Pixel> As shown in FIG. 30 , a pixel 3E of the fifth embodiment, like the pixel 3 of the first embodiment, includes a photoelectric conversion unit 25 and an n-type floating diffusion region (floating diffusion region) FD as a charge retention unit that retains (accumulates) signal charges photoelectrically converted by the photoelectric conversion unit 25. The pixel 3E of the fifth embodiment includes a transfer transistor TRL and a pixel circuit (readout circuit) 16E instead of the transfer transistor TR and pixel circuit (readout circuit) 16 shown in FIG. 3 of the first embodiment. The pixel 3E of the fifth embodiment also includes a photoelectric conversion region 22E shown in FIGS. 31 and 32 instead of the photoelectric conversion region 22 shown in FIGS. 5 and 6A of the first embodiment. The photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TRL are each provided in the photoelectric conversion region 22E. Furthermore, the pixel transistor Q included in the pixel circuit 16E is also provided in the photoelectric conversion region 22E, similar to the first embodiment described above.

[0236] 30 shows a pixel circuit 16E, whose input side is electrically connected to the floating diffusion region FD of the pixel 3E. Unlike the pixel circuit 16 of the first embodiment described above, the pixel circuit 16E of this first embodiment is provided, for example, for each pixel 3E. This pixel circuit 16E also reads out the signal charge held in the floating diffusion region FD of the pixel 3E and outputs a pixel signal based on the read-out signal charge. In other words, the pixel circuit 16E also converts the signal charge photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on this signal charge and outputs it.

[0237] As shown in Fig. 30, the pixel circuit 16E of the fifth embodiment has a circuit configuration in which a switching transistor FCG is newly added to the configuration of the pixel circuit 16 of the first embodiment shown in Fig. 3. That is, the pixel circuit 16E of the fifth embodiment includes, as pixel transistors Q that constitute the circuit, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and two switching transistors FCG and FDG.

[0238] The switching transistor FCG has a source region electrically connected to the drain region of the switching transistor FDG, a drain region electrically connected to the source region of the reset transistor RST, and a gate electrode electrically connected to the first switching transistor drive line of the pixel drive lines 10 shown in FIG.

[0239] The switching transistor FDG has a source region electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion region FD, and a drain region electrically connected to the source region of the switching transistor FCG. The gate electrode of the switching transistor FDG is electrically connected to the second switching transistor drive line of the pixel drive line 10 shown in FIG. 2 of the first embodiment described above.

[0240] 30, like the switching transistor FDG of the first embodiment, controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP. By switching on / off each of these two switching transistors FCG and FDG, the FD capacitance can be made variable and the conversion efficiency can be switched, like the pixel circuit 16 of the first embodiment.

[0241] 32 , the semiconductor layer 21 includes an inter-pixel isolation region 110 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22E partitioned by the inter-pixel isolation region 110. The photoelectric conversion region 22E is provided for each pixel 3. Similarly to the first embodiment, the photoelectric conversion region 22E includes a first surface portion S1 and a second surface portion S2 of the semiconductor layer 21. The semiconductor layer 21 may be formed of a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the fifth embodiment, although not limited thereto, an n-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21.

[0242] 31 , the inter-pixel isolation region 110 includes a first planar extending portion 110x extending in the X direction in a plan view and a second planar extending portion 110y extending in the Y direction, as in the first embodiment described above. The inter-pixel isolation region 110 further includes an intersection portion (point of intersection) where the first planar extending portion 110x and the second planar extending portion 110y intersect with each other on the same plane. In this fifth embodiment, the first planar extending portion 110x and the second planar extending portion 110y are also orthogonal to each other, for example.

[0243] The first planar extending portions 110x are repeatedly arranged at predetermined intervals in the Y direction. The second planar extending portions 110y are repeatedly arranged at predetermined intervals in the X direction. That is, the inter-pixel isolation region 110 of the fifth embodiment also has a grid-like planar pattern in plan view.

[0244] 31 , the inter-pixel isolation region 110 corresponding to one photoelectric conversion region 22E has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22E. That is, the inter-pixel isolation region 110 corresponding to one photoelectric conversion region 22E includes first planar extending portions 110x spaced apart from each other in the Y direction and extending in the X direction, and two second planar extending portions 110y spaced apart from each other in the X direction and extending in the Y direction.

[0245] 32 , the inter-pixel isolation region 110 extends in the thickness direction (Z direction) of the semiconductor layer 21, and electrically and optically isolates two photoelectric conversion regions 22E that are adjacent to each other in a plan view. The inter-pixel isolation region 110 is, for example, an indented type, a so-called trench type, in which an indented portion 111 is formed in the semiconductor layer 21 to partition and isolate the photoelectric conversion regions 22E.

[0246] As shown in FIG. 32 , the inter-pixel isolation region 110 includes, but is not limited to, a recessed portion 111 extending across the first surface S1 and the second surface S2 of the semiconductor layer 21, an n-type epitaxial layer 112 extending along the side surfaces of the semiconductor layer 21 inside the recessed portion 111, and an isolation insulating film 115 provided within the recessed portion 111 via the n-type epitaxial layer 112. That is, unlike the inter-pixel isolation region 31 shown in FIG. 6A of the first embodiment, the inter-pixel isolation region 110 of the fifth embodiment extends across the first surface S1 and the second surface S2 of the semiconductor layer 21. The isolation insulating film 115 may be, for example, a silicon oxide film. In the first embodiment, the recessed portion 111 is filled with, for example, the isolation insulating film 115. The isolation insulating film 115 may be, for example, a silicon oxide film.

[0247] In the fifth embodiment, the inter-pixel isolation region 110 corresponds to a specific but not limitative example of "isolation region" of the present technology.

[0248] 31 , the photoelectric conversion region 22E is surrounded by the inter-pixel isolation region 110 in a plan view and has a rectangular planar shape. Specifically, in the inter-pixel isolation region 110E, the photoelectric conversion region 22E is surrounded by a first planar extension portion 110X that is spaced apart from each other in the Y direction and extends in the X direction, and two second planar extension portions 110y that are spaced apart from each other in the X direction and extend in the Y direction. The photoelectric conversion region 22E is partitioned by the first planar extension portion 110x and the second planar extension portion 110y and is separated from other photoelectric conversion regions 22.

[0249] 32 , the photoelectric conversion region 22E has a p-type well region 23 provided on the first surface S1 side of the semiconductor layer 21, and a p-type well region 23 provided on the second surface S2 side of the semiconductor layer 21. The photoelectric conversion region 22E further has, between the well region 23 on the first surface S1 side of the semiconductor layer 21 and the well region 23 on the second surface S2 side of the semiconductor layer 21, an inter-pixel isolation region 110, an n-type semiconductor region 24 provided spaced apart from each of the first surface S1 and the second surface S2 of the semiconductor layer 21, and a photoelectric conversion unit 25 including this n-type semiconductor region 24.

[0250] The photoelectric conversion region 22E further includes an n-type semiconductor region 24a provided in contact with the n-type semiconductor region 24 in the p-type well region 23 on the first surface S1 side of the semiconductor layer 21. The n-type semiconductor region 24a is for guiding the signal charge photoelectrically converted in the photoelectric conversion unit 25 to the transfer transistor TRL.

[0251] The photoelectric conversion region 22E also has a p-type semiconductor region 37 provided between the inter-pixel isolation region 110 and the n-type semiconductor region 24. The photoelectric conversion region 22E also has an n-type floating diffusion region FD provided on the first surface S1 side of the semiconductor layer 21 and serving as a charge holding section that holds (accumulates) signal charges photoelectrically converted by the photoelectric conversion section 25, and a transfer transistor TRL provided on the first surface S1 side of the semiconductor layer 21 and that transfers the signal charges photoelectrically converted by the photoelectric conversion section 25 to the floating diffusion region FD.

[0252] The photoelectric conversion region 22 also has a field isolation region (inter-element isolation region) 120 provided on the first surface portion side of the semiconductor layer 21, and an island-shaped element formation region 123 partitioned by the field isolation region 120 and the inter-pixel isolation region 110 and provided on the first surface portion S1 of the semiconductor layer 21. The photoelectric conversion region 22E also has a p-type power supply contact region WC provided on the first surface portion S1 side of the semiconductor layer 21 in contact with the p-type well region 23.

[0253] 32 , the p-type well region 23 located on the first surface S1 side of the semiconductor layer 21 is provided over the entire area of ​​the photoelectric conversion region 22. In addition, the p-type well region 23 located on the first surface S1 side of the semiconductor layer 21 is also provided over the entire area of ​​the photoelectric conversion region 22.

[0254] 32 , the n-type semiconductor region 24 has a three-dimensional structure, with its top surface in contact with the upper p-type well region 23, its bottom surface opposite the top surface in contact with the lower p-type well region 23, and its side surface in contact with the p-type semiconductor region 37. The n-type semiconductor region 24 forms a pn junction with the p-type well region 23 and the p-type semiconductor region 37.

[0255] 32 , the photoelectric conversion unit 25 is provided in the photoelectric conversion region 22E. In the photoelectric conversion region 22E, the photoelectric conversion unit 25 includes an n-type semiconductor region 24, and further includes a p-type well region 23 and a p-type semiconductor region 37. The photoelectric conversion unit 25 is configured as a pn junction photodiode (PD) including a pn junction between the p-type well region 23, the p-type semiconductor region 37, and the n-type semiconductor region 24.

[0256] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at a pn junction between the p-type well region 23 and the p-type semiconductor region 37 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is provided for each photoelectric conversion region 22E (pixel 3E) at a distance from the first surface S1 and the second surface S2 of the semiconductor layer 21.

[0257] 32 , the n-type floating diffusion region FD is provided in the p-type well region 23 in the element formation region 123 of the photoelectric conversion region 22E. The n-type floating diffusion region FD overlaps with the n-type semiconductor region 24 in a plan view, and is spaced apart from the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21. That is, the p-type well region 23 is provided between the n-type floating diffusion region FD and the n-type semiconductor region 24. The n-type floating diffusion region FD is composed of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24.

[0258] 32, the field isolation region 120 is provided in the surface layer portion on the upper surface side of the photoelectric conversion region 22E, i.e., the surface layer portion on the first surface portion S1 side of the semiconductor layer. The field isolation region 120 has, but is not limited to, an STI (Shallow Trench Isolation) structure including, for example, a shallow groove portion 121 recessed from the first surface portion S1 to the second surface portion S2 side of the semiconductor layer 21, and an isolation insulating film 122 embedded inside this shallow groove portion 121. The isolation insulating film 122 can be, for example, a silicon oxide film.

[0259] As shown in Figure 31, the field isolation region 120 has an island-shaped planar pattern in which a part of it is connected to the inter-pixel isolation region 110 in a planar view, and another part is separated from the inter-pixel isolation region 110, and together with the inter-pixel isolation region 110, it defines the element formation region 123.

[0260] 31 , the element formation region 123 is partitioned by the inter-pixel isolation region 110 and the field isolation region 120. The element formation region 123 extends in a ribbon shape along the four sides of the photoelectric conversion region 22E in a plan view, and has a planar pattern extending from the outer peripheral edge side to the center of the photoelectric conversion region 22E. As shown in FIG. 32 , a p-type well region 23 is provided in the element formation region 123.

[0261] (P-Type Power Supply Contact Region) As shown in FIG. 31 , the p-type power supply contact region WC is provided on a corner side between two sides of the photoelectric conversion region 22E in a plan view. Although not shown in detail, the p-type power supply contact region WC is provided in a surface layer portion on the upper surface side of the photoelectric conversion region 22E, i.e., on the surface layer portion on the first surface S1 side of the semiconductor layer 21. The p-type power supply contact region WC is provided in an island-shaped power supply region 124 defined by the field isolation region 120 and the inter-pixel isolation region 110 on the upper surface side of the photoelectric conversion region 22E. The p-type power supply contact region WC is composed of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23. The p-type power supply contact region WC is connected to the p-type well region 23 and is electrically conductive. A first reference potential of, for example, 0 V is applied to this p-type power supply contact region WC as a reference potential within the solid-state imaging device 1E during operation, and the potential is fixed to this first reference potential.

[0262] (Power supply region) As shown in Figure 31, the island-shaped power supply region 124 is provided on the corner side (lower left side of Figure 31) where the other first planar extension portion 110x and the other second planar extension portion 110y intersect, out of the two first planar extension portions 110x extending in the X direction and the two second planar extension portions 110y extending in the Y direction of the interpixel isolation region 110 that surrounds the photoelectric conversion region 22E in a planar view.

[0263] (Transfer Transistor) As shown in FIG. 32, the transfer transistor TRL has a horizontal structure (planar type), unlike the transfer transistor TR of the first embodiment shown in FIG. 5A, which has a vertical structure (vertical type).

[0264] 31 and 32 , the transfer transistor TRL is provided in an element formation region 123 in the center of the photoelectric conversion region 22E in a plan view. The transfer transistor TRL has a gate electrode 126t provided outside the first surface portion S1 of the semiconductor layer 21, and a gate insulating film 125 provided between the gate electrode 126t and the semiconductor layer 21. The transfer transistor TRL also has a p-type well region 23 functioning as a channel formation region, and an n-type semiconductor region 24 and an n-type floating diffusion region FD functioning as a source region and a drain region.

[0265] <Pixel Transistors> As shown in FIGS. 31 and 32, the element formation region 123 is provided with a plurality of pixel transistors Q (AMP, SEL, RST, FCG, FDG) included in the pixel circuit 16E described above.

[0266] (Amplification transistor) As shown in Figures 31 and 32, the amplification transistor AMP is provided in the element formation region 123 on the side of one of the two second planar extension portions 110y extending in the Y direction of the inter-pixel isolation region 110 surrounding the photoelectric conversion region 22E in a planar view (the right side of Figure 31).

[0267] The amplifier transistor AMP includes a gate electrode 126a overlapping the element formation region 123 (semiconductor layer 21) in a plan view, and a gate insulating film 125 interposed between the gate electrode 126a and the element formation region 123. The amplifier transistor AMP also includes a pair of main electrode regions 127as and 127ar provided in the element formation region 123 on both sides of the gate electrode 126a in the gate length direction and functioning as a source region and a drain region, and a channel formation region (not shown) provided in the element formation region 123 overlapping the gate electrode 126a in a plan view. The pair of main electrode regions 127as and 127ar are spaced apart from each other in the gate length direction via the channel formation region. The pair of main electrode regions 127as and 127ar are formed of n-type semiconductor regions provided in the element formation region 123, and the channel formation region is formed of a p-type well region 23 provided in the element formation region 123.

[0268] (Selection transistor) As shown in Figure 31, the selection transistor SEL is provided in the element formation region 123 on the side of the other first planar extension portion 110x (lower side of Figure 31) of the two first planar extension portions 110x extending in the X direction of the inter-pixel isolation region 110 surrounding the photoelectric conversion region 22E in a planar view.

[0269] Although not shown in detail, the select transistor SEL has a configuration basically similar to that of the amplifier transistor AMP. It includes a gate electrode 126s overlapping the element formation region 123 (semiconductor layer 21) in a plan view and a gate insulating film interposed between the gate electrode 126s and the element formation region 123. The select transistor SEL also includes a pair of main electrode regions 127s and 127as provided in the element formation region 123 on both sides of the gate electrode 126s in the gate length direction and functioning as a source region and a drain region, and a channel formation region (not shown) provided in the element formation region 123 overlapping the gate electrode 126s in a plan view. The pair of main electrode regions 127s and 127as are spaced apart from each other in the gate length direction via the channel formation region. The pair of main electrode regions 127s and 127as are formed by n-type semiconductor regions provided in the element formation region 123, and the channel formation region is formed by a p-type well region 23 provided in the element formation region 123.

[0270] The selection transistor SEL and the amplification transistor AMP share a main electrode region 127as of the selection transistor SEL and a main electrode region 127as of the amplification transistor AMP, and are provided in the element formation region 123 in series connection.

[0271] (Reset transistor) As shown in Figure 31, the reset transistor RST is provided in the element formation region 123 on the corner side (upper right side of Figure 31) where one first planar extension portion 110x and one second planar extension portion 110y intersect, out of two first planar extension portions 110x extending in the X direction and two second planar extension portions 110y extending in the Y direction of the interpixel isolation region 110 surrounding the photoelectric conversion region 22E in a planar view.

[0272] Although not shown in detail, the reset transistor RST has a configuration basically similar to that of the amplifier transistor AMP, including a gate electrode 126r provided overlapping the element formation region 123 (semiconductor layer 21) in a plan view, and a gate insulating film interposed between the gate electrode 126r and the element formation region 123. The reset transistor RST also includes a pair of main electrode regions 127r and 127ar provided in the element formation region 123 on both sides of the gate electrode 126r in the gate length direction and functioning as a source region and a drain region, and a channel formation region (not shown) provided in the element formation region 123 overlapping the gate electrode 126r in a plan view. The pair of main electrode regions 127r and 127ar are spaced apart from each other in the gate length direction via the channel formation region. The pair of main electrode regions 127r and 127ar are formed of n-type semiconductor regions provided in the element formation region 123, and the channel formation region is formed of a p-type well region 23 provided in the element formation region 123.

[0273] The reset transistor RST and the amplifier transistor AMP share a main electrode region 127ar of the reset transistor RST and a main electrode region 127ar of the amplifier transistor AMP, and are provided in the element formation region 123 in series connection.

[0274] (First switching transistor) As shown in Figure 31, the switching transistor FCG is provided in the element formation region 123 on the side of one of the two first planar extension portions 110x (upper side of Figure 31) that extend in the X direction of the inter-pixel isolation region 110 that surrounds the photoelectric conversion region 22E in a planar view.

[0275] Although not shown in detail, the switching transistor FCG basically has the same configuration as the amplification transistor AMP, and includes a gate electrode 126fc provided so as to overlap the element formation region 123 (semiconductor layer 21) in a plan view, and a gate insulating film interposed between the gate electrode 126fc and the element formation region 123. The switching transistor FCG also includes a pair of main electrode regions 127fc and 127r provided in the element formation region 123 on both sides of the gate electrode 126fc in the gate length direction and functioning as a source region and a drain region, and a channel formation portion (not shown) provided in the element formation region 123 overlapping with the gate electrode 126fc in a plan view. The pair of main electrode regions 127fc and 127r are spaced apart from each other in the gate length direction via the channel formation portion. The pair of main electrode regions 127fc and 127r are formed of n-type semiconductor regions provided in the element forming region 123, and the channel forming portion is formed of a p-type well region 23 provided in the element forming region 123.

[0276] The switching transistor FCG and the reset transistor RST share a main electrode region 127r of the switching transistor FCG and a main electrode region 127r of the reset transistor RST, and are provided in the element formation region 123 in series connection.

[0277] (Second switching transistor) As shown in Figure 31, the switching transistor FDG is provided in the element formation region 123 on the side of the other second planar extension portion 110y (left side of Figure 31) of two second planar extension portions 110y extending in the Y direction of the inter-pixel isolation region 110 surrounding the photoelectric conversion region 22E in a planar view.

[0278] Although not shown in detail, the switching transistor FDG has basically the same configuration as the amplification transistor AMP, and includes a gate electrode 126fd provided overlapping the element formation region 123 (semiconductor layer 21) in a plan view, and a gate insulating film interposed between the gate electrode 126fd and the element formation region 123. The switching transistor FDG also includes a pair of main electrode regions 127f and 127fc provided in the element formation region 123 on both sides of the gate electrode 126fd in the gate length direction and functioning as a source region and a drain region, and a channel formation portion (not shown) provided in the element formation region 123 overlapping with the gate electrode 126fd in a plan view. The pair of main electrode regions 127f and 127fc are spaced apart from each other in the gate length direction via the channel formation portion. The pair of main electrode regions 127 f and 127 fc are formed by n-type semiconductor regions provided in the element forming region 123 , and the channel forming portion is formed by a p-type well region 23 provided in the element forming region 123 .

[0279] The switching transistor FDG and the switching transistor FCG share a main electrode region 127fc of the switching transistor FDG and a main electrode region 127fc of the switching transistor FCG, and are provided in series connection in the element formation region 123. Of the pair of main electrode regions 127f and 127fd of the switching transistor FDG, one main electrode region 127f is also used as the floating diffusion region FD. In other words, the floating diffusion region FD is formed of the n-type main electrode region 127f.

[0280] (Materials of Gate Electrodes and Gate Insulating Film) The gate electrodes 126t, 126a, 126s, 126r, 126fc, and 126fd of the transfer transistor TRL and pixel transistors Q (AMP, SEL, RST, FCD, and FDG) are each made of, for example, a polycrystalline silicon film (doped polysilicon film) doped with impurities that reduce resistance. Furthermore, the gate insulating film 125 of the transfer transistor TRL and pixel transistors Q (AMP, SEL, RST, FCD, and FDG) is each made of, for example, a silicon oxide film.

[0281] (P-Type Semiconductor Region) As shown in FIG. 32 , the p-type semiconductor region 37 is provided between the inter-pixel isolation region 110 and the n-type semiconductor region 24. The p-type semiconductor region 37 extends along the inter-pixel isolation region 110 in the thickness direction (Z direction) of the semiconductor layer 21. One end of the p-type semiconductor region 37 terminates at a position one level deeper on the second surface S2 side of the semiconductor layer 21 than on the first surface S1 side, and the other end opposite the one end reaches the p-type semiconductor region 128 provided on the second surface S2 side. As shown in FIG. 33B , the p-type semiconductor region 37 extends along the inter-pixel isolation region 110 surrounding the photoelectric conversion region 22E in a planar view, and has an annular (ring-shaped) planar pattern in a planar view. The p-type semiconductor region 37 and the p-type semiconductor region 128 each have an impurity concentration higher than the impurity concentration of the p-type well region 23.

[0282] The p-type semiconductor region 37 is formed in the manufacturing process of the solid-state imaging device 1E by introducing impurities into the side surface of the semiconductor layer 21 (photoelectric conversion region 22E) from inside the deep recess 111 formed in the semiconductor layer 21. Therefore, the p-type semiconductor region 37 is provided in alignment with the inter-pixel isolation region 110. The p-type semiconductor region 37 is also provided on the inner side (n-type semiconductor region 22E) of the side surface of the semiconductor layer 21, opposite to the inter-pixel isolation region 110 side.

[0283] 32 , an n-type epitaxial layer 112 serving as a charge discharge layer is provided on the side surface of the semiconductor layer 21 inside the recessed portion 111 of the inter-pixel isolation region 110. The n-type epitaxial layer 112 is provided on the recessed portion 111 side, opposite to the inner side (the n-type semiconductor region 24 side) of the side surface of the semiconductor layer 21. That is, the charge discharge layer (n-type epitaxial layer 112) of this fifth embodiment is provided inside the inter-pixel isolation region 110 together with the buried insulating film 113. The charge discharge layer (n-type epitaxial layer 112) of this fifth embodiment is provided between the side surface of the semiconductor layer 21 and the isolation insulating film 115 of the inter-pixel isolation region 110.

[0284] As shown in Figure 32, the n-type epitaxial layer 112 extends along the inter-pixel isolation region 110 in the thickness direction of the semiconductor layer 21. One end of the n-type epitaxial layer 112 terminates at a position one level deeper than the first surface portion S1 side of the semiconductor layer 21, and the other end opposite the one end reaches the p-type semiconductor region 128 provided on the second surface portion S2 side. As shown in Figures 33A and 33B, the n-type epitaxial layer 112 extends along the inter-pixel isolation region 110 surrounding the photoelectric conversion region 22E in a planar view, and has an annular (ring-shaped) planar pattern in a planar view. The n-type epitaxial layer 112 is configured with an impurity concentration higher than the impurity concentration of the n-type semiconductor region 24.

[0285] The n-type epitaxial layer 112 is formed by epitaxial growth from the inside of the deep recess 111 formed in the semiconductor layer 21 to the side surface of the semiconductor layer 21 (photoelectric conversion region 22E) during the manufacturing process of the solid-state imaging device 1E. Therefore, the n-type epitaxial layer 112 is provided in alignment with the inter-pixel isolation region 110. The n-type epitaxial layer 112 is also provided on the side surface of the semiconductor layer 21 on the inter-pixel isolation region 110 side.

[0286] 32 , the n-type epitaxial layer 112 is provided on the outer side of the side surface of the semiconductor layer 21 in contact with the semiconductor layer 21, and is composed of a layer different from the semiconductor layer 21. The epitaxial layer 112 is provided in the recessed portion 111 of the inter-pixel isolation region 110.

[0287] The n-type epitaxial layer 112 is a layer formed by epitaxial growth on the semiconductor layer 21. Epitaxial growth can form an n-type, p-type, or i-type single crystal layer that inherits the crystallinity of the underlying semiconductor layer 21. Therefore, the n-type epitaxial layer 112 is covalently bonded to the semiconductor layer 21. In the fifth embodiment, the n-type epitaxial layer 112 is formed of, for example, an n-type single crystal silicon layer doped with arsenic (As) or phosphorus (P) as an impurity that imparts n-type conductivity, but is not limited thereto.

[0288] <Relay Semiconductor Region> As shown in FIG. 32 , the photoelectric conversion region 22E is provided with an n-type relay semiconductor region 116. This n-type relay semiconductor region 116 is provided in the p-type well region 23 between the first surface portion S1 of the semiconductor layer 21 and the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21, spaced apart from both the first surface portion S1 of the semiconductor layer 21 and the n-type semiconductor region 24. As shown in FIG. 33A , the n-type relay semiconductor region 116 extends along the inter-pixel isolation region 110 (recessed portion 111) surrounding the photoelectric conversion region 22E in a planar view, and has an annular (ring-shaped) planar pattern in a planar view. As shown in FIGS. 32 and 33A , the n-type relay semiconductor region 116 contacts the n-type epitaxial layer 112 in a ring shape along the inter-pixel isolation region 110 in a planar view and is electrically connected to the n-type epitaxial layer 112. The n-type relay semiconductor region 116 has an impurity concentration higher than that of the n-type semiconductor region 24 .

[0289] 32, the n-type relay semiconductor region 116 is electrically connected to the main electrode region 127ar of the amplifier transistor AMP via the n-type relay semiconductor region 117 provided in the p-type well region 23. The main electrode region 127ar is electrically connected to the contact electrode 53a provided in the interlayer insulating film 52 of the multilayer wiring layer 51. １ The contact electrode 53a is electrically and mechanically connected to the １ is a wiring 54a as a conductor to which a potential is applied. １ That is, the p-type epitaxial layer 112 as a charge discharging layer is electrically and mechanically connected to the wiring 54a as a conductor to which a potential is applied. １ This wiring 54a is electrically connected to １is applied (supplied) to the p-type epitaxial layer 112. The potentials include a power supply potential supplied from a power generation circuit provided inside the solid-state imaging device 1E and a power supply potential supplied from outside the solid-state imaging device 1E via the bonding pad 14 (see FIG. 1). These power supply potentials include, for example, a first reference potential of "0 V," a second reference potential that is a positive potential higher than the first reference potential, and a third reference potential that is a negative potential lower than the first reference potential. In this fifth embodiment, since the epitaxial layer 112 serving as the charge discharging layer is made of n-type, a positive potential of, for example, 3.3 V is applied as the second reference potential to the wiring 54a serving as a conductor. １ The voltage is applied to the wiring 54a. １ The application of the potential is maintained during operation of the solid-state imaging device 1E.

[0290] <Conductive Path> As shown in FIG. 32, the solid-state imaging device 1E according to the fifth embodiment includes an n-type epitaxial layer 112 as a charge discharging layer and wiring 54a as a conductor to which a potential is applied. １ In the fifth embodiment, the conductive path 118 includes an n-type relay semiconductor region 116 electrically and physically (structurally) connected to the n-type epitaxial layer 112, and an n-type relay semiconductor region 117 electrically and physically connected to the n-type relay semiconductor region 116. The conductive path 118 also includes an n-type main electrode region 127ar electrically and physically connected to the n-type relay semiconductor region 117, and an n-type main electrode region 127ar connected to the n-type main electrode region 127ar and the wiring 54a. １ and a contact electrode 53a electrically and physically connected to the １ That is, the n-type epitaxial layer 112 as a charge discharging layer and the wiring 54a as a conductor. １ are electrically connected to each other via a conductive path 118 including one main electrode region 127ar of a pair of main electrode regions 127as, 127ar of the amplification transistor AMP serving as the pixel transistor Q.

[0291] <Functions of n-type epitaxial layer and p-type semiconductor region> The n-type epitaxial layer 112 shown in FIGS. 32, 33A, and 33B has the wiring 54a.１ When the second reference potential is applied to the n-type semiconductor region 24, the n-type semiconductor region 24 functions as a drain region that sweeps away dark current that has welled up at the sidewall of the inter-pixel isolation region 110 (the recessed portion 111). On the other hand, the p-type semiconductor region 37 functions as a depletion layer expansion suppression region that suppresses the expansion of a depletion layer from the n-type epitaxial layer 112 to the n-type semiconductor region 24.

[0292] In the fifth embodiment, the inter-pixel isolation region 110 corresponds to a specific example of an "isolation region" in the present technology, and the n-type epitaxial layer 112 corresponds to a specific example of a "charge discharge layer" in the present technology. In the fifth embodiment, the n-type semiconductor region 24 corresponds to a "first semiconductor region of a first conductivity type" in the present technology, the n-type epitaxial layer 112 corresponds to a "second semiconductor region of a first conductivity type" in the present technology, and the p-type semiconductor region 37 corresponds to a "third semiconductor region of a second conductivity type" in the present technology. The n-type epitaxial layer 112 as a charge discharge layer corresponds to a "second semiconductor region" in the present technology.

[0293] 34A to 34F , a method for manufacturing a solid-state imaging device according to a fifth embodiment of the present technology will be described. In this fifth embodiment, the description will be focused on the formation of the inter-pixel isolation region 110 included in the method for manufacturing the solid-state imaging device 1E.

[0294] First, as shown in Fig. 34A , a dug portion 111 extending from the first surface S1 toward the second surface S2 of the semiconductor layer 21 is formed by a method similar to that of the first embodiment described above, and a photoelectric conversion region 22E partitioned by this dug portion 111 is formed. Here, similar to the first embodiment described above, the semiconductor layer 21 is thinned down to the thinning line S2a shown in Fig. 34A in a thinning step during the manufacturing process of the solid-state imaging device 1E. Therefore, the dug portion 111 is formed deeper than the thinning line S2a of the semiconductor layer 21.

[0295] Next, as shown in FIG. 34B , a p-type semiconductor region 37 is formed on the side surface of the semiconductor layer 21 (side surface of the photoelectric conversion region 22E) inside the recessed portion 111 using a method similar to that of the first embodiment described above. The p-type semiconductor region 37 can be formed by introducing impurities into the side surface of the semiconductor layer 21 (side surface of the photoelectric conversion region 22E) from inside the recessed portion 111 while the first surface S1 side of the semiconductor layer 21 and the side surface of the semiconductor layer 21 inside the shallow recessed portion 111 (side surface of the photoelectric conversion region 22E) are covered with a mask. The introduction of the impurity can be performed by ion implantation, solid-phase diffusion, plasma doping, or the like. The impurity may be, for example, boron (B) or boron difluoride (BF), which exhibits p-type conductivity when introduced into silicon (Si). ２ ) can be used.

[0296] In the case of ion implantation or plasma doping, p-type impurities are introduced from inside the recessed portion 111 into the side surface portion of the semiconductor layer 21 (the side surface portion of the photoelectric conversion region 22E) to form the p-type semiconductor region 37, and then a heat treatment is performed to activate the introduced impurities. The heat treatment may be performed in the step of forming the n-type epitaxial layer 112, which will be described later, or may be performed before the step of forming the n-type epitaxial layer 112. The introduction of the impurities is performed in a state in which the first surface S1 side of the semiconductor layer 21 and the upper side of the side surface portion of the semiconductor layer 21 inside the shallow recessed portion 111 (the side surface portion of the photoelectric conversion region 22) are covered with a mask (masked state).

[0297] In the case of the solid-phase diffusion method, a solid-phase diffusion medium film doped (introduced) with p-type impurities is formed in the recessed portion 111, and then heat treatment is performed to diffuse and introduce the impurities from the solid-phase diffusion medium film from the inside of the recessed portion 111 into the side surfaces of the semiconductor layer 21 (side surfaces of the photoelectric conversion region 22E), thereby forming the p-type semiconductor region 37. The solid-phase diffusion medium film is formed, for example, in a state where the side surfaces of the semiconductor layer 21 inside the recessed portion 111 (side surfaces of the photoelectric conversion region 22E) are selectively covered with a mask such as a silicon oxide film or a silicon nitride film. The solid-phase diffusion medium film can be, for example, a polycrystalline silicon film doped with impurities.

[0298] In any of the ion implantation method, the plasma doping method, and the solid-phase diffusion method, the p-type semiconductor region 37 is formed in alignment with the recessed portion 111. The p-type semiconductor region 37 is formed along the recessed portion 111 in the thickness direction (Z direction) of the semiconductor layer 21. In the fifth embodiment, the p-type semiconductor region 37 is formed by, for example, the plasma doping method.

[0299] The p-type semiconductor region 37 is formed so that its thickness, measured from the inside of the recessed portion 111 toward the semiconductor layer 21 (the photoelectric conversion region 22E side) in a plan view, is thicker than the thickness of the later-described n-type epitaxial layer 112. Furthermore, the p-type semiconductor region 37 is formed with an impurity concentration higher than the impurity concentration of the p-type well region 23.

[0300] 34C , n-type epitaxial layer 112 is formed by epitaxial growth on the side surface of semiconductor layer 21 inside dug portion 111 (the side surface of photoelectric conversion region 22E). N-type epitaxial layer 112 can be formed by supplying gas required for epitaxial growth to the side surface of semiconductor layer 21 through dug portion 111. N-type epitaxial layer 112 is formed to a thickness that does not fill dug portion 111, i.e., a thickness of ½ or less of the width of dug portion 111 in the short direction.

[0301] 34D , a polycrystalline silicon film 113 and a silicon oxide film 114 are formed in this order inside dug portion 111 with n-type epitaxial layer 112 interposed therebetween. Polycrystalline silicon film 113 is formed so as to fill dug portion 111 from a position one step lower toward second surface S2 than first surface S1 portion of semiconductor layer 21 toward second surface S2. Silicon oxide film 114 is formed so as to fill dug portion 111 from a position one step lower toward second surface S2 than first surface S1 portion of semiconductor layer 21 toward polycrystalline silicon film 113.

[0302] Next, using the silicon oxide film 114 as an etching mask, the upper side of the n-type epitaxial layer is selectively etched to remove the upper side (the side of the first surface S1 of the semiconductor layer 21) of the n-type epitaxial layer 112, as shown in Fig. 34E. This process forms the n-type epitaxial layer 112, one end of which terminates at a position one step deeper than the first surface S1 of the semiconductor layer 21 and which folds back at the bottom side of the dug portion 111.

[0303] Next, the silicon oxide film 114 and the polycrystalline silicon film 113 are selectively removed, and then, as shown in FIG. 34F , an isolation insulating film 115 is formed so as to be embedded inside the recessed portion 111 with an n-type epitaxial layer 112 interposed therebetween. This process forms the inter-pixel isolation region 110, and also forms the photoelectric conversion region 22E partitioned by this inter-pixel isolation region 110.

[0304] <<Main Effects of Fifth Embodiment>> Next, the main effects of the fifth embodiment will be described. A solid-state imaging device 1E according to the fifth embodiment includes a semiconductor layer 21, an inter-pixel isolation region 110 including a recessed portion 111 extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side, a photoelectric conversion region 22E provided in the semiconductor layer 21 and partitioned by the inter-pixel isolation region 110, and an n-type epitaxial layer 112 serving as a charge discharging layer provided on a side surface of the semiconductor layer 21 inside the recessed portion 111. The n-type epitaxial layer 112 is connected to wiring 54a serving as a conductor to which a second reference potential is applied as a potential. １ and is electrically connected.

[0305] According to the solid-state imaging device 1E having such a configuration, the wiring 54a １, the n-type epitaxial layer 112 functions as a drain region, and dark current that has welled up at the sidewall of the inter-pixel isolation region 110 can be swept away into the n-type epitaxial layer 112 (the dark current that has occurred at the sidewall of the inter-pixel isolation region 110 can be discharged without being taken into the photoelectric conversion unit 25). Therefore, compared to the conventional technology in which a p-type semiconductor region is provided as a pinning layer at the interface between the recessed isolation region and the photoelectric conversion region, it is possible to further suppress the intrusion of dark current into the photoelectric conversion unit 25 of the photoelectric conversion region 22E. Therefore, even in the solid-state imaging device 1E according to the fifth embodiment, it is possible to achieve even higher image quality.

[0306] The solid-state imaging device 1E according to the fifth embodiment also includes a p-type semiconductor region (third semiconductor region of second conductivity type) 37 provided between the n-type epitaxial layer (second semiconductor region of first conductivity type) 112 of the inter-pixel isolation region 110 and the n-type semiconductor region (first semiconductor region of first conductivity type) 24. The solid-state imaging device 1E including such a configuration can electrically isolate the n-type epitaxial layer 112, which serves as a charge discharging layer, from the photoelectric conversion unit 25 (n-type semiconductor region 24). Furthermore, the p-type semiconductor region 37 can suppress the expansion of a depletion layer from the n-type epitaxial layer 112 to the n-type semiconductor region 24, thereby suppressing a decrease in the saturation signal quantity Qs due to the expansion of the depletion layer.

[0307] In the above-described fifth embodiment, the n-type relay semiconductor region 116 and the n-type relay semiconductor region 117 are described as separate components, but the n-type relay semiconductor region 116 and the n-type relay semiconductor region 117 may be regarded as a single component, and each of the n-type relay semiconductor region 116 and the n-type relay semiconductor region 117 may also be referred to as a relay electrode. Also, a part of the relay electrode may be provided in one of the main electrode regions 127ar of the amplifier transistor AMP.

[0308] 35 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to a sixth embodiment of the present technology. Note that, in Fig. 35, for ease of viewing, layers above the first wiring layer 54 included in the multi-layer wiring layer 51 are not shown, as in Fig. 6A of the first embodiment described above.

[0309] A solid-state imaging device 1F according to the sixth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1E according to the above-described fifth embodiment, but differs in that it includes an inter-pixel isolation region 110F shown in Fig. 35 instead of the inter-pixel isolation region 110 shown in Fig. 32 of the above-described fifth embodiment, and further differs in that it does not include the p-type semiconductor region 37 shown in Fig. 32. The solid-state imaging device 1F according to the sixth embodiment also includes a conductive path 118F shown in Fig. 35 instead of the conductive path 118 shown in Fig. 32 of the above-described fifth embodiment.

[0310] The inter-pixel isolation region 110F of the sixth embodiment has a configuration basically similar to that of the inter-pixel isolation region 110 of the above-described fifth embodiment, but differs in the configuration of the vertical cross section along the depth direction of the semiconductor layer 21. The planar pattern of the inter-pixel isolation region 110F is basically similar to that of the inter-pixel isolation region 110 of the above-described fifth embodiment, and therefore will not be described here.

[0311] 35 , the inter-pixel isolation region 110F includes a dug portion 111 extending across the first surface S1 and the second surface S2 of the semiconductor layer 21, and a p-type epitaxial layer 112F provided along a side surface of the semiconductor layer 21 inside the dug portion 111. The inter-pixel isolation region 110F also includes a fixed charge film 131 having a fixed charge and provided along the p-type epitaxial layer 112F inside the dug portion 111 on the side of the p-type epitaxial layer 112F opposite to the dug portion 111 side, and an isolation insulating film 115 provided inside the dug portion 111 on the side of the fixed charge film 131 opposite to the epitaxial layer 112F side. The inter-pixel isolation region 110F further includes an isolation insulating film 115f provided so as to fill the recessed portion 111 on the first surface portion S1 side of the semiconductor layer 21 relative to the fixed charge film 131 and the isolation insulating film 115.

[0312] In the sixth embodiment, the fixed charge film 131 corresponds to a specific example of a "charge discharging layer" of the present technology.

[0313] 35 , the p-type epitaxial layer 112F, like the n-type epitaxial layer 112 according to the fifth embodiment, is provided on the carved portion 111 side opposite to the inner side (n-type semiconductor region 24 side) of the side surface of the semiconductor layer 21. That is, the p-type epitaxial layer 112F is provided between the n-type semiconductor region 24 in the photoelectric conversion region 22E and the fixed charge film 131 in the inter-pixel isolation region 110F.

[0314] As shown in FIG. 35 , the p-type epitaxial layer 112F extends along the inter-pixel isolation region 110F in the thickness direction of the semiconductor layer 21. One end of the p-type epitaxial layer 112F terminates at a position one level deeper than the first surface portion S1 of the semiconductor layer 21, and the other end opposite the one end reaches the p-type semiconductor region 128 provided on the second surface portion S2 side. Although not shown in detail, the p-type epitaxial layer 112F extends along the inter-pixel isolation region 110F surrounding the photoelectric conversion region 22E in a planar view, similar to the n-type epitaxial layer 112 according to the fifth embodiment, and has an annular (ring-shaped) planar pattern in a planar view. The p-type epitaxial layer 112F has an impurity concentration higher than the impurity concentration of the p-type well region 23.

[0315] The p-type epitaxial layer 112F is formed by epitaxial growth from the inside of the deep recess 111 formed in the semiconductor layer 21 to the side surface of the semiconductor layer 21 (photoelectric conversion region 22E) during the manufacturing process of the solid-state imaging device 1F. Therefore, the p-type epitaxial layer 112F is provided in alignment with the inter-pixel isolation region 110F. The p-type epitaxial layer 112F is also provided on the side surface of the semiconductor layer 21 facing the inter-pixel isolation region 110F.

[0316] 35 , the p-type epitaxial layer 112F is provided on the outer side of the side surface of the semiconductor layer 21 in contact with the semiconductor layer 21, and is composed of a layer different from the semiconductor layer 21. The p-type epitaxial layer 112F is provided in the recessed portion 111 of the inter-pixel isolation region 110F.

[0317] The p-type epitaxial layer 112F is a layer formed on the semiconductor layer 21 by epitaxial growth. Therefore, the p-type epitaxial layer 112F is covalently bonded to the semiconductor layer 21. In the sixth embodiment, the p-type epitaxial layer 112F contains, but is not limited to, boron (B) or boron difluoride (BF) as an impurity that provides p-type conductivity. ２ ) is introduced into a p-type single crystal silicon layer.

[0318] (Fixed Charge Film) The fixed charge film 131 is provided along two sidewalls located on opposite sides of the recessed portion 111. The fixed charge film 131 folds back on the first surface S1 side of the semiconductor layer 21 so as to surround the isolation insulating film 115 at a position one step lower toward the second surface S2 side than the first surface S1 of the semiconductor layer 21, and reaches the p-type semiconductor region 128 provided on the second surface S2 side of the semiconductor layer 21. Although not shown in detail, the fixed charge film 131, like the p-type epitaxial layer 112F, extends along the inter-pixel isolation region 110F surrounding the photoelectric conversion region 22E in a planar view, forming an annular (ring-shaped) planar pattern in a planar view. The fixed charge film 131 is in contact with the p-type epitaxial layer 112F along the inter-pixel isolation region 110F surrounding the photoelectric conversion region 22E in a planar view.

[0319] The fixed charge film 131 is in contact with the p-type epitaxial layer 112F along the thickness direction (Z direction) of the semiconductor layer 21. The fixed charge film 131 is also in contact with the n-type relay semiconductor region 116 on the first surface portion S1 side of the semiconductor layer 21. The fixed charge film 131 has, for example, a positive fixed charge. The fixed charge film 131 having this positive fixed charge is made of hafnium oxide (HfO ２ ) film and silicon oxide (SiO ２) film can be used.

[0320] 35, the conductive path 118F includes an n-type relay semiconductor region 116 electrically and physically (structurally) connected to the fixed charge film 131, and an n-type relay semiconductor region 117 electrically and physically connected to the n-type relay semiconductor region 116. The conductive path 118F also includes an n-type main electrode region 127ar electrically and physically connected to the n-type relay semiconductor region 117, and an n-type main electrode region 127ar and a wiring 54a １ and a contact electrode 53a electrically and physically connected to the １ That is, the fixed charge film 131 as a charge discharging layer and the wiring 54a as a conductor. １ are electrically connected to each other via a conductive path 118F including one main electrode region 127ar of a pair of main electrode regions 127as, 127ar of the amplification transistor AMP serving as the pixel transistor Q.

[0321] <Functions of Fixed Charge Film and P-Type Epitaxial Layer> The fixed charge film 131 shown in FIG. 35 is a wiring 54a １ When a second reference potential is applied to the p-type epitaxial layer 112F, the p-type epitaxial layer 112F functions as a drain region that sweeps away dark current that has welled up on the sidewall of the inter-pixel isolation region 110 (dug portion 111). On the other hand, the p-type epitaxial layer 112F electrically separates the fixed charge film 131, which serves as a charge discharging layer, from the photoelectric conversion unit 25 (n-type semiconductor region 24), and also functions as a depletion layer expansion suppression region that suppresses the expansion of a depletion layer from the fixed charge film 131 side to the n-type semiconductor region 24.

[0322] <<Major Effects of Sixth Embodiment>> A solid-state imaging device 1F according to the sixth embodiment includes a semiconductor layer 21, an inter-pixel isolation region 110 including a recessed portion 111 extending from the first surface S1 side of the semiconductor layer 21 toward the second surface S2 side, a photoelectric conversion region 22E provided in the semiconductor layer 21 and partitioned by the inter-pixel isolation region 110, and a fixed charge film 131 serving as a charge discharge layer provided on a side surface of the semiconductor layer 21 inside the recessed portion 111. The fixed charge film 131 is connected to a wiring 54a serving as a conductor to which a second reference potential is applied as a potential. １and is electrically connected.

[0323] According to the solid-state imaging device 1F having such a configuration, the wiring 54a １ , the fixed charge film 131 functions as a drain region, and the dark current that has welled up on the sidewall of the inter-pixel isolation region 110F can be swept away into the fixed charge film 131 (the dark current that has occurred on the sidewall of the inter-pixel isolation region 110F can be discharged without being taken into the photoelectric conversion unit 25). Therefore, compared to the conventional technology in which a p-type semiconductor region is provided as a pinning layer at the interface between the recessed isolation region and the photoelectric conversion region, it is possible to further suppress the intrusion of dark current into the photoelectric conversion unit 25 of the photoelectric conversion region 22E. Therefore, even in the solid-state imaging device 1F according to the sixth embodiment, it is possible to achieve even higher image quality.

[0324] The solid-state imaging device 1F according to the sixth embodiment also includes a p-type epitaxial layer (a third semiconductor region of a second conductivity type) 112F provided between the fixed charge film 131 of the inter-pixel isolation region 110F and the n-type semiconductor region (a first semiconductor region of a first conductivity type) 24. The solid-state imaging device 1F including such a configuration can electrically separate the fixed charge film 131 serving as a charge discharge layer from the photoelectric conversion unit 25 (the n-type semiconductor region 24) by the p-type epitaxial layer 112F, and can suppress the expansion of a depletion layer from the fixed charge film 131 side to the n-type semiconductor region 24 by the p-type epitaxial layer 112F, thereby suppressing a decrease in the saturation signal amount Qs due to the expansion of the depletion layer.

[0325] 36 is a longitudinal sectional view schematically illustrating a longitudinal sectional structure of a solid-state imaging device according to a seventh embodiment of the present technology. Note that, in Fig. 36, for ease of viewing, layers above the first wiring layer 54 included in the multi-layer wiring layer 51 are not illustrated, as in Fig. 6A of the first embodiment described above.

[0326] A solid-state imaging device 1G according to the seventh embodiment of the present technology has basically the same configuration as the solid-state imaging device 1E according to the fifth embodiment described above, but differs in the following configuration. That is, the solid-state imaging device 1G according to the seventh embodiment of the present technology includes an inter-pixel isolation region 110G shown in FIG. 36 instead of the inter-pixel isolation region 110 shown in FIG. 32 of the fifth embodiment described above. Similarly to the first embodiment described above, the solid-state imaging device 1G according to the seventh embodiment of the present technology includes a p-type semiconductor region 37 and an n-type semiconductor region 38 in the photoelectric conversion region 22E. The n-type semiconductor region 38 of the seventh embodiment contacts an n-type relay semiconductor region 116 on the first surface S1 side of the semiconductor layer 21 and is electrically and physically (structurally) connected to the n-type relay semiconductor region 116. Furthermore, the solid-state imaging device 1G according to the seventh embodiment of the present technology includes a conductive path 118G shown in FIG. 36 instead of the conductive path 118 shown in FIG. 32 of the fifth embodiment described above.

[0327] As shown in Figure 36, the inter-pixel isolation region 110G includes a recessed portion 111 extending across the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, and an isolation insulating film 115 provided inside this recessed portion 111 so as to bury the recessed portion 111.

[0328] The photoelectric conversion region 22E of this seventh embodiment has a photoelectric conversion section 25 including an n-type semiconductor region 24 provided at a distance from each of the inter-pixel isolation region 110G and the first surface portion S1 of the semiconductor layer 21, an n-type semiconductor region 38 provided between the inter-pixel isolation region 110G and the n-type semiconductor region 24, and a p-type semiconductor region 37 provided between the n-type semiconductor region 38 and the n-type semiconductor region 24.

[0329] The n-type semiconductor region 38 shown in FIG. １ When the second reference potential is applied to the n-type semiconductor region 24, the p-type semiconductor region 37 functions as a drain region that sweeps away dark current that has welled up on the sidewall of the inter-pixel isolation region 110G (the recessed portion 111). On the other hand, the p-type semiconductor region 37 functions as a depletion layer expansion suppression region that suppresses the expansion of a depletion layer from the inter-pixel isolation region 110G side to the n-type semiconductor region 24.

[0330] In the seventh embodiment, the inter-pixel isolation region 110G corresponds to a specific example of an "isolation region" in the present technology, the n-type semiconductor region 24 corresponds to a specific example of a "first semiconductor region of a first conductivity type" in the present technology, the n-type semiconductor region 38 corresponds to a specific example of a "second semiconductor region of a first conductivity type" in the present technology, the p-type semiconductor region 37 corresponds to a specific example of a "third semiconductor region of a second conductivity type" in the present technology, and the n-type semiconductor region 38 corresponds to a specific example of a "charge discharge layer" in the present technology.

[0331] 36, the conductive path 118G includes an n-type relay semiconductor region 116 electrically and physically (structurally) connected to the n-type semiconductor region 38, and an n-type relay semiconductor region 117 electrically and physically connected to the n-type relay semiconductor region 116. The conductive path 118G also includes an n-type main electrode region 127ar electrically and physically connected to the n-type relay semiconductor region 117, and an n-type main electrode region 127ar and a wiring 54a. １ and a contact electrode 53a electrically and physically connected to the １ That is, the n-type semiconductor region 38 as a charge discharging layer and the wiring 54a as a conductor. １ are electrically connected to each other via a conductive path 118G including one main electrode region 127ar of a pair of main electrode regions 127as, 127ar of the amplification transistor AMP serving as the pixel transistor Q.

[0332] <<Major Effects of Seventh Embodiment>> The solid-state imaging device 1G according to the seventh embodiment includes a photoelectric conversion region 22E partitioned by an inter-pixel isolation region 110G and provided in the semiconductor layer 21. The photoelectric conversion region 22E includes a photoelectric conversion unit 25 including an n-type semiconductor region 24 provided spaced apart from each of the inter-pixel isolation region 110G and the first surface portion S1 of the semiconductor layer 21, an n-type semiconductor region 38 provided between the inter-pixel isolation region 110G and the n-type semiconductor region 24, and a p-type semiconductor region 37 provided between the n-type semiconductor region 38 and the n-type semiconductor region 24. The n-type semiconductor region 38 is connected to wiring 54a as a conductor to which a potential is applied. １ and is electrically connected.

[0333] According to the solid-state imaging device 1G having such a configuration, the wiring 54a １ 11G, the n-type semiconductor region 38 functions as a drain region, and the dark current that wells up at the sidewall of the inter-pixel isolation region 110G can be swept away in the n-type semiconductor region 38 (the dark current generated at the sidewall of the inter-pixel isolation region 110G can be discharged without being taken into the photoelectric conversion unit 25). Therefore, compared to the conventional technology in which a p-type semiconductor region is provided as a pinning layer at the interface between the recessed isolation region and the photoelectric conversion region, it is possible to further suppress the intrusion of dark current into the photoelectric conversion unit 25 of the photoelectric conversion region 22E. Therefore, even in the solid-state imaging device 1G according to the seventh embodiment, it is possible to achieve even higher image quality.

[0334] Furthermore, in the solid-state imaging device 1G according to the seventh embodiment, the p-type semiconductor region 37 is provided between the n-type semiconductor region 38 and the n-type semiconductor region 24. This makes it possible to electrically separate the n-type semiconductor region 38, which serves as a charge discharge layer, from the photoelectric conversion section 25 (n-type semiconductor region 24). In addition, the p-type semiconductor region 37 can suppress the expansion of the depletion layer from the n-type semiconductor region 38 to the n-type semiconductor region 24, thereby suppressing the decrease in the saturation signal amount Qs caused by the expansion of the depletion layer.

[0335] 37 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a solid-state imaging device according to an eighth embodiment of the present technology. Note that, in Fig. 37, for ease of viewing, layers above the first wiring layer 54 included in the multi-layer wiring layer 51 are not shown, as in Fig. 6A of the first embodiment described above.

[0336] A solid-state imaging device 1H according to an eighth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1E according to the above-described fifth embodiment, but differs in the following configuration. That is, the solid-state imaging device 1H according to the eighth embodiment of the present technology includes an inter-pixel isolation region 110H and an n-type semiconductor region 38h shown in FIG. 37 instead of the inter-pixel isolation region 110G and the n-type semiconductor region 38 shown in FIG. 36 of the above-described seventh embodiment. The solid-state imaging device 1H according to the eighth embodiment of the present technology does not include the p-type semiconductor region 37 shown in FIG. 36. Furthermore, the solid-state imaging device 1H according to the eighth embodiment of the present technology includes a conductive path 118H shown in FIG. 37 instead of the conductive path 118G shown in FIG. 36 of the above-described seventh embodiment.

[0337] 37 , the inter-pixel isolation region 110H extends from the second surface S2 of the semiconductor layer 21 toward the first surface S1, and terminates at a distance from the first surface S1 on the first surface S1 side of the semiconductor layer 21. In the eighth embodiment, the inter-pixel isolation region 110H terminates closer to the second surface S2 of the semiconductor layer 21 than the top surface of the n-type semiconductor region 24.

[0338] The inter-pixel isolation region 110H includes a recessed portion 111h extending from the second surface portion S2 side of the semiconductor layer 21 toward the second surface portion S1 side, and an isolation insulating film 115 provided inside this recessed portion 111h so as to bury the recessed portion 111h.

[0339] As shown in FIG. 37, the n-type semiconductor region 38h is a first portion 38h provided between the inter-pixel isolation region 110h and the n-type relay semiconductor region 116. １ and this first portion 38h １ a second portion 38h extending from the first portion 38h toward the second surface portion S2 of the semiconductor layer 21 and branching off to contact two side surfaces located opposite to each other in the short-side direction of the inter-pixel isolation region 110h; ２ and the first portion 38h. １ The second portion 38h is in contact with the n-type relay semiconductor region 116 and is electrically and physically connected to the n-type relay semiconductor region 116. ２ is the first portion 38h １The side opposite to the side is spaced apart from the second surface portion S2 of the semiconductor layer 21. The n-type semiconductor region 38h is spaced apart from the n-type semiconductor region 24 via the p-type well region 23. The n-type semiconductor region 38h functions as an inter-pixel isolation region.

[0340] The n-type semiconductor region 38h shown in FIG. １ When the second reference potential is applied to the n-type well region 24, the p-type well region 23 functions as a drain region that sweeps away dark current that has welled up on the sidewall of the inter-pixel isolation region 110H (recessed portion 111h). On the other hand, the p-type well region 23 between the n-type semiconductor region 38h and the n-type semiconductor region 24 functions as a depletion layer expansion suppression region that suppresses the expansion of a depletion layer from the inter-pixel isolation region 110h side to the n-type semiconductor region 24.

[0341] Here, in the eighth embodiment, the inter-pixel isolation region 110h corresponds to a specific example of "isolation region" in the present technology, the n-type semiconductor region 24 corresponds to a specific example of "first semiconductor region of first conductivity type" in the present technology, the n-type semiconductor region 38h corresponds to a specific example of "second semiconductor region of first conductivity type" in the present technology, and the p-type well region 23 between the n-type semiconductor region 38h and the n-type semiconductor region 24 corresponds to a specific example of "third semiconductor region of second conductivity type" in the present technology. Furthermore, the n-type semiconductor region 38h corresponds to a specific example of "charge discharge layer" in the present technology.

[0342] 37, the conductive path 118H includes an n-type relay semiconductor region 116 electrically and physically (structurally) connected to the n-type semiconductor region 38h, and an n-type relay semiconductor region 117 electrically and physically connected to the n-type relay semiconductor region 116. The conductive path 118H also includes an n-type main electrode region 127ar electrically and physically connected to the n-type relay semiconductor region 117, and an n-type main electrode region 127ar and a wiring 54a. １ and a contact electrode 53a electrically and physically connected to the １ That is, the n-type semiconductor region 38h as a charge discharging layer and the wiring 54a as a conductor. １are electrically connected to each other via a conductive path 118H including one main electrode region 127ar of a pair of main electrode regions 127as, 127ar of the amplification transistor AMP serving as the pixel transistor Q.

[0343] <<Major Effects of Eighth Embodiment>> According to the solid-state imaging device 1H according to the eighth embodiment, the wiring 54a １ 11H, the n-type semiconductor region 38h functions as a drain region, and the dark current that has welled up at the sidewall of the inter-pixel isolation region 110H can be swept away in the n-type semiconductor region 38h (the dark current that has occurred at the sidewall of the inter-pixel isolation region 110H can be discharged without being taken into the photoelectric conversion unit 25). Therefore, compared to the conventional technology in which a p-type semiconductor region is provided as a pinning layer at the interface between the recessed isolation region and the photoelectric conversion region, it is possible to further suppress the intrusion of dark current into the photoelectric conversion unit 25 of the photoelectric conversion region 22E. Therefore, even in the solid-state imaging device 1H according to the eighth embodiment, it is possible to achieve even higher image quality.

[0344] Furthermore, in the solid-state imaging device 1H according to the eighth embodiment, the p-type well region 23 is provided between the n-type semiconductor region 38h and the n-type semiconductor region 24. This makes it possible to electrically separate the n-type semiconductor region 38h, which serves as a charge discharge layer, from the photoelectric conversion section 25 (n-type semiconductor region 24) by the p-type well region 23, and also makes it possible to suppress the expansion of a depletion layer from the n-type semiconductor region 38h to the n-type semiconductor region 24 by the p-type well region 23, thereby suppressing a decrease in the saturation signal quantity Qs due to the expansion of the depletion layer.

[0345] [Ninth embodiment] Fig. 38 is a plan view schematically showing a plane pattern of pixels in a solid-state imaging device according to a ninth embodiment of the present technology. Fig. 39A is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a38-a38 cutting line in Fig. 38. Fig. 39B is a transverse sectional view schematically showing a longitudinal sectional structure taken along the b38-b38 cutting line in Fig. 38. Fig. 40 is a transverse sectional view schematically showing a transverse sectional structure taken along the a39-a39 cutting line in Fig. 39A.

[0346] 5 of the first embodiment, Fig. 38 is a plan view seen from the multilayer wiring layer side opposite to the light incident surface side of the semiconductor chip 2. In Fig. 39A and Fig. 39B, for ease of viewing, layers above the first wiring layer 54 included in the multilayer wiring layer 51 are omitted, similar to Fig. 6A of the first embodiment.

[0347] The solid-state imaging device 1I according to the ninth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1E according to the fifth embodiment described above, but differs in the following configuration. That is, the solid-state imaging device 1I according to the eighth embodiment of the present technology includes an inter-pixel isolation region 110I and a conductive path 118I shown in FIGS. 39A and 39B instead of the inter-pixel isolation region 110 and the conductive path 118 shown in FIG. 32 of the fifth embodiment described above. Furthermore, as shown in FIGS. 38 and 39B , the solid-state imaging device 1I according to the eighth embodiment of the present technology additionally includes a wiring 54i as a conductor to which a potential is applied, an island-shaped power supply region 124i partitioned by the inter-pixel isolation region 110I and the field insulating film 120, and an n-type power supply contact region WCi (see FIG. 39B ) provided in the power supply region 124i and electrically connected to the wiring 54i. The solid-state imaging device 1I according to the ninth embodiment of the present technology does not include the p-type relay semiconductor region 117 shown in FIG. 36 . The wiring 54 i is provided in the wiring layer 54 included in the multi-layer wiring layer 51 , for example.

[0348] <Inter-pixel isolation region> The inter-pixel isolation region 110I of the ninth embodiment has a configuration basically similar to that of the inter-pixel isolation region 110 of the above-described fifth embodiment, but differs in the configuration of the vertical cross section along the depth direction of the semiconductor layer 21. The planar pattern of the inter-pixel isolation region 110I is basically similar to the planar pattern of the inter-pixel isolation region 110 of the above-described fifth embodiment, and therefore description thereof will be omitted here.

[0349] 39A and 39B , the inter-pixel isolation region 110I includes a recessed portion 111 extending across the first surface S1 and the second surface S2 of the semiconductor layer 21, and an isolation insulating film 132 provided on a side surface of the semiconductor layer 21 inside the recessed portion 111. The inter-pixel isolation region 110I also includes a conductor (discharge electrode) 133 serving as a charge discharge layer provided inside the recessed portion 111 on the side of the isolation insulating film 132 opposite the semiconductor layer 21 side. The inter-pixel isolation region 110I also includes an isolation insulating film 115i provided so as to fill the recessed portion 111 closer to the first surface S1 of the semiconductor layer 21 than the conductor 133 and the isolation insulating film 132. The isolation insulating films 132 and 115i can be, for example, silicon oxide films. The conductor 133 may be, for example, a polycrystalline silicon film (doped polysilicon film) into which an impurity that reduces the resistance value is introduced.

[0350] <Photoelectric Conversion Region> The photoelectric conversion region 22E of the ninth embodiment has a configuration basically similar to that of the photoelectric conversion region 22E of the fifth embodiment described above, with the following differences: That is, as shown in Figures 38 and 39B, the photoelectric conversion region 22E of the ninth embodiment is newly provided with island-shaped power supply regions 124i, and the positions of the island-shaped power supply regions 124 are different.

[0351] In the ninth embodiment, the p-type semiconductor region 37 included in the photoelectric conversion region 22E is provided between the inter-pixel isolation region 110I and the n-type semiconductor region 24. In the ninth embodiment, the inter-pixel isolation region 110I corresponds to a specific but not limitative example of an “isolation region” in the present technology, and the conductor 132 corresponds to a specific but not limitative example of a “charge discharge layer” in the present technology.

[0352] (Power supply region) As shown in Figures 38 and 39B, the island-shaped power supply region 124i is provided on the corner side (lower left side of Figure 38) where the other first planar extension portion 110x and the other second planar extension portion 110y intersect, out of the two first planar extension portions 110x extending in the X direction and the two second planar extension portions 110y extending in the Y direction of the interpixel isolation region 110I surrounding the photoelectric conversion region 22E in a planar view.

[0353] The island-shaped power supply region 124 is located on the other second planar extension portion 110y side included in the inter-pixel isolation region 110I in a planar view, and is provided between the power supply region 124i and the element formation region 123 and spaced apart from the power supply region 124i and the element formation region 123.

[0354] 38 and 39B, the n-type power supply contact region WCi is provided in the island-shaped power supply region 124i. As shown in Fig. 39B, the n-type power supply contact region WCi is in contact with the conductor 133 on the first surface S1 side of the semiconductor layer 21, and is electrically and physically connected to this conductor 133. The n-type power supply contact region WCi is composed of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24.

[0355] As shown in Figure 39B, the n-type power supply contact region WCi is in contact with an n-type relay semiconductor region 116 that overlaps the n-type power supply contact region WCi in a planar view, and is electrically and physically connected to this n-type relay semiconductor region 116.

[0356] As shown in Figures 39A and 39B, the n-type relay semiconductor region 116 is provided in the p-type well region 23 between the first surface portion S1 of the semiconductor layer 21 and the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21, as in the fifth embodiment described above, at a distance from both the first surface portion S1 of the semiconductor layer 21 and the n-type semiconductor region 24. As shown in Figure 39B, the n-type relay semiconductor region 116 extends along the inter-pixel isolation region 110I (recessed portion 111) surrounding the photoelectric conversion region 22E in a planar view, and has an annular (ring-shaped) planar pattern in a planar view. As shown in Figure 40, in this fifth embodiment, the n-type relay semiconductor region 116 is insulated and isolated from the conductor 133 of the inter-pixel isolation region 110I by an isolation insulating film 132 interposed along a ring shape between the n-type relay semiconductor region 116 and the inter-pixel isolation region 110I in a planar view.

[0357] 39B , the solid-state imaging device 1I according to the ninth embodiment includes a conductive path 118I that electrically connects the conductor 133 serving as a charge discharging layer and the wiring 54i serving as a conductor to which a potential is applied. In the ninth embodiment, the conductive path 118I includes an n-type power supply contact region WCi electrically and physically (structurally) connected to the conductor 133, and a contact electrode 53i provided in the interlayer insulating film 52 of the multilayer wiring layer 51 and electrically and physically connected to each of the n-type power supply contact region WCi and the wiring 54i. That is, unlike the conductive path 118 of the fifth embodiment described above, the conductive path 118I of the ninth embodiment does not include the main electrode region 127ar of the amplifier transistor AMP.

[0358] 39A and 39B functions as a drain region that sweeps away dark current that wells up at the sidewall of the inter-pixel isolation region 110I (recessed portion 111) when a second reference potential is applied to the wiring 54i. On the other hand, the p-type semiconductor region 37 electrically separates the conductor 133, which serves as a charge discharging layer, from the photoelectric conversion unit 25 (n-type semiconductor region 24), and also functions as a depletion layer expansion suppression region that suppresses expansion of a depletion layer from the inter-pixel isolation region 110I side to the n-type semiconductor region 24.

[0359] <<Major Effects of the Ninth Embodiment>> In the solid-state imaging device 1I according to the ninth embodiment, by applying the second reference potential to the wiring 54i, the conductor 133 in the inter-pixel isolation region 110I functions as a drain region, and the dark current that has welled up at the sidewall of the inter-pixel isolation region 110I can be swept away by the conductor 133 (the dark current that has occurred at the sidewall of the inter-pixel isolation region 110I can be discharged without being taken into the photoelectric conversion unit 25). Therefore, compared to the conventional technology in which a p-type semiconductor region is provided as a pinning layer at the interface between a recessed isolation region and a photoelectric conversion region, it is possible to further suppress the intrusion of dark current into the photoelectric conversion unit 25 in the photoelectric conversion region 22E. Therefore, the solid-state imaging device 1I according to the ninth embodiment can also achieve even higher image quality.

[0360] Furthermore, in the solid-state imaging device 1I according to the ninth embodiment, the p-type semiconductor region 37 is provided between the conductor 133 and the n-type semiconductor region 24. This makes it possible to electrically separate the conductor 133, which serves as a charge discharging layer, from the photoelectric conversion section 25 (n-type semiconductor region 24) by the p-type semiconductor region 37, and also makes it possible to suppress the expansion of the depletion layer from the inter-pixel isolation region 110I side to the n-type semiconductor region 24 by the p-type well region 23, thereby suppressing the decrease in the saturation signal quantity Qs caused by the expansion of the depletion layer.

[0361] [Tenth embodiment] Fig. 41 is a plan view schematically showing a plane pattern of pixels in a solid-state imaging device according to a tenth embodiment of the present technology. Fig. 42 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a41-a41 cutting line in Fig. 41. Fig. 43 is a transverse sectional view schematically showing a transverse sectional structure taken along the a42-a42 cutting line in Fig. 42.

[0362] 5 of the first embodiment, Fig. 41 is a plan view seen from the multilayer wiring layer side opposite to the light incident surface side of the semiconductor chip 2. In Fig. 42, for ease of viewing, layers above the first wiring layer 54 included in the multilayer wiring layer 51 are omitted, similar to Fig. 6A of the first embodiment.

[0363] 41 to 43 , a solid-state imaging device 1J according to a tenth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1I according to the above-described ninth embodiment, but differs in the following configuration. That is, the solid-state imaging device 1J according to the tenth embodiment of the present technology includes the conductive path 118 shown in FIG. 42 instead of the conductive path 118I shown in FIG. 39 of the above-described ninth embodiment. The solid-state imaging device 1J according to the tenth embodiment of the present technology does not include the island-shaped power supply region 124i and the n-type power supply contact region WCi shown in FIG. 38 of the above-described ninth embodiment. In the solid-state imaging device 1J according to the tenth embodiment of the present technology, the island-shaped power supply region 124 and the n-type power supply contact region WC are provided, as in the fifth embodiment described above, on the corner side (lower left side of Figure 41) where the other first extension portion 110x and the other second planar extension portion 110y intersect, out of the two first planar extension portions 110x extending in the X direction and the two second planar extension portions 110y extending in the Y direction of the interpixel isolation region 110I surrounding the photoelectric conversion region 22E in a planar view.

[0364] 42 and 43 , the n-type relay semiconductor region 116 of the tenth embodiment is partially in contact with the conductor 133 in the inter-pixel isolation region 110I, and is electrically and physically connected to this conductor 133. The n-type relay semiconductor region 116 is connected to the side surface of the conductor 133 at the side surface of the inter-pixel isolation region where the n-type relay semiconductor region 117 is provided.

[0365] The conductive path 118 of the tenth embodiment includes a conductor 133 as a charge discharging layer and a wiring 54a as a conductor to which a potential is applied. １ The conductive path 118 of the tenth embodiment is a conductive path that electrically connects the n-type relay semiconductor region 116 and the wiring 54a. Similarly to the conductive path 118 of the fifth embodiment, the conductive path 118 of the tenth embodiment includes an n-type relay semiconductor region 116 that is electrically and physically (structurally) connected to the conductor 133, and an n-type relay semiconductor region 117 that is electrically and physically connected to the n-type relay semiconductor region 116. The conductive path 118 of the tenth embodiment also includes an n-type main electrode region 127ar that is electrically and physically connected to the n-type relay semiconductor region 117, and an n-type main electrode region 127ar that is electrically and physically connected to the n-type relay semiconductor region 117. １and a contact electrode 53a electrically and physically connected to the １ and,

[0366] The present technology can also be applied to the solid-state imaging device 1J according to the tenth embodiment, and the same effects as those of the ninth embodiment can be obtained.

[0367] 44 is a cross-sectional view schematically illustrating a cross-sectional structure of a pixel according to Modification 10-1 of the tenth embodiment of the present technology. As shown in Fig. 44, in Modification 10-1, the conductor 133 of the inter-pixel isolation region 110I and the n-type relay semiconductor region 116 are connected along the outer periphery of the photoelectric conversion region 22E in plan view.

[0368] The present technology can also be applied to this modification 10-1, and the same effects as those of the above-described tenth embodiment can be obtained.

[0369] 45 is a plan view schematically showing a plane pattern of a pixel according to Modification 10-2 of the tenth embodiment of the present technology. Fig. 46 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a45-a45 cutting line in Fig. 45.

[0370] 45 and 46 , in this modification 10-2, in a region overlapping with the inter-pixel isolation region 110I in a plan view, a wiring 54j to which a potential is applied is electrically connected to the conductor 133 in the inter-pixel isolation region 110I. The wiring 54j is electrically connected to the conductor 133 in the inter-pixel isolation region 110I via a contact electrode 53j provided in the interlayer insulating film 52 of the multilayer wiring layer 51. The wiring 54j is provided in the wiring layer 54 of the multilayer wiring layer 51. The contact electrode 53j extends from the wiring 54j through the interlayer insulating film 52 and the isolation insulating film 115i of the inter-pixel isolation region 110I to reach the conductor 133.

[0371] The present technology can also be applied to this modified example 10-2, and the same effects as those of the above-described tenth embodiment can be obtained.

[0372] 1, the wiring 54j serving as a conductor to which a potential is applied and the conductor 133 in the inter-pixel isolation region serving as a charge discharging layer are electrically connected in the pixel array section 2A, but the wiring 54j and the conductor 133 may be electrically connected in the peripheral section 2B surrounding the pixel array section 2A. In this case, it is preferable to connect the wiring 54j to the isolation region extended from the pixel array section 2A to the peripheral section 2B.

[0373] 47 is a plan view schematically showing a planar pattern of pixels in a solid-state imaging device according to an eleventh embodiment of the present technology. Fig. 48 is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a47-a47 cutting line in Fig. 47.

[0374] 5 of the first embodiment described above, Fig. 47 is a plan view seen from the multilayer wiring layer side opposite to the light incident surface side of the semiconductor chip 2. In Fig. 48, for ease of viewing, layers above the first wiring layer 54 included in the multilayer wiring layer 51 are not shown, similar to Fig. 6A of the first embodiment described above.

[0375] 47 and 48 , a solid-state imaging device 1K according to an eleventh embodiment of the present technology has basically the same configuration as the solid-state imaging device 1E according to the above-described fifth embodiment, but differs in the following configuration. That is, the solid-state imaging device 1K according to the eleventh embodiment of the present technology includes a conductive path 118K shown in Fig. 48 instead of the conductive path 118 of the above-described fifth embodiment shown in Fig. 32. This conductive path 118K electrically connects the n-type epitaxial layer 112 serving as a charge discharging layer and the wiring 54r serving as a conductor to which a potential is applied.

[0376] 48, the conductive path 118K of the eleventh embodiment includes an n-type relay semiconductor region 116 electrically and physically (structurally) connected to the n-type epitaxial layer 112, and an n-type relay semiconductor region 117 electrically and physically connected to the n-type relay semiconductor region 116. The conductive path 118K also includes an n-type main electrode region 127r electrically and physically connected to the n-type relay semiconductor region 117, and a contact electrode 53r electrically and physically connected to the n-type main electrode region 127r and the wiring 54r. That is, the n-type epitaxial layer 112 as a charge discharging layer and the wiring 54a as a conductor １ are electrically connected to each other via a conductive path 118K including a main electrode region 127r of the pixel transistor Q. The wiring 54r is provided in the wiring layer 54 of the multilayer wiring layer 51. The contact electrode 53r extends from the wiring 54j through the interlayer insulating film 52 to reach the main electrode region 127.

[0377] The present technology can also be applied to the solid-state imaging device 1J according to the eleventh embodiment, and the same effects as those of the fifth embodiment described above can be obtained.

[0378] Twelfth Embodiment Application Examples to Electronic Devices The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0379] FIG. 49 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a fourth embodiment of the present technology.

[0380] 49 , the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging devices 1A to 1K according to the first to third embodiments of the present technology are used as the solid-state imaging device 101 in an electronic device (for example, a camera).

[0381] The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause charge transfer in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0382] With this configuration, the solid-state imaging device 101 can achieve even higher image quality, and the image quality performance of the electronic device 100 of the twelfth embodiment can be improved.

[0383] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0384] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0385] The present technology may be configured as follows: (1) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; an isolation region including a recessed portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a photoelectric conversion region provided in the semiconductor layer and partitioned by the isolation region, wherein the photoelectric conversion region has: a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided spaced apart from the isolation region and the first surface portion of the semiconductor layer; a second semiconductor region of the first conductivity type provided between the isolation region and the first semiconductor region; and a third semiconductor region of a second conductivity type provided between the second semiconductor region and the first semiconductor region. (2) The photodetector according to (1), wherein the second semiconductor region is connected to a conductor to which a potential is applied. (3) The photodetector according to (2), wherein the conductor is provided in the recessed portion. (4) The photodetector according to (3), wherein the conductor is provided on the first surface side of the semiconductor layer. (5) The photodetector according to (3), wherein the conductor is provided on the second surface side of the semiconductor layer. (6) The photodetector according to (3), wherein the conductor is provided across the first surface side and the second surface side of the semiconductor layer. (7) The photodetector according to (3), further comprising a light-shielding film provided outside the second surface side of the semiconductor layer so as to overlap with the isolation region, and the conductor is connected to the light-shielding film. (8) The photodetector according to any one of (3) to (7), wherein the conductor surrounds the photoelectric conversion region in a planar view. (9) The photodetector according to any one of (3) to (7), wherein the conductor extends linearly in a planar view. (10) The photodetector according to (2), further comprising a multilayer wiring layer provided on the first surface side of the semiconductor layer, wherein the conductor is a contact electrode that electrically connects wiring in the multilayer wiring layer and the second semiconductor region. (11) The photodetector according to any one of (1) to (10), wherein the second semiconductor region and the third semiconductor region each extend across the first surface and the second surface of the semiconductor layer.(12) The photodetector according to any one of (1) to (11), wherein the photoelectric conversion region further comprises a charge holding portion that holds signal charges photoelectrically converted by the photoelectric conversion portion, and a transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion portion to the charge holding portion. (13) The photodetector according to (12), further comprising: a first semiconductor layer, a second semiconductor layer provided so as to overlap with the semiconductor layer in the one direction, and a pixel circuit that reads out the signal charges held in the charge holding portion and outputs a pixel signal based on the read signal charges, wherein the pixel transistor included in the pixel circuit is provided in the second semiconductor layer. (14) The photodetector according to any one of (1) to (13), wherein the photoelectric conversion region further includes a separation barrier connected to the separation region and a first photoelectric conversion cell and a second photoelectric conversion cell separated by the separation barrier, wherein each of the first photoelectric conversion cell and the second photoelectric conversion cell has the photoelectric conversion portion, and wherein the second semiconductor region and the third semiconductor region are each provided on a side surface of the separation barrier. (15) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion positioned opposite each other in one direction; a separation region including a recessed portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; a photoelectric conversion region provided in the semiconductor layer and partitioned by the separation region; and a charge discharge layer provided on a side surface of the semiconductor layer inside the recessed portion. (16) The photodetector according to (15), wherein the charge discharge layer is electrically connected to a conductor to which a potential is applied. (17) The photodetector according to (15) or (16), wherein the photoelectric conversion region has a pixel transistor provided on the first surface side of the semiconductor layer, the pixel transistor has a pair of main electrode regions functioning as a source region and a drain region, and the charge discharging layer is electrically connected to the conductor via a conductive path including one of the pair of main electrode regions. (18) The photodetector according to any of (15) to (17), wherein the charge discharging layer is a first conductivity type epitaxial layer provided on the recessed portion side of the side surface portion of the semiconductor layer.(19) The photodetector according to any one of (15) to (18), wherein the photoelectric conversion region has: a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided spaced apart from the isolation region and the first surface portion of the semiconductor layer; and a second semiconductor region of a second conductivity type provided between the isolation region and the first semiconductor region. (20) The photodetector according to (15) or (16), wherein the charge discharging layer is provided on the recessed portion side of the side surface portion of the semiconductor layer and is a fixed charge film having positive fixed charges. (21) The photodetector according to (20), wherein the isolation region further includes a p-type epitaxial layer between the side surface portion of the semiconductor layer and the charge discharging layer. (22) The photodetector according to (15), wherein the photoelectric conversion region has a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided spaced apart from the isolation region and the first surface portion of the semiconductor layer, a second semiconductor region of the first conductivity type provided between the isolation region and the first semiconductor region, and a third semiconductor region of a second conductivity type provided between the second semiconductor region and the first semiconductor region, and the charge discharging layer is the second semiconductor region. (23) The photodetector according to (15), wherein the charge discharging layer is provided on the isolation region side of the side portion of the semiconductor layer with an insulating film interposed therebetween. (24) An electronic device comprising: a photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that performs signal processing on a signal output from the photodetector, wherein the photodetector comprises: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; an isolation region including a recessed portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a photoelectric conversion region provided in the semiconductor layer and partitioned by the isolation region, wherein the photoelectric conversion region has: a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided spaced apart from each of the isolation region and the first surface portion of the semiconductor layer; a second semiconductor region of the first conductivity type provided between the isolation region and the first semiconductor region; and a third semiconductor region of a second conductivity type provided between the second semiconductor region and the first semiconductor region.

[0386] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0387] DESCRIPTION OF SYMBOLS 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K...Solid-state imaging device (photodetector) 2...Semiconductor chip 2A...Pixel array section 2B...Peripheral section 3, 3E...Pixel 4...Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7...Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14...Bonding pad 15...Pixel block 16, 16E...Pixel circuit 17...Pixel block forming region 18...Pixel block group 21...Semiconductor layer 22, 22E...Photoelectric conversion region 23...P-type well region 24...N-type semiconductor region 25...Photoelectric conversion section 31...Inter-pixel isolation region (isolation region) 32...Field isolation region 33...Discontinued portion 34...Dug-in portion forming region 35: shallow recess 36: deep recess 37: p-type semiconductor region (depletion layer expansion suppression portion) 38, 38h: n-type semiconductor region (drain electrode) 38h １ …First part 38h ２ Second portion 39: Isolation insulating film 41: Conductor 41a: Metal film 42: Isolation insulating film 43a, 43b: Element forming region 44: Gate recessed portion 45: Gate insulating film 46: Gate electrode 46a: Head portion 46b: Body portion 47: Gate electrode 48a １ , 48a ２ Main electrode region 49 Relay conductive pad 51 Multilayer wiring layer 52 Interlayer insulating film 53a １ , 53a ２ , 53f, 53r, 53t, 53x...contact electrodes 54...first wiring layer 54a １ , 54a ２, 54f, 54r, 54t, 54x... wiring 61... planarization film 62... light-shielding film 63... optical filter layer 64... lens layer 65... conductor 66... ​​isolation barrier 71... insulating layer 81... semiconductor layer 91... insulating layer 92... through contact electrode 93, 94... contact electrode 95... wiring 96... conductive path 100... electronic device 101... solid-state imaging device 102... optical lens (optical system) 103... shutter device 104... drive circuit 105... signal processing circuit 106... incident light 110, 110F, 110G, 110H... inter-pixel isolation region 110x... first planar extension portion 110y... second planar extension portion 111, 111h... dug portion 112... n-type epitaxial layer (charge discharge layer) 112F... p-type epitaxial layer 113... polysilicon film 114... silicon oxide film 115, 115f, 115i... isolation insulating film 116... n-type relay semiconductor region 117... n-type relay semiconductor region 118, 118F, 118G, 118H... conductive path 120... field isolation region 121... shallow trench portion 122... isolation insulating film 123... island-shaped element formation region 124, 124i... island-shaped power supply region 125... gate insulating film 126a, 126c, 126d, 126r, 126s, 126s, 126t... gate electrodes 127ar, 127as, 127f, 127fc, 127r, 127s... main electrode region 128... p-type semiconductor region 131... fixed charge film 132... isolation insulating film 133...conductor (discharge electrode) AMP...amplifying transistor FD...n-type floating diffusion region M1...etching mask M1a...opening M1b...mask portion Q...pixel transistor RST...reset transistor SEL...selection transistor S1...first surface portion S2...second surface portion TR, TRL...transfer transistor WC, WCi...p-type power supply contact region

Claims

1. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located on opposite sides of each other in one direction; a separation region including a dug-in portion extending from the first surface portion side to the second surface portion side of the semiconductor layer; and a photoelectric conversion region provided in the semiconductor layer and partitioned by the separation region, wherein the photoelectric conversion region includes a photoelectric conversion portion including a first semiconductor region of a first conductivity type provided separately from each of the separation region and the first surface portion of the semiconductor layer, a second semiconductor region of the first conductivity type provided between the separation region and the first semiconductor region, and a third semiconductor region of a second conductivity type provided between the second semiconductor region and the first semiconductor region.

2. The photodetector according to claim 1, wherein the second semiconductor region is connected to a conductor to which a potential is applied.

3. The photodetector according to claim 2, wherein the conductor is provided in the dug-in portion.

4. The photodetector according to claim 3, wherein the conductor is provided on the first surface portion side of the semiconductor layer.

5. The photodetector according to claim 3, wherein the conductor is provided on the second surface portion side of the semiconductor layer.

6. The photodetector according to claim 3, wherein the conductor is provided across the first surface portion side and the second surface portion side of the semiconductor layer.

7. The photodetector according to claim 3, further comprising a light-shielding film provided outside the second surface portion of the semiconductor layer and overlapping the separation region, wherein the conductor is connected to the light-shielding film.

8. The photodetector according to claim 3, wherein the conductor surrounds the photoelectric conversion region in a plan view.

9. The photodetector according to claim 3, wherein the conductor extends linearly in a plan view.

10. The photodetector according to claim 2, further comprising a multilayer wiring layer provided on the first surface portion side of the semiconductor layer, wherein the conductor is a contact electrode that electrically connects the wiring of the multilayer wiring layer and the second semiconductor region.

11. The photodetector according to claim 1, wherein each of the second semiconductor region and the third semiconductor region extends across the first surface portion and the second surface portion of the semiconductor layer.

12. The photoelectric conversion region further includes a charge holding unit that holds signal charges photoelectrically converted by the photoelectric conversion unit, and a transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit. The photodetection device according to claim 1.

13. The semiconductor layer is a first semiconductor layer, a second semiconductor layer provided to overlap the semiconductor layer in the one direction, and a pixel circuit that reads out the signal charges held in the charge holding unit and outputs a pixel signal based on the read signal charges. The pixel transistors included in the pixel circuit are provided in the second semiconductor layer. The photodetection device according to claim 12.

14. The photoelectric conversion region further includes a separation barrier connected to the separation region, and a first photoelectric conversion cell and a second photoelectric conversion cell partitioned by the separation barrier. Each of the first photoelectric conversion cell and the second photoelectric conversion cell has the photoelectric conversion unit. Each of the second semiconductor region and the third semiconductor region is also provided on a side surface portion of the separation barrier. The photodetection device according to claim 1.

15. A semiconductor layer having a first surface portion and a second surface portion located on opposite sides in one direction, a separation region including a dug-in portion extending from the first surface portion side to the second surface portion side of the semiconductor layer, a photoelectric conversion region provided in the semiconductor layer partitioned by the separation region, and a charge discharge layer provided on a side surface portion of the semiconductor layer inside the dug-in portion. A photodetection device.

16. The charge discharge layer is electrically connected to a conductor to which a potential is applied. The photodetection device according to claim 15.

17. The photoelectric conversion region has a pixel transistor provided on the first surface portion side of the semiconductor layer. The pixel transistor has a pair of main electrode regions that function as a source region and a drain region. The charge discharge layer is electrically connected to the conductor via a conductive path including one of the pair of main electrode regions. The photodetection device according to claim 15.

18. The charge discharge layer is an epitaxial layer of a first conductivity type provided on the side surface portion of the semiconductor layer on the dug-in portion side. The photodetection device according to claim 15.

19. The photoelectric conversion region includes a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided separately from each of the separation region and the first surface portion of the semiconductor layer, and a second semiconductor region of a second conductivity type provided between the separation region and the first semiconductor region. The photodetection device according to claim 18.

20. The charge discharge layer is a fixed charge film provided on the side surface portion of the semiconductor layer on the side of the recessed portion and having positive fixed charges. The photodetection device according to claim 15.

21. The separation region further includes a p-type epitaxial layer between the side surface portion of the semiconductor layer and the charge discharge layer. The photodetection device according to claim 20.

22. The photoelectric conversion region includes a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided separately from each of the separation region and the first surface portion of the semiconductor layer, a second semiconductor region of the first conductivity type provided between the separation region and the first semiconductor region, and a third semiconductor region of the second conductivity type provided between the second semiconductor region and the first semiconductor region. The charge discharge layer is the second semiconductor region. The photodetection device according to claim 15.

23. The charge discharge layer is provided on the side surface portion of the semiconductor layer on the side of the separation region with an insulating film interposed therebetween. The photodetection device according to claim 15.

24. An electronic device comprising: a photodetection device; an optical lens that forms image light from a subject on an imaging surface of the photodetection device; and a signal processing circuit that performs signal processing on a signal output from the photodetection device. The photodetection device includes a semiconductor layer having a first surface portion and a second surface portion located on opposite sides in one direction, a separation region including a recessed portion extending from the first surface portion side to the second surface portion side of the semiconductor layer, and a photoelectric conversion region provided in the semiconductor layer partitioned by the separation region. The photoelectric conversion region includes a photoelectric conversion unit including a first semiconductor region of a first conductivity type provided separately from each of the separation region and the first surface portion of the semiconductor layer, a second semiconductor region of the first conductivity type provided between the separation region and the first semiconductor region, and a third semiconductor region of the second conductivity type provided between the second semiconductor region and the first semiconductor region.

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