NF3 ultra low flow

Abstract

A system of semiconductor manufacturing may include a gas canister may including a gas mix with NF3 in a range of about.5% to about 5%, inclusive. The system may include a semiconductor processing chamber. The system may include a mass flow controller, configured to provide the gas mix to the semiconductor processing chamber. The system may include a substrate support disposed within the semiconductor processing chamber.

Description

NF3 ULTRA LOW FLOWCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 622,455, filed on January 18, 2024, and titled “NF3 ULTRA LOW FLOW,” the content of which is herein incorporated by reference in its entirety for all purposes.TECHNICAL FIELD

[0002] The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to providing etchants for semiconductor manufacturing.BACKGROUND

[0003] Etch rates for semiconductor substrates are controlled, at least in part, by an amount of etchant provided in a semiconductor processing chamber. Etchants are typically delivered as a component in a gas mix, where the etchant is combined with an inert gas as a dilution agent. The concentrations of etchants within the gas mix may cause unwanted effects for even small errors in the delivery of the gas mix to the semiconductor processing chamber.BRIEF SUMMARY

[0004] A system of semiconductor manufacturing may include a gas canister may including a gas mix with NF3 in a range of about .5% to about 5%, inclusive. The system may include a semiconductor processing chamber. The system may include a mass flow controller, configured to provide the gas mix to the semiconductor processing chamber. The system may include a substrate support disposed within the semiconductor processing chamber.

[0005] A method may include providing a semiconductor substrate disposed within a processing chamber, where the semiconductor substrate may include a layer of silicon germanium (SiGe). The method may include connecting a gas canister may include a gas mix of about 1% nitrogen trifluoride (NF3) to the processing chamber. The method may include providing the gas mix from the gas canister to the processing chamber via a mass flow controller. The method may include adjusting the mass flow controller such that a component of the gas reaches a predetermined level within the semiconductor processing chamber. The method may include generating a plasma within the semiconductor processing chamber such that F2 is formed. The method may include etching the sige layer of the semiconductor substrate using the F2.

[0006] A system may include a semiconductor processing chamber, may include a substrate holder, configured to support a semiconductor substrate. The system may include a gas canister, may include a gas mix. The system may include a mass flow controller, fluidly connected to the gas canister and configured to provide a gas to the semiconductor chamber. The system may include one or more processors. The system may include a computer-readable medium including instructions, that, when executed by the one or more processors, cause the system to perform operations. The operations may include causing the gas mix from the gas canister to be provided to the processing chamber via the mass flow controller, and adjusting the mass flow controller such that a component of the gas reaches a predetermined level within the semiconductor processing chamber.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 A shows a top plan view of one embodiment of a processing system of deposition, treating, etching, baking, and curing chambers, according to certain embodiments.

[0008] FIG. IB shows a cross-sectional view of an exemplary processing chamber, according to certain embodiments.

[0009] FIG. 2 illustrates a gas canister including a gas mix, according to certain embodiments.

[0010] FIG. 3 illustrates a flowchart of a method for providing an etchant to a semiconductor processing chamber, according to certain embodiments.

[0011] FIG. 4 illustrates an exemplary computer system, in which various embodiments may be implemented.DETAILED DESCRIPTION

[0012] As the amount of mobile devices and other electronics has exploded globally, the demand for more efficient manufacture of various semiconductor components of these electronics has similarly exploded. Furthermore, a size of the structures of the various semiconductor components may shrink, requiring finer control over various processes during the manufacturing process.

[0013] For example, a substrate used to manufacture the semiconductor devices may include a silicon layer and a silicon germanium SiGe layer. The SiGe layer may be etched in order to create various structures on the substrate. However, etchants used to etch the SiGe layer may also etch the silicon layer. Smaller and / or more complex structures on the substrate may require a finer control of the etch rate of each of the SiGe and Silicon layers. The etch rate may be dependent, at least in part, by a mass of etchant present in a semiconductor processing chamber during the etching process. For example, a higher amount of etchant may increase the etch rate of both theSiGe and the silicon layers. In some cases, this may be desirable. In other cases, a more selective etching process may be desired, and a lower amount of etchant may be used.

[0014] To deliver the etchant to the semiconductor processing chamber, a gas mix may be introduced and broken down by a plasma. Commonly, the etchant may be included in the gas mix in percentages of about 10% to about 20%. For example, a common gas mix may include 10% nitrogen trifluoride (NF3) and 90% inert gas (e.g., helium). Common flow rates of gas mixes into the semiconductor processing chamber may range from 1 standard cubic centimeter per minute (SCCM) to 100 SCCMs or more. Even at a low flow rate, a .1 SCCM error may introduce more etchant (e.g., NF3 and / or F2) into the semiconductor processing chamber, leading to unwanted effects during the manufacturing process. While the effects of any error may be less impactful at higher flow rates (e.g., at 100 SCCMs, an error of .1 SCCM and a gas mix of 10% NF3 may result in a .01% increase in etchant), the overall amount of etchant in the semiconductor chamber may result in too high an etch rate of the SiGe and / or silicon layers.

[0015] To provide finer control over the etch rate of the SiGe and silicon layers, a gas mix of about 1% NF3 (or other etchants) may be utilized. The gas mix may be delivered in commonly used semiconductor processing chambers and tools. The lower concentration of etchant in the gas mix may allow for greater flow rates of the gas mix into the semiconductor processing chamber. For example the gas mix may be delivered to the semiconductor processing chamber at 100 SCCMs. An error of .1 SCCM in the flow rate may therefore only result in a .1% increase in the amount of NF3 in the semiconductor processing chamber during an etching process. This error may impact the etch rates of the SiGe and silicon layers within acceptable parameters.

[0016] FIG. 1A shows a top plan view of one embodiment of a processing system 10 of deposition, treating, etching, baking, and curing chambers, according to certain embodiments. In the figure, a pair of front opening unified pods 12 supply substrates of a variety of sizes that are received by robotic arms 14 and placed into a low pressure holding area 16 before being placed into one of the semiconductor processing chambers 18a-f, positioned in tandem sections 19a-c. A second robotic arm 11 may be used to transport the substrate wafers from the holding area 16 to the semiconductor processing chambers 18a-f and back. Each semiconductor processing chamber 18a-f, can be outfitted to perform a number of substrate processing operations including formation of stacks of semiconductor materials described herein in addition to plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etch, pre-clean, degas, orientation, and other substrate processes including, plasma treatments, annealing, ashing, etc.

[0017] The semiconductor processing chambers 18a-f may include one or more system components for depositing, plasma treating, curing and / or etching a dielectric or other fdm on the substrate. In one configuration, two pairs of the semiconductor processing chambers, e.g., 18c-d and 18e-f, may be used to deposit dielectric material on the substrate, and the third pair of semiconductor processing chambers, e.g., 18a-b, may be used to treat the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 18a-f, may be configured to deposit and treat stacks of alternating dielectric films on the substrate. Any one or more of the processes described may be carried out in chambers separated from the fabrication system shown in different embodiments. It will be appreciated that additional configurations of deposition, treating, etching, annealing, and curing chambers for dielectric films are contemplated by system 10.

[0018] FIG. IB shows a cross-sectional view of an exemplary processing chamber 100, according to certain embodiments. The figure may illustrate an overview of a system incorporating one or more aspects of the present technology, and / or which may be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of chamber 100 or methods performed may be described further below. Chamber 100 may be utilized to form film layers, etch material layers, form other material layers, or a combination thereof, although it is to be understood that deposition and etch methods may similarly be performed in any chamber within which deposition and etch processes may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled with the chamber body 102 and enclosing the substrate support 104 in a processing volume 120. A substrate 103 may be provided to the processing volume 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be seated on a surface 105 of the substrate support during processing. In some embodiments, the substrate support 104 may be rotatable, as indicated by the arrow 145, along an axis 147, where a shaft 144 of the substrate support 104 may be locate, or may be stationary. Alternatively, the substrate support 104 may be lifted up to rotate as necessary during a deposition process.

[0019] A gas distributor 112 may define apertures 118 for distributing process precursors into the processing volume 120. The gas distributor 112 may be coupled with a first source of electric power 142, such as an RF generator, RF power source, DC power source, pulsed DC power source, pulsed RF power source, or any other power source that may be coupled with the processing chamber. In some embodiments, the first source of electric power 142 may be an RF power source.

[0020] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, a body of the gas distributor 112 may be conductive while a face plate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by the first source of electric power 142 as shown in FIG. 1, or the gas distributor 112 may be coupled with ground in some embodiments.

[0021] A first electrode 122 may be coupled with the substrate support 104. The first electrode 122 may be embedded within the substrate support 104 or coupled with a surface of the substrate support 104. The first electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The first electrode 122 may be a tuning electrode and may be coupled with a tuning circuit 136 by a conduit 146, for example a cable having a selected resistance, such as 50 ohms, for example, disposed in the shaft 144 of the substrate support 104. The tuning circuit 136 may have an electronic sensor 138 and an electronic controller 140, which may be a variable capacitor. The electronic sensor 138 may be a voltage or current sensor and may be coupled with the second electronic controller 140 to provide further control over plasma conditions in the processing volume 120.

[0022] A second electrode 124, which may be a bias electrode and / or an electrostatic chucking electrode, may be coupled with the substrate support 104. The second electrode may be coupled with a second source of electric power 150 through a fdter 148, which may be an impedance matching circuit. The second source of electric power 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second source of electric power 150 may be an RF bias power. The substrate support 104 may also include one or more heating elements configured to heat the substrate to a processing temperature, which may be between about 25 °C and about 800 °C or greater.

[0023] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 may afford real-time control of plasma conditions in the processing volume 120, such as via a system controller 101 which may be contained within a processor 107. The substrate 103 may be disposed on the substrate support 104, and process gases may be flowed through the lid assembly 106 using an inlet 114 according to any desired flow plan. Gases may exit the processing chamber 100 through an outlet 152. Electric power may be coupled with the gas distributor 112 to establisha plasma in the processing volume 120. The substrate may be subjected to an electrical bias using the second electrode 124 in some embodiments.

[0024] Upon energizing a plasma in the processing volume 120, a potential difference may be established between the plasma and the first electrode 122. The electronic controller 140 may then be used to adjust the flow properties of the ground paths represented by the tuning circuit 136. A set point may be delivered to the first circuit 136 to provide independent control of deposition rate and of plasma density uniformity from center to edge. In embodiments where the electronic controllers may both be variable capacitors, the electronic sensors may adjust the variable capacitors to maximize deposition rate and minimize thickness non-uniformity independently.

[0025] Tuning circuit 136 may have a variable impedance that may be adjusted using the electronic controller 140. Where the electronic controller 140 is a variable capacitor, the capacitance range of each of the variable capacitors, may be chosen to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum in the capacitance range of each variable capacitor. Hence, when the capacitance of the electronic controller 140 is at a minimum or maximum, impedance of the tuning circuit 136 may be high, resulting in a plasma shape that has a minimum aerial or lateral coverage over the substrate support. When the capacitance of the electronic controller 140 approaches a value that minimizes the impedance of the tuning circuit 136, the aerial coverage of the plasma may grow to a maximum, effectively covering the entire working area of the substrate support 104. As the capacitance of the electronic controller 140 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and aerial coverage of the substrate support may decline.

[0026] The electronic sensor 138 may be used to tune the circuit 136 in a closed loop. A set point for current or voltage, depending on the type of sensor used, may be installed in each sensor, and the sensor may be provided with control software that determines an adjustment to the respective electronic controller 140 to minimize deviation from the set point. Consequently, a plasma shape may be selected and dynamically controlled during processing. It is to be understood that, while the foregoing discussion is based on electronic controller 140, which may be a variable capacitor, any electronic component with adjustable characteristic may be used to provide tuning circuit 136 with adjustable impedance.

[0027] FIG. 2 illustrates a gas canister 200 including a gas mix, according to certain embodiments. The gas canister 200 may be configured to provide gases to a semiconductor processing chamber such as the processing chamber 100 in FIG. IB. The gas canister may befluidly connected to the semiconductor processing chamber such as via the inlet 114. During operation. The gas mix may be provided to the semiconductor processing chamber via a mass flow controller. The mass flow controller may be a component of the semiconductor processing chamber or may be an independent controller. The mass flow controller may accept one or more parameters and deliver the gas mix from the gas canister 200 to the semiconductor processing chamber according to the one or more parameters. The mass flow controller may include an operating range of about .5 SCCM to about 150 SCCM, inclusive. In some embodiments, the mass flow controller may include an operating metric of about .1 SCCM to about 5 SCCM, inclusive. In some embodiments, the mass flow controller may include an operating metric of about 3 SCCM.

[0028] In some cases, the mass flow controller may have an operating range of about 10% to about 90%. This means that if the mass flow controller has an operating metric of 3 SCCM, the mass flow controller may be inaccurate at flows below about .3 SCCM and / or above about 2.7 SCCM. Thus, the range of gas mix that may be reliably provided by the mass flow controller is about 2.4 SCCM. At higher concentrations of NF3, this may not provide for enough tunability to reliably control the etching process.

[0029] The gas mix may include fluorine, chlorine, and / or another gas suitable for etching semiconductor components. The gas mix may also include one or more inert gases such as such as nitrogen, argon, helium, and other such gases. The gas mix may include etchants and inert gases at a predetermined mixture such that a specific concentration of etchant is provided to the semiconductor chamber. For example, the gas mix may include NF3 and He. During operation of the semiconductor processing chamber, the gas mix may be introduced to a plasma, as described above. Upon being introduced to the plasma, the gas mix break down into different species of gas. For example, the gas mix may include NF3 in such quantities that upon breaking down into the different species of gas, the NF3 makes up about 5% of the different species of gas (by mass). In some embodiments, the NF3 may make up about 4% of the different species of gas. In other embodiments, the NF3 may make up about 3% of the different species of gas. In other embodiments, the NF3 may make up about 2% of the different species of gas. In other embodiments, the NF3 may make up about 1% of the different species of gas. In other embodiments, the NF3 may make up about .5% of the different species of gas.

[0030] By delivering an etchant (e.g., fluorine) to the semiconductor processing chamber in concentrations of about .5% to about 5% by mass, greater control may be gained during an etching process. For example, a substrate within the semiconductor processing chamber may include asilicon layer and a silicon germanium (SiGe) layer. In order to form a desired semiconductor device, the SiGe layer may be etched using the etchant. However, while the etchant may selectively etch the SiGe layer faster than the silicon layer, some etching of the silicon layer may occur. The etch rate of the silicon layer may impact the structures able to be formed by etching the SiGe layer. For example, a desired structure may be formed by etching the SiGe layer for a given time period. The silicon layer may be etched too, however, leaving the resulting semiconductor device unusable and / or with reduced performance.

[0031] This may be especially true with commonly available concentrations of gas mixes. Furthermore, the effects of an error in the delivery of the gas mix to the semiconductor processing chamber may be magnified using the commonly available concentrations of gas mixes. For example, the mass flow controller may provide the gas mix to the semiconductor processing chamber at a rate of about three standard cubic centimeters per minute (SCCMs). To properly control the etch rate of the SiGe layer versus that of the silicon layer, the mass flow controller may slow the rate to about one SCCM. With such a low flows, the effects of any error on the etch rates may be impactful. For example, a commonly available gas mix may include 10% NF3 by mass. At 1 SCCM, an error of .1 SCCM (or a 10% error) may result in an additional 1% NF3 within the semiconductor chamber. This may result in the silicon layer being etched faster than desired, especially as compared to the etch rate of the SiGe Layer.

[0032] By contrast, a gas mix including a 1% NF3 component may provide greater control over the etch rates. For example, if the mass flow controller provides the gas mix at 10 SCCM and has the same error of .1 SCCM (or an error of 1%), the concentration of NF3 within the semiconductor processing chamber may only increase by .1% NF3 by mass. Thus, the effect on the etch rates of the silicon layer and SiGe layers may be minimized to be within acceptable parameters. If even finer control is desired, the mass flow rate may be further lowered, and the concentrations of etchants even more controlled.

[0033] FIG. 3 illustrates a flowchart of a method 300 for providing an etchant to a semiconductor processing chamber, according to certain embodiments. The method 300 may be preformed by some or all of the components and systems described herein. Some or all of the steps of the method 300 may be combined with other steps and / or performed in a different order than is described. Some steps may be skipped altogether.

[0034] At step 302, the method 300 may include providing a semiconductor substrate to a semiconductor processing chamber. The semiconductor substrate may include a silicon layer and a silicon germanium layer. The semiconductor processing chamber may be similar to the processingchamber 100 in FIG. IB. The silicon layer and the SiGe layer may be patterned to form one or more structures for a semiconductor device, the semiconductor substrate may include an etching mask to selectively etch portions of the silicon and / or SiGe layers.

[0035] At step 304, the method 300 may include connecting a gas canister to the processing chamber. The gas canister may include a gas mix. The gas mix may include NF3 in such quantities that upon breaking down into the different species of gas, the NF3 makes up about 5% of the different species of gas (by mass). In some embodiments, the NF3 may make up about 4% of the different species of gas. In other embodiments, the NF3 may make up about 3% of the different species of gas. In other embodiments, the NF3 may make up about 2% of the different species of gas. In other embodiments, the NF3 may make up about 1% of the different species of gas. In other embodiments, the NF3 may make up about .5% of the different species of gas.

[0036] At step 306, the method 300 may include providing the gas mix from the gas container to the processing chamber via a mass flow controller. The mass flow controller may provide a flow of the gas mix into the semiconductor processing chamber according to predetermined parameters. For example, the mass flow controller may provide the gas mix to the semiconductor processing chamber in a range of about 1 SCCM to about 150 SCCMs.

[0037] The gas mix may be provided to the semiconductor chamber such that an amount of NF3 within the semiconductor chamber reaches a predetermined threshold. A wafer (or substrate) within the semiconductor chamber may need to be etched in order to form a semiconductor device. A second wafer in a second semiconductor chamber may also need to be etched to form an identical semiconductor device. Because of the number of semiconductor devices produced and used throughout various industries is so high, it may be desireable to have uniform semiconductor devices produced regardless of the particular semiconductor processing chamber used. Therefore, the predetermined threshold may be a starting point for the etching process.

[0038] For example, the starting point may be a mass or volume of NF3 used to etch wafers. A first mass flow controller attached to the first semiconductor processing chamber may be slightly off, meaning that instead of providing the 3 SCCM needed to reach the starting point, the first mass controller actually provides 3.2 SCCM. A second mass controller attached to the second semiconductor processing chamber may actually provide 2.8 SCCM. Thus, although the wafers within each of the first and second semiconductor processing chambers should be identical, the wafers may experience different etch rates based on the varying levels of NF3 present within each chamber.

[0039] A computing system configured to monitor the NF3 within the semiconductor processing chambers (e.g., via monitoring an etch rate, etc.) may determine that the amount of NF3 in each of the semiconductor processing chambers is different. In response, the computing system may alter one or both of the mass flow controllers such that a consistent mass or volume of NF3 is provided to each of the semiconductor processing chambers. In other words, the amount of gas mix provided to the first semiconductor processing chamber may be based at least in part on the operating metric of the second mass flow controller.

[0040] The process described above may be performed during a semiconductor manufacturing process; that is during production of semiconductor devices. In some embodiments, the above process may be performed as part of a validation process (e.g., before actual production begins).

[0041] At step 308, the method 300 may include generating a plasma within the semiconductor processing chamber such that F2 is formed. For example, the gas mix may include 1% NF3 and 99% Helium. When introduced to the plasma, the gas mix may break down into NF and F2. The F2 may be radical fluorine and may interact with the silicon and / or the SiGe layers to etch the semiconductor substrate.

[0042] At step 310, the method 300 may include etching the SiGe layer of the semiconductor substrate using the F2. The silicon layer may also be etched by the F2. After etching the SiGe and / or the silicon layer, the semiconductor substrate may be further processed to manufacture a semiconductor device.

[0043] FIG. 4 illustrates an exemplary computer system 400, in which various embodiments may be implemented. The system 400 may be used to implement any of the computer systems described above. As shown in the figure, computer system 400 includes a processing unit 404 that communicates with a number of peripheral subsystems via a bus subsystem 402. These peripheral subsystems may include a processing acceleration unit 406, an I / O subsystem 408, a storage subsystem 418 and a communications subsystem 424. Storage subsystem 418 includes tangible computer-readable storage media 422 and a system memory 410.

[0044] Bus subsystem 402 provides a mechanism for letting the various components and subsystems of computer system 400 communicate with each other as intended. Although bus subsystem 402 is shown schematically as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. Bus subsystem 402 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. For example, such architectures may include an Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA)bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus, which can be implemented as a Mezzanine bus manufactured to the IEEE Pl 386.1 standard.

[0045] Processing unit 404, which can be implemented as one or more integrated circuits (e.g., a conventional microprocessor or microcontroller), controls the operation of computer system 400. One or more processors may be included in processing unit 404. These processors may include single core or multicore processors. In certain embodiments, processing unit 404 may be implemented as one or more independent processing units 432 and / or 434 with single or multicore processors included in each processing unit. In other embodiments, processing unit 404 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0046] In various embodiments, processing unit 404 can execute a variety of programs in response to program code and can maintain multiple concurrently executing programs or processes. At any given time, some or all of the program code to be executed can be resident in processor(s) 404 and / or in storage subsystem 418. Through suitable programming, processor(s) 404 can provide various functionalities described above. Computer system 400 may additionally include a processing acceleration unit 406, which can include a digital signal processor (DSP), a special-purpose processor, and / or the like.

[0047] I / O subsystem 408 may include user interface input devices and user interface output devices. User interface input devices may include a keyboard, pointing devices such as a mouse or trackball, a touchpad or touch screen incorporated into a display, a scroll wheel, a click wheel, a dial, a button, a switch, a keypad, audio input devices with voice command recognition systems, microphones, and other types of input devices. User interface input devices may include, for example, motion sensing and / or gesture recognition devices that enables users to control and interact with an input device through a natural user interface using gestures and spoken commands. Additionally, user interface input devices may include voice recognition sensing devices that enable users to interact with voice recognition systems through voice commands.

[0048] User interface input devices may also include, without limitation, three dimensional (3D) mice, joysticks or pointing sticks, gamepads and graphic tablets, and audio / visual devices such as speakers, digital cameras, digital camcorders, portable media players, webcams, image scanners, fingerprint scanners, barcode reader, 3D scanners, 3D printers, laser rangefinders, and eye gaze tracking devices. Additionally, user interface input devices may include, for example, medical imaging input devices such as computed tomography, magnetic resonance imaging, positionemission tomography, medical ultrasonography devices. User interface input devices may also include, for example, audio input devices such as MIDI keyboards, digital musical instruments and the like.

[0049] User interface output devices may include a display subsystem, indicator lights, or nonvisual displays such as audio output devices, etc. The display subsystem may be a cathode ray tube (CRT), a flat-panel device, such as that using a liquid crystal display (LCD) or plasma display, a projection device, a touch screen, and the like. In general, use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from computer system 400 to a user or other computer. For example, user interface output devices may include, without limitation, a variety of display devices that visually convey text, graphics and audio / video information such as monitors, printers, speakers, headphones, automotive navigation systems, plotters, voice output devices, and modems.

[0050] Computer system 400 may comprise a storage subsystem 418 that comprises software elements, shown as being currently located within a system memory 410. System memory 410 may store program instructions that are loadable and executable on processing unit 404, as well as data generated during the execution of these programs.

[0051] Depending on the configuration and type of computer system 400, system memory 410 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read-only memory (ROM), flash memory, etc.). The RAM typically contains data and / or program modules that are immediately accessible to and / or presently being operated and executed by processing unit 404. In some implementations, system memory 410 may include multiple different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, a basic input / output system (BIOS), containing the basic routines that help to transfer information between elements within computer system 400, such as during start-up, may typically be stored in the ROM. By way of example, and not limitation, system memory 410 also illustrates application programs 412, which may include client applications, Web browsers, mid-tier applications, relational database management systems (RDBMS), etc., program data 414, and an operating system 416.

[0052] Storage subsystem 418 may also provide a tangible computer-readable storage medium for storing the basic programming and data constructs that provide the functionality of some embodiments. Software (programs, code modules, instructions) that when executed by a processor provide the functionality described above may be stored in storage subsystem 418. These softwaremodules or instructions may be executed by processing unit 404. Storage subsystem 418 may also provide a repository for storing data used in accordance with some embodiments.

[0053] Storage subsystem 400 may also include a computer-readable storage media reader 420 that can further be connected to computer-readable storage media 422. Together and, optionally, in combination with system memory 410, computer-readable storage media 422 may comprehensively represent remote, local, fixed, and / or removable storage devices plus storage media for temporarily and / or more permanently containing, storing, transmitting, and retrieving computer-readable information.

[0054] Computer-readable storage media 422 containing code, or portions of code, can also include any appropriate media, including storage media and communication media, such as but not limited to, volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage and / or transmission of information. This can include tangible computer-readable storage media such as RAM, ROM, electronically erasable programmable ROM (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD), or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other tangible computer readable media. This can also include nontangible computer-readable media, such as data signals, data transmissions, or any other medium which can be used to transmit the desired information and which can be accessed by computing system 400.

[0055] By way of example, computer-readable storage media 422 may include a hard disk drive that reads from or writes to non-removable, nonvolatile magnetic media, a magnetic disk drive that reads from or writes to a removable, nonvolatile magnetic disk, and an optical disk drive that reads from or writes to a removable, nonvolatile optical disk such as a CD ROM, DVD or other optical media. Computer-readable storage media 422 may include, but is not limited to, flash memory cards, universal serial bus (USB) flash drives, secure digital (SD) cards, DVD disks, digital video tape, and the like. Computer-readable storage media 422 may also include, solid-state drives (SSD) based on non-volatile memory such as flash-memory based SSDs, enterprise flash drives, solid state ROM, and the like, SSDs based on volatile memory such as solid state RAM, dynamic RAM, static RAM, DRAM-based SSDs, magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs that use a combination of DRAM and flash memory based SSDs. The disk drives and their associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for computer system 400.

[0056] Communications subsystem 424 provides an interface to other computer systems and networks. Communications subsystem 424 serves as an interface for receiving data from and transmitting data to other systems from computer system 400. For example, communications subsystem 424 may enable computer system 400 to connect to one or more devices via the Internet. In some embodiments communications subsystem 424 can include radio frequency (RF) transceiver components for accessing wireless voice and / or data networks (e.g., using cellular telephone technology, advanced data network technology, such as 3G, 4G, 5G, or EDGE (enhanced data rates for global evolution), WiFi (IEEE 802.4 family standards, or other mobile communication technologies, or any combination thereof), global positioning system (GPS) receiver components, and / or other components. In some embodiments communications subsystem 424 can provide wired network connectivity (e.g., Ethernet) in addition to or instead of a wireless interface.

[0057] In some embodiments, communications subsystem 424 may also receive input communication in the form of structured and / or unstructured data feeds 426, event streams 428, event updates 430, and the like on behalf of one or more users who may use computer system 400.

[0058] By way of example, communications subsystem 424 may be configured to receive data feeds 426 in real-time from users of social networks and / or other communication services, web feeds such as Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third party information sources.

[0059] Additionally, communications subsystem 424 may also be configured to receive data in the form of continuous data streams, which may include event streams 428 of real-time events and / or event updates 430, that may be continuous or unbounded in nature with no explicit end. Examples of applications that generate continuous data may include, for example, sensor data applications, financial tickers, network performance measuring tools (e.g. network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, and the like.

[0060] Communications subsystem 424 may also be configured to output the structured and / or unstructured data feeds 426, event streams 428, event updates 430, and the like to one or more databases that may be in communication with one or more streaming data source computers coupled to computer system 400.

[0061] Due to the ever-changing nature of computers and networks, the description of computer system 400 depicted in the figure is intended only as a specific example. Many other configurations having more or fewer components than the system depicted in the figure arepossible. For example, customized hardware might also be used and / or particular elements might be implemented in hardware, firmware, software (including applets), or a combination. Further, connection to other computing devices, such as network input / output devices, may be employed. Based on the disclosure and teachings provided herein, other ways and / or methods to implement the various embodiments should be apparent.

[0062] In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0063] The foregoing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments as set forth in the appended claims.

[0064] Specific details are given in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail in order to avoid obscuring the embodiments.

[0065] Also, it is noted that individual embodiments may have beeen described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may have described the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed, but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

[0066] The term “computer-readable medium” includes, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable ofstoring, containing, or carrying instruction(s) and / or data. A code segment or machine-executable instructions may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0067] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine readable medium. A processor(s) may perform the necessary tasks.

[0068] In the foregoing specification, features are described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or jointly. Further, embodiments can be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive.

[0069] Additionally, for the purposes of illustration, methods were described in a particular order. It should be appreciated that in alternate embodiments, the methods may be performed in a different order than that described. It should also be appreciated that the methods described above may be performed by hardware components or may be embodied in sequences of machineexecutable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the methods. These machine-executable instructions may be stored on one or more machine readable mediums, such as CD-ROMs or other type of optical disks, floppy diskettes, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or other types of machine- readable mediums suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

[0070] In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of various embodiments. It will beapparent, however, that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0071] The foregoing description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments as set forth in the appended claims.

[0072] Specific details are given in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail in order to avoid obscuring the embodiments.

[0073] Also, it is noted that individual embodiments may have beeen described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may have described the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

Claims

WHAT IS CLAIMED IS:

1. A system of semiconductor manufacturing, comprising: a gas canister comprising a gas mix comprising NF3 in a range of about .5% to about 5%, inclusive; a semiconductor processing chamber; a mass flow controller, configured to provide the gas mix to the semiconductor processing chamber; and a substrate support disposed within the semiconductor processing chamber.

2. The system of any of the preceding claims, wherein the mass flow controller provides the gas mix to the semiconductor processing chamber at about 1 standard cubic centimeter per minute to about 150 standard cubic centimeters per minute.

3. The system of any of the preceding claims, wherein the gas mix is used to perform an etching process on a substrate comprising silicon germanium.

4. The system of any of the preceding claims, wherein the gas mix comprises nitrogen.

5. The system of any of the preceding claims, wherein the gas mix comprises helium.

6. The system of any of the preceding claims, wherein the mass flow controller operates within a window of between 10% and 90% of an operating range of the mass flow controller.

7. The system of any of the preceding claims, wherein the mass flow controller is adjusted such that a volume of NF3 in the semiconductor processing chamber reaches a predetermined threshold.

8. A method, comprising: providing a semiconductor substrate disposed within a processing chamber, wherein the semiconductor substrate comprises a layer of silicon germanium (SiGe); connecting a gas canister comprising a gas mix of about 1% nitrogen trifluoride (NF3) to the processing chamber; providing the gas mix from the gas canister to the processing chamber via a mass flow controller;adjusting the mass flow controller such that a component of the gas reaches a predetermined level within the semiconductor processing chamber; generating a plasma within the semiconductor processing chamber such that F2 is formed; and etching the SiGe layer of the semiconductor substrate using the F2.

9. The method of claim 8, wherein the mass flow controller comprises an operating metric within a range of 1 standard cubic centimeter per minute (SCCM) to 5 SCCM, inclusive.

10. The method of any of claims 8-9, wherein the predetermined level within the semiconductor processing chamber is based at least partially on an operating metric of a second mass flow controller of a second semiconductor processing chamber.

11. The method of any of claims 8-10, wherein adjusting the mass flow controller is performed as part of a verification routine.

12. The method of any of claims 8-11, wherein the mass flow controller is adjusted at least in part by a computing system configured to match a volume of the component of the gas within the semiconductor processing chamber to a second volume of the component of the gas within a second semiconductor chamber.

13. The method of any of claims 8-12 wherein the mass flow controller operates within a window of between 10% and 90% of an operating range of the mass flow controller.

14. A system, comprising: a semiconductor processing chamber, comprising: a substrate holder, configured to support a semiconductor substrate; a gas canister, comprising a gas mix; a mass flow controller, fluidly connected to the gas canister and configured to provide a gas to the semiconductor chamber; one or more processors; and a computer-readable medium comprising instructions, that, when executed by the one or more processors, cause the system to perform operations comprising: causing the gas mix from the gas canister to be provided to the processing chamber via the mass flow controller; andadjusting the mass flow controller such that a component of the gas reaches a predetermined level within the semiconductor processing chamber.

15. The system of claim 14, wherein the mass flow controller comprises an operating metric within a range of 1 standard cubic centimeter per minute (SCCM) to 5 SCCM, inclusive.

16. The system of any of claims 14-15, wherein the predetermined level within the semiconductor processing chamber is based at least partially on an operating metric of a second mass flow controller of a second semiconductor processing chamber.

17. The system of any of claims 14-16, wherein adjusting the mass flow controller is performed as part of a verification routine.

18. The system of any of claims 14-17, wherein the mass flow controller is adjusted at least in part by a computing system configured to match a volume of the component of the gas within the semiconductor processing chamber to a second volume of the component of the gas within a second semiconductor chamber.

19. The system of any of claims 14-18, wherein the mass flow controller operates within a window of between 10% and 90% of an operating range of the mass flow controller.

20. The system of any of claims 14-18, wherein the gas mix comprises NF3.19

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