Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. In the display panel, by means of connecting a second electrode of a photoelectric unit to one of a first initialization signal line and a second initialization signal line, the number of signal lines in a drive circuit layer is reduced, and the total area occupied by a sensing circuit and pixel driving circuits is reduced, thereby improving the aperture ratio of the display panel and enhancing the resolution of the display panel.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays are widely used in various fields due to their lightweight, wide viewing angle, fast response, low-temperature resistance, high luminous efficiency, and the ability to create flexible, curved displays. To implement fingerprint recognition, OLED displays often incorporate a fingerprint module. Fingerprint recognition technologies are categorized into capacitive, optical, and ultrasonic technologies. Optical fingerprint recognition includes both under-display and in-display technologies. With the trend toward thinner and lighter displays, in-display optical fingerprint recognition has become a popular choice for OLED displays. In-display optical fingerprint recognition integrates an optical fingerprint sensor within the display. This technology uses infrared light to illuminate a finger and reflect it back. The optical fingerprint sensor then receives the reflected light and extracts fingerprint features, thereby enabling fingerprint recognition. To achieve this, an optical fingerprint sensor and thin-film transistors form a fingerprint recognition circuit to accurately identify fingerprints. Furthermore, the display device requires a pixel driver circuit to ensure proper display. Existing separate fingerprint recognition and pixel driver circuits occupy a large space and reduce the resolution of the display device.

[0003] Therefore, existing display devices have a technical problem in that the fingerprint recognition circuit and the pixel driving circuit occupy a large space, resulting in a low resolution of the display device. SUMMARY OF THE INVENTION

[0004] Embodiments of the present application provide a display panel and a display device to solve the technical problem in existing display devices that a fingerprint recognition circuit and a pixel driving circuit occupy a large space, resulting in a low resolution of the display device.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] An embodiment of the present application provides a display panel, comprising:

[0007] substrate;

[0008] A driving circuit layer, the driving circuit layer being arranged on one side of the substrate, the driving circuit layer comprising: a pixel driving circuit and a sensing circuit arranged between adjacent pixel driving circuits;

[0009] a light-emitting layer, arranged on a side of the driving circuit layer away from the substrate, the light-emitting layer comprising: light-emitting devices arranged corresponding to the pixel driving circuits, the light-emitting devices being electrically connected to the corresponding pixel driving circuits;

[0010] The pixel driving circuit includes: a switching transistor, a driving transistor, a first initialization transistor, and a second initialization transistor, wherein the switching transistor and the driving transistor are connected to a first node, and the switching transistor is used to input a data signal to the first node under the control of a first scanning signal, an electrode of the first initialization transistor is connected to the driving transistor at a second node, and the other electrode of the first initialization transistor is connected to a first initialization signal line, an electrode of the second initialization transistor is connected to the light-emitting device at a third node, and the other electrode of the second initialization transistor is connected to a second initialization signal line, the second initialization transistor is used to input a second initialization signal to an anode of the light-emitting device under the control of a second scanning signal, and the first initialization transistor is used to input a first initialization signal to the second node under the control of a third scanning signal;

[0011] The sensing circuit includes a photoelectric unit and a sensing signal output line, wherein a first electrode of the photoelectric unit is electrically connected to the sensing signal output line, and a second electrode of the photoelectric unit is connected to one of the first initialization signal line and the second initialization signal line.

[0012] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0014] FIG1 is a first schematic diagram of a display panel provided in an embodiment of the present application.

[0015] FIG2 is a circuit diagram of a pixel driving circuit provided in an embodiment of the present application.

[0016] FIG3 is a circuit diagram of a sensing circuit provided in an embodiment of the present application.

[0017] FIG4 is a second schematic diagram of a display panel provided in an embodiment of the present application.

[0018] FIG5 is a schematic diagram of a first stacking method of each film layer in a repeating unit provided in an embodiment of the present application.

[0019] FIG. 6 is an exploded view of each film layer of the repeating unit in FIG. 5 .

[0020] FIG7 is a schematic diagram of a second stacking method of each film layer in a repeating unit provided in an embodiment of the present application.

[0021] FIG. 8 is an exploded view of the film layers of the repeating unit provided in FIG. 7 .

[0022] FIG9 is a schematic diagram of a third stacking method of each film layer in a repeating unit provided in an embodiment of the present application.

[0023] FIG. 10 is an exploded view of the film layers of the repeating unit provided in FIG. 9 .

[0024] FIG11 is a schematic diagram of a fourth stacking method of each film layer in a repeating unit provided in an embodiment of the present application.

[0025] FIG. 12 is an exploded view of the film layers of the repeating unit provided in FIG. 11 . Modes for Carrying Out the Invention

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0027] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0029] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0030] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0031] The embodiments of the present application address the technical problem that a fingerprint recognition circuit and a pixel driving circuit in existing display devices occupy a large space, resulting in a low resolution of the display device. A display panel and a display device are provided to improve the above technical problem.

[0032] Figure 1 is a first schematic diagram of a display panel provided in an embodiment of the present application. Figure 2 is a circuit diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 3 is a circuit diagram of a sensing circuit provided in an embodiment of the present application. Figure 4 is a second schematic diagram of a display panel provided in an embodiment of the present application. Figure 5 is a first schematic diagram of stacking of each film layer in a repeating unit provided in an embodiment of the present application. Figure 6 is an exploded view of each film layer of the repeating unit in Figure 5. Figure 7 is a second schematic diagram of stacking of each film layer in a repeating unit provided in an embodiment of the present application. Figure 8 is an exploded view of each film layer of the repeating unit provided in Figure 7. Figure 9 is a third schematic diagram of stacking of each film layer in a repeating unit provided in an embodiment of the present application. Figure 10 is an exploded view of each film layer of the repeating unit provided in Figure 9. Figure 11 is a fourth schematic diagram of stacking of each film layer in a repeating unit provided in an embodiment of the present application. Figure 12 is an exploded view of each film layer of the repeating unit provided in Figure 11.

[0033] As shown in FIG. 1 to FIG. 12 , an embodiment of the present application provides a display panel. The display panel 1 includes:

[0034] substrate 101;

[0035] A driving circuit layer 12 , which is disposed on one side of the substrate 101 , and includes: a pixel driving circuit 10 and a sensing circuit 20 disposed between adjacent pixel driving circuits 10 ;

[0036] a light-emitting layer 13 disposed on a side of the driving circuit layer 12 away from the substrate, the light-emitting layer 13 including: light-emitting devices LEDs disposed corresponding to the pixel driving circuits 10, the light-emitting devices LEDs being electrically connected to the corresponding pixel driving circuits 10;

[0037] The pixel driving circuit 10 includes: a switching transistor T2, a driving transistor T1, a first initialization transistor T4, and a second initialization transistor T7. The switching transistor T2 and the driving transistor T1 are connected to a first node A. The switching transistor T2 is used to input a data signal to the first node A under the control of a first scan signal. One electrode of the first initialization transistor T4 is connected to the driving transistor T1 and a second node Q. The other electrode of the first initialization transistor T4 is connected to a first initialization signal line VI-G. One electrode of the second initialization transistor T7 is connected to a third node C of the light-emitting device LED. The other electrode of the second initialization transistor T7 is connected to a second initialization signal line VI-ANO. The second initialization transistor T7 is used to input a second initialization signal to the anode of the light-emitting device LED under the control of a second scan signal. The first initialization transistor T4 is used to input a first initialization signal to the second node Q under the control of a third scan signal.

[0038] The sensing circuit 20 includes: a photoelectric unit 21 and a sensing signal output line Readout, the first electrode of the photoelectric unit 21 is electrically connected to the sensing signal output line Readout, and the second electrode of the photoelectric unit 21 is connected to one of the first initialization signal line VI-G and the second initialization signal line VI-ANO.

[0039] An embodiment of the present application provides a display panel, which reduces the number of signal lines in the driving circuit layer and the total area occupied by the sensing circuit and the pixel driving circuit by connecting the second electrode of the photoelectric unit to one of the first initialization signal line and the second initialization signal line, thereby improving the aperture ratio of the display panel and improving the resolution of the display panel.

[0040] Specifically, the photoelectric unit includes a photodiode.

[0041] Specifically, in FIG. 3 , the photoelectric unit 21 is represented by a fixed capacitor Cs and a diode PD. It can be understood that the photoelectric unit 21 has a fixed capacitor Cs, and the photoelectric unit 21 can be simplified as a diode PD.

[0042] Specifically, the drawings in the embodiments of the present application show the design of a repeating unit 100 in the display panel. For the design of other parts of the display panel, reference can be made to the design in this repeating unit 100.

[0043] Specifically, a pixel driving circuit and a light-emitting device are provided in the sub-pixel unit, and each sub-pixel unit has a corresponding pixel driving circuit. The correspondence between a pixel driving circuit and a sub-pixel unit means that each sub-pixel unit will be driven by the corresponding pixel driving circuit. When each transistor and signal line in the pixel driving circuit is located in the sub-pixel unit, the pixel driving circuit located in the sub-pixel unit corresponds to the sub-pixel unit. When some transistors and wirings in the pixel driving circuit will adopt transistors and wirings set in other sub-pixel units, the pixel driving circuit that adopts the transistors and wirings in other sub-pixel units and drives the sub-pixel unit corresponds to the sub-pixel unit.

[0044] Specifically, in Figures 5 to 12, since the second initialization transistor T7 and the second initialization signal line VI-ANO in the pixel driving circuit are the second initialization transistor T7 and the second initialization signal line VI-ANO in the sub-pixel unit of the previous row, the other transistors and signal lines in the pixel driving circuit are the transistors and signal lines in the sub-pixel unit of this row. Therefore, in order to illustrate the design of the signal lines and transistors of the pixel driving circuit and the sensing circuit in the repeating unit, in Figures 5 to 12, the drawings do not show the second initialization transistor T7 in the sub-pixel unit of this row, and some drawings do not show the second initialization transistor T7 in the sub-pixel unit of this row. Signal line VI-ANO, it can be understood that the structure of the pixel driving circuit in each adjacent two sub-pixel units is the same. Therefore, when the structure and setting position of the second initialization transistor T7 in the sub-pixel unit of the current row and the second initialization signal line VI-ANO in the sub-pixel unit of the current row are not shown, the structure and setting position of the second initialization transistor T7 in the sub-pixel unit of the current row and the second initialization signal line VI-ANO in the sub-pixel unit of the current row can refer to the structure and setting position of the second initialization transistor T7 in the sub-pixel unit of the previous row and the second initialization signal line VI-ANO in the sub-pixel unit of the previous row. Therefore, in the following embodiments, when not specifically stated, the second initialization transistor T7 and the second initialization signal line VI-ANO are the second initialization transistor T7 and the second initialization signal line VI-ANO determined according to the connection relationship between each transistor and the signal line in the pixel driving circuit, that is, the second initialization transistor T7 and the second initialization signal line VI-ANO in the pixel driving circuit of the sub-pixel unit of the current row refer to the second initialization transistor T7 and the second initialization signal line VI-ANO in the sub-pixel unit of the previous row.

[0045] Specifically, the structure of the light emitting device LED is not shown in FIG5 to FIG12.

[0046] For example, as shown in Figures 5 and 6, the repeating unit 100 includes two sub-pixel units 40, and the repeating unit 100 includes a pixel driving circuit 10 and a sensing circuit 20. Since the second initialization transistor T7 and the second initialization signal line VI-ANO in the pixel driving circuit 10 corresponding to the sub-pixel unit in this row use the second initialization transistor T7 and the second initialization signal line VI-ANO in the sub-pixel unit in the previous row, Figures 5 and 6 show the structure of the second initialization transistor T7 and the second initialization signal line VI-ANO in the sub-pixel unit in the previous row, and the structure of the second initialization transistor T7 and the second initialization signal line VI-ANO in the sub-pixel unit in this row is not shown. It can be understood that the structure of the second initialization transistor T7 and the second initialization signal line VI-ANO in the sub-pixel unit in this row can refer to the structure and setting position of the second initialization transistor T7 and the second initialization signal line VI-ANO in the sub-pixel unit in the previous row.

[0047] Specifically, with respect to Figures 9 to 12, since only the connection between the second initialization transistor T7 in the upper row of sub-pixel units and the second initialization signal line VI-ANO is shown, the connection relationship between the second initialization signal line VI-ANO in the upper row of sub-pixel units and the second electrode of the photoelectric unit is not shown. Therefore, in Figures 9 to 12, there is a difference in the structure of the second initialization signal line VI-ANO in the upper row and the second initialization signal line VI-ANO in the current row. When the second initialization signal line VI-ANO in the upper row of sub-pixel units and the second initialization signal line VI-ANO in the current row are respectively connected to the second electrodes of the two photoelectric units, the structure of the second initialization signal line VI-ANO in the upper row and the second initialization signal line VI-ANO in the current row are the same.

[0048] Specifically, in Figures 5 to 12, compared to the pixel driving circuit 10 and the sensing circuit 20, which show various nodes, electrodes of various transistors, and signal lines, in actual designs, some nodes and electrodes are shared, so that in Figures 5 to 12, some structures can be electrodes or active portions of multiple transistors, or can be connection points between transistors and signal lines, or can be electrodes and nodes of various transistors. For example, in Figure 2, it can be seen that the first electrode of the switching transistor T2 is connected to the data line Data. Therefore, in (f) in Figure 6, a structure is both the data connection line Data-1 and the first electrode T2S of the switching transistor T2. Similarly, other structures can be multiple of signal lines, nodes, electrodes, and active portions. Accordingly, when signal lines and electrodes are connected, the signal lines and electrodes can also share various parts of the same structure.

[0049] Specifically, since some electrodes and / or signal lines are connected together, a structure may only indicate one electrode or one signal line. It is understandable that the structure may also include other electrodes or signal lines connected to the electrode or signal line.

[0050] Specifically, since the active parts of some transistors are connected together, some nodes and electrodes in the circuit diagram are not marked. For example, the first node A is the connection node of the first electrode of the driving transistor T1, the second electrode of the switching transistor T2, and the second electrode of the first light-emitting transistor T5. The active parts of the driving transistor T1, the switching transistor T2, and the first light-emitting transistor T5 share the same structure. Therefore, there is no need to separately set the first electrode of the driving transistor T1, the second electrode of the switching transistor T2, and the second electrode of the first light-emitting transistor T5. Accordingly, the first node A does not exist in the exploded view of each film layer. It can be understood that the first node A is located at the connection point of the active parts of the driving transistor T1, the switching transistor T2, and the first light-emitting transistor T5.

[0051] Specifically, in actual design, the second initialization signal lines VI-ANO of each row will be connected together and input signals at the same time. Therefore, the distinction between the second initialization signal lines VI-ANO of each row is only to illustrate their connection method. For the signals of each second initialization signal line VI-ANO, it can be understood that, without considering the impedance, the signals of the second initialization signal lines VI-ANO of each row are the same.

[0052] Specifically, in the following embodiments, the connection between the second electrode of the photoelectric unit and the second initialization signal line VI-ANO in the sub-pixel unit of the current row is taken as an example for explanation. Therefore, Figures 9 to 12 will show the second electrode of the photoelectric unit and the second initialization signal line VI-ANO in the sub-pixel unit of the current row, and at the same time, the second initialization signal line VI-ANO in the sub-pixel unit of the previous row will be shown.

[0053] Specifically, since each level of gate driving unit in the gate driving circuit outputs one Pscan signal and each level of gate driving unit outputs two Nscan signals, in Figure 2, the first scan line Pscan (n) is a scan line within the sub-pixel unit of this row, the second scan line Pscan (n-1) is a scan line within the sub-pixel unit of the previous row, the third scan line Nscan (n-5) and the fourth scan line Nscan (n) are two scan lines connected to the first-level gate driving unit, and the third scan line Nscan (n-5) and the fourth scan line Nscan (n) are two scan lines within a row of sub-pixel units.

[0054] Specifically, n is greater than or equal to 6, and n is a positive integer.

[0055] In some embodiments, the driving chip includes a voltage dividing circuit 30 , which includes a high-potential signal line SVDD, a voltage dividing transistor T0 , and a voltage dividing control line Vb.

[0056] In some embodiments, as shown in FIG5 , the repeating unit 100 includes two sub-pixel units 40, the two pixel driving circuits 10 corresponding to the two sub-pixel units 40 are symmetrically arranged, and the photoelectric unit 21 is arranged along the symmetry axis of the two pixel driving circuits 10. By having the repeating unit include two sub-pixel units, the pixel driving circuits of the two sub-pixel units are symmetrically arranged, and the photoelectric unit is arranged on one side of the pixel driving circuit along the symmetry axis of the two pixel driving circuits. This allows the pixel circuits in the display panel to be symmetrically arranged, maintains a consistent voltage drop, and prevents signal lines of the pixel driving circuit and the sensing circuit from interfering with each other, thereby improving the display effect.

[0057] Specifically, as shown in FIG. 5 , the two adjacent pixel driving circuits 10 are symmetrically arranged, and the photoelectric unit 21 is arranged along the direction of the symmetry axis of the two pixel driving circuits 10 and is arranged on one side of one pixel driving circuit 10 .

[0058] Specifically, the signal lines in the sensing circuit are arranged at the lower side of the pixel driving circuit, so that the pixel circuits are symmetrically arranged with a consistent voltage drop, and the signal lines of the pixel driving circuit and the sensing circuit do not interfere with each other, thereby improving the display effect.

[0059] In some embodiments, as shown in FIG2 , the pixel driving circuit 10 further includes a compensation transistor T3 , a first light emitting transistor T5 , and a second light emitting transistor T6 ;

[0060] The compensation transistor T3 and the driving transistor T1 are connected to the second node Q and the fourth node B, and are used to compensate for the threshold voltage of the driving transistor T1 under the control of the fourth scan signal;

[0061] A first light-emitting transistor T5 is connected to the driving transistor T1 at a first node A, and is used to conduct current from the first power signal line VDD to the driving transistor T1 under the control of a light-emitting control signal;

[0062] The second light emitting transistor T6 is connected to the driving transistor T1 at a fourth node B, and is configured to conduct the current from the driving transistor T1 to the light emitting device LED under the control of a light emitting control signal.

[0063] In some embodiments, as shown in FIG2 , the pixel driving circuit 10 further includes a storage capacitor Cst and a boost capacitor Cboost, wherein one plate of the storage capacitor Cst is connected to the first power signal line VDD, the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1, one plate of the boost capacitor Cboost is connected to the first scan line Pscan(n), and the other plate of the boost capacitor Cboost is connected to the gate of the driving transistor T1.

[0064] In some embodiments, as shown in FIG7 , the repeating unit 100 includes two sub-pixel units 40. The two pixel driving circuits 10 corresponding to the two sub-pixel units 40 are symmetrically arranged. A portion of the sensing circuit 20 is arranged on a side of one pixel driving circuit 10 away from the other pixel driving circuit 10, and a portion of the sensing circuit 20 is arranged on one side of the pixel driving circuit 10 along the direction of the symmetry axis of the two pixel driving circuits 10. By arranging the sensing circuit on one side of the pixel driving circuit in the second direction and on a side of one pixel driving circuit away from the other pixel driving circuit in the first direction, the second initialization transistor does not need to be provided with a jumper, the distribution of the holes within the repeating unit is more uniform, the process requirements are lower, and higher resolution can be achieved.

[0065] In some embodiments, as shown in FIG3 , the sensing circuit 20 further includes an amplifier transistor T9, a control transistor T10, and a reset transistor T11. The gate of the amplifier transistor T9 is connected to one end of the photoelectric cell 21. One electrode of the amplifier transistor T9 is connected to one electrode of the control transistor T10, and the other electrode of the amplifier transistor T9 is connected to one electrode of the reset transistor T11. The other electrode of the control transistor T10 is connected to a sensing signal output line Readout, and the other electrode of the reset transistor T11 is connected to one end of the photoelectric cell 21. The amplifier transistor T9 is used to amplify the signal of the photoelectric cell 21. The control transistor T10 is used to control the output of the signal of the photoelectric cell 21 under the control of a control signal. The reset transistor T11 is used to reset the first electrode of the photoelectric cell under the control of a reset control signal. By providing a reset transistor to reset the first electrode of the photoelectric cell, signal interference caused by failure to reset the first electrode of the photoelectric cell is avoided, the accuracy of the photoelectric cell signal is improved, and the accuracy of fingerprint recognition is improved. By amplifying the signal of the photoelectric cell by the amplifier transistor, the range of fingerprint recognition can be increased, and the sensitivity of fingerprint recognition can be increased.

[0066] In some embodiments, as shown in FIG4 , the driving circuit layer 12 further includes:

[0067] A first active layer 106 is provided on one side of the substrate 101;

[0068] A first metal layer 108 is disposed on a side of the first active layer 106 away from the substrate 101;

[0069] The second metal layer 110 is disposed on a side of the first metal layer 108 away from the first active layer 106;

[0070] a second active layer 116 disposed on a side of the second metal layer 110 away from the first metal layer 108;

[0071] A third metal layer 118 is disposed on a side of the second active layer 116 away from the second metal layer 110 ;

[0072] A first source and drain electrode layer 120 is disposed on a side of the third metal layer 118 away from the second active layer 116 ;

[0073] A second source-drain electrode layer 122 is disposed on a side of the first source-drain electrode layer 120 away from the third metal layer 118 ;

[0074] The second electrode of the photoelectric unit 21 is disposed on the second metal layer 110. By disposing the second electrode of the photoelectric unit on the second metal layer, the film layers of the display panel can be reduced, thereby reducing the thickness of the display panel.

[0075] Specifically, as shown in Figure 4, the photoelectric unit 21 includes a second electrode located in the second metal layer 110, a photosensitive pattern 112, a first electrode 114 and a plate of a fixed capacitor. The second electrode of the photoelectric unit 21 serves as another plate of the fixed capacitor, and the first electrode 114 of the photoelectric unit 21 is connected to the plate of the fixed capacitor through the pattern of the first source and drain layer 120.

[0076] Specifically, FIG6(a) is an exploded view of the first active layer of the repeating unit in FIG6. FIG6(b) is an exploded view of the first metal layer of the repeating unit in FIG6. FIG6(c) is an exploded view of the second metal layer of the repeating unit in FIG6. FIG6(d) is an exploded view of the second active layer of the repeating unit in FIG6. FIG6(e) is an exploded view of the third metal layer of the repeating unit in FIG6. FIG6(f) is an exploded view of the first source and drain layer of the repeating unit in FIG6. FIG6(g) is an exploded view of the second source and drain layer of the repeating unit in FIG6.

[0077] Specifically, FIG8(a) is an exploded view of the first active layer of the repeating unit in FIG8 . FIG8(b) is an exploded view of the first metal layer of the repeating unit in FIG8 . FIG8(c) is an exploded view of the second metal layer of the repeating unit in FIG8 . FIG8(d) is an exploded view of the second active layer of the repeating unit in FIG8 . FIG8(e) is an exploded view of the third metal layer of the repeating unit in FIG8 . FIG8(f) is an exploded view of the first source and drain layer of the repeating unit in FIG8 . FIG8(g) is an exploded view of the second source and drain layer of the repeating unit in FIG8 .

[0078] Specifically, FIG10(a) is an exploded view of the first active layer of the repeating unit in FIG9. FIG10(b) is an exploded view of the first metal layer of the repeating unit in FIG9. FIG10(c) is an exploded view of the second metal layer of the repeating unit in FIG9. FIG10(d) is an exploded view of the second active layer of the repeating unit in FIG9. FIG10(e) is an exploded view of the third metal layer of the repeating unit in FIG9. FIG10(f) is an exploded view of the first source and drain layer of the repeating unit in FIG9. FIG10(g) is an exploded view of the second source and drain layer of the repeating unit in FIG9.

[0079] Specifically, FIG12(a) is an exploded view of the first active layer of the repeating unit in FIG11. FIG12(b) is an exploded view of the first metal layer of the repeating unit in FIG11. FIG12(c) is an exploded view of the second metal layer of the repeating unit in FIG11. FIG12(d) is an exploded view of the second active layer of the repeating unit in FIG11. FIG12(e) is an exploded view of the third metal layer of the repeating unit in FIG11. FIG12(f) is an exploded view of the first source and drain layer of the repeating unit in FIG11. FIG12(g) is an exploded view of the second source and drain layer of the repeating unit in FIG11.

[0080] In some embodiments, as shown in FIG. 5 , FIG. 6 ( a ), FIG. 9 , and FIG. 10 ( a ), the first active layer 106 includes an active portion T2A of the switching transistor T2 , an active portion T1A of the driving transistor T1 , an active portion T7A of the second initialization transistor T7 , an active portion T9A of the amplifying transistor T9 , and an active portion T10A of the control transistor T10 ;

[0081] The active portion T1A of the driving transistor T1 is arranged along a first direction X, the active portion T2A of the switching transistor T2, the active portion T9A of the amplifying transistor T9, the active portion T10A of the control transistor T10, and the active portion T7A of the second initialization transistor T7 are arranged along a second direction Y, and the active portion T1A of the driving transistor T1 is connected to the active portion T2A of the switching transistor T2, the active portion T9A of the amplifying transistor T9 is connected to the active portion T10A of the control transistor T10, and the active portion T9A of the amplifying transistor T9 and the active portion of the second initialization transistor T7A are arranged on both sides of the active portion T1A of the driving transistor T1 along the second direction, and an angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By arranging the active portion of the amplifying transistor T9 and the active portion of the control transistor T10 on one side of the active portion of the driving transistor, the patterns in the two pixel driving circuits are symmetrically arranged. When other structures are subsequently prepared, the structures in the pixel driving circuits can also be symmetrically arranged, thereby keeping the impedance of the two pixel driving circuits consistent, and preventing the signal lines in the pixel driving circuit from interfering with the signal lines in the sensing circuit, thereby improving the display effect.

[0082] Specifically, as shown in FIG. 6( a ) and FIG. 10 ( a ), the first active layer 106 further includes an active portion T5A of the first light emitting transistor T5 and an active portion T6A of the second light emitting transistor T6 .

[0083] Specifically, as shown in (a) in Figure 6 and (a) in Figure 10, it can be seen that the active parts of the driving transistor T1, the switching transistor T2, the first light-emitting transistor T5 and the second light-emitting transistor T6 are parts of an active pattern, and the specific position of each active part can be determined according to the overlapping position of the gate and the active pattern, and the connection position of the first electrode and the second electrode with the active pattern.

[0084] In some embodiments, as shown in FIG. 5 , FIG. 6 ( b ), FIG. 9 , and FIG. 10 ( b ), the first metal layer 108 includes a first scan line Pscan(n), a second scan line Pscan(n−1), a control signal line SEL, a first transfer line L1 , a capacitor plate Cs1 of the photoelectric unit, a gate T1G of the driving transistor T1 , a gate T9G of the amplifying transistor T9 , a gate T10G of the control transistor T10 , and a gate T7G of the second initialization transistor T7 , which are arranged along the first direction X;

[0085] In which, the first scan line Pscan (n) is arranged between the second scan line Pscan (n-1) and the control signal line SEL, the first adapter line L1 is arranged between the gate T1G of the driving transistor T1 and the second scan line Pscan (n-1), a capacitor plate Cs1 of the photoelectric unit is arranged on the side of the control signal line SEL away from the first scan line Pscan (n), the gate T10G of the control transistor T10 is connected to the control signal line SEL, the gate T9G of the amplifying transistor T9 is connected to a capacitor plate Cs1 of the photoelectric unit, and the gate T7G of the second initialization transistor T7 is connected to the second scan line Pscan (n-1). By arranging the control signal line, a capacitor plate of the photoelectric unit, the gate T10G of the control transistor T10, and the gate T9G of the amplifying transistor T9 on one side of the pixel driving circuit, the patterns in the two pixel driving circuits can be arranged symmetrically. When other structures are subsequently prepared, the structures in the pixel driving circuit can also be arranged symmetrically, so that the impedance of the two pixel driving circuits remains consistent, and the signal lines in the pixel driving circuit and the signal lines in the sensing circuit do not interfere with each other, thereby improving the display effect.

[0086] Specifically, as shown in (b) in Figure 6, (b) in Figure 8, (b) in Figure 10 and (b) in Figure 12, it can be understood that the first scan line Pscan (n) is a scan line within the sub-pixel unit of this row, and the first scan line Pscan (n) is connected to the gate of the switching transistor in the pixel driving circuit corresponding to the sub-pixel unit of this row and the gate of the second initialization transistor in the pixel driving circuit corresponding to the sub-pixel unit of the next row. Therefore, although the first scan line Pscan (n) and the second scan line Pscan (n-1) have the same structure, the gate T2G of the switching transistor is marked on the first scan line Pscan (n), and the gate T7G of the second initialization transistor is marked on the second scan line Pscan (n-1). It can be understood that a portion of the first scan line Pscan (n) can serve as the gate of the second initialization transistor T7, and the second scan line Pscan (n-1) can serve as the gate of the switching transistor.

[0087] Specifically, as shown in (b) of FIG6 and (b) of FIG10, since the sensing circuit is provided under the pixel driving circuit, the second electrode T7D of the second initialization transistor T7 and the second electrode of the second light-emitting transistor T6 are connected through the first connecting line L1 and the second connecting line L2.

[0088] Specifically, as shown in (b) of Figure 6 and (b) of Figure 10, the first metal layer also includes a gate T2G of the switching transistor T2, a gate T5G of the first light-emitting transistor T5, a gate T6G of the second light-emitting transistor T6, and a light-emitting signal line EM. The gate T1G of the driving transistor T1 is arranged corresponding to the active portion of the driving transistor T1, the gate T2G of the switching transistor T2 is arranged corresponding to the active portion of the switching transistor T2, the gate T5G of the first light-emitting transistor T5 is arranged corresponding to the active portion of the first light-emitting transistor T5, the gate T6G of the second light-emitting transistor T6 is arranged corresponding to the active portion of the second light-emitting transistor T6, the gate T7G of the second initialization transistor T7 is arranged corresponding to the active portion of the second initialization transistor T7, the gate T9G of the amplifying transistor T9 is arranged corresponding to the active portion of the amplifying transistor T9, and the gate T10G of the control transistor T10 is arranged corresponding to the active portion of the control transistor T10.

[0089] In some embodiments, as shown in FIG. 5 , FIG. 6 (c), FIG. 9 , and FIG. 10 (c), the second metal layer 110 includes a first portion Nscan (n-5)-1 of a third scan line Nscan (n-5) arranged along the first direction X, a first portion Nscan (n)-1 of a fourth scan line Nscan (n), a first initialization signal line VI-G, a first portion RST-1 of a reset signal line RST, a first gate T11Ga of a reset transistor T11, a first gate T4Ga of a first initialization transistor T4, and a second electrode S1 of a photoelectric unit;

[0090] In which, the first part Nscan (n-5)-1 of the third scan line Nscan (n-5) is arranged between the first part Nscan (n)-1 of the fourth scan line Nscan (n) and the first initialization signal line VI-G, the second electrode S1 of the photoelectric unit is arranged on the side of the first initialization signal line VI-G away from the first part Nscan (n)-1 of the fourth scan line Nscan (n), the first part RST-1 of the reset signal line RST is arranged on the side of the second electrode S1 of the photoelectric unit away from the first initialization signal line VI-G, the first part Nscan (n-5)-1 of Nscan (n-5) is connected to the first gate T4Ga of the first initialization transistor T4, and the first gate T11Ga of the reset transistor T11 is connected to the first part RST-1 of the reset signal line RST. By arranging the first part of the reset signal line, the second electrode of the photoelectric unit, and the first gate of the reset transistor on one side of the pixel driving circuit, the patterns in the two pixel driving circuits can be arranged symmetrically. When other structures are subsequently prepared, the structures in the pixel driving circuit can also be arranged symmetrically, so that the impedance of the two pixel driving circuits remains consistent, and the signal lines in the pixel driving circuit and the signal lines in the sensing circuit do not interfere with each other, thereby improving the display effect.

[0091] Specifically, as shown in (c) of Figure 6 and (c) of Figure 10, the second metal layer also includes a plate Cst1 of the storage capacitor Cst, and the plate Cst1 of the storage capacitor Cst is connected to the first power signal line VDD. The other plate of the storage capacitor Cst is the gate T1G of the driving transistor T1.

[0092] Specifically, as shown in (c) of FIG6 and (c) of FIG10 , the second metal layer further includes a first gate T3Ga of the compensation transistor T3 , and the first gate T3Ga of the compensation transistor T3 is connected to the first portion Nscan(n)-1 of the fourth scan line Nscan(n).

[0093] In some embodiments, as shown in Figures 2, 5, (d) in Figure 6, 7, (d) in Figure 8, 9, (d) in Figure 10, 11, and (d) in Figure 12, the pixel driving circuit 10 further includes a compensation transistor T3, and the second active layer 116 includes an active portion T4A of a first initialization transistor T4, an active portion T11A of a reset transistor T11, and an active portion T3A of a compensation transistor T3, arranged along a second direction Y. The active portion T4A of the first initialization transistor T4 and the active portion T11A of the reset transistor T11 are spaced apart from each other. In the first direction X, the active portion T4A of the first initialization transistor T4 is located between the active portion T3A of the compensation transistor T3 and the active portion T11A of the reset transistor T11. By arranging the active portion of the reset transistor on a side of the active portion of the first initialization transistor away from the active portion of the compensation transistor, the reset transistor does not interfere with the first initialization transistor and the compensation transistor.

[0094] In some embodiments, as shown in FIG. 5 , FIG. 6 (e), FIG. 9 , and FIG. 10 (e), the third metal layer 118 includes a second portion Nscan (n-5)-2 of the third scan line Nscan (n-5), a second portion Nscan (n)-2 of the fourth scan line Nscan (n), a second portion RST-2 of the reset signal line RST, a second gate T4Gb of the first initialization transistor T4, and a second gate T11Gb of the reset transistor T11;

[0095] The second portion RST-2 of the reset signal line RST is disposed on a side of the second portion Nscan(n-5)-2 of the third scan line Nscan(n-5) away from the second portion Nscan(n)-2 of the fourth scan line Nscan(n). The second portion Nscan(n-5)-2 of the third scan line Nscan(n-5) is connected to the second gate T4Gb of the first initialization transistor T4. The second portion RST-2 of the reset signal line RST is connected to the second gate T11Gb of the reset transistor T11. By disposing the second portion of the reset signal line and the second gate of the reset transistor on a side of the third scan line away from the fourth scan line, the patterns in the two pixel driving circuits are symmetrically arranged. When other structures are subsequently prepared, the structures in the pixel driving circuits can also be symmetrically arranged, thereby maintaining consistent impedance in the two pixel driving circuits and preventing interference between the signal lines in the pixel driving circuit and the signal lines in the sensing circuit, thereby improving display quality.

[0096] Specifically, the first portion of the third scan line is connected to the second portion of the third scan line, the first portion of the fourth scan line is connected to the second portion of the fourth scan line, and the first portion of the reset signal line is connected to the second portion of the reset signal line.

[0097] Specifically, as shown in (e) of FIG6 and (e) of FIG10, the third metal layer further includes a second gate T3Gb of the compensation transistor T3, and the second gate T3Gb of the compensation transistor T3 is connected to the second portion Nscan(n)-2 of the fourth scan line Nscan(n).

[0098] Specifically, in the above embodiment, the first initialization transistor, compensation transistor and reset transistor adopt a dual-gate design to improve gate control capability, but the embodiments of the present application are not limited thereto. The first initialization transistor, compensation transistor and reset transistor can adopt a single-gate design.

[0099] In some embodiments, as shown in FIG. 5 , FIG. 6 (g), FIG. 9 , and FIG. 10 (g), the second source-drain electrode layer 122 includes two data lines Data, a first power signal line VDD, a second power signal line VSS, a sensing signal output line Readout, and a low potential signal line SVSS arranged along the second direction Y;

[0100] In the pixel driving circuit 10 corresponding to two adjacent sub-pixel units 40, the sensing signal output line Readout is arranged between one of the data lines Data and the first power signal line VDD, and the low-potential signal line SVSS is arranged between the other data line Data and the first power signal line VDD. By arranging the sensing signal output line between one data line and the first power signal line, and the low-potential signal line between the other data line and the first power signal line, the patterns in the two pixel driving circuits can be arranged symmetrically. When other structures are subsequently prepared, the structures in the pixel driving circuits can also be arranged symmetrically, thereby maintaining the impedance of the two pixel driving circuits consistent, and the signal lines in the pixel driving circuit and the signal lines in the sensing circuit do not interfere with each other, thereby improving the display effect.

[0101] In some embodiments, as shown in FIG. 5 , FIG. 6 ( f ), FIG. 9 , and FIG. 10 ( f ), the first source-drain electrode layer 120 includes the second initialization signal line VI-ANO in the sub-pixel unit 40 of the previous row and the second initialization signal line VI-ANO in the sub-pixel unit 40 of the current row, the second transfer line L2, the first power connection line VDD-1, the second power connection line VSS-1, the third transfer line L3, the data connection line Data-1, the sensing connection line Readout-1, the low potential connection line SVSS-1, the first initialization connection line VI-G-1, and the second electrode T1D of the driving transistor T1;

[0102] In the second direction Y, the second initialization signal line VI-ANO in the sub-pixel unit 40 in the previous row is arranged on the side of the second adapter line L2 away from the first power connection line VDD-1, the second power connection line VSS-1 is arranged between the first power connection line VDD-1 and the second adapter line L2, the third adapter line L3 is arranged on the side of the first power connection line VDD-1 away from the second adapter line L2, the second initialization signal line VI-ANO in the sub-pixel unit 40 in this row is arranged on the side of the third adapter line L3 away from the first power connection line VDD-1, and the data connection line Dat a-1 is arranged on a side of the second initialization signal line VI-ANO in the sub-pixel unit 40 of this row away from the third adapter line L3, the first initialization connection line VI-G-1 is arranged on a side of the data connection line Data-1 away from the second initialization signal line VI-ANO in the sub-pixel unit 40 of this row, the sensing connection line Readout-1 is arranged on a side of the first initialization connection line VI-G-1 away from the data connection line Data-1, and the low potential connection line SVSS-1 is arranged on a side of the sensing connection line Readout-1 away from the first initialization connection line VI-G-1;

[0103] The second initialization signal line VI-ANO in the sub-pixel unit 40 of the previous row is connected to the first electrode T7S of the second initialization transistor T7, the second electrode T7D of the second initialization transistor T7 is connected to one end of the second adapter line L2, the other end of the second adapter line L2 is connected to the first adapter line L1, one end of the first power connection line VDD-1 is connected to the first power signal line VDD, the second power connection line VSS-1 is connected to the second power signal line VSS and an electrode (not shown) of the light-emitting device, one end of the third adapter line L3 is connected to the gate T1G of the driving transistor T1, and the other end of the third adapter line L3 is connected to the first scan line Pscan(n), the data connection line Data-1 is connected to the first electrode T2S of the switching transistor T2 and the data line Data, the sensing connection line Readout-1 is connected to the sensing signal output line Readout and the second electrode T10D of the control transistor T10, and the low potential connection line SVSS-1 is connected to the low potential signal line SVSS, the first electrode T11S of the reset transistor T11, and the first electrode T9S of the amplifying transistor T9;

[0104] As shown in Figure 5, the first initialization connection line VI-G-1 connects the second electrode S1 of the photoelectric unit, the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4; or as shown in Figure 9, the first initialization connection line VI-G-1 connects the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4, and the second initialization signal line VI-ANO in the sub-pixel unit 40 of this row is connected to the second electrode S1 of the photoelectric unit.

[0105] Specifically, by symmetrically arranging the patterns in the two pixel drive circuits, the structures in the pixel drive circuits can also be symmetrically arranged when subsequently preparing other structures, thereby maintaining consistent impedance between the two pixel drive circuits and preventing interference between the signal lines in the pixel drive circuit and the signal lines in the sensing circuit, thereby improving the display effect. Furthermore, by connecting the second electrode of the photoelectric unit to either the first initialization signal line or the second initialization signal line, the number of signal lines can be reduced, reducing the area occupied by each repeating unit, thereby increasing the aperture ratio of the display panel, improving the resolution of the display panel, and increasing the fingerprint recognition area.

[0106] Specifically, in Figures 5 to 12, since the common electrode layer and the pixel electrode layer are not shown, the light-emitting device LED is not shown accordingly. Therefore, the second light-emitting transistor T6 is connected to the second power signal line VSS. However, in practice, the connection relationship between the second light-emitting transistor T6 and the second power signal line VSS can be seen in Figure 2. The second light-emitting transistor T6 is connected to one electrode of the light-emitting device LED, and the second power signal line is connected to the other electrode of the light-emitting device LED.

[0107] In some embodiments, as shown in FIG. 7 , FIG. 8 ( a ), FIG. 11 , and FIG. 12 ( a ), the first active layer 106 includes an active portion T2A of the switching transistor T2 , an active portion T1A of the driving transistor T1 , an active portion T7A of the second initialization transistor T7 , an active portion T9A of the amplifying transistor T9 , and an active portion T10A of the control transistor T10 ;

[0108] The active portion T1A of the driving transistor T1 is arranged along a first direction X, the active portion T2A of the switching transistor T2, the active portion T9A of the amplifying transistor T9, the active portion T10A of the control transistor T10, and the active portion T7A of the second initialization transistor T7 are arranged along a second direction Y, and the active portion T1A of the driving transistor T1 is connected to the active portion T2A of the switching transistor T2, the active portion T1A of the driving transistor T1 is electrically connected to the active portion T7A of the second initialization transistor T7, the active portion T9A of the amplifying transistor T9 is connected to the active portion T10A of the control transistor T10, and the active portion T9A of the amplifying transistor T9 is arranged along the first direction X on a side of the active portion T2A of the switching transistor T2 away from the active portion T1A of the driving transistor T1, and an angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By arranging the active portions of the amplifying transistor and the control transistor on a side of the active portion of the switching transistor away from the active portion of the driving transistor, when forming the amplifying transistor and the control transistor, the amplifying transistor, the control transistor, and the connected signal lines will not affect the arrangement of the second initialization transistor. The sensing circuit is arranged on one side of the pixel driving circuit in the second direction and on a side of one pixel driving circuit away from another pixel driving circuit in the first direction. As a result, the second initialization transistor does not require a jumper arrangement, the distribution of the holes in the repeating unit is more uniform, the process requirements are lower, and a higher resolution can be achieved.

[0109] Specifically, as shown in FIG. 8( a ) and FIG. 12 ( a ), the first active layer 106 further includes an active portion T5A of the first light emitting transistor T5 and an active portion T6A of the second light emitting transistor T6 .

[0110] Specifically, as shown in (a) in Figure 8 and (a) in Figure 12, it can be seen that the active parts of the driving transistor T1, the switching transistor T2, the first light-emitting transistor T5, the second light-emitting transistor T6, and the second initialization transistor are parts of an active pattern, and the specific position of each active part can be determined according to the overlapping position of the gate and the active pattern, and the connection position of the first electrode and the second electrode with the active pattern.

[0111] In some embodiments, as shown in FIG. 7 , FIG. 8 ( b ), FIG. 11 , and FIG. 12 ( b ), the first metal layer 108 includes a first scan line Pscan(n), a second scan line Pscan(n−1), a capacitor plate Cs1 of a photoelectric unit, a gate T1G of a driving transistor T1 , a gate T2G of a switching transistor T2 , a gate T9G of an amplifying transistor T9 , a gate T10G of a control transistor T10 , and a gate T7G of a second initialization transistor T7 , arranged along a first direction X;

[0112] In which, the first scan line Pscan(n) is arranged between the second scan line Pscan(n-1) and a capacitor plate Cs1 of the photoelectric unit, the first scan line Pscan(n) is connected to the gate T2G of the switching transistor T2, the gate T1G of the driving transistor T1 is arranged between the first scan line Pscan(n) and the second scan line Pscan(n-1), the gate T9G of the amplifying transistor T9 and the gate T10G of the control transistor T10 are located between the first scan line Pscan(n) and the second scan line Pscan(n-1), and the gate T10G of the control transistor T10 is arranged on a side of the gate T9G of the amplifying transistor T9 away from the gate T1G of the driving transistor T1, and the gate T7G of the second initialization transistor T7 is connected to the second scan line Pscan(n-1). By arranging the gate of the amplifying transistor and the gate of the driving transistor on a side of the gate T1G of one driving transistor T1 away from the gate T1G of another driving transistor T1, the amplifying transistor and the driving transistor and the connected signal line will not affect the arrangement of the second initialization transistor, so that the sensing circuit is arranged on one side of the pixel driving circuit in the second direction and on a side of one pixel driving circuit away from another pixel driving circuit in the first direction. As a result, the second initialization transistor does not need to be arranged with a jumper, the distribution of the holes in the repeating unit is more uniform, the process requirements are lower, and a higher resolution can be achieved.

[0113] Specifically, as shown in (b) of Figure 8 and (b) of Figure 12, the first metal layer also includes a gate T5G of the first light-emitting transistor T5, a gate T6G of the second light-emitting transistor T6 and a light-emitting signal line EM, the gate T1G of the driving transistor T1 is arranged corresponding to the active portion of the driving transistor T1, the gate T2G of the switching transistor T2 is arranged corresponding to the active portion of the switching transistor T2, the gate T5G of the first light-emitting transistor T5 is arranged corresponding to the active portion of the first light-emitting transistor T5, the gate T6G of the second light-emitting transistor T6 is arranged corresponding to the active portion of the second light-emitting transistor T6, the gate T7G of the second initialization transistor T7 is arranged corresponding to the active portion of the second initialization transistor T7, the gate T9G of the amplifying transistor T9 is arranged corresponding to the active portion of the amplifying transistor T9, and the gate T10G of the control transistor T10 is arranged corresponding to the active portion of the control transistor T10.

[0114] In some embodiments, as shown in FIG. 7 , FIG. 8 (c), FIG. 11 , and FIG. 12 (c), the second metal layer 110 includes a first portion Nscan (n-5)-1 of a third scan line Nscan (n-5) arranged along the first direction X, a first portion Nscan (n)-1 of a fourth scan line Nscan (n), a first initialization signal line VI-G, a reset signal line RST, a gate T11G of a reset transistor T11, a first gate T4Ga of a first initialization transistor T4, and a second electrode S1 of a photoelectric unit;

[0115] In which, the first part Nscan(n)-1 of the fourth scan line Nscan(n) is arranged between the first part Nscan(n-5)-1 of the third scan line Nscan(n-5) and the first initialization signal line VI-G, the second electrode S1 of the photoelectric unit is arranged on the side of the first initialization signal line VI-G away from the first part Nscan(n)-1 of the fourth scan line Nscan(n), the reset signal line RST is arranged on the side of the second electrode S1 of the photoelectric unit away from the first initialization signal line VI-G, the first part Nscan(n-5)-1 of the third scan line Nscan(n-5) is connected to the first gate T4Ga of the first initialization transistor T4, and the gate T11G of the reset transistor T11 is connected to the reset signal line RST. By arranging the reset signal line, the second electrode of the photoelectric unit, and the gate of the reset transistor on one side of the pixel driving circuit, when the second electrode of the photoelectric unit is connected to the first initialization signal line and the second initialization signal line, the distance between the second electrode of the photoelectric unit and the first initialization signal line and the second initialization signal line is small, and there is no need for multiple line crossings, thereby reducing the process difficulty.

[0116] Specifically, as shown in (c) of Figure 8 and (c) of Figure 12, the second metal layer also includes a plate Cst1 of the storage capacitor Cst, and the plate Cst1 of the storage capacitor Cst is connected to the first power signal line VDD, and the other plate of the storage capacitor Cst is the gate T1G of the driving transistor T1.

[0117] Specifically, as shown in (c) of FIG8 and (c) of FIG12 , the second metal layer further includes a first gate T3Ga of the compensation transistor T3 , and the first gate T3Ga of the compensation transistor T3 is connected to the first portion Nscan(n)-1 of the fourth scan line Nscan(n).

[0118] In some embodiments, as shown in FIG. 7 , FIG. 8 (e), FIG. 11 , and FIG. 12 (e), within the repeating unit 100 , the third metal layer 118 includes the second portion Nscan (n-5)-2 of the third scan line Nscan (n-5), the second portion Nscan (n)-2 of the fourth scan line Nscan (n), and the second gate T4Gb of the first initialization transistor T4;

[0119] The second portion Nscan(n-5)-2 of the third scan line Nscan(n-5) is connected to the second gate T4Gb of the first initialization transistor T4. By connecting the second portion of the third scan line to the second gate of the first initialization transistor, the controllability of the first initialization transistor can be improved.

[0120] Specifically, as shown in (e) of FIG8 and (e) of FIG12 , the third metal layer further includes a second gate T3Gb of the compensation transistor T3 , and the second gate T3Gb of the compensation transistor T3 is connected to the second portion Nscan(n)-2 of the fourth scan line Nscan(n).

[0121] In some embodiments, as shown in FIG. 7 , FIG. 8 (g), FIG. 11 , and FIG. 12 (g), the second source-drain layer 122 includes a Data line, a first power signal line VDD, a second power signal line VSS, a sensing signal output line Readout, and a low potential signal line SVSS arranged along the second direction Y;

[0122] In the pixel driver circuit 10 of two adjacent sub-pixel units 40, in the first direction X, the sensing signal output line Readout is arranged on the side of the data line Data away from the first power signal line VDD, and the low-potential signal line SVSS is arranged on the side of the sensing signal output line Readout closer to the data line Data. By arranging the sensing signal output line and the low-potential signal line on the side of the data line away from the first power signal line, the sensing circuit is arranged on the side of one pixel driver circuit away from the other pixel driver circuit in the first direction. This eliminates the need for a jumper for the second initialization transistor, makes the distribution of holes within the repeating unit more uniform, reduces process requirements, and achieves higher resolution.

[0123] In some embodiments, as shown in FIG. 7 , FIG. 8 ( f ), FIG. 11 , and FIG. 12 ( f ), the first source-drain electrode layer 120 includes the second initialization signal line VI-ANO in the sub-pixel unit 40 of the previous row and the second initialization signal line VI-ANO in the sub-pixel unit 40 of the current row, a first power connection line VDD-1, a second power connection line VSS-1, a fourth transfer line L4, a data connection line Data-1, a sensing connection line Readout-1, a low potential connection line SVSS-1, a first initialization connection line VI-G-1, a control signal line SEL, and the second electrode T1D of the driving transistor T1;

[0124] In the second direction Y, the second initialization signal line VI-ANO in the sub-pixel unit 40 in the previous row is set on one side of the first power connection line VDD-1, the second power connection line VSS-1 is set between adjacent first power connection lines VDD-1, the fourth adapter line L4 is set on the side of the first power connection line VDD-1 away from the second initialization signal line VI-ANO in the sub-pixel unit 40 in the previous row, the second initialization signal line VI-ANO in the sub-pixel unit 40 in this row is set on the side of the fourth adapter line L4 away from the first power connection line VDD-1, and the data connection line Data-1 is set on the second initialization signal line VI-ANO in the sub-pixel unit 40 in this row. The initialization signal line VI-ANO is located on a side away from the fourth adapter line L4, the first initialization connection line VI-G-1 is located on a side of the data connection line Data-1 away from the second initialization signal line VI-ANO in the sub-pixel unit 40 of the same row, in the first direction X, the sensing connection line Readout-1 is located on a side of the data connection line Data-1 away from the first initialization connection line VI-G-1, the low potential connection line SVSS-1 is located on a side of the first power connection line VDD-1 away from the second power connection line VSS-1, and the control signal line SEL is located on a side of the sensing connection line Readout-1 away from the first initialization connection line VI-G-1;

[0125] The second initialization signal line VI-ANO in the sub-pixel unit 40 of the previous row is connected to the first electrode T7S of the second initialization transistor T7, the first power connection line VDD-1 is connected to the first power signal line VDD, the second power connection line VSS-1 is connected to the second power signal line VSS and an electrode (not shown) of the light-emitting device, one end of the fourth adapter line L4 is connected to the gate T1G of the driving transistor T1, and the other end of the fourth adapter line L4 is connected to the first scan line Pscan(n), the data connection line Data-1 is connected to the first electrode T2S of the switching transistor T2 and the data line Data, the sensing connection line Readout-1 is connected to the sensing signal output line Readout and the second electrode T10D of the control transistor T10, the low potential connection line SVSS-1 is connected to the low potential signal line SVSS, the first electrode T11S of the reset transistor T11, and the first electrode T9S of the amplifying transistor T9, and the control signal line SEL is connected to the gate T10G of the control transistor T10;

[0126] As shown in Figure 7, the first initialization connection line VI-G-1 connects the second electrode S1 of the photoelectric unit, the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4; or as shown in Figure 11, the first initialization connection line VI-G-1 connects the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4, and the second initialization signal line VI-ANO in the sub-pixel unit 40 of this row is connected to the second electrode S1 of the photoelectric unit.

[0127] Specifically, by setting the sensing circuit on one side of the pixel driving circuit in the second direction and on the side of a pixel driving circuit away from another pixel driving circuit in the first direction, the second initialization transistor does not need to be set with a jumper, the distribution of holes in the repeating unit is more uniform, the process requirements are lower, and a higher resolution can be achieved.

[0128] Specifically, the above embodiment is described using the design within a repeating unit as an example. It can be understood that the display panel can be composed of multiple repeating units, and the designs within the multiple repeating units are the same, but the embodiments of the present application are not limited to this. For example, the display panel includes multiple repeating units, and some repeating units can adopt the structure shown in Figures 5 and 6, some repeating units can adopt the structure shown in Figures 7 and 8, some repeating units can adopt the structure of Figures 9 and 10, and some repeating units can adopt the structure of Figures 11 and 12.

[0129] In some embodiments, as shown in Figure 4, the driving circuit layer 12 also includes a first insulating layer 102, a light-shielding layer 103, a second insulating layer 104, a third insulating layer 105, a first gate insulating layer 107, a second gate insulating layer 109, a third gate insulating layer 111, a fourth gate insulating layer 113, a fifth gate insulating layer 115, a sixth gate insulating layer 117, a first interlayer insulating layer 119, a second interlayer insulating layer 121, and a planarization layer 123.

[0130] In some embodiments, the light emitting layer 13 includes a pixel electrode layer 124 , a pixel definition layer 125 , a light emitting material layer, and a common electrode layer.

[0131] In some embodiments, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0132] In some embodiments, the first electrode of the photovoltaic cell is an anode, and the second electrode of the photovoltaic cell is a cathode.

[0133] In some embodiments, the material of the first active layer includes low-temperature polysilicon, and the material of the second active layer includes metal oxide.

[0134] In some embodiments, the driving transistor, the switching transistor, the first light emitting transistor, the second light emitting transistor, the second initialization transistor, the amplifying transistor, and the control transistor are P-type transistors, and the first initialization transistor, the compensation transistor, and the reset transistor are N-type transistors.

[0135] At the same time, an embodiment of the present application provides a display device, which includes the display panel as described in any of the above embodiments.

[0136] According to the above embodiments, it can be seen that:

[0137] The embodiments of the present application provide a display panel and a display device; the display panel includes a substrate, a driving circuit layer and a light-emitting layer, the driving circuit layer is arranged on one side of the substrate, the driving circuit layer includes a pixel driving circuit and a sensing circuit arranged between adjacent pixel driving circuits, the light-emitting layer is arranged on a side of the driving circuit layer away from the substrate, the light-emitting layer includes a light-emitting device arranged corresponding to the pixel driving circuit, the light-emitting device is electrically connected to the corresponding pixel driving circuit, wherein the pixel driving circuit includes a switching transistor, a driving transistor, a first initialization transistor and a second initialization transistor, the switching transistor and the driving transistor are connected to a first node, the switching transistor is used to input a data signal to the first node under the control of a first scan signal, the first initialization transistor One electrode of the first initialization transistor is connected to the second node, the other electrode of the first initialization transistor is connected to the first initialization signal line, one electrode of the second initialization transistor is connected to the light-emitting device at a third node, the other electrode of the second initialization transistor is connected to the second initialization signal line, the second initialization transistor is used to output the second initialization signal to the anode of the light-emitting device under the control of the second scan signal, the first initialization transistor is used to input the first initialization signal to the second node under the control of the third scan signal, the sensing circuit includes a photoelectric unit and a sensing signal output line, the first electrode of the photoelectric unit is electrically connected to the sensing signal output line, and the second electrode of the photoelectric unit is connected to one of the first initialization signal line and the second initialization signal line. By connecting the second electrode of the photoelectric unit to one of the first initialization signal line and the second initialization signal line, the present application reduces the number of signal lines in the driving circuit layer and reduces the total area occupied by the sensing circuit and the pixel driving circuit, thereby improving the aperture ratio of the display panel and improving the resolution of the display panel.

[0138] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0139] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising: A substrate; A driving circuit layer disposed on one side of the substrate, the driving circuit layer including: a pixel driving circuit and a sensing circuit disposed between adjacent pixel driving circuits; A light-emitting layer disposed on the side of the driving circuit layer away from the substrate, the light-emitting layer including: a light-emitting device corresponding to the pixel driving circuit, and the light-emitting device is electrically connected to the corresponding pixel driving circuit; Wherein, the pixel driving circuit includes: a switching transistor, a driving transistor, a first initialization transistor, and a second initialization transistor. The switching transistor and the driving transistor are connected to a first node. The switching transistor is configured to input a data signal to the first node under the control of a first scan signal. One electrode of the first initialization transistor is connected to the driving transistor at a second node, and the other electrode of the first initialization transistor is connected to a first initialization signal line. One electrode of the second initialization transistor is connected to the light-emitting device at a third node, and the other electrode of the second initialization transistor is connected to a second initialization signal line. The second initialization transistor is configured to input a second initialization signal to the anode of the light-emitting device under the control of a second scan signal. The first initialization transistor is configured to input a first initialization signal to the second node under the control of a third scan signal; The sensing circuit includes: a photoelectric unit and a sensing signal output line. A first electrode of the photoelectric unit is electrically connected to the sensing signal output line, and a second electrode of the photoelectric unit is connected to one of the first initialization signal line and the second initialization signal line.

2. The display panel according to claim 1, wherein, Two adjacent pixel driving circuits are symmetrically arranged, and the photoelectric unit is arranged along the direction of the symmetry axis of the two pixel driving circuits.

3. The display panel according to claim 1, wherein, The sensing circuit further includes an amplifying transistor, a control transistor, and a reset transistor. A gate of the amplifying transistor is connected to one end of the photoelectric unit. One electrode of the amplifying transistor is connected to one electrode of the control transistor, and the other electrode of the amplifying transistor is connected to one electrode of the reset transistor. The other electrode of the control transistor is connected to the sensing signal output line, and the other electrode of the reset transistor is connected to one end of the photoelectric unit. The amplifying transistor is configured to amplify the signal of the photoelectric unit. The control transistor is configured to control the output of the signal of the photoelectric unit under the control of a control signal. The reset transistor is configured to reset the first electrode of the photoelectric unit under the control of a reset control signal.

4. The display panel according to claim 3, wherein, The driving circuit layer includes: A first active layer disposed on one side of the substrate; A first metal layer disposed on the side of the first active layer away from the substrate; A second metal layer disposed on the side of the first metal layer away from the first active layer; A second active layer disposed on the side of the second metal layer away from the first metal layer; A third metal layer disposed on the side of the second active layer away from the second metal layer; A first source-drain layer disposed on the side of the third metal layer away from the second active layer; A second source-drain layer, disposed on a side of the first source-drain layer away from the third metal layer; Wherein, a second electrode of the optoelectronic unit is disposed on the second metal layer.

5. The display panel according to claim 4, wherein, The first active layer includes an active portion of a switching transistor, an active portion of a driving transistor, an active portion of a second initialization transistor, an active portion of an amplifying transistor, and an active portion of a control transistor; Wherein, the active portion of the driving transistor is disposed along a first direction, the active portions of the switching transistor, the amplifying transistor, the control transistor, and the second initialization transistor are disposed along a second direction, and the active portion of the driving transistor is connected to the active portion of the switching transistor, the active portion of the amplifying transistor is connected to the active portion of the control transistor, the active portions of the amplifying transistor and the second initialization transistor are disposed on both sides of the active portion of the driving transistor along the second direction, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

6. The display panel according to claim 5, wherein, The first metal layer includes a first scan line, a second scan line, a control signal line, a first transfer line, a capacitor plate of the optoelectronic unit, a gate of the driving transistor, a gate of the amplifying transistor, a gate of the control transistor, and a gate of the second initialization transistor disposed along the first direction; Wherein, the first scan line is disposed between the second scan line and the control signal line, the first transfer line is disposed between the gate of the driving transistor and the second scan line, a capacitor plate of the optoelectronic unit is disposed on a side of the control signal line away from the first scan line, the gate of the control transistor is connected to the control signal line, the gate of the amplifying transistor is connected to a capacitor plate of the optoelectronic unit, and the gate of the second initialization transistor is connected to the second scan line.

7. The display panel according to claim 6, wherein, The second metal layer includes a first portion of a third scan line, a first portion of a fourth scan line, a first initialization signal line, a first portion of a reset signal line, a first gate of a reset transistor, a first gate of a first initialization transistor, and a second electrode of the optoelectronic unit disposed along the first direction; Wherein, the first portion of the third scan line is disposed between the first portion of the fourth scan line and the first initialization signal line, the second electrode of the optoelectronic unit is disposed on a side of the first initialization signal line away from the first portion of the fourth scan line, the first portion of the reset signal line is disposed on a side of the second electrode of the optoelectronic unit away from the first initialization signal line, the first portion of the third scan line is connected to the first gate of the first initialization transistor, and the first gate of the reset transistor is connected to the first portion of the reset signal line.

8. The display panel according to claim 7, wherein, The pixel driving circuit further includes a compensation transistor. The second active layer includes the active parts of a first initialization transistor, a reset transistor, and a compensation transistor arranged along a second direction. The active parts of the first initialization transistor and the reset transistor are arranged at intervals. In a first direction, the active part of the first initialization transistor is located between the active part of the compensation transistor and the active part of the reset transistor.

9. The display panel according to claim 8, wherein, The third metal layer includes a second part of a third scanning line, a second part of a fourth scanning line, a second part of a reset signal line, a second gate of the first initialization transistor, and a second gate of the reset transistor; Wherein, the second part of the reset signal line is arranged on a side of the second part of the third scanning line away from the second part of the fourth scanning line. The second part of the third scanning line is connected to the second gate of the first initialization transistor, and the second part of the reset signal line is connected to the second gate of the reset transistor.

10. The display panel according to claim 9, wherein, The second source-drain layer includes two data lines, a first power supply signal line, a second power supply signal line, a sensing signal output line, and a low-potential signal line arranged along the second direction; Wherein, within the pixel driving circuits corresponding to two adjacent sub-pixel units, the sensing signal output line is arranged between one of the data lines and the first power supply signal line, and the low-potential signal line is arranged between the other data line and the first power supply signal line.

11. The display panel according to claim 10, wherein, The first source-drain layer includes a second initialization signal line in the sub-pixel unit of the previous row and a second initialization signal line in the sub-pixel unit of the current row, a second transfer line, a first power supply connection line, a second power supply connection line, a third transfer line, a data connection line, a sensing connection line, a low-potential connection line, a first initialization connection line, and a second electrode of the driving transistor; In the second direction, the second initialization signal line in the sub-pixel unit of the previous row is arranged on a side of the second transfer line away from the first power supply connection line. The second power supply connection line is arranged between the first power supply connection line and the second transfer line. The third transfer line is arranged on a side of the first power supply connection line away from the second transfer line. The second initialization signal line in the sub-pixel unit of the current row is arranged on a side of the third transfer line away from the first power supply connection line. The data connection line is arranged on a side of the second initialization signal line in the sub-pixel unit of the current row away from the third transfer line. The first initialization connection line is arranged on a side of the data connection line away from the second initialization signal line in the sub-pixel unit of the current row. The sensing connection line is arranged on a side of the first initialization connection line away from the data connection line. The low-potential connection line is arranged on a side of the sensing connection line away from the first initialization connection line; The second initialization signal line in the sub-pixel unit described in the previous line is connected to the first electrode of the second initialization transistor. The second electrode of the second initialization transistor is connected to one end of the second transfer line. The other end of the second transfer line is connected to the first transfer line. The first power connection line is connected to the first power signal line. The second power connection line is connected to the second power signal line and one electrode of the light-emitting device. One end of the third transfer line is connected to the gate of the driving transistor. The other end of the third transfer line is connected to the first scan line. The data connection line is connected to the first electrode of the switching transistor and the data line. The sensing connection line is connected to the sensing signal output line and the second electrode of the control transistor. The low-potential connection line is connected to the low-potential signal line, the first electrode of the reset transistor, and the first electrode of the amplifying transistor; Wherein, the first initialization connection line is connected to the second electrode of the optoelectronic unit, the first initialization signal line, and the first electrode of the first initialization transistor; or the first initialization connection line is connected to the first initialization signal line and the first electrode of the first initialization transistor, and the second initialization signal line in the sub-pixel unit described in this line is connected to the second electrode of the optoelectronic unit.

12. The display panel according to claim 4, wherein, The first active layer includes the active part of the switching transistor, the active part of the driving transistor, the active part of the second initialization transistor, the active part of the amplifying transistor, and the active part of the control transistor; Wherein, the active part of the driving transistor is arranged along the first direction, the active parts of the switching transistor, the amplifying transistor, the control transistor, and the second initialization transistor are arranged along the second direction, and the active part of the driving transistor is connected to the active part of the switching transistor, the active part of the driving transistor is electrically connected to the active part of the second initialization transistor, the active part of the amplifying transistor is connected to the active part of the control transistor, the active part of the amplifying transistor is arranged along the first direction on the side of the active part of the switching transistor away from the active part of the driving transistor, and the included angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

13. The display panel according to claim 12, wherein, The first metal layer includes the first scan line, the second scan line, a capacitor plate of the optoelectronic unit, the gate of the driving transistor, the gate of the switching transistor, the gate of the amplifying transistor, the gate of the control transistor, and the gate of the second initialization transistor arranged along the first direction; Wherein, the first scan line is arranged between the second scan line and a capacitor plate of the optoelectronic unit. The first scan line is connected to the gate of the switching transistor. The gate of the driving transistor is arranged between the first scan line and the second scan line. The gates of the amplifying transistor and the control transistor are located between the first scan line and the second scan line, and the gate of the control transistor is arranged on the side of the gate of the amplifying transistor away from the gate of the driving transistor. The gate of the second initialization transistor is connected to the second scan line.

14. The display panel according to claim 13, wherein, The second metal layer includes a first portion of a third scan line, a first portion of a fourth scan line, a first initialization signal line, a reset signal line, a gate of a reset transistor, a first gate of a first initialization transistor, and a second electrode of an optoelectronic unit, which are arranged in a first direction; Among them, the first portion of the fourth scan line is disposed between the first portion of the third scan line and the first initialization signal line. The second electrode of the optoelectronic unit is disposed on a side of the first initialization signal line away from the first portion of the fourth scan line. The reset signal line is disposed on a side of the second electrode of the optoelectronic unit away from the first initialization signal line. The first portion of the third scan line is connected to the first gate of the first initialization transistor, and the gate of the reset transistor is connected to the reset signal line.

15. The display panel according to claim 14, wherein, The third metal layer includes a second portion of the third scan line, a second portion of the fourth scan line, and a second gate of the first initialization transistor; Among them, the second portion of the third scan line is connected to the second gate of the first initialization transistor.

16. The display panel according to claim 15, wherein, The second source-drain layer includes a data line, a first power supply signal line, a second power supply signal line, a sense signal output line, and a low potential signal line, which are arranged in a second direction; Among them, within the pixel driving circuits of two adjacent sub-pixel units, in the first direction, the sense signal output line is disposed on a side of the data line away from the first power supply signal line, and the low potential signal line is disposed on a side of the sense signal output line close to the data line.

17. The display panel according to claim 16, wherein, The second initialization signal line in the sub-pixel unit of the row above the first source-drain layer, the second initialization signal line in the sub-pixel unit of the current row, a first power connection line, a second power connection line, a fourth transfer line, a data connection line, a sense connection line, a low potential connection line, a first initialization connection line, a control signal line, and a second electrode of the driving transistor; In the second direction, the second initialization signal line in the sub-pixel unit of the row above is disposed on one side of the first power connection line. The second power connection line is disposed between adjacent first power connection lines. The fourth transfer line is disposed on a side of the first power connection line away from the second initialization signal line in the sub-pixel unit of the row above. The second initialization signal line in the sub-pixel unit of the current row is disposed on a side of the fourth transfer line away from the first power connection line. The data connection line is disposed on a side of the second initialization signal line in the sub-pixel unit of the current row away from the fourth transfer line. The first initialization connection line is disposed on a side of the data connection line away from the second initialization signal line in the sub-pixel unit of the current row. In the first direction, the sense connection line is disposed on a side of the data connection line away from the first initialization connection line. The low potential connection line is disposed on a side of the first power connection line away from the second power connection line. The control signal line is disposed on a side of the sense connection line away from the first initialization connection line; The second initialization signal line in the sub-pixel unit described in the previous line is connected to the first electrode of the second initialization transistor. The first power connection line is connected to the first power signal line. The second power connection line is connected to the second power signal line and one electrode of the light-emitting device. One end of the fourth transfer line is connected to the gate of the driving transistor, and the other end of the fourth transfer line is connected to the first scan line. The data connection line is connected to the first electrode of the switching transistor and the data line. The sensing connection line is connected to the sensing signal output line and the second electrode of the control transistor. The low-potential connection line is connected to the low-potential signal line, the first electrode of the reset transistor, and the first electrode of the amplifying transistor. The control signal line is connected to the gate of the control transistor; Wherein, the first initialization connection line is connected to the second electrode of the optoelectronic unit, the first initialization signal line, and the first electrode of the first initialization transistor; or the first initialization connection line is connected to the first initialization signal line and the first electrode of the first initialization transistor, and the second initialization signal line in the sub-pixel unit described in this line is connected to the second electrode of the optoelectronic unit.

18. A display device, which includes a display panel, and the display panel includes: A substrate; A driving circuit layer, which is disposed on one side of the substrate. The driving circuit layer includes: a pixel driving circuit and a sensing circuit disposed between adjacent pixel driving circuits; A light-emitting layer, which is disposed on the side of the driving circuit layer away from the substrate. The light-emitting layer includes: a light-emitting device corresponding to the pixel driving circuit, and the light-emitting device is electrically connected to the corresponding pixel driving circuit; Wherein, the pixel driving circuit includes: a switching transistor, a driving transistor, a first initialization transistor, and a second initialization transistor. The switching transistor and the driving transistor are connected to a first node. The switching transistor is configured to input a data signal to the first node under the control of a first scan signal. One electrode of the first initialization transistor is connected to the driving transistor at a second node, and the other electrode of the first initialization transistor is connected to a first initialization signal line. One electrode of the second initialization transistor is connected to the light-emitting device at a third node, and the other electrode of the second initialization transistor is connected to a second initialization signal line. The second initialization transistor is configured to input a second initialization signal to the anode of the light-emitting device under the control of a second scan signal. The first initialization transistor is configured to input a first initialization signal to the second node under the control of a third scan signal; The sensing circuit includes: an optoelectronic unit and a sensing signal output line. The first electrode of the optoelectronic unit is electrically connected to the sensing signal output line, and the second electrode of the optoelectronic unit is connected to one of the first initialization signal line and the second initialization signal line.

19. The display device according to claim 18, wherein, Two adjacent pixel driving circuits are symmetrically arranged, and the optoelectronic unit is arranged along the direction of the axis of symmetry of the two pixel driving circuits.

20. The display device according to claim 18, wherein, The sensing circuit further includes an amplifying transistor, a control transistor, and a reset transistor. The gate of the amplifying transistor is connected to one end of the optoelectronic unit. One electrode of the amplifying transistor is connected to one electrode of the control transistor, and the other electrode of the amplifying transistor is connected to one electrode of the reset transistor. The other electrode of the control transistor is connected to the sensing signal output line, and the other electrode of the reset transistor is connected to one end of the optoelectronic unit. The amplifying transistor is used to amplify the signal of the optoelectronic unit. The control transistor is used to control the output of the signal of the optoelectronic unit under the control of a control signal. The reset transistor is used to reset the first electrode of the optoelectronic unit under the control of a reset control signal.

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