Refresh control structure, refresh control method, and memory

Abstract

The present disclosure relates to the field of semiconductor device structure design, and in particular to a refresh control structure, a refresh control method, and a memory. A processing circuit is used for executing, on the basis of a refresh window, a refresh on an address to be refreshed; a counting circuit is used for generating said address, and on the basis of a count clock, controlling said generated address to increment by 1; and the counting circuit is further used for resetting a least significant bit of said address on the basis of an abort signal, and remaining a next least significant bit of said address unchanged in the process of resetting the least significant bit of said address. The present disclosure is at least used for enhancing the accuracy of memory self-refresh.

Description

Refresh control structure, refresh control method and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 26, 2024, with application number 202410111236.6 and application name “Refresh control structure, refresh control method and memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor device structure design, and in particular to a refresh control structure, a refresh control method and a memory. Background Art

[0003] Memory is a storage component used to store programs and various data. Memory can be categorized as either volatile or non-volatile. Dynamic Random Access Memory (DRAM), a type of volatile memory, stores data by charging or discharging capacitors within its storage cells. This data is lost when power is removed. Non-volatile memory, on the other hand, retains stored data even when power is removed.

[0004] Volatile memory devices are widely used as main memories of various devices, whereas non-volatile memory devices are widely used to store program codes and / or data in various electronic devices such as computers, mobile devices, and the like.

[0005] Regardless of whether it is a volatile memory or a non-volatile memory, the memory ensures the accuracy of the stored data by continuously performing a refresh operation during operation. Ensuring the accuracy of the refresh operation ensures the accuracy of the stored data to a certain extent.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a refresh control structure, a refresh control method, and a memory, which are at least used to improve the accuracy of memory self-refresh.

[0008] An embodiment of the present disclosure provides a refresh control structure, which is arranged in a storage block, and includes: a processing circuit, configured to refresh an address to be refreshed based on a refresh window; a counting circuit, configured to generate an address to be refreshed, and add 1 to the generated address to be refreshed based on a counting clock control; the counting circuit is also configured to reset the lowest bit of the address to be refreshed based on a termination signal, and in the process of resetting the lowest bit of the address to be refreshed, the second lowest bit of the address to be refreshed remains unchanged.

[0009] For the refresh control structure provided in this embodiment, when the counting circuit resets the lowest bit of the address to be refreshed, the second lowest bit of the address to be refreshed remains unchanged, thereby avoiding the counting process of the address to be refreshed due to the carry signal during the process of resetting the lowest bit, thereby avoiding the problem of missed refresh of the memory.

[0010] In some embodiments, the address to be refreshed is an n-bit binary signal, and the counting circuit includes n cascaded counting units, each counting unit including: a first clock end, for receiving a counting clock; a second clock end, for receiving a delay clock, the delay clock being a delay signal of the counting clock; a reset control end, for receiving a reset signal, and the reset control end of the first-level counting unit is also used to receive a termination signal; a first output end, for generating an address signal, and the n address signals generated by the n counting units constitute the address to be refreshed; a second output end, connected to the control end of the next-level counting unit, for generating a carry signal, wherein the control end of the first-level counting unit receives a high level; the counting unit is configured to, when the signal input from the control end is valid, flip the address signal based on the delay clock, and flip the carry signal based on the counting clock.

[0011] In some embodiments, the counting unit includes: a NAND logic circuit, a first input terminal connected to a control terminal, and a second input terminal for receiving a delayed clock; a first trigger, an inverted clock terminal connected to the output terminal of the NAND logic circuit, an output terminal connected to a first output terminal, and a reset terminal connected to a reset control terminal; a second trigger, a clock terminal for receiving a counting clock, an input terminal connected to the output terminal of the first trigger, an inverted output terminal connected to the input terminal of the first trigger, and a set terminal connected to the reset control terminal.

[0012] In some embodiments, the counting unit further includes: an AND logic circuit, wherein the first input terminal is connected to the output terminal of the second trigger, the second input terminal is connected to the control terminal, and the output terminal is connected to the second output terminal.

[0013] In some embodiments, the refresh control structure further includes: a delay unit, configured to generate a delay clock based on the counting clock.

[0014] In some embodiments, the delay unit includes: a non-logic circuit, whose input end is used to receive a counting clock; a delay circuit, whose input end is connected to the output end of the non-logic circuit; or a non-logic circuit, whose first input end is used to receive a counting clock, whose second input end is connected to the output end of the delay circuit, and whose output end is used to output a delayed clock.

[0015] In some embodiments, the delay unit includes: a delay circuit, an input end for receiving a counting clock, and an output end for outputting a delayed clock.

[0016] In some embodiments, the counting circuit is configured to reset the address to be refreshed based on a reset signal.

[0017] Another embodiment of the present disclosure further provides a refresh control method, which is applied to the self-refresh mode of the memory, including: the self-refresh mode applied to the memory, including: obtaining the address to be refreshed, and performing a refresh on the address to be refreshed based on the refresh window; after completing the refresh, controlling the address to be refreshed to be incremented by 1 based on the counting clock; wherein, the refresh windows opened based on the same refresh command are even numbers; during the refresh process, if a termination signal is received, adjusting the address to be refreshed based on the refresh control structure provided in the above embodiment.

[0018] Yet another embodiment of the present disclosure provides a memory, which includes a plurality of memory blocks, and each of the plurality of memory blocks includes the refresh control structure provided in the above embodiment, and performs a self-refresh function based on the refresh control structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] FIG1 shows the correspondence between refresh commands and refresh windows in different refresh modes of the memory provided by the present disclosure;

[0021] FIG2 is a schematic diagram showing the principle of executing refresh address counting in the self-refresh mode of the memory provided by the present disclosure;

[0022] FIG3 is a schematic diagram showing the principle of executing refresh address counting when the memory provided by the present disclosure is in self-refresh mode and the self-refresh process is interrupted;

[0023] FIG4 is a schematic structural diagram of a counting structure provided by the present disclosure;

[0024] FIG5 is a schematic structural diagram of each counting unit in the counting structure shown in FIG4 provided by the present disclosure;

[0025] FIG6 is a schematic diagram of the counting principle of the counting structure shown in FIG4 and FIG5 provided by the present disclosure;

[0026] FIG7 is a schematic structural diagram of a refresh control structure provided by an embodiment of the present disclosure;

[0027] FIG8 is a schematic structural diagram of a counting circuit provided in one embodiment of the present disclosure;

[0028] FIG9 is a schematic structural diagram of each counting unit in the counting circuit shown in FIG8 according to an embodiment of the present disclosure;

[0029] FIG10 is a schematic diagram of the counting principle of the counting circuits shown in FIG8 and FIG9 according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As known from the background art, during the working process of the memory, the accuracy of the stored data is ensured by continuously executing the refresh operation. Ensuring the accuracy of the refresh operation ensures the accuracy of the stored data to a certain extent.

[0031] An embodiment of the present disclosure provides a refresh control structure, which is at least used to improve the accuracy of memory self-refresh.

[0032] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0033] The refresh control structure provided by this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0034] For the memory provided by the embodiment of the present disclosure, the refresh commands of the memory include two categories, namely the full array refresh command (refresh all bank, REFab) and the same array refresh command (refresh same bank, REFsb). Among them, REFab is used to instruct all storage blocks in the memory to perform a refresh on the address to be refreshed; REFsb is used to instruct the target storage block in the memory to perform a refresh on the address to be refreshed. And the number of refresh windows opened by a single REFab is greater than the number of refresh windows opened by a single REFsb. Referring to Figure 1, Figure 1 shows the correspondence between the refresh command and the refresh window in different refresh modes of the memory provided by the present disclosure. In one example, the refresh windows opened by a single REFab are 4, and the refresh windows opened by a single REFsb are 2. In other examples, the refresh windows opened by a single REFab can be 5, and the refresh windows opened by a single REFsb can be 3.

[0035] In addition, the refresh modes of the memory include three categories, namely normal refresh mode, fine grained refresh (FGR) mode and self refresh (SREF) mode. Among them, the memory performs refresh based on REFab in normal refresh mode, and the memory is also refreshed based on REFab in FGR mode, but the number of refresh windows opened by REFab in FGR mode is less than the number of refresh windows opened by REFab in normal refresh mode, and the memory is refreshed based on REFsb in SREF mode. Referring to Figure 1, in one example, the number of refresh windows opened by a single REFab in normal refresh mode is 4, the number of refresh windows opened by a single REFab in FGR mode is 2, and the number of refresh windows opened by a single REFsb in SREF mode is 2. In other examples, the number of refresh windows opened by a single REFab in normal refresh mode can be 5, the number of refresh windows opened by a single REFab in FGR mode can be 3, and the number of refresh windows opened by a single REFsb in SREF mode can be 3.

[0036] For REFab refresh, a refresh address counter is set in the memory controller, and the refresh address counter counts up by 1 based on the refresh window execution. For example, for a single REFab, four refresh windows are opened. In the first refresh window, the refresh address counter's refresh address is n, and all memory blocks in the memory execute refreshes on refresh address n; in the second refresh window, the refresh address counter's refresh address is n+1, and all memory blocks in the memory execute refreshes on refresh address n+1; in the third refresh window, the refresh address counter's refresh address is n+2, and all memory blocks in the memory execute refreshes on refresh address n+2; and in the fourth refresh window, the refresh address counter's refresh address is n+3, and all memory blocks in the memory execute refreshes on refresh address n+3. For REFsb refresh, the refresh address counter is set in the storage controller and each storage block. The first REFsb is used to instruct the first storage block to perform a refresh. In the first refresh window, the first storage block refreshes the refresh address n issued by the refresh address counter in the storage controller, and then the refresh address counter inside the storage block counts 1 based on the refresh address n. In the second refresh window, the first storage block refreshes the refresh address n+1 obtained by the internal refresh address counter; the second REFsb is used to instruct the second storage block to perform the above refresh operation until all storage blocks complete the refresh of refresh address n and refresh address n+1, and the refresh address counter in the storage controller executes refresh address +2, so that under the next REFsb, the first storage block starts to refresh the refresh address n+2.

[0037] Based on the above discussion, it can be seen that the number of refresh windows opened by the refresh command in different refresh modes is different, and the number of different refresh windows will affect the configuration of the refresh address counter inside the storage block. For example, if the value of the refresh address counter inside the storage block is both odd and even when a refresh command ends, the refresh address counter can only be configured through a full adder. The circuit area of ​​the full adder is large. If a full adder is set in each storage block, the circuit area of ​​the memory will be greatly increased. If the refresh windows opened by different refresh commands are all set to even numbers, then at the end of any refresh command, the value of the refresh address counter inside the storage block must be an even number. At this time, for the second refresh window opened by REFsb, it can be achieved by inverting the end address. Compared with the circuit implemented using a full adder, inverting the end address only involves one inverter, and the circuit area of ​​the memory can be greatly reduced.

[0038] According to DDR specifications, after the memory exits SREF, if a refresh operation is currently in progress, the DRAM completes the entire refresh operation to continue refreshing the remaining row addresses. Because the refresh operation simultaneously turns on and precharges all memory blocks, the required peak and average currents are very high. This high current demand can easily cause disturbances in the memory power supply. However, the delay phase-locked loop (DLL) lock begins when the memory controller issues the SREF instruction. This results in DLL locking occurring in an environment with significant memory power disturbances.

[0039] To address this issue, the memory's SREF needs to implement a forced interrupt function (SREF Abort). The SREF forced interrupt function is used to interrupt the ongoing refresh operation when exiting the SREF. However, forcing the interruption of the currently executing refresh operation may cause the refresh address counter inside the memory block to be an odd number after exiting the SREF. If REFsb is executed at this time, the refresh address will be missed. In other words, for the SREF Abort function, the refresh address counter inside the memory block needs to be reset to an even address.

[0040] Referring to Figure 2, Figure 2 is a schematic diagram of the principle of executing refresh address counting in the self-refresh mode of the memory provided by the present disclosure. Ideally, SREF WIN is used to characterize the time when the memory executes SREF, that is, in the example of Figure 2, when SREF WIN is valid, the memory executes SREF. When the memory executes SREF, it refreshes the address to be refreshed based on the refresh window opened by the self-refresh command SREFc, and each time a self-refresh window is opened, a counting clock CLK is generated. The counting clock CLK is used to count the refresh address and obtain the address to be refreshed required for the next self-refresh window. As shown in Figure 2, in a normal SREF process, the memory refreshes the address to be refreshed 2n-4 to 2n+4 in sequence.

[0041] In combination with Figure 2 and referring to Figure 3, Figure 3 is a schematic diagram of the principle of executing refresh address counting when the memory provided by the present invention is in self-refresh mode and the self-refresh process is interrupted. If the forced interrupt function (SREF Abort) of SREF is executed during the process of the memory executing SREF, in the example of Figure 3, the forced interrupt function of SREF is based on the interrupt signal RST. When the interrupt signal RST is at a high level, the forced interrupt function of SREF is executed.

[0042] Specifically, the interrupt signal RST forcibly ends the memory's SREF process, i.e., turns off SREF WIN and invalidates the current self-refresh command SREFc. At this time, the to-be-refreshed address corresponding to 2n+4 cannot be refreshed, and the count value of the internal refresh address counter is 2n+3, which is an odd number. Based on the previous description, the interrupt signal RST also requires the use of related circuits to adjust the count value of the internal refresh address counter to an even number. For the example in Figure 3, the count value of the internal refresh address counter needs to be adjusted to 2n+2, 2n, or 2n-2, etc.

[0043] In this regard, currently a counting structure is provided in the memory, which is provided in the memory block and is used to realize the function of refreshing the address counter and also to adjust the count value to an even number in conjunction with the interrupt signal RST.

[0044] 4, which is a schematic diagram of the structure of the counting structure provided by the present disclosure. The address to be refreshed is an n-bit binary signal. The counting structure includes n cascaded counting units 10. Each counting unit 10 includes: a clock terminal CNTCLK for receiving a counting clock CBR_CLK; a reset control terminal CNTRST for receiving a reset signal CBR_RST, and the reset control terminal of the first-stage counting unit 10 is also used to receive a termination signal SrefAbortRst; a first output terminal OUT for generating an address signal, wherein the n address signals generated by the n counting units 10 constitute the address to be refreshed RA <n:0>; The second output terminal CAOUT is connected to the control terminal CAIN of the next-stage counting unit 10 for generating a carry signal, wherein the control terminal CAIN of the first-stage counting unit 10 receives a high level; the counting unit 10 is configured to flip the address signal and the carry signal based on the counting clock CBR_CLK when the signal input from the control terminal is valid.

[0045] It should be noted that, for the first-stage counting unit 10 , the simultaneous reception of the reset signal CBR_RST and the termination signal SrefAbortRst can be achieved through an OR logic circuit.

[0046] Specifically, one input terminal of the OR logic circuit is used to receive the reset signal CBR_RST, the other input terminal is used to receive the termination signal SrefAbortRst, and the output terminal is connected to the reset control terminal CNTRST of the first-stage counting unit 10. It should be noted that in the example of FIG4 , the OR logic circuit is implemented based on cascaded NOR gates and inverters. In other examples, the OR logic circuit can be directly based on OR gates or other multiple cascaded gate circuits.

[0047] It should also be noted that FIG4 is an example of an example in which the counting structure includes five cascaded counting units 10. At this time, the counting structure generates a to-be-refreshed address RA<4:0>. Those skilled in the art can use the to-be-refreshed address RA<4:0> as an example. <n:0>The specific number of bits is used to configure the corresponding number of counting units 10.

[0048] Referring to Figure 5, Figure 5 is a structural schematic diagram of each counting unit in the counting structure shown in Figure 4 provided by the present disclosure, and each counting unit 10 includes: a first inverter, whose input end is connected to the clock end CNTCLK of the counting unit 10 to receive the counting clock CBR_CLK; a NAND gate, whose first input end is connected to the output end of the first inverter, and whose second input end is connected to the control end CAIN of the counting unit 10; the inverting clock end of the first trigger is connected to the output end of the NAND gate, and the output end Q is connected to the first output end OUT of the counting unit 10; the clock end of the second trigger is connected to the output end of the NAND gate, the input end D is connected to the output end Q of the first trigger, and the inverting output end / Q is connected to the input end D of the first trigger.

[0049] Referring to FIG. 5 and in conjunction with FIG. 6 , FIG. 6 is a schematic diagram of the counting principle of the counting structure shown in FIG. 4 and FIG. 5 provided by the present disclosure. For the first-stage counting unit 10, the control terminal CAIN of the first-stage counting unit 10 receives a high level. At this time, the NAND gate can be regarded as an inverter, and the indication signal CLKx output by the NAND gate can be regarded as the same signal as the counting clock CBR_CLK after two stages of inversion. It should be noted that with respect to the indication signal CLKx, i.e., CLK shown in FIG. 6 , the indication signal in the first-stage counting unit 10 is CLK0, the indication signal in the second-stage counting unit 10 is CLK1, and the indication signal in the n+1th-stage counting unit 10 is CLKn.

[0050] Since the output of the NAND gate is connected to the inverting clock terminal of the first flip-flop, the inverting clock terminal of the flip-flop is driven based on a falling edge, that is, the first flip-flop is driven based on the falling edge of the indication signal CLKx output by the NAND gate. Since the output Q of the first flip-flop is connected to the input of the second flip-flop, and the inverting output / Q of the second flip-flop is connected to the input D of the first flip-flop, the first flip-flop and the second flip-flop can be regarded as controlling the output signal to flip based on the valid signal of the clock terminal or the inverted clock terminal. Referring to Figures 5 and 6, the first flip-flop in the first-stage counting unit 10 flips the address signal OUT0 based on the indication signal CLK0 to form the address to be refreshed RA <n:0>It should be noted that the data outputted to the first output terminal OUT by the first-stage counting unit 10 is the address signal OUT0, the data outputted to the first output terminal OUT by the second-stage counting unit 10 is the address signal OUT1, ..., the data outputted to the first output terminal OUT by the n+1th-stage counting unit 10 is the address signal OUTn.

[0051] For the second flip-flop, the clock terminal of the second flip-flop is connected to the clock terminal CNTCLK of the counting unit 10 to receive the counting clock CBR_CLK. The clock terminal of the flip-flop is driven based on the rising edge, that is, the second flip-flop can be regarded as flipping the output signal based on the rising edge of the counting clock CBR_CLK. Referring to Figures 5 and 6, the second flip-flop in the first-stage counting unit 10 flips the output signal based on the rising edge of the counting clock CBR_CLK to generate the carry signal CAOUT0. It should be noted that the carry signal output by the first-stage counting unit 10 is CAOUT0, the carry signal output by the second-stage counting unit 10 is CAOUT1, and the carry signal output by the n+1th-stage counting unit 10 is CAOUTn.

[0052] For non-first-stage counting units 10, the control terminal CAIN of each counting unit 10 is connected to the second output terminal CAOUT of the previous-stage counting unit 10 for receiving the carry signal CAOUTx. Based on the operating principle of the first inverter and the NAND gate, as shown in FIG6 , the NAND gate in the second-stage counting unit 10 generates the indication signal CLK1 based on the carry signal CAOUT0 generated by the first-stage counting unit 10 and the count clock CBR_CLK. The first flip-flop in the second-stage counting unit 10 flips the address signal OUT1 based on the falling edge of the indication signal CLK1.

[0053] For each counting unit 10, the set terminal SET of the second flip-flop is connected to the reset control terminal CNTRST. The reset control terminal CNTRST of the first-stage counting unit 10 is used to receive the reset signal CBR_RST and the termination signal SrefAbortRst, while the reset control terminal CNTRST of the other counting units 10 is used only to receive the reset signal CBR_RST. When the termination signal SrefAbortRst is valid, the carry signal CAOUT0 output of the second flip-flop in the first-stage counting unit 10 is set to 1. In the process of setting the carry signal CAOUT0 output of the second flip-flop in the first-stage counting unit 10 to 1, because the indication signal CLK0 is at a low level, the inverted output data of the second flip-flop is sampled by the first flip-flop, and the first flip-flop sets the output address signal OUT0 to 0, thereby resetting the least significant bit of the address to be refreshed to 0. However, during this process, because the carry signal CAOUT0 generated by the first-stage counting unit 10 is 1, a falling edge occurs in the indication signal CLK1 generated by the AND gate in the second-stage counting unit 10. The falling edge of the indication signal CLK1 instructs the first flip-flop to flip the data, causing the counting structure to count forward. That is, the counting structure counts based on the termination signal SrefAbortRst, and the counting address is incremented by 1. As shown in Figure 6, during the refresh process of address 3 to be refreshed, the termination signal SrefAbortRst is valid, the address to be refreshed is counted to 4, and the subsequent refresh process starts based on address 4 to be refreshed, thus missing the refresh of address 3 to be refreshed.

[0054] Therefore, although the current counting structure in the memory can adjust the count value to an even number in conjunction with the interrupt signal RST, the adjusted count value will cause the memory to miss refreshing a certain address, which may cause abnormalities in the data stored in the memory.

[0055] In this regard, an embodiment of the present disclosure provides a refresh control structure. Referring to FIG7 , FIG7 is a schematic diagram of the structure of the refresh control structure provided by an embodiment of the present disclosure. The refresh control structure is provided in the storage block, and is at least used to improve the accuracy of the memory self-refresh. The refresh control structure includes: a processing circuit 102 and a counting circuit 101. The processing circuit 102 is configured to perform a refresh on the address to be refreshed based on the refresh window. The counting circuit 101 is configured to generate an address to be refreshed, and to add 1 to the generated address to be refreshed based on the counting clock control; and the counting circuit 101 is also configured to reset the lowest bit of the address to be refreshed based on the termination signal, and in the process of resetting the lowest bit of the address to be refreshed, the second lowest bit of the address to be refreshed remains unchanged.

[0056] For the refresh control structure provided in this embodiment, when the counting circuit 101 resets the lowest bit of the address to be refreshed, the second lowest bit of the address to be refreshed remains unchanged, thereby avoiding the counting process of the address to be refreshed due to the carry signal during the process of resetting the lowest bit, thereby avoiding the problem of missed refresh of the memory.

[0057] It should be noted that the refresh control structure shown in FIG. 7 is also used to receive a reset signal, which is used to reset or set the count value of the counting circuit 101 , thereby resetting the address to be refreshed generated by the counting circuit 101 based on the reset signal.

[0058] Specifically, referring to Figure 8, Figure 8 is a structural diagram of a counting circuit provided by an embodiment of the present disclosure. The address to be refreshed is an n-bit binary signal. The counting circuit 101 includes n cascaded counting units 201, and each counting unit 201 includes: a first clock terminal CNTCLK, for receiving a counting clock CBR_CLK; a second clock terminal CNTEnd, for receiving a delayed clock CBR_CLKEnd, wherein the delayed clock CBR_CLKEnd is a delayed signal of the counting clock CBR_CLK; a reset control terminal CNTRST, for receiving a reset signal CBR_RST, and the reset control terminal of the first-stage counting unit 201 is also used to receive a termination signal SrefAbortRst; a first output terminal OUT, for generating an address signal, wherein the n address signals generated by the n counting units 201 constitute the address to be refreshed RA <n:0>; The second output terminal CAOUT is connected to the control terminal CAIN of the next-stage counting unit 201, and is used to generate a carry signal, wherein the control terminal CAIN of the first-stage counting unit 201 receives a high level; the counting unit 201 is configured to, when the signal input from the control terminal is valid, flip the address signal based on the delay clock CBR_CLKEnd, and flip the carry signal based on the counting clock CBR_CLK.

[0059] It should be noted that, for the first-stage counting circuit 101, the simultaneous reception of the reset signal CBR_RST and the termination signal SrefAbortRst can be achieved through an OR logic circuit 202. Specifically, one input terminal of the OR logic circuit 202 is used to receive the reset signal CBR_RST, the other input terminal is used to receive the termination signal SrefAbortRst, and the output terminal is connected to the reset control terminal CNTRST of the first-stage counting circuit 101. It should be noted that in the example of FIG8 , the OR logic circuit 202 is implemented based on cascaded NOR gates and inverters; in other examples, the OR logic circuit can be directly based on an OR gate, or other multiple cascaded gate circuits.

[0060] It should also be noted that FIG8 is an example of an example in which the counting circuit 101 includes five cascaded counting units 201. At this time, the refresh address RA<4:0> is generated, and this does not limit the number of counting units 201 in the counting circuit 101 in this embodiment. Those skilled in the art can select the number of counting units 201 according to the refresh address RA<4:0>. <n:0>The specific number of bits is used to configure the corresponding number of counting units 201.

[0061] Referring to FIG9 , FIG9 is a schematic diagram of the structure of each counting unit in the counting circuit shown in FIG8 according to an embodiment of the present disclosure. Each counting unit 201 includes: a NAND logic circuit 203, a first flip-flop 301, and a second flip-flop 302. The first input terminal of the NAND logic circuit 203 is connected to the control terminal CAIN of the counting unit 201, and the second input terminal is used to receive the delay clock CNTCLKEnd. The inverted clock terminal of the first flip-flop 301 is connected to the output terminal of the NAND logic circuit 203, the output terminal Q is connected to the first output terminal OUT of the counting unit 201, and the reset terminal RST is connected to the reset control terminal CNTRST of the counting unit 201. The clock terminal of the second flip-flop 302 is used to receive the counting clock CBR_CLK, the input terminal D is connected to the output terminal Q of the first flip-flop 301, the inverted output terminal / Q is connected to the input terminal D of the first flip-flop 301, and the set terminal SET is connected to the reset control terminal CNTRST of the counting unit 201.

[0062] In one example, the NAND logic circuit 203 is implemented by a NAND gate; in other examples, the NAND logic circuit can also be implemented by a cascade of NAND gates and inverters, or by a combination of other logic gate circuits.

[0063] Referring to FIG. 9 and in conjunction with FIG. 10 , FIG. 10 is a schematic diagram of the counting principle of the counting circuit shown in FIG. 8 and FIG. 9 , provided in one embodiment of the present disclosure. For the first-stage counting unit 201, the control terminal CAIN of the first-stage counting unit 201 receives a high level. At this time, the NAND logic circuit 203 can be regarded as an inverter, and the indication signal CLKx output by the NAND logic circuit 203 and the delay clock CBR_CLKEnd are mutually inverted signals. It should be noted that with respect to the indication signal CLKx, i.e., CLK shown in FIG. 9 , the indication signal in the first-stage counting unit 201 is CLK0, the indication signal in the second-stage counting unit 201 is CLK1, and the indication signal in the n+1th-stage counting unit 201 is CLKn.

[0064] Since the output terminal of the NAND logic circuit 203 is connected to the inverted clock terminal of the first flip-flop 301, the inverted clock terminal of the flip-flop is driven based on the falling edge, that is, the first flip-flop 301 is driven based on the falling edge of the indication signal CLKx output by the NAND logic circuit 203. Moreover, the indication signal CLKx output by the NAND logic circuit 203 and the delay clock CBR_CLKEnd are mutually inverted signals, which can be regarded as the first flip-flop 301 being driven based on the rising edge of the delay clock CBR_CLKEnd. Since the output terminal Q of the first flip-flop 301 is connected to the input terminal of the second flip-flop 302, and the inverted output terminal / Q of the second flip-flop 302 is connected to the input terminal D of the first flip-flop 301, the first flip-flop 301 and the second flip-flop 302 can be regarded as controlling the output signal to be flipped based on the valid signal of the clock terminal or the inverted clock terminal. Referring to Figures 9 and 10, the first flip-flop 301 in the first-stage counting unit 201 flips the address signal OUT0 based on the falling edge of the indication signal CLK0 to form the address RA to be refreshed <n:0>It should be noted that the data outputted to the first output terminal OUT by the first stage counting unit 201 is OUT0, the data outputted to the first output terminal OUT by the second stage counting unit 201 is OUT1, ..., the data outputted to the first output terminal OUT by the n+1th stage counting unit 201 is OUTn.

[0065] Regarding the second flip-flop 302, the clock terminal of the second flip-flop 302 is connected to the first clock terminal CNTCLK to receive the count clock CBR_CLK. The clock terminal of the flip-flop is driven based on the rising edge. The second flip-flop 302 can be regarded as flipping the output signal CAOUTx based on the rising edge of the count clock CBR_CLK. Referring to Figures 9 and 10, the second flip-flop 302 in the first-stage counting unit 201 flips the output signal based on the rising edge of the count clock CBR_CLK to generate the carry signal CAOUT0. It should be noted that the carry signal output by the first-stage counting unit 201 is CAOUT0, the carry signal output by the second-stage counting unit 201 is CAOUT1, and the carry signal output by the (n+1)th-stage counting unit 201 is CAOUTn.

[0066] For non-first-stage counting units 201, the control terminal CAIN of the counting unit 201 is connected to the second output terminal CAOUT of the previous-stage counting unit 201 to receive the carry signal CAOUTx. Based on the operating principle of the NAND logic circuit 203, when the carry signal generated by the previous-stage counting unit 201 is high, an inverted pulse of the delay clock CNTCLKEnd is generated accordingly. As shown in Figure 10, the NAND logic circuit 203 in the second-stage counting unit 201 generates the indication signal CLK1 based on the carry signal CAOUT0 generated by the first-stage counting unit 201 and the delay clock CNTCLKEnd. The first flip-flop 301 in the second-stage counting unit 201 flips the address signal OUT1 based on the falling edge of the indication signal CLK1.

[0067] For each counting unit 201, the reset terminal RST of the first flip-flop 301 and the set terminal SET of the second flip-flop 302 are connected to the reset control terminal CNTRST. The reset control terminal CNTRST of the first-stage counting unit 201 is used to receive both the reset signal CBR_RST and the termination signal SrefAbortRst. The reset control terminals CNTRST of the other counting units 201 are used only to receive the reset signal CBR_RST. When the termination signal SrefAbortRst is asserted, the address signal OUT0 outputted by the first flip-flop 301 in the first-stage counting unit 201 is reset to 0, and the carry signal CAOUT0 outputted by the second flip-flop 302 in the first-stage counting unit 201 is set to 1. However, due to the structural configuration of the counting unit 201, the carry signal set to 1 does not affect the value of the indicator signal CLKx in the subsequent counting unit 201. Referring to Figure 10, when the first-stage counting unit 201 changes the output carry signal CAOUT0 to 1 based on the termination signal SrefAbortRst, the indicator signal CLK1 in the second-stage counting unit 201 does not jump, and the counting circuit 101 does not continue counting, only resetting the least significant bit. In other words, during the refresh process of the to-be-refreshed address 3, the termination signal SrefAbortRst is valid, the to-be-refreshed address is reset to 2, and the subsequent refresh process begins based on the to-be-refreshed address 2. The refresh process continues, and no refresh is missed.

[0068] It should be noted that, compared with the counting structure, the counting circuit 101 provided in this embodiment has a delay in the output signal of the first trigger 301, as the first trigger 301 is driven based on the delay clock CNTCLKEnd, and the second trigger 302 is driven based on the counting clock CBR_CLK. This results in a certain delay between the output data of the first trigger 301 and the output data of the second trigger 302, which are originally inversely phased.

[0069] In some embodiments, referring to FIG9 , the counting unit 201 further includes an AND logic circuit 204 having a first input connected to the output Q of the second flip-flop 302, a second input connected to the control terminal CAIN of the counting unit 201, and an output connected to the second output terminal CAIN of the counting unit 201, such that the carry signal output by the counting unit 201 is controlled by the input signal at the control terminal. In one example, the AND logic circuit 204 is implemented by a NAND gate connected in series with an inverter. In other examples, the AND logic circuit can also be implemented based on an AND gate or a combination of other logic gate circuits.

[0070] In some embodiments, the refresh control structure further includes a delay unit, and the delay unit is configured to generate a delay clock CBR_CLKEnd based on the counting clock CBR_CLK.

[0071] In one example, referring to FIG8 , the delay unit 303 includes: a non-logic circuit 310, whose input end is used to receive the counting clock CBR_CLK; a delay circuit 320, whose input end is connected to the output end of the non-logic circuit 310; or a non-logic circuit 330, whose first input end is used to receive the counting clock CBR_CLK, whose second input end is connected to the output end of the delay circuit 320, and whose output end is used to output the delayed clock CBR_CLKEnd.

[0072] In another example, the delay unit includes a delay circuit, wherein the input end of the delay circuit is used to receive the counting clock CBR_CLK, and the output end of the delay circuit is used to output the delayed clock CBR_CLKEnd, so as to directly delay the counting clock CBR_CLK to generate and output the delayed clock CBR_CLKEnd.

[0073] For the refresh control structure provided in this embodiment, when the counting circuit resets the lowest bit of the address to be refreshed, the second lowest bit of the address to be refreshed remains unchanged, thereby avoiding the counting process of the address to be refreshed due to the carry signal during the process of resetting the lowest bit, thereby avoiding the problem of missed refresh of the memory.

[0074] It should be noted that the features disclosed in the refresh control structure provided in the above embodiments can be arbitrarily combined without conflict to obtain a new refresh control structure embodiment.

[0075] Another embodiment of the present disclosure provides a refresh control method, which is at least used to improve the accuracy of memory self-refresh.

[0076] Specifically, the refresh control method includes: obtaining the address to be refreshed, and performing a refresh on the address to be refreshed based on the refresh window, and after the refresh is completed, controlling the address to be refreshed to be increased by 1 based on the missing count; wherein, the refresh windows opened based on the same refresh command are even numbers; during the refresh process, if a termination signal is received, the address to be refreshed is adjusted based on the refresh control structure provided in the above embodiment.

[0077] Referring to FIG. 9 and in conjunction with FIG. 10 , for the first-stage counting unit 201, the control terminal CAIN of the first-stage counting unit 201 receives a high level. At this time, the NAND logic circuit 203 can be regarded as an inverter, and the indication signal CLKx output by the NAND logic circuit 203 and the delay clock CBR_CLKEnd are mutually inverted signals. It should be noted that the indication signal CLKx, i.e., the CLK shown in FIG. 9 , is CLK0 in the first-stage counting unit 201, CLK1 in the second-stage counting unit 201, and CLKn in the (n+1)th-stage counting unit 201.

[0078] Since the output terminal of the NAND logic circuit 203 is connected to the inverted clock terminal of the first flip-flop 301, the inverted clock terminal of the flip-flop is driven based on the falling edge, that is, the first flip-flop 301 is driven based on the falling edge of the indication signal CLKx output by the NAND logic circuit 203. Moreover, the indication signal CLKx output by the NAND logic circuit 203 and the delay clock CBR_CLKEnd are mutually inverted signals, which can be regarded as the first flip-flop 301 being driven based on the rising edge of the delay clock CBR_CLKEnd. Since the output terminal Q of the first flip-flop 301 is connected to the input terminal of the second flip-flop 302, and the inverted output terminal / Q of the second flip-flop 302 is connected to the input terminal D of the first flip-flop 301, the first flip-flop 301 and the second flip-flop 302 can be regarded as controlling the output signal to be flipped based on the valid signal of the clock terminal or the inverted clock terminal. Referring to Figures 9 and 10, the first flip-flop 301 in the first-stage counting unit 201 flips the address signal OUT0 based on the falling edge of the indication signal CLK0 to form the address RA to be refreshed <n:0>It should be noted that the data outputted to the first output terminal OUT by the first stage counting unit 201 is OUT0, the data outputted to the first output terminal OUT by the second stage counting unit 201 is OUT1, ..., the data outputted to the first output terminal OUT by the n+1th stage counting unit 201 is OUTn.

[0079] Regarding the second flip-flop 302, the clock terminal of the second flip-flop 302 is connected to the first clock terminal CNTCLK to receive the count clock CBR_CLK. The clock terminal of the flip-flop is driven based on the rising edge. The second flip-flop 302 can be regarded as flipping the output signal CAOUTx based on the rising edge of the count clock CBR_CLK. Referring to Figures 9 and 10, the second flip-flop 302 in the first-stage counting unit 201 flips the output signal based on the rising edge of the count clock CBR_CLK to generate the carry signal CAOUT0. It should be noted that the carry signal output by the first-stage counting unit 201 is CAOUT0, the carry signal output by the second-stage counting unit 201 is CAOUT1, and the carry signal output by the (n+1)th-stage counting unit 201 is CAOUTn.

[0080] For non-first-stage counting units 201, the control terminal CAIN of the counting unit 201 is connected to the second output terminal CAOUT of the previous-stage counting unit 201 to receive the carry signal CAOUTx. Based on the operating principle of the NAND logic circuit 203, when the carry signal generated by the previous-stage counting unit 201 is high, an inverted pulse of the delay clock CNTCLKEnd is generated accordingly. As shown in Figure 10, the NAND logic circuit 203 in the second-stage counting unit 201 generates the indication signal CLK1 based on the carry signal CAOUT0 generated by the first-stage counting unit 201 and the delay clock CNTCLKEnd. The first flip-flop 301 in the second-stage counting unit 201 flips the address signal OUT1 based on the falling edge of the indication signal CLK1.

[0081] For each counting unit 201, the reset terminal RST of the first flip-flop 301 and the set terminal SET of the second flip-flop 302 are connected to the reset control terminal CNTRST. The reset control terminal CNTRST of the first-stage counting unit 201 is used to receive both the reset signal CBR_RST and the termination signal SrefAbortRst. The reset control terminals CNTRST of the other counting units 201 are used only to receive the reset signal CBR_RST. When the termination signal SrefAbortRst is asserted, the address signal OUT0 outputted by the first flip-flop 301 in the first-stage counting unit 201 is reset to 0, and the carry signal CAOUT0 outputted by the second flip-flop 302 in the first-stage counting unit 201 is set to 1. However, due to the structural configuration of the counting unit 201, the carry signal set to 1 does not affect the value of the indicator signal CLKx in the subsequent counting unit 201. Referring to Figure 10, when the first-stage counting unit 201 changes the output carry signal CAOUT0 to 1 based on the termination signal SrefAbortRst, the indicator signal CLK1 in the second-stage counting unit 201 does not jump, and the counting circuit 101 does not continue counting, only resetting the least significant bit. In other words, during the refresh process of the to-be-refreshed address 3, the termination signal SrefAbortRst is valid, the to-be-refreshed address is reset to 2, and the subsequent refresh process begins based on the to-be-refreshed address 2. The refresh process continues, and no refresh is missed.

[0082] It is not difficult to find that this embodiment can be implemented in conjunction with the refresh control structure provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment and will not be repeated here to reduce repetition.

[0083] Another embodiment of the present disclosure provides a memory, which includes a plurality of memory blocks, each of which includes the refresh control structure provided by the above embodiment, and performs a self-refresh function based on the refresh control structure.

[0084] Among them, when the counting circuit resets the lowest bit of the address to be refreshed, the second lowest bit of the address to be refreshed remains unchanged, avoiding the counting process of the address to be refreshed due to the carry signal during the process of resetting the lowest bit, thereby avoiding the problem of missed refresh of the memory.

[0085] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0086] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A refresh control structure is provided in a storage block, characterized in that, Including: A processing circuit (102), configured to perform a refresh on a to-be-refreshed address based on a refresh window; A counting circuit (101), configured to generate the to-be-refreshed address and control the generated to-be-refreshed address to increment by 1 based on a counting clock; The counting circuit is further configured to reset the least significant bit of the to-be-refreshed address based on a termination signal, and during the process of resetting the least significant bit of the to-be-refreshed address, the second least significant bit of the to-be-refreshed address remains unchanged.

2. The refresh control structure according to claim 1, wherein The to-be-refreshed address is an n-bit binary signal, and the counting circuit includes n cascaded counting units (201), and each counting unit includes: A first clock terminal (CNTCLK), for receiving the counting clock; A second clock terminal (CNTEnd), for receiving a delayed clock, and the delayed clock is a delayed signal of the counting clock; A reset control terminal (CNTRST), for receiving a reset signal, and the reset control terminal of the first-stage counting unit is further used for receiving the termination signal; A first output terminal (OUT), for generating an address signal, and the n address signals generated by the n counting units constitute the to-be-refreshed address; A second output terminal (CAOUT), connected to the control terminal of the next-stage counting unit, for generating a carry signal, wherein the control terminal of the first-stage counting unit receives a high level; The counting unit is configured to, when the signal input to the control terminal is valid, flip the address signal based on the delayed clock and flip the carry signal based on the counting clock.

3. The refresh control structure according to claim 2, wherein The counting unit includes: A NAND logic circuit (203), with a first input terminal connected to the control terminal and a second input terminal for receiving the delayed clock; A first flip-flop (301), with an inverted clock terminal connected to the output terminal of the NAND logic circuit, an output terminal connected to the first output terminal, and a reset terminal connected to the reset control terminal; A second flip-flop (302), with a clock terminal for receiving the counting clock, an input terminal connected to the output terminal of the first flip-flop, an inverted output terminal connected to the input terminal of the first flip-flop, and a set terminal connected to the reset control terminal.

4. The refresh control structure according to claim 3, wherein The counting unit further includes: an AND logic circuit (204), with a first input terminal connected to the output terminal of the second flip-flop, a second input terminal connected to the control terminal, and an output terminal connected to the second output terminal.

5. The refresh control structure according to claim 3, wherein It further includes: A delay unit (303), for generating the delayed clock based on the counting clock.

6. The refresh control structure according to claim 5, characterized in that, The delay unit includes: A NOT logic circuit (310), with an input terminal for receiving the counting clock; A delay circuit (320), with an input terminal connected to the output terminal of the NOT logic circuit; A NOR logic circuit (330), with a first input terminal for receiving the counting clock, a second input terminal connected to the output terminal of the delay circuit, and an output terminal for outputting the delayed clock.

7. The refresh control structure according to claim 5, characterized in that, The delay unit includes: a delay circuit, with an input terminal for receiving the counting clock and an output terminal for outputting the delayed clock.

8. The refresh control structure according to claim 1, wherein The counting circuit is configured to reset the to-be-refreshed address based on a reset signal.

9. A refresh control method, characterized in that, Applied to the self-refresh mode of a memory, including: Obtaining a to-be-refreshed address and performing a refresh on the to-be-refreshed address based on a refresh window; After the refresh is completed, control the address to be refreshed to increment by 1 based on the counting clock; wherein, the refresh window opened based on the same refresh command is an even number; During the execution of the refresh, if a termination signal is received, adjust the address to be refreshed based on the refresh control structure according to any one of claims 1 to 8.

10. A memory, characterized in that, The memory is provided with a plurality of memory blocks, and each of the plurality of memory blocks includes the refresh control structure according to any one of claims 1 to 8, and executes the self-refresh function based on the refresh control structure.

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