Solar cell and manufacturing method therefor

Abstract

The present application relates to the technical field of photovoltaics, and discloses a solar cell and a manufacturing method therefor, for use in increasing the conductivity and the effective doping concentration of a first part, covering tops of at least some of pyramid-like structures, of a first semiconductor layer, thereby reducing the transmission loss of transmitting carriers collected in the first semiconductor layer to a conductive material. The solar cell comprises a semiconductor substrate and a first semiconductor layer. The semiconductor substrate has a first surface and a second surface which are opposite to each other. At least one of the first surface and the second surface is a target surface. At least partial surface of the target surface is a textured surface, and a plurality of pyramid-like structures are formed on the textured surface. The plurality of pyramid-like structures comprise a plurality of first pyramid-like structures. The first semiconductor layer is provided on the textured surface. The material of the first semiconductor layer includes amorphous silicon and / or nano-crystalline silicon. The first semiconductor layer comprises a first part covering the tops of the first pyramid-like structures and a second part covering the bases of the first pyramid-like structures. The crystallization degree of the first part is greater than that of the second part.

Description

Solar cell and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of the Chinese patent application filed with the Patent Office of China on January 23, 2024, with application number 202410092536.4, and with the invention name “A solar cell, its preparation method and battery assembly”, the priority of the Chinese patent application filed with the Patent Office of China on August 16, 2024, with application number 202411131776.7, and with the invention name “A solar cell and its manufacturing method”, and the priority of the Chinese patent application filed with the Patent Office of China on September 3, 2024, with application number 202411230518.4, and with the invention name “A solar cell and its manufacturing method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a method for manufacturing the same. Background Art

[0004] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the solar cell's semiconductor pn junction, forming new hole-electron pairs. Under the influence of the pn junction's built-in electric field, photogenerated holes flow to the p-region and photogenerated electrons flow to the n-region, generating current when the circuit is connected. Amorphous silicon and nanocrystalline silicon contain hydrogen, which can hydrogenate dangling bonds on the surface of the semiconductor substrate, reducing surface defects and thus having a high passivation effect on the semiconductor substrate. Therefore, when the semiconductor layer in a solar cell is made of amorphous silicon and / or nanocrystalline silicon, it helps reduce the carrier recombination rate.

[0005] However, in existing solar cells, the contact resistance between the semiconductor layer including amorphous silicon and / or nanocrystalline silicon and the conductive material (transparent conductive layer or electrode) is large, and the transmission loss is high, which is not conducive to improving the working efficiency of the solar cell. Summary of the Invention

[0006] The purpose of the present application is to provide a solar cell and a method for manufacturing the same, which are used to increase the conductivity and effective doping concentration of the first part of the first semiconductor layer covering the top of the first type of pyramid, reduce the contact resistance between the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and thereby help reduce the transmission loss of carriers collected in the first semiconductor layer to the conductive material, thereby improving the working efficiency of the solar cell.

[0007] In order to achieve the above-mentioned objectives, in a first aspect, the present application provides a solar cell comprising: a semiconductor substrate and a first semiconductor layer. The semiconductor substrate comprises a first surface and a second surface opposite to each other. At least one of the first surface and the second surface is a target surface. At least a portion of the surface of the target surface is a velvet surface, and a plurality of pyramid-like layers are formed on the velvet surface. The plurality of pyramid-like layers comprise a plurality of first-type pyramids, the first semiconductor layer is disposed on the velvet surface, and the material of the first semiconductor layer comprises amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer comprises a first portion covering the top of the first-type pyramid and a second portion covering the base of the first-type pyramid. The degree of crystallization of the first portion is greater than that of the second portion.

[0008] In the case of adopting the above technical solution, compared with the surface of the first semiconductor layer facing away from the semiconductor substrate being a plane, when the first semiconductor layer is arranged on the velvet surface, the side of the first semiconductor layer facing away from the semiconductor substrate has a undulating morphology substantially the same as the velvet surface. At this time, the first semiconductor layer has a larger specific surface area, which can increase the contact area between the first semiconductor layer and the conductive material (transparent conductive layer or electrode, etc.), and reduce the transmission loss of the carriers collected in the first semiconductor layer to the conductive material. In addition, it can be understood that, under the same conditions as other factors, when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of amorphous silicon material is presented. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be greater. In addition, in the actual manufacturing process, the semiconductor layer is generally crystallized at a relatively high temperature to improve the degree of crystallization of the semiconductor layer; and the semiconductor layer with smaller grains is more sensitive to temperature, and the effective doping concentration of the semiconductor layer obtained at a relatively low doping temperature is also relatively low. Therefore, compared with the case where the degree of crystallization of the portion of the first semiconductor layer covering the top of the pyramid-like layer and the degree of crystallization of the portion of the first semiconductor layer covering the base of the pyramid-like layer are both low, when in the solar cell provided by the present application, the degree of crystallization of the first portion of the first semiconductor layer covering the top of the first-type pyramid is greater than the degree of crystallization of the second portion of the first semiconductor layer covering the base of the first-type pyramid, it is beneficial to reduce the number of interfaces between the grains in the first portion of the first semiconductor layer covering the top of the first-type pyramid, thereby reducing the transmission resistance of the first portion; and, at this time, the first portion included in the first semiconductor layer can be crystallized at a relatively high temperature, so that more dopants can be doped into the first portion included in the first semiconductor layer, thereby increasing the effective doping concentration of the first portion included in the first semiconductor layer, improving the conductivity of the first portion included in the first semiconductor layer, reducing the contact resistance between the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and thus helping to reduce the transmission loss of carriers collected in the first semiconductor layer to the conductive material. At the same time, in the first semiconductor layer, at least the second portion of the first semiconductor layer covering the base of the first-type pyramid has a relatively low degree of crystallization. Under the condition of crystallization treatment at a reduced temperature, at least the second portion has a relatively high hydrogen content, so that at least the second portion has a high passivation effect on the velvet surface, reducing the number of defects in the velvet surface and improving the operating efficiency of the solar cell. In short, the treatment at the top of the first-type pyramid to form a first portion with a high degree of crystallization can ensure that the contact resistance between the conductive material and the first semiconductor layer is reduced. However, at the same time, the first portion with a high degree of crystallization cannot be too large. That is, the second portion at the base of the first-type pyramid has a low degree of crystallization, which can ensure the passivation effect of the first semiconductor layer, thus taking into account the balance between contact resistance and passivation effect.

[0009] As a possible implementation solution, in the first semiconductor layer, the material of the first portion includes nanocrystalline silicon; and the material of the second portion includes amorphous silicon.

[0010] When the above technical solution is adopted, under the same conditions as other factors, the amorphous silicon material has a lower degree of crystallization than nanocrystalline silicon, and the amorphous silicon material is less affected by heat during the crystallization process, so that the hydrogen content in the amorphous silicon material is relatively high. Based on this, when the material of the second part in the first semiconductor layer includes amorphous silicon, it is beneficial to make the second part contain more hydrogen, which is beneficial to hydrogenate the dangling bonds on the surface of the semiconductor substrate and reduce surface defects, thereby having a higher passivation effect on the semiconductor substrate. When the material of the first part in the first semiconductor layer includes nanocrystalline silicon, it is beneficial to make at least the first part with a greater degree of crystallization in the first semiconductor layer have a higher conductivity and effective doping concentration, reduce the contact resistance between the first part of the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and thus help reduce the transmission loss of carriers collected in the first semiconductor layer to the conductive material.

[0011] As a possible implementation solution, the first portion of the first semiconductor layer contains crystal grains, and the maximum size of the crystal grains is smaller than the thickness of the first portion.

[0012] When the above technical solution is adopted, in an actual manufacturing process, the larger the grain size in the first portion of the first semiconductor layer, the higher the temperature during the crystallization treatment of the first portion of the first semiconductor layer. The higher the treatment temperature, the greater the amount of hydrogen released from the first portion of the first semiconductor layer, resulting in a reduced passivation effect of the first portion of the first semiconductor layer on the semiconductor substrate. Therefore, compared with a case where the maximum size of the grains in the first portion of the first semiconductor layer is equal to the thickness of the first portion, when the maximum size of the grains in the first portion of the first semiconductor layer is less than the thickness of the first portion, the corresponding crystallization temperature of the first semiconductor layer is lower. This is beneficial for ensuring that the first portion of the first semiconductor layer has a higher conductivity and effective doping concentration, reducing the transmission loss between the first portion of the first semiconductor layer and the conductive material, while also ensuring that the portion of the first semiconductor layer where the grains are not extended has a higher passivation effect on the semiconductor substrate. This helps to achieve a balance between the passivation effect and transmission loss of the first semiconductor layer, further improving the performance of the solar cell.

[0013] As a possible implementation solution, the crystallization depth of the first portion of the first semiconductor layer is less than the thickness of the first portion. The beneficial effects and application principles of this case can be referred to the beneficial effects and application principles of the maximum size of the grains in the first portion of the first semiconductor layer being less than the thickness of the first portion described above, and will not be repeated here.

[0014] As a possible implementation solution, the crystallization depth of the first portion of the first semiconductor layer gradually decreases along the inclination direction of the pyramid-like side and in the direction close to the pyramid-like base. In this case, when performing a crystallization treatment on at least a portion of the first semiconductor layer, the treatment temperature of each portion of the first semiconductor layer covering the pyramid-like layer gradually decreases along the inclination direction of the pyramid-like side and in the direction close to the pyramid-like base. While ensuring that the first portion of the first semiconductor layer has a higher conductivity and effective doping concentration, it is beneficial to reduce the impact of the higher crystallization temperature on the remaining portions of the first semiconductor layer, ensuring that the remaining portions of the first semiconductor layer have a higher hydrogen content, thereby ensuring that the remaining portions of the first semiconductor layer have a higher passivation effect on the semiconductor substrate.

[0015] As a possible implementation solution, along the inclination direction of the pyramid-like side, the ratio of the maximum extension length of the first part on the side of the first-type pyramid located below the first part to the length of the side of the first-type pyramid is less than or equal to 0.3.

[0016] When the above technical solution is adopted, as described above, although the first portion included in the first semiconductor layer can reduce the transmission loss between the first semiconductor layer and the conductive material, the hydrogen content in the first portion of the first semiconductor layer is relatively low, so that the passivation effect of the first portion on the semiconductor substrate is relatively weak (compared with the second portion); based on this, when the ratio between the maximum extension length of the first portion of the first semiconductor layer on the side of the first-class pyramid located below it and the length of the side of the first-class pyramid is less than or equal to 0.3 along the inclination direction of the side of the first-class pyramid, the portion of the first semiconductor layer with a higher passivation effect (including the second portion) can have a larger coverage area on the velvet surface, which can further reduce the number of surface defects on the velvet surface. In addition, in the actual manufacturing process, the heating rate of the top of the pyramid is faster than the heating rate of its own base, and it is easier to accumulate more heat at its top to make its own crystallization higher. Based on this, when the ratio of the maximum extension length of the first part of the first semiconductor layer on the side of the first type of pyramid located below itself to the length of the side of the first type of pyramid is less than or equal to 0.3 along the inclination direction of the side of the first type of pyramid, it can prevent the first semiconductor layer from overheating at the top of the first type of pyramid due to the large extension length of the first part of the first semiconductor layer above the first type of pyramid, thereby affecting its own passivation effect, ensuring that the first part of the first semiconductor layer at the top of the first type of pyramid also has a certain passivation effect, thereby further improving the working efficiency of the solar cell.

[0017] As a possible implementation scheme, the thickness of the first semiconductor layer is greater than or equal to 10nm, and / or the thickness of the first semiconductor layer is less than or equal to 45nm. In this case, the lower limit and / or upper limit of the thickness of the first semiconductor layer whose material includes amorphous silicon and / or nanocrystalline silicon is larger, which is conducive to reducing the thermal impact of heat on the semiconductor substrate through the first semiconductor layer with a thicker thickness, preventing thermal damage to the semiconductor substrate during the crystallization process of at least part of the first semiconductor layer, and ensuring that the solar cell has a higher yield. In addition, the first semiconductor layer with a thicker thickness has a higher passivation effect, which can further reduce the carrier recombination rate at the velvet surface and further improve the working efficiency of the solar cell.

[0018] As one possible implementation, the solar cell further includes a transparent conductive layer that covers at least the side of the first semiconductor layer facing away from the semiconductor substrate. In this case, the transparent conductive layer has high conductivity and can promptly conduct carriers collected by the first semiconductor layer, thereby reducing the carrier recombination rate.

[0019] As a possible implementation, the quasi-pyramid can be a pyramid with sharp apex angles; alternatively, the quasi-pyramid can be a pyramid with rounded chamfers; or alternatively, the quasi-pyramid can be a pyramid with flattened apex angles. In this case, the quasi-pyramid can have at least the three aforementioned examples, which helps improve the applicability of the solar cell provided in this application in different application scenarios. Furthermore, there is no need to strictly control manufacturing precision to obtain a quasi-pyramid with a single morphology, reducing process difficulty and helping to improve the yield of the solar cell.

[0020] As a possible implementation solution, the pyramid-like surface is flat. In this case, compared with an uneven pyramid-like surface, when the pyramid-like surface is flat, the pyramid-like surface has a relatively low degree of undulation, which is conducive to making the first semiconductor layer deposited on the velvet surface have a greater thickness, further improving the passivation effect of the first semiconductor layer.

[0021] As a possible implementation, the surface roughness of the first portion of the first semiconductor layer is greater than the surface roughness of the second portion. In this case, the larger specific surface area of ​​the first portion of the first semiconductor layer increases the contact area between the first portion and the conductive material, reduces the contact resistance between the first portion and the conductive material, further reduces the transmission loss of carriers transmitted from the first semiconductor layer to the conductive material, and further improves the operating efficiency of the solar cell. Furthermore, in the actual manufacturing process, laser irradiation or high-temperature annealing is required to achieve crystallization modification of a portion of the first semiconductor layer. The heating rate of the pyramid-like top is faster than that of the base, making crystallization modification easier to achieve. Furthermore, changes in the surface roughness of the first portion are related to changes in the degree of crystallization of the first portion and hydrogen release within the first portion. Therefore, when the surface roughness of the first portion is greater than that of the second portion, there is no need to ensure that the second portion of the first semiconductor layer covering the base of the first pyramid also has a larger surface roughness, which would cause dehydrogenation due to the longer heating time of various portions of the first semiconductor layer, thereby ensuring a high passivation effect for the first semiconductor layer.

[0022] As a possible implementation, the first semiconductor layer includes: a first intrinsic semiconductor layer and a first doped semiconductor layer. The first doped semiconductor layer is disposed on a side of the first intrinsic semiconductor layer facing away from the semiconductor substrate. Furthermore, along a direction approaching the velvet surface, the maximum size of crystal grains contained in a first portion of the first semiconductor layer is less than or equal to the thickness of the first doped semiconductor layer; and / or the crystallization depth of the first portion of the first semiconductor layer is less than or equal to the thickness of the first doped semiconductor layer.

[0023] When the above technical solution is adopted, the first intrinsic semiconductor layer and the first doped semiconductor layer can form a selective contact structure, which has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate in the area where the first semiconductor layer is formed on the semiconductor substrate, and further improve the photoelectric conversion efficiency of the solar cell. Secondly, along the direction close to the velvet surface, the maximum size of the grains contained in the first part of the first semiconductor layer is less than or equal to the thickness of the first doped semiconductor layer. At this time, the part of the first intrinsic semiconductor layer corresponding to the largest grain still has a passivation effect on the semiconductor substrate, which can further reduce the carrier recombination rate. Secondly, the beneficial effects and application principles of the crystallization depth of the first part of the first semiconductor layer being less than or equal to the thickness of the first doped semiconductor layer can be referred to in the previous text and will not be repeated here.

[0024] As a possible implementation, the solar cell further includes a second semiconductor layer of opposite conductivity type to the first semiconductor layer. The second semiconductor layer and the first semiconductor layer are disposed on the same surface of the semiconductor substrate, with the first semiconductor layer extending over a portion of the second semiconductor layer facing away from the semiconductor substrate. Alternatively, the second semiconductor layer is disposed on the second surface of the semiconductor substrate, and the material of the second semiconductor layer comprises at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0025] When the above-mentioned technical solution is adopted, when the second semiconductor layer and the first semiconductor layer are arranged on the same surface of the semiconductor substrate, the solar cell provided by this application is a back-contact cell, which can reduce the impact of the light-shielding electrode structure on the light utilization rate on the light-facing side, further improving the photoelectric conversion efficiency of the solar cell. In addition, when the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, the material of the second semiconductor layer has multiple possible examples, which is conducive to improving the applicability of the solar cell provided by this application in different application scenarios.

[0026] In a second aspect, the present application provides a method for manufacturing a solar cell, which comprises: providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. At least a portion of the surface of the target surface is a velvet surface. A plurality of pyramid-like layers are formed on the velvet surface, and the plurality of pyramid-like layers include a plurality of first-type pyramids. Next, a first semiconductor layer is formed on the velvet surface, and the material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer includes a first portion covering the top of the first-type pyramid and a second portion covering the base of the first-type pyramid; the degree of crystallization of the first portion is greater than the degree of crystallization of the second portion.

[0027] As a possible implementation solution, a laser irradiation process is used to crystallize at least a portion of the first semiconductor layer, so that the degree of crystallization of the first portion of the first semiconductor layer is greater than that of the second portion of the first semiconductor layer.

[0028] As a possible implementation scheme, the wavelength of the laser used in the laser irradiation process is greater than or equal to 325nm and less than or equal to 532nm; and / or the pulse width of the laser irradiation process is in the picosecond or nanosecond level; and / or the laser energy density of the laser irradiation process is greater than or equal to 200mJ / cm 2 , and less than or equal to 6000mJ / cm 2 .

[0029] The beneficial effects of the second aspect and its various implementations in this application can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0031] FIG1 is a schematic longitudinal cross-sectional view of a first structure of a solar cell provided in an embodiment of the present application;

[0032] FIG2 is a SEM image of a partial structure of a single pyramid-like structure in a solar cell provided in an embodiment of the present application;

[0033] FIG3 is a partially enlarged TEM image of the area framed by the bold rectangular solid line in FIG2 at the first magnification;

[0034] FIG4 is a partially enlarged TEM image of the area framed by the bold rectangular solid line in FIG2 at a second magnification;

[0035] FIG5 is a partial enlarged TEM image of the area framed by the rectangular dashed line in FIG2 ;

[0036] FIG6 is a partial enlarged TEM image of the area framed by the thinner rectangular dashed line in FIG2 ;

[0037] FIG7 is a SEM image of a partial structure of multiple pyramid-like structures in a solar cell provided by an embodiment of the present application;

[0038] FIG8 is a schematic longitudinal cross-sectional view of a second structure of a solar cell provided in an embodiment of the present application;

[0039] FIG9 is a schematic longitudinal cross-sectional view of a third structure of a solar cell provided in an embodiment of the present application;

[0040] FIG10 is a schematic longitudinal cross-sectional view of a fourth structure of a solar cell provided in an embodiment of the present application;

[0041] FIG11 is a schematic longitudinal cross-sectional view of a fifth structure of a solar cell provided in an embodiment of the present application;

[0042] FIG12 is a schematic longitudinal cross-sectional view of a sixth structure of a solar cell provided in an embodiment of the present application;

[0043] FIG13 is a schematic diagram showing a pyramid-like morphology in a solar cell provided by an embodiment of the present application;

[0044] FIG14 is a schematic diagram showing another pyramid-like morphology in a solar cell provided by an embodiment of the present application;

[0045] FIG15 is a schematic longitudinal cross-sectional view of a seventh structure of a solar cell provided in an embodiment of the present application;

[0046] FIG16 is a schematic longitudinal cross-sectional view of an eighth structure of a solar cell provided in an embodiment of the present application;

[0047] FIG17 is a schematic longitudinal cross-sectional view of a ninth structure of a solar cell provided in an embodiment of the present application;

[0048] FIG18 is a schematic longitudinal cross-sectional view of a tenth structure of a solar cell provided in an embodiment of the present application;

[0049] FIG19 is a schematic longitudinal cross-sectional view of an eleventh structure of a solar cell provided in an embodiment of the present application;

[0050] FIG20 is a schematic longitudinal cross-sectional view of a twelfth structure of a solar cell provided in an embodiment of the present application;

[0051] FIG21 is a schematic diagram of a partial structure of a solar cell according to an embodiment of the present application.

[0052] Figure numerals: 11 is a semiconductor substrate, 12 is a target surface, 13 is a pyramid-like layer, 14 is a first semiconductor layer, 15 is a first part, 16 is a second part, 17 is a transparent conductive layer, 18 is a first intrinsic semiconductor layer, 19 is a first doped semiconductor layer, 20 is a second semiconductor layer, 21 is an insulating layer, 22 is an interface passivation layer, 23 is a second doped semiconductor layer, 141 is a first electrode, 142 is a second electrode, 152 is a first crystallized region, 155 is a second crystallized region, 156 is a first amorphous region A, 157 is a second amorphous region B, and 158 is a first amorphous region B. DETAILED DESCRIPTION

[0053] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion in the concepts of the present application.

[0054] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present application. These figures are not drawn to scale, and certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0055] In the context of this application, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application more clearly understood, the application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain this application and are not intended to limit this application.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0057] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0058] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the solar cell's semiconductor pn junction, forming new hole-electron pairs. Under the influence of the pn junction's built-in electric field, photogenerated holes flow to the p-region and photogenerated electrons flow to the n-region, generating current when the circuit is connected. Amorphous silicon and nanocrystalline silicon contain hydrogen, which can hydrogenate dangling bonds on the surface of the semiconductor substrate, reducing surface defects and thus having a high passivation effect on the semiconductor substrate. Therefore, when the semiconductor layer in a solar cell is made of amorphous silicon and / or nanocrystalline silicon, it helps reduce the carrier recombination rate.

[0059] However, compared with semiconductor layers with a higher degree of crystallization such as polycrystalline silicon or single crystal silicon, the effective doping concentration of semiconductor layers made of amorphous silicon and / or nanocrystalline silicon is lower, resulting in poor conductivity of semiconductor layers made of amorphous silicon and / or nanocrystalline silicon in existing solar cells, which in turn leads to high transmission loss between the semiconductor layers made of amorphous silicon and / or nanocrystalline silicon and the conductive material (transparent conductive layer or electrode), which is not conducive to improving the working efficiency of solar cells.

[0060] To address the above technical issues, in a first aspect, embodiments of the present application provide a solar cell. As shown in Figures 1 to 7, the solar cell comprises a semiconductor substrate 11 and a first semiconductor layer 14. The semiconductor substrate 11 includes a first and a second opposing surface. At least one of the first and second surfaces is a target surface 12. At least a portion of the target surface 12 is a velvet surface, on which a plurality of quasi-pyramids 13 are formed. The quasi-pyramids 13 include a plurality of first-type pyramids. A first semiconductor layer 14 is disposed on the velvet surface. The material of the first semiconductor layer 14 comprises amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer 14 comprises a first portion 15 covering the top of the first-type pyramids and a second portion 16 covering the base of the first-type pyramids. The degree of crystallization of the first portion 15 is greater than that of the second portion 16. The number of the first-type pyramids can be a fraction of the total number of quasi-pyramids 13, for example, 70%, 50%, 40%, etc., and can be appropriately set based on the thickness of the first semiconductor layer and laser conditions.

[0061] As shown in Figures 1 to 7 , the first semiconductor layer 14 may have an undulating surface morphology similar to the suede surface. In this case, the side of the first semiconductor layer 14 facing away from the semiconductor substrate 11 has an undulating morphology substantially similar to the suede surface. However, due to the influence of the deposition process, the thickness of the first semiconductor layer 14 at the top of the pyramid-like structure 13 may be different from the thickness of the first semiconductor layer 14 at the base of the pyramid-like structure 13.

[0062] In the case of adopting the above technical solution, as shown in Figures 1 to 7, compared with the surface of the side of the first semiconductor layer 14 away from the semiconductor substrate 11 being a plane, when the first semiconductor layer 14 is arranged on the velvet surface, the side of the first semiconductor layer 14 away from the semiconductor substrate 11 has a undulating morphology substantially the same as the velvet surface, and the first semiconductor layer 14 has a larger specific surface area, which can increase the contact area between the first semiconductor layer 14 and the conductive material (transparent conductive layer or electrode, etc.), and reduce the transmission loss of the carriers collected in the first semiconductor layer 14 to the conductive material. In addition, it can be understood that, when other factors are the same, the smaller the degree of crystallization of the semiconductor layer, the smaller the grains in the semiconductor layer, and even the disorder of the amorphous silicon material is presented. The smaller the grains in the semiconductor layer, the more interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be greater. The greater the degree of crystallization referred to in the embodiments of the present application can refer to a greater crystallization rate, a larger grain size and / or a greater number of grains. For example, when the first semiconductor layer is a nanocrystalline silicon layer (this nanocrystalline silicon layer generally still contains some amorphous silicon, which is difficult to avoid, but the content of the amorphous silicon is relatively low, as is known in the art), the first portion with a higher degree of crystallization has a larger crystallization rate and grain size than the second portion. When the first semiconductor layer is amorphous silicon (the amorphous silicon may contain a small amount of nanocrystalline silicon, but the content of the nanocrystalline silicon is very small, for example, less than 5%, as is known in the art), the first portion with a higher degree of crystallization will generate lattice-ordered grains within it, and its degree of crystallization will increase, while the second portion with a lower degree of crystallization will still be amorphous silicon material and will not be subjected to the generation of grains after laser treatment or the like.

[0063] Moreover, in the actual manufacturing process, the semiconductor layer is generally crystallized at a relatively high temperature to improve the degree of crystallization of the semiconductor layer; while the semiconductor layer with smaller grains is more sensitive to temperature, and the effective doping concentration of the semiconductor layer obtained at a relatively low doping temperature is also relatively low. Therefore, compared with the case where the degree of crystallization of the portion of the first semiconductor layer covering the top of the pyramid-like layer and the degree of crystallization of the portion of the first semiconductor layer covering the base of the pyramid-like layer are both low, as shown in Figures 1 to 7, when the degree of crystallization of the first portion 15 of the first semiconductor layer 14 in the solar cell provided in the embodiment of the present application (as can be seen from Figures 2 to 6, the first portion 15 of the first semiconductor layer 14 contains grains, that is, at least part of it has a relatively regular lattice distribution) is greater than the degree of crystallization of the second portion 16 of the first semiconductor layer 14, it is beneficial to reduce the number of interfaces between the grains in the first portion 15 of the first semiconductor layer 14. The amount of dopant is reduced, thereby reducing the transmission resistance of the first portion 15 of the first semiconductor layer 14. Furthermore, the first portion 15 of the first semiconductor layer 14 can be crystallized at a relatively high temperature, allowing more dopants to be doped into the first portion 15 of the first semiconductor layer 14, thereby increasing the effective doping concentration of the first portion 15 of the first semiconductor layer 14, improving the conductivity of the first portion 15 of the first semiconductor layer 14, and reducing the contact resistance between the first semiconductor layer 14 and the conductive material (transparent conductive layer or electrode), thereby reducing the transmission loss of carriers collected in the first semiconductor layer 14 to the conductive material. At the same time, in the first semiconductor layer 14, the second portion 16 has a relatively low degree of crystallization. Under the crystallization treatment at a lower temperature, at least the second portion 16 of the first semiconductor layer 14 has a relatively high hydrogen content, so that at least the second portion 16 of the first semiconductor layer 14 has a high passivation effect on the velvet surface, reducing the number of defects in the velvet surface and improving the operating efficiency of the solar cell. In short, forming a first portion 15 with a higher degree of crystallization at the top of the first-type pyramid can ensure that the contact resistance between the conductive material and the first semiconductor layer 14 is reduced. However, at the same time, the first portion 15 with a higher degree of crystallization cannot be too large. In other words, the second portion 16 at the base of the first-type pyramid has a lower degree of crystallization, which can ensure the passivation effect of the first semiconductor layer 14, thus achieving a balance between contact resistance and passivation effect. As for the boundary between the first portion 15 and the second portion 16 in the first semiconductor layer 14, Figure 6 shows that the portion of the first semiconductor layer 14 near the top of the first-type pyramid, with a larger grain size and / or crystallization depth than the first semiconductor layer 14, and distributed above the rest of the first-type pyramid is the first portion 15. The edge contour of this first portion 15 is the boundary between the first portion 15 and the second portion 16.

[0064] In actual applications, the present invention does not specifically limit the material and conductivity type of the semiconductor substrate. For example, the semiconductor substrate may be a silicon substrate. Alternatively, the semiconductor substrate may be a substrate made of any semiconductor material, such as a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0065] Secondly, the semiconductor substrate has a first surface and a second surface that are opposite to each other. The first surface of the semiconductor substrate can correspond to the light-facing surface of the solar cell, in which case the second surface of the semiconductor substrate corresponds to the backlight surface of the solar cell; alternatively, the first surface of the semiconductor substrate can correspond to the backlight surface of the solar cell, in which case the second surface of the semiconductor substrate corresponds to the light-facing surface of the solar cell. In addition, because the first semiconductor layer is formed on the velvet surface of the target surface, whether the first and second surfaces of the semiconductor substrate are the target surfaces can be determined based on the requirements for the formation position of the first semiconductor layer in the actual application scenario, and no specific limitation is made here.

[0066] For example, as shown in Figures 1, 8, and 9, when the solar cell provided in the embodiments of the present application is a double-sided contact cell, of the first and second surfaces, only the first surface may be the target surface 12, or only the second surface may be the target surface 12, or both the first and second surfaces may be the target surfaces 12. It should be noted that, as shown in Figure 9, when both the first and second surfaces are the target surfaces 12, the conductivity types of the two first semiconductor layers 14 formed on the first and second surfaces, respectively, are opposite.

[0067] For example, as shown in FIG10 , when the solar cell provided in an embodiment of the present application is a back-contact cell, one of the first and second surfaces corresponding to the backlight side of the solar cell is the target surface 12. Specifically, when the first surface of the semiconductor substrate 11 corresponds to the backlight side of the solar cell, the first surface is the target surface 12; and when the second surface of the semiconductor substrate 11 corresponds to the backlight side of the solar cell, the second surface is the target surface 12.

[0068] Furthermore, as shown in FIG10 , the surface of target surface 12 may be velvet only in a local area, while the remaining surface may be polished or have an uneven curved surface. Alternatively, as shown in FIG8 and FIG9 , the entire surface of target surface 12 may be velvet. Specifically, the distribution range of the velvet surface on target surface 12 can be determined based on the type of solar cell and the actual application scenario, and is not specifically limited here.

[0069] For example, as shown in Figures 8 and 9 , in the case of a double-sided contact solar cell, the entire target surface 12 may be velvet-finished. Alternatively, as shown in Figure 11 , only a portion of the target surface 12 may be velvet-finished, while the remaining surface of the target surface 12 may be polished or have an uneven curved surface.

[0070] For example, as shown in FIG10 , in the case of a back-contact solar cell, only the surface of the target surface 12 corresponding to the first semiconductor layer 14 may be a velvet surface, while the surface of the remaining target surface 12 may be a polished surface or other morphology. Alternatively, as shown in FIG12 , the entire target surface 12 may be a velvet surface.

[0071] In terms of the setting of the pyramid-like structures, the embodiments of the present application do not specifically limit the morphology, size and distribution of the pyramid-like structures formed on the velvet surface, as long as they can be applied to the solar cells provided in the embodiments of the present application.

[0072] For example, as shown in Figures 11 and 12, the pyramid-like 13 can be a pyramid with a sharp apex; or, as shown in Figure 13, the pyramid-like 13 can also be a pyramid-like 13 with a smooth chamfer; or, as shown in Figure 14, the pyramid-like 13 can also be a pyramid-like 13 with a flattened apex. In this case, the pyramid-like 13 can have at least the three aforementioned examples, which is beneficial to improving the applicability of the solar cell provided by the embodiment of the present application in different application scenarios. In addition, there is no need to strictly control the manufacturing accuracy in order to obtain a pyramid-like 13 with a single morphology, which can reduce the process difficulty and help improve the yield of the solar cell.

[0073] For example, as shown in Figures 11 and 12, the surface of the pyramid-like 13 can also be a plane. In this case, compared with the uneven surface of the pyramid-like surface, when the surface of the pyramid-like 13 is a plane, the surface of the pyramid-like 13 is relatively flat, and the degree of undulation of the pyramid-like 13 on the velvet surface is relatively low, which is conducive to making the first semiconductor layer 14 deposited on the velvet surface have a larger thickness, further improving the first semiconductor layer 14 having a higher passivation effect. Alternatively, as shown in Figures 2 to 4, the surface of the pyramid-like 13 can also have an uneven microstructure, and the position of the microstructure can correspond to the portion of the first semiconductor layer 14 having a greater degree of crystallization.

[0074] For example, the one-dimensional size of the pyramid-like structure (which may be the side length, diagonal length, or height of the base of the pyramid-like structure) may be greater than or equal to 2 μm and less than or equal to 4 μm. For example, the one-dimensional size of the pyramid-like structure may be 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, 3.6 μm, 3.8 μm, or 4 μm. In this case, not only can the presence of the pyramid-like structure increase the contact area between the first semiconductor layer and the conductive material, but it can also provide a certain light-trapping effect on the velvet surface, thereby improving the utilization rate of light by the semiconductor substrate. In addition, it can also prevent the passivation effect of the first semiconductor layer from being affected by excessively high processing temperature due to the small one-dimensional size of the pyramid-like pyramid, which is used to form a first part with a larger degree of crystallization in a fixed range above the top of the first type of pyramid among multiple pyramid-like pyramids; or prevent the extension range of the first part with a larger degree of crystallization in the first semiconductor layer above the top of the first type of pyramid from being larger or the crystallization depth of the first part with a larger degree of crystallization in the first semiconductor layer from being larger under the same processing conditions due to the large one-dimensional size of the first type of pyramid, thereby ensuring that the first semiconductor layer has a higher passivation effect.

[0075] Regarding the distribution of different pyramid-like structures on the velvet surface, it is understood that the distance between the top of a taller pyramid-like structure and its base is greater. Since the base of a pyramid-like structure has a larger contact area with the semiconductor substrate, and the semiconductor substrate has excellent heat dissipation, during the crystallization process of at least a portion of the first semiconductor layer, the top of a taller pyramid-like structure may dissipate less heat after being heated, and thus more easily accumulate heat for crystallization. Furthermore, when using a laser irradiation process to crystallize at least a portion of the first semiconductor layer, the pyramid-like structures reflect laser light, and the reflected laser light is more likely to be concentrated on the top of the taller pyramid-like structure, resulting in a higher degree of heat exposure at the top of the taller pyramid-like structure, making crystallization more likely in the portion of the first semiconductor layer corresponding to the top of the taller pyramid-like structure. Furthermore, when the density of other pyramid-like structures surrounding a single pyramid-like structure is high, the reflected laser light is more likely to be concentrated on the top of that single pyramid-like structure. Based on this, the distribution of different pyramid-like structures on the velvet surface can be determined based on the distribution requirements of the first portion of the first semiconductor layer with a higher degree of crystallization in actual application scenarios, and this is not specifically limited here.

[0076] As for the first semiconductor layer, from the perspective of the film layer structure, as shown in Figures 11 and 12, the first semiconductor layer 14 can be a single-layer structure; in this case, the first semiconductor layer 14 can only include a first doped semiconductor layer. Alternatively, the first semiconductor layer can also be a stacked layer composed of at least two film layers. For example, as shown in Figure 15, the first semiconductor layer 14 can include: a first intrinsic semiconductor layer 18 and a first doped semiconductor layer 19. The first doped semiconductor layer 19 is arranged on the side of the first intrinsic semiconductor layer 18 away from the semiconductor substrate 11. In this case, the first intrinsic semiconductor layer 18 and the first doped semiconductor layer 19 can form a selective contact structure, which has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the area of ​​the semiconductor substrate 11 where the first semiconductor layer 14 is formed, and further improve the photoelectric conversion efficiency of the solar cell.

[0077] From the material perspective, the material of the first semiconductor layer can include only any one of amorphous silicon and nanocrystalline silicon, or can include both amorphous silicon and nanocrystalline silicon, as long as the degree of crystallization of the first portion of the first semiconductor layer covering at least part of the top of the pyramid-like layer is greater than the degree of crystallization of the second portion of the first semiconductor layer covering the base of the pyramid-like layer.

[0078] Among them, it should be noted that, in the first semiconductor layer, the degree of crystallization of the first part that only covers part of the top of the pyramid-like layer is greater than the degree of crystallization of the second part of the first semiconductor layer covering the base of the pyramid-like layer, and the material of the remaining parts of the first semiconductor layer except the first part is all amorphous silicon. Since the pyramid-like layer is a microstructure formed on the velvet surface, when the number of first-class pyramids located below the first part is limited, it can be considered that the material of the first semiconductor layer is only amorphous silicon, and this situation should also be considered to be included in the scope of protection of this application.

[0079] Secondly, when the first semiconductor layer includes at least two materials, the distribution of different materials in the first semiconductor layer can be determined according to the degree of crystallization of different parts of the first semiconductor layer and the actual manufacturing process, and is not specifically limited here.

[0080] For example, as shown in Figures 2 to 6, in the first semiconductor layer 14, the material of the first portion may include nanocrystalline silicon; and / or, in the first semiconductor layer 14, the material of the second portion may include amorphous silicon. In this case, under the same conditions as other factors, the degree of crystallization of amorphous silicon material is lower than that of nanocrystalline silicon, and the amorphous silicon material is less affected by heat during the crystallization process, so that the hydrogen content in the amorphous silicon material is relatively high. Based on this, when the material of the second portion in the first semiconductor layer 14 includes amorphous silicon, it is beneficial for the first semiconductor layer 14, at least the second portion covering the base of the first type of pyramid, to contain more hydrogen, which is beneficial for hydrogenating the dangling bonds on the surface of the semiconductor substrate and reducing surface defects, thereby having a higher passivation effect on the semiconductor substrate. In the first semiconductor layer 14, when the material of at least the first part with a greater degree of crystallization includes nanocrystalline silicon, it is beneficial to make the first part of the first semiconductor layer 14 have higher conductivity and effective doping concentration, reduce the contact resistance between the first part of the first semiconductor layer 14 and the conductive material (transparent conductive layer or electrode), and thus help reduce the transmission loss of carriers collected in the first semiconductor layer 14 to the conductive material.

[0081] For example, as shown in FIG2 , in the first semiconductor layer 14, the material of the portion having a greater degree of crystallization may include nanocrystalline silicon, and the material of the portion having a lesser degree of crystallization (including the second portion 16 of the first semiconductor layer 14) may be amorphous silicon. The beneficial effects and application principles of this case can be referred to the beneficial effects and application principles described above in which the material of at least the portion covering the base of the pyramid-like layer 13 in the first semiconductor layer 14 includes amorphous silicon, and the material of at least the portion having a greater degree of crystallization in the first semiconductor layer 14 includes nanocrystalline silicon, and are not further described here.

[0082] In actual application, the material of the portion of the first semiconductor layer covering the pyramid-like base may be only amorphous silicon. In this case, the material of the first semiconductor layer covering the first portion of the first-type pyramid top may be only nanocrystalline silicon, or may include both nanocrystalline silicon and amorphous silicon. In the actual manufacturing process, the heat exposure of different regions of the first portion of the first semiconductor layer covering the first-type pyramid top gradually decreases in the direction close to the velvet surface. Therefore, the region of the first portion of the first semiconductor layer covering the first-type pyramid top away from the velvet surface is more likely to crystallize. Based on this, when the material of the first semiconductor layer covering the first portion of the first-type pyramid top includes nanocrystalline silicon and amorphous silicon, the region of nanocrystalline silicon material is more likely to be distributed in the region of the first portion of the first semiconductor layer covering the first-type pyramid top away from the velvet surface.

[0083] Alternatively, the material of the portion of the first semiconductor layer covering the base of the pyramid-like portion may include nanocrystalline silicon in addition to amorphous silicon. In this case, the proportion of nanocrystalline silicon in the portion of the first semiconductor layer covering the base of the pyramid-like portion may be less than, equal to, or greater than the proportion of amorphous silicon. In this case, the material of the first semiconductor layer covering the first portion of the top of the first type of pyramid may be only nanocrystalline silicon, or may include both nanocrystalline silicon and amorphous silicon. When the material of the first semiconductor layer covering the first portion of the top of the first type of pyramid includes nanocrystalline silicon and amorphous silicon, the distribution of nanocrystalline silicon and amorphous silicon can be referred to the previous text and will not be repeated here.

[0084] Alternatively, the material of each part of the first semiconductor layer can be nanocrystalline silicon, and the degree of crystallization of the nanocrystalline silicon in the first part of the first semiconductor layer covering the top of the first type of pyramid is greater than the degree of crystallization of the nanocrystalline silicon in the second part of the first semiconductor layer covering the base of the first type of pyramid.

[0085] In terms of the degree of crystallization, the embodiments of the present application do not limit the specific degree of crystallization of the first portion of the first semiconductor layer covering the top of the first-type pyramid and the second portion of the first semiconductor layer covering the base of the first-type pyramid. It is understood that, as described above, when the degree of crystallization of the first portion of the first semiconductor layer covering the top of the first-type pyramid is relatively high, it is beneficial to improve the conductivity of the first portion of the first semiconductor layer covering the top of the first-type pyramid, reduce the contact resistance between the first semiconductor layer and the conductive material (transparent conductive layer or electrode), and thus help reduce the transmission loss of carriers collected in the first semiconductor layer to the conductive material. At the same time, in the first semiconductor layer, at least the second portion has a relatively low degree of crystallization. Under the condition of crystallization treatment at a reduced temperature, at least the second portion has a relatively high hydrogen content, so that at least the second portion has a high passivation effect on the velvet surface. Therefore, the degree of crystallization, grain size, and crystallization depth of different portions of the first semiconductor layer can be determined based on the requirements for the passivation effect and transmission loss of the first semiconductor layer in actual application scenarios.

[0086] In terms of grain size, the first portion of the first semiconductor layer contains grains, and the maximum size of the grains can be equal to the thickness of the first portion. In this case, the first portion of the first semiconductor layer has high conductivity, which can further reduce the transmission loss of carriers collected in the first semiconductor layer to the conductive material.

[0087] Alternatively, as shown in FIG2 , the maximum size of the grains in the first portion of the first semiconductor layer 14 may be smaller than the thickness of the first portion. In this case, during the actual manufacturing process, the larger the grain size in the first portion of the first semiconductor layer 14, the higher the temperature at which the first portion of the first semiconductor layer 14 is crystallized. The higher the treatment temperature, the greater the amount of hydrogen released from the first portion of the first semiconductor layer 14, resulting in a reduced passivation effect of the first portion of the first semiconductor layer 14 on the semiconductor substrate. Therefore, compared to when the grain size in the first portion of the first semiconductor layer 14 is equal to the thickness of the first portion, when the grain size in the first portion of the first semiconductor layer 14 is smaller than the thickness of the first portion, the corresponding crystallization temperature of the first semiconductor layer 14 is lower. This facilitates the first portion of the first semiconductor layer 14 to have a higher conductivity and effective doping concentration, reduces the transmission loss between the first portion of the first semiconductor layer 14 and the conductive material, and enables the portion of the first semiconductor layer 14 where the grains do not extend and grow to have a passivation effect on the semiconductor substrate. This helps to achieve a balance between the passivation effect and transmission loss of the first semiconductor layer 14, further improving the performance of the solar cell.

[0088] The specific value of the grain size in the first semiconductor layer can be determined based on the thickness of the first semiconductor layer in the actual application scenario, as well as the requirements for the passivation effect and transmission loss of the first semiconductor layer, and is not specifically limited here.

[0089] Illustratively, the grain size in the first semiconductor layer may be less than or equal to 50 nm. For example, the grain size in the first semiconductor layer may be 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 30 nm, 40 nm, or 50 nm.

[0090] In terms of crystallization depth, the crystallization depth of the first portion of the first semiconductor layer can be equal to the thickness of the first portion. Alternatively, the crystallization depth of the first portion of the first semiconductor layer can be less than the thickness of the first portion. The beneficial effects and application principles of this case can be referred to the beneficial effects and application principles of the grain size in the first portion of the first semiconductor layer being less than the thickness of the first portion described above, and will not be repeated here.

[0091] The crystallization depths of the first portion of the first semiconductor layer can be the same in each region. Alternatively, as shown in FIG2 , the crystallization depth of the first portion of the first semiconductor layer 14 (i.e., the portion with a greater degree of crystallization) gradually decreases along the side tilt direction of the first-type pyramid and in the direction close to the base of the first-type pyramid. In this case, when at least a portion of the first semiconductor layer 14 is crystallized, the processing temperature of each portion of the first semiconductor layer 14 covering the pyramid-like 13 is gradually reduced along the side tilt direction of the pyramid-like 13 and in the direction close to the base of the pyramid-like 13. While the first portion of the first semiconductor layer 14 with a greater degree of crystallization has a higher conductivity and effective doping concentration, it is beneficial to reduce the impact of the higher temperature of the crystallization process on the remaining portions of the first semiconductor layer 14, ensuring that the remaining portions of the first semiconductor layer 14 have a higher hydrogen content, so that the remaining portions of the first semiconductor layer 14 have a higher passivation effect on the semiconductor substrate 11.

[0092] It can be seen that when the grain size and crystallization depth of the portion of the first semiconductor layer covering the top of the first type of pyramid are different, different beneficial effects correspond to each other. The appropriate grain size and crystallization depth can be obtained by adjusting the manufacturing parameters according to the requirements of the actual application scenario, thereby improving the applicability of the solar cell provided by the embodiment of the present application in different application scenarios. In addition, when the first semiconductor layer includes a first intrinsic passivation layer and a first doped semiconductor layer, and the crystallization depth is less than the thickness of the first portion, along the direction close to the velvet surface, the maximum crystallization depth of the first portion of the first semiconductor layer with a greater degree of crystallization can be less than or equal to the thickness of the first doped semiconductor layer. At this time, the first intrinsic semiconductor layer corresponding to the portion of the first semiconductor layer with a greater degree of crystallization still has a passivation effect on the semiconductor substrate, which can further reduce the carrier recombination rate. Along the direction close to the velvet surface, the grain size of the first portion of the first semiconductor layer with a greater degree of crystallization can be less than or equal to the thickness of the first doped semiconductor layer.

[0093] In addition, in the actual application process, the first portion with a greater degree of crystallization in the first semiconductor layer can be set only above the top of some of the pyramids included in the velvet surface (that is, in this case, the multiple pyramids include not only the first pyramids but also the remaining pyramids), or can be set above the top of all the pyramids included in the velvet surface (that is, in this case, the multiple pyramids only include the first pyramids). The number of first-class pyramids corresponding to the first portion with a greater degree of crystallization in the first semiconductor layer can be determined according to the distribution and height of different pyramids in the actual manufacturing process. In addition, as mentioned above, although the first portion with a greater degree of crystallization in the first semiconductor layer can reduce the transmission loss between the first semiconductor layer and the conductive material, the first portion with a greater degree of crystallization in the first semiconductor layer has a relatively weak passivation effect on the semiconductor substrate (compared to the second portion with a smaller degree of crystallization in the first semiconductor layer). Based on this, the setting range of the first portion with a greater degree of crystallization in the first semiconductor layer at the top of the first-class pyramid can be determined according to the requirements of the passivation effect and transmission loss corresponding to the first semiconductor layer in the actual application scenario, and is not specifically limited here.

[0094] Illustratively, along the inclination direction of the side of the first type of pyramid, the ratio between the maximum extension length of the first part of the first semiconductor layer on the side of the first type of pyramid located below itself and the length of the side of the first type of pyramid can be less than or equal to 0.3. For example, the ratio between the maximum extension length of the first part of the first semiconductor layer on the side of the first type of pyramid located below itself and the length of the side of the first type of pyramid can be 0.05, 0.1, 0.15, 0.2, 0.25 or 0.3, etc. In this case, the first part of the first semiconductor layer can have a larger coverage area on the velvet surface, which can further reduce the number of surface defects of the velvet surface. In addition, in the actual manufacturing process, the heating rate of the top of the pyramid is faster than the heating rate of its own base, and it is easier to accumulate more heat at its own top to make its own crystallization higher. Based on this, when the ratio of the maximum extension length of the first part of the first semiconductor layer on the side of the first type of pyramid located below itself to the length of the side of the first type of pyramid is less than or equal to 0.3 along the inclination direction of the side of the first type of pyramid, it can prevent the first semiconductor layer from overheating in the first part of the top of the first type of pyramid due to the large extension length of the first part of the first semiconductor layer above the first type of pyramid, thereby affecting its own passivation effect, ensuring that the first semiconductor layer in the first part of the top of the first type of pyramid also has a certain passivation effect, thereby further improving the working efficiency of the solar cell.

[0095] In terms of conductivity type, the embodiment of the present application does not limit the conductivity type of the first doped semiconductor layer included in the first semiconductor layer. Specifically, the conductivity type of the first doped semiconductor layer included in the first semiconductor layer can be opposite to or the same as the conductivity type of the semiconductor substrate.

[0096] In addition, when the first surface and the second surface of the semiconductor substrate are not both target surfaces, as shown in Figures 15 and 16, the solar cell may further include a second semiconductor layer 20 having a conductivity type opposite to that of the first semiconductor layer 14. The location of the second semiconductor layer 20 on the semiconductor substrate 11 can be determined based on the type of solar cell and actual needs, and is not specifically limited here.

[0097] Specifically, as shown in FIG16 , in the case where the solar cell is a double-sided contact cell, the first semiconductor layer 14 and the second semiconductor layer 20 are respectively disposed on two opposite surfaces of the semiconductor substrate 11 .

[0098] Alternatively, as shown in FIG15 , in the case where the solar cell is a back-contact cell, the second semiconductor layer 20 and the first semiconductor layer 14 are arranged on the same surface of the semiconductor substrate 11. In this case, the solar cell provided by the embodiment of the present application is a back-contact cell, which can reduce the influence of the light-shielding electrode structure on the light utilization rate on the light-facing side, and further improve the photoelectric conversion efficiency of the solar cell. At this time, as shown in FIG17 , the first semiconductor layer 14 and the second semiconductor layer 20 can be spaced apart and distributed in a direction parallel to the target surface 12; or, as shown in FIG15 , the first semiconductor layer 14 can also extend to cover the portion of the second semiconductor layer 20 on the side away from the semiconductor substrate 11. In this case, when forming the first semiconductor layer 14, the first semiconductor material used to manufacture the first semiconductor layer 14 and arranged in an entire layer is selectively etched to improve the manufacturing efficiency of the solar cell.

[0099] 18 and 19 , when the first semiconductor layer 14 extends to cover the portion of the second semiconductor layer 20 facing away from the semiconductor substrate 11, the portion of the first semiconductor layer 14 extending onto the second semiconductor layer 20 may be isolated by an insulating layer 21 such as silicon oxide or silicon nitride, or the first doped semiconductor layer 19 included in the first semiconductor layer 14 may also be isolated by the first intrinsic semiconductor layer 18. Specifically, when the first doped semiconductor layer 19 included in the first semiconductor layer 14 is isolated by the first intrinsic semiconductor layer 18, it is understood that the thickness of the first intrinsic semiconductor layer 18 not only affects the transmission loss of carriers transmitted from the first intrinsic semiconductor layer 18 to the first doped semiconductor layer 19, but also affects the passivation effect of the first intrinsic semiconductor layer 18 and the leakage isolation effect of the first doped semiconductor layer 19 and the second semiconductor layer 20. Based on this, the first part covering the top of the first type of pyramid in the first semiconductor layer 14 and having a greater degree of crystallization has higher conductivity. On the premise of reducing the transmission loss between the first part and the conductive material, the working efficiency of the solar cell provided in the embodiment of the present application can be not reduced compared with the working efficiency of the existing solar cell. At the same time, the setting of the first part with a greater degree of crystallization can reserve adjustable space for thickening the thickness of the first intrinsic semiconductor layer 18. Not only can the leakage between the first doped semiconductor layer 19 and the second semiconductor layer 20 be further suppressed by the first intrinsic semiconductor layer 18 with a larger thickness, but the passivation effect of the first intrinsic semiconductor layer 18 on the semiconductor substrate 11 can also be improved, thereby reducing the carrier recombination rate.

[0100] Specifically, as shown in Figure 18, the second semiconductor layer 20 can be a single-layer structure, in which case the second semiconductor layer 20 can only include a second doped semiconductor layer. Alternatively, the second semiconductor layer can also be a stack of at least two film layers. For example, as shown in Figure 19, the second semiconductor layer 20 can include: an interface passivation layer 22 and a second doped semiconductor layer 23. The second doped semiconductor layer 23 is arranged on the side of the interface passivation layer 22 away from the semiconductor substrate 11. In this case, the interface passivation layer 22 and the second doped semiconductor layer 23 can constitute a selective contact structure, which has an excellent interface passivation effect, and can achieve selective collection of carriers, reduce the carrier recombination rate in the area of ​​the semiconductor substrate 11 where the second semiconductor layer 20 is formed, and further improve the photoelectric conversion efficiency of the solar cell.

[0101] In terms of materials, the material of the second semiconductor layer may be the same as or different from the material of the first semiconductor layer. When the material of the second semiconductor layer is different from that of the first semiconductor layer, the material of the second semiconductor layer may include any semiconductor material different from that of the first semiconductor layer. For example, the material of the second semiconductor layer may include at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. In this case, the material of the second semiconductor layer has a variety of possible examples, which is conducive to improving the applicability of the solar cell provided in this application in different application scenarios.

[0102] Preferably, when the solar cell provided in the embodiments of the present application is a back-contact cell, the first semiconductor layer includes a first intrinsic semiconductor layer and a first doped semiconductor layer, and the second semiconductor layer includes an interface passivation layer and a second doped semiconductor layer. The interface passivation layer includes a tunneling passivation layer, and the second doped semiconductor layer includes a doped polysilicon layer.

[0103] As for the surface morphology of the semiconductor substrate on which the second semiconductor layer is formed, the embodiments of the present application do not specifically limit the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer. For example, the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer can be a polished surface, a velvet surface, or an uneven curved surface. When the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer is a velvet surface, and the material of the second semiconductor layer includes amorphous silicon and / or nanocrystalline silicon, the degree of crystallization of the first portion of the second semiconductor layer covering at least a portion of the pyramid-like top can be greater than the degree of crystallization of the second portion covering the pyramid-like base; alternatively, the degree of crystallization of each portion of the second semiconductor layer can be approximately the same. Specifically, when the degree of crystallization of the first portion of the second semiconductor layer covering at least a portion of the pyramid-like top can be greater than the degree of crystallization of the second portion covering the pyramid-like base, the characteristics of the degree of crystallization, grain size, and crystallization depth of the first and second portions of the second semiconductor layer, as well as the distribution of the first portion, can refer to the corresponding situation of the first and second portions included in the first semiconductor layer above, and will not be repeated here.

[0104] It should be noted that when the conductivity type of the first doped semiconductor layer included in the first semiconductor layer is the same as the conductivity type of the semiconductor substrate, the solar cell includes the second semiconductor layer. However, when the conductivity type of the first doped semiconductor layer included in the first semiconductor layer is opposite to the conductivity type of the semiconductor substrate, the solar cell may or may not include the second semiconductor layer.

[0105] As for the thickness of the first semiconductor layer, the embodiment of the present application does not specifically limit the thickness of the first semiconductor layer, and can be determined based on the type of solar cell in the actual application scenario, as well as requirements for the passivation effect and transmission loss of the first semiconductor layer.

[0106] Exemplarily, the thickness of the first semiconductor layer may be greater than or equal to 10 nm, and / or the thickness of the first semiconductor layer may be less than or equal to 45 nm. For example, the thickness of the first semiconductor layer may be 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm or 45 nm, etc. In this case, the lower limit and / or upper limit of the thickness of the first semiconductor layer whose material includes amorphous silicon and / or nanocrystalline silicon is larger, which is beneficial for reducing the thermal impact of heat on the semiconductor substrate through the thicker first semiconductor layer, preventing thermal damage to the semiconductor substrate during the crystallization process of at least a portion of the first semiconductor layer, and ensuring that the solar cell has a higher yield. In addition, the thicker first semiconductor layer has a higher passivation effect, which can further reduce the carrier recombination rate at the velvet surface and further improve the working efficiency of the solar cell.

[0107] In terms of surface morphology, the surface roughness of each part of the surface of the first semiconductor layer facing away from the semiconductor substrate can be roughly the same. Alternatively, as shown in Figure 2, the surface roughness of the first part of the first semiconductor layer 14 can also be greater than the surface roughness of the second part. In this case, the specific surface area of ​​the first part of the first semiconductor layer 14 is larger, which is conducive to increasing the contact area between the first part and the conductive material, reducing the contact resistance between the first part and the conductive material, further reducing the transmission loss of carriers transmitted from the first semiconductor layer 14 to the conductive material, and further improving the working efficiency of the solar cell. In addition, in the actual manufacturing process, laser irradiation or high-temperature annealing is required to achieve crystallization modification of part of the first semiconductor layer 14, and the heating rate of the top of the pyramid-like 13 is faster than the heating rate of its own base, making it easier to achieve crystallization modification; and the change in the surface roughness of the first part is related to the change in the degree of crystallization of the first part and the escape of hydrogen within itself. Based on this, when the surface roughness of the first portion is greater than that of the second portion, there is no need to ensure that the second portion of the first semiconductor layer 14 covering the base of the first-type pyramid also has a larger surface roughness, which would otherwise lead to dehydrogenation due to the prolonged heating time of various portions of the first semiconductor layer 14. This ensures that the first semiconductor layer 14 has a higher passivation effect. In this case, the difference in surface roughness between the first portion and the second portion can be determined based on the difference in the degree of crystallization of the first portion and the second portion, as well as the actual application scenario, and will not be further explained here.

[0108] As a possible implementation, as shown in FIG20 , the solar cell may further include a transparent conductive layer 17, which covers at least the side of the first semiconductor layer 14 facing away from the semiconductor substrate 11. In this case, the transparent conductive layer 17 has a high electrical conductivity and can promptly conduct the carriers collected by the first semiconductor layer 14, thereby reducing the carrier recombination rate.

[0109] In actual application, the embodiment of the present application does not specifically limit the material and thickness of the transparent conductive layer, as long as it can be applied to the solar cell provided in the embodiment of the present application. It should be noted that when the solar cell provided in the embodiment of the present application is a back-contact cell, the transparent conductive layer can only cover the side of the first semiconductor layer away from the semiconductor substrate. Alternatively, as shown in Figure 20, the transparent conductive layer 17 not only covers the side of the first semiconductor layer 14 away from the semiconductor substrate 11, but also covers the side of the second semiconductor layer 20 away from the semiconductor substrate 11, and an insulating groove is provided in the transparent conductive layer 17 to isolate the parts of the transparent conductive layer 17 covering the first semiconductor layer 14 and the second semiconductor layer 20 respectively to prevent short circuits.

[0110] In a second aspect, an embodiment of the present application provides a method for manufacturing a solar cell, which comprises the following steps: first, providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The surface of at least a portion of the target surface is a velvet surface. A plurality of pyramid-like layers are formed on the velvet surface, and the plurality of pyramid-like layers include a plurality of first-type pyramids. Next, a first semiconductor layer is formed on the velvet surface, and the material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon. The first semiconductor layer includes a first portion covering the top of the first-type pyramid and a second portion covering the base of the first-type pyramid, and the degree of crystallization of the first portion is greater than the degree of crystallization of the second portion.

[0111] Specifically, information such as the structure and materials of the solar cell manufactured using the manufacturing method provided in the embodiment of the present application can refer to the description of the structure and materials of the solar cell provided in the first aspect above, and will not be repeated here.

[0112] The specific process of forming the first semiconductor layer may be determined according to the type of solar cell being manufactured.

[0113] For example, in the case where the solar cell manufactured is a double-sided contact cell, after a velvet surface is formed on at least a portion of the target surface of the semiconductor substrate, a process such as chemical vapor deposition can be used to form a first semiconductor material layer that is disposed on the target surface as a whole. If only a portion of the target surface is velvet, after the first semiconductor material layer is formed, a process such as laser or wet etching can be used to selectively etch the first semiconductor material layer to remove the portion of the first semiconductor material layer that does not correspond to the velvet. If all areas of the target surface are velvet, the first semiconductor material layer disposed as a whole is the first semiconductor layer. Then, after obtaining the first semiconductor layer, a laser irradiation process can be used to crystallize at least a portion of the first semiconductor layer so that the degree of crystallization of the first portion of the first semiconductor layer is greater than the degree of crystallization of the second portion. Specifically, the first semiconductor layer generates heat after absorbing light, causing its own temperature to rise. After the temperature rises to a certain level, the first semiconductor layer will be crystalline. Moreover, due to the reflection of the laser on the surface of the pyramid-like structure and the difference in heat dissipation speed at different positions of the pyramid-like structure (the heat dissipation speed at the top of the pyramid-like structure is slower, and the heat dissipation speed at the base of the pyramid-like structure is faster), the temperature of the first part of the first semiconductor layer covering the top of the first pyramid-like structure is higher than the temperature of the parts at other positions. Therefore, the first part of the first semiconductor layer covering the top of the first pyramid-like structure has a greater degree of crystallization.

[0114] Specifically, parameters such as the processing wavelength, pulse width, laser energy density, and processing time of the laser irradiation process can be determined based on requirements for the extension range of the first portion of the first semiconductor layer covering the top of the first-type pyramid and having a greater degree of crystallization in actual application scenarios, and are not specifically limited here. It is understandable that when the processing wavelength of the laser irradiation process is smaller, the pulse width is larger, the laser energy density is higher, and the processing time is longer, when the laser irradiation process is used to treat the first semiconductor layer, the temperature rise of the first semiconductor layer is greater, and it is more conducive to forming a first portion with a greater crystallization depth and a longer extension length.

[0115] For example, the processing wavelength of the laser irradiation process may be greater than or equal to 325 nm and less than or equal to 532 nm. For example, the processing wavelength may be 325 nm, 330 nm, 350 nm, 80 nm, 400 nm, 430 nm, 450 nm, 480 nm, 500 nm, or 532 nm.

[0116] For example, the pulse width of the laser irradiation process may be in the picosecond or nanosecond range, for example, 10 ps, ​​50 ps, ​​100 ps, ​​300 ps, ​​500 ps, ​​800 ps, ​​1 ns, or 5 ns.

[0117] For example, the laser energy density of the laser irradiation process may be greater than or equal to 200 mJ / cm 2 , and less than or equal to 6000mJ / cm 2 For example, the laser energy density can be 200mJ / cm 2 、240mJ / cm 2 、280mJ / cm 2 、300mJ / cm 2 , 400mJ / cm 2 , 500mJ / cm 2 、1000mJ / cm 2 , 2000mJ / cm 2 、3000mJ / cm 2 , 4000mJ / cm 2 , 5000mJ / cm 2 or 6000mJ / cm 2 wait.

[0118] In addition, when the manufactured solar cell is a double-sided contact cell, if the solar cell also includes a second semiconductor layer, the second semiconductor layer can be formed on the side of the semiconductor substrate away from the first semiconductor layer by at least a doping process before or after the formation of the first semiconductor layer.

[0119] For example, in the case of a back-contact solar cell, if the first semiconductor layer and the second semiconductor layer are spaced apart and arranged parallel to the first surface, the first semiconductor layer and the second semiconductor layer can be formed separately using the method described above for forming the first semiconductor layer in a localized area of ​​the target surface. A laser irradiation process can then be used to crystallize at least a portion of the first semiconductor layer, such that the degree of crystallization of the first portion of the first semiconductor layer covering the top of the first-type pyramid is greater than the degree of crystallization of the second portion of the first semiconductor layer covering the base of the first-type pyramid. If the first semiconductor layer extends over a portion of the second semiconductor layer, a deposition process and a doping process can be used to form an entire layer of the second semiconductor material disposed on the target surface. Laser or wet etching processes can then be used to selectively remove portions of the second semiconductor material layer to expose the area of ​​the semiconductor substrate used to form the first semiconductor layer. A textured surface can then be applied to at least the area of ​​the semiconductor substrate used to form the first semiconductor layer, under the masking action of a corresponding mask layer, to form a textured surface on the surface of the portion of the target surface. Then, a first semiconductor layer can be formed using the method described above, with the degree of crystallization of the first portion of the first semiconductor layer covering the top of the first-type pyramid being greater than the degree of crystallization of the second portion of the first semiconductor layer covering the base of the first-type pyramid. In this case, the parameter settings of the laser irradiation process can be referred to above and will not be repeated here.

[0120] In other embodiments of the present application, a solar cell is provided. As shown in FIG14 , the solar cell includes a semiconductor substrate 11 (e.g., a silicon substrate), and a surface of one side of the semiconductor substrate 11 includes a first region, a second region, and a third region adjacent to each other in sequence.

[0121] In the first region, a first doped layer (i.e., a first semiconductor layer 14) and a first electrode 141 are sequentially stacked on the semiconductor substrate 11; in the third region, a second doped layer (i.e., a second semiconductor layer 20) and a second electrode 142 are sequentially stacked on the semiconductor substrate 11; the first doped layer and the second doped layer have opposite conductivity;

[0122] At least one of the first doped layer in the first region and the second doped layer in the third region has a crystallized region; a projection of the crystallized region on the semiconductor substrate 11 at least partially overlaps with a projection of the first electrode 141 on the semiconductor substrate 11, and / or a projection of the crystallized region on the semiconductor substrate 11 at least partially overlaps with a projection of the second electrode 142 on the semiconductor substrate 11;

[0123] And wherein the first doped layer and the second doped layer extend to the second region; wherein, within the second region, at least a portion of the first doped layer is an amorphous region, and at least a portion of the second doped layer is an amorphous region.

[0124] In the solar cell provided in this embodiment, since photogenerated carriers migrate and diffuse laterally (perpendicular to the thickness direction of the doping layer) and longitudinally (parallel to the thickness direction of the doping layer) in doping layers of different doping types, the present application provides a second region with high resistivity between the first doping layer in the first region and the second doping layer in the third region for isolation, thereby reducing lateral carrier migration and leakage. In addition, at least one of the first doping layer in the first region and the second doping layer in the third region comprises a crystallized region, which has good conductivity and is conducive to carrier collection. In addition, in the second region, at least a portion of the first doping layer is an amorphous region, and at least a portion of the second doping layer is an amorphous region. The amorphous region has lower carrier mobility and lower sheet resistance than the crystalline region, which can greatly reduce leakage current.

[0125] The silicon substrate includes a light-receiving surface and a backlight surface, which are arranged relative to each other. The backlight surface of the silicon substrate includes a first region, a second region, and a third region that are adjacent to each other in sequence. Adjacent here means that the first region, the second region, and the third region are adjacent to each other in sequence but do not overlap.

[0126] The silicon substrate, the first doped layer, and the second doped layer all have a velvet structure; or, the silicon substrate, the first doped layer, and the second doped layer all have a smooth surface; or, the silicon substrate and the first doped layer in the first region have a velvet surface, and the functional layers in the third region have a smooth surface; or, the silicon substrate and the first doped layer in the first region have a smooth surface, and the functional layers in the third region all have a velvet structure.

[0127] In some embodiments, when the first doped layer in the first region has a textured surface, only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.

[0128] In some embodiments, when the second doped layer in the third region has a textured surface, only the raised portions of the textured surface in the laser irradiated region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.

[0129] In the solar cell shown in Figure 14, within the first region, the first doped layer includes a first crystallized region 152 and a first amorphized region A 156; at least the portion of the first crystallized region 152 facing away from the silicon substrate contains crystals. Within the third region, the second doped layer includes a second crystallized region 155. Within the second region, at least the side of the first doped layer proximal to the first region is a first amorphized region B 158, and at least the side of the second doped layer proximal to the first region is a second amorphized region B 157. A light-incident passivation layer and an anti-reflection layer are sequentially formed on the light-receiving surface of the silicon substrate.

[0130] The method for preparing a solar cell of this embodiment includes the following steps:

[0131] Step 1: Polish and clean the silicon wafer, and perform texturing on the light-incident surface.

[0132] Step 2: PECVD is used to deposit a 5nm intrinsic hydrogenated amorphous silicon passivation layer, a 30nm amorphous n layer, a 100nm SiNx layer (refractive index 2.5), and a 30nm laser absorption layer on the back of the battery.

[0133] Step 3: Use laser to remove the laser absorption layer in the first region, thereby forming a laser opening to expose the SiNx layer.

[0134] Step 4: Perform a wet process, use 10% concentration hydrofluoric acid to remove the SiNx layer in the laser opening to expose the amorphous n layer, and use 10% concentration potassium hydroxide to remove the exposed amorphous n layer, the intrinsic hydrogenated amorphous silicon passivation layer underneath, and the laser absorption layer in the second and third regions, thereby exposing the silicon wafer in the first region and the silicon nitride layer in the second and third regions.

[0135] Step 5: On the back of the cell, a 5nm intrinsic hydrogenated amorphous silicon passivation layer and a 30nm amorphous p-layer are sequentially deposited on the silicon wafer in the first area, the silicon nitride layer in the second area, and the silicon nitride layer in the third area using PECVD technology.

[0136] Step 6: Use laser (the energy density of the laser spot is 200mJ / cm 2 ) removing the amorphous p-layer and the intrinsic hydrogenated amorphous silicon passivation layer in the third region to form an opening, thereby exposing the SiNx layer in the third region.

[0137] Step 7: Perform wet treatment and use 10% concentration hydrofluoric acid to remove the SiNx layer in the third area.

[0138] Step 8: Use PECVD to deposit an intrinsic hydrogenated amorphous silicon passivation layer and a SiNx anti-reflection film on the light-incident surface, with a refractive index of 2 and a thickness of 70nm.

[0139] Step 9: Perform laser crystallization treatment, using laser to crystallize the middle area of ​​the amorphous p layer in the first region into a nanocrystalline p region, that is, the first nanocrystalline silicon p-doped region and the first amorphous silicon p-doped region exist in the first region at the same time, the first amorphous silicon p-doped region surrounds the first nanocrystalline silicon p-doped region, and the part of the amorphous n layer and the electrode layer stacked in the third region is crystallized into a nanocrystalline n region.

[0140] Step 10: sequentially depositing a TCO layer and an Ag electrode (first electrode 141 ) on the nanocrystalline p-layer; and sequentially depositing a TCO layer and an Ag electrode (second electrode 142 ) on the nanocrystalline n-layer.

[0141] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0142] The beneficial effects of the second aspect and its various implementations in the embodiments of the present application can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0143] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0144] The above describes the embodiments of the present application. However, these embodiments are only for the purpose of illustrating more clearly and are not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Without departing from the scope of this application, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of this application.

Claims

1. A solar cell, characterized in that, Comprising: A semiconductor substrate, the semiconductor substrate including opposite first and second surfaces; at least one of the first surface and the second surface being a target surface; At least a partial region of the surface of the target surface is a matte surface, and a plurality of pyramid-like structures are formed on the matte surface; And a first semiconductor layer disposed on the matte surface, the material of the first semiconductor layer including amorphous silicon and / or nanocrystalline silicon; the plurality of pyramid-like structures include a plurality of first pyramid-like structures, the first semiconductor layer including a first portion covering the top of the first pyramid-like structures and a second portion covering the base of the first pyramid-like structures, the crystallization degree of the first portion being greater than that of the second portion.

2. The solar cell according to claim 1, characterized in that, The first portion contains crystal grains, and the maximum size of the crystal grains is less than the thickness of the first portion.

3. The solar cell according to claim 1, characterized in that, Along the inclined direction of the side surface of the pyramid-like structure, the ratio between the maximum extension length of the first portion on the side surface of the first pyramid-like structure located below itself and the length of the side surface of the first pyramid-like structure is less than or equal to 0.

3.

4. The solar cell according to claim 1, characterized in that, The thickness of the first semiconductor layer is greater than or equal to 10 nm, and / or the thickness of the first semiconductor layer is less than or equal to 45 nm.

5. The solar cell according to claim 1, characterized in that, The solar cell further includes a transparent conductive layer, and the transparent conductive layer at least covers one side of the first semiconductor layer facing away from the semiconductor substrate.

6. The solar cell according to claim 1, wherein The pyramid-like structure is a pyramid with a sharp apex angle; Or, the pyramid-like structure is a pyramid-like structure with a smooth chamfer; Or, the pyramid-like structure is a pyramid-like structure with a flattened apex angle.

7. The solar cell according to claim 1, characterized in that, The surface of the pyramid-like structure is a plane; And / or, the surface roughness of the first portion is greater than that of the second portion.

8. The solar cell according to any one of claims 1 to 7, characterized in that, The first semiconductor layer includes: a first intrinsic semiconductor layer and a first doped semiconductor layer; the first doped semiconductor layer is disposed on one side of the first intrinsic semiconductor layer facing away from the semiconductor substrate; Along the direction approaching the matte surface, the maximum size of the crystal grains included in the first portion is less than or equal to the thickness of the first doped semiconductor layer.

9. The solar cell according to any one of claims 1 to 7, characterized in that, The solar cell further includes a second semiconductor layer having a conductive type opposite to that of the first semiconductor layer; Wherein, the second semiconductor layer and the first semiconductor layer are disposed on the same surface of the semiconductor substrate, and the first semiconductor layer extends to cover a part of the side of the second semiconductor layer facing away from the semiconductor substrate; and / or, the second semiconductor layer is disposed on the second surface of the semiconductor substrate, and the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

10. The solar cell according to any one of claims 1 to 7, characterized in that The material of the first portion includes nanocrystalline silicon; the material of the second portion is amorphous silicon.

11. A manufacturing method of a solar cell, characterized in that, Comprising: Providing a semiconductor substrate; The semiconductor substrate has opposite first and second surfaces; at least one of the first surface and the second surface is a target surface; At least a partial region of the surface of the target surface is a matte surface; a plurality of pyramid-like structures are formed on the matte surface; the plurality of pyramid-like structures include a plurality of first pyramid-like structures, A first semiconductor layer is formed on the velvet surface, and the material of the first semiconductor layer includes amorphous silicon and / or nanocrystalline silicon; the first semiconductor layer includes a first portion covering the top of the first type of pyramid and a second portion covering the base of the first type of pyramid, and the crystallization degree of the first portion is greater than that of the second portion.

12. The manufacturing method of the solar cell according to claim 11, characterized in that, A laser irradiation process is adopted to crystallize at least part of the first semiconductor layer, so that the crystallization degree of the first portion is greater than that of the second portion.

13. The manufacturing method of a solar cell according to claim 12, characterized in that, The wavelength of the laser used in the laser irradiation process is greater than or equal to 325 nm and less than or equal to 532 nm; And / or, the pulse width of the laser irradiation process is picosecond level or nanosecond level; And / or, the laser energy density of the laser irradiation process is greater than or equal to 200 mJ / cm 2 and less than or equal to 6000 mJ / cm 2 .

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