Device for saving overvoltage event information, and reading device

Abstract

The invention relates to a device for saving overvoltage event information and to a reading device, wherein the device has: a protective element (10) and a memory cell (20), and the protective element (10) is designed to be electrically connected to a connection (32) of an electrical circuit (30) and to protect the electrical circuit (30) from an overvoltage (U1) occurring at the connection (32) due to an overvoltage event. The memory cell (20) is connected in parallel with the protective element (10) and is designed to save electrical charges generated by an overvoltage event in a non-volatile manner and to be read via a reading connection (40).

Description

[0001] Description

[0002] title

[0003] Device for storing information about an overvoltage event and readout device

[0004] State of the art

[0005] The present invention relates to a device for storing information about an overvoltage event and a readout device for reading this information.

[0006] Modern integrated circuits (e.g., ASICs, etc.) typically have a large number of connection pins that require protection, particularly against electrostatic discharge (ESD). Most of the protective measures provided for this purpose are intended for an unpowered state of these integrated circuits (e.g., during their manufacturing), in which ESD events can lead to damage and / or degradation of the integrated circuit even before the integrated circuits are actually used in production. Furthermore, such ESD measures are intended to protect integrated circuits at a system level.

[0007] Since such ESD discharges are usually caused by voltages of several kilovolts, each of these discharges represents a potential risk of damage and / or impairment to the integrated circuit. As long as the ESD protection functions properly, the risk is minimized. However, each of these discharges leads to accelerated aging and degradation of the integrated circuit.

[0008] Since the ESD protection of the integrated circuit functions not only during active operation, but also during manufacture and / or handling of the integrated circuit, the integrated circuit can dissipate such ESD discharges and store information about them even before initial commissioning. The ESD protection, which can be provided in the form of a so-called ESD clamp, which provides a low-resistance path for accumulated charges to dissipate the charges, is normally only designed for a certain maximum voltage or a certain maximum current. If this voltage is exceeded, it is possible that the voltage is no longer sufficiently clamped (i.e., dissipated) by the ESD protection and that critical values ​​for the integrated circuit are exceeded. This can, for example, lead to damage to individual elements such as the gate oxides of the integrated circuit, etc.

[0009] Knowing how frequently and / or with which voltage an ESD protection and thus the integrated circuit protected by the ESD protection has been loaded in the past and whether the maximum specified voltage has been exceeded, provides important information about the future reliability of integrated circuits.

[0010] To store information about the occurrence of such events, non-volatile memory (NVM) cells are typically written. In the current state of the art, this is done based on additional circuitry that stores the acquired information in memories such as one-time programmable (OTP) devices, fuses, and EEPROMs.

[0011] DE102016207920A1 discloses a device for detecting a number of electrostatic discharges with a discharge protection device, which is characterized in that a detection unit is electrically connected in parallel to the discharge protection device and the detection unit generates an output signal representing the number of electrostatic discharges.

[0012] Disclosure of the invention

[0013] According to a first aspect of the present invention, a device for storing information about an overvoltage event is proposed.

[0014] The device comprises a protective element and a memory cell, wherein the protective element is configured to be electrically connected to a terminal of an electrical circuit, wherein the electrical circuit is, for example, an integrated circuit or the like, and wherein the electrical terminal is, for example, an externally contactable connection pin of the electrical circuit. Furthermore, the electrical circuit can be, for example, any semiconductor chip such as an ASIC or a chip other than the ASIC.

[0015] The protective element is further configured to protect the electrical circuit from an overvoltage occurring at the terminal due to an overvoltage event. Such an overvoltage event can be caused, in particular, by electrostatic discharges (ESD), which can arise, for example, due to friction during manufacture and / or handling (e.g., due to contact by a person) of the electrical circuit.

[0016] The protective element can therefore preferably be designed as an ESD clamp known from the prior art for the low-resistance discharge of ESD charges.

[0017] The memory cell is connected in parallel to the protection element and is configured to store electrical charges generated by an overvoltage event in a non-volatile manner and to be read out via a readout terminal.

[0018] According to the invention, the memory cell is explicitly permitted to be operated outside its specifications (i.e., outside of predefined programming times and predefined programming voltages) for secure bit writing, since no additional circuit components are provided for supplying and / or controlling the memory cells, as is typically required in the prior art. This allows, among other things, a reduction in space and component requirements, thus resulting in corresponding cost savings.

[0019] In other words, the memory cell is not described in such a way that its respective stored charge quantity represents a clear 0 or a clear 1, but that, for example, only a fraction of the charge quantity is introduced, which does not result in a saturated state of the memory cell, which usually represents a 1. Since even the introduction of a fraction of the usual charge quantity changes the conductivity of the memory cell, which correlates with a programming duration and a voltage applied during programming, information about an overvoltage event that has occurred can be obtained from the memory cell by evaluating a current conductance of the memory cell.Accordingly, the device according to the invention can be used particularly advantageously in connection with electrical circuits subject to special safety requirements, such as circuits used in safety-relevant systems in vehicles and / or other environments, since information about the load on the respective electrical circuit can be determined based on the charges stored in the storage cell. Based on this information, it is possible to assess whether the reliability of the electrical circuit is sufficient for use in a safety-critical environment.

[0020] The subclaims show preferred developments of the invention.

[0021] Further preferably, the device is designed as an integrated circuit and / or encapsulated in a housing. A device designed in this way can, for example, have a plurality of externally accessible terminals (pins), wherein at least some of the terminals, and advantageously all of the terminals, are monitored for overvoltages by means of a device according to the invention.

[0022] Particularly preferably, the memory cell is designed as a floating-gate transistor and in particular as an OTP (“one time programmable”) memory cell or as an EEPROM (“electrically erasable programmable read-only memory”).

[0023] The storage cell is advantageously configured to accumulate charges generated by a plurality of overvoltage events. For this purpose, the storage cell and / or an electrical connection of the storage cell is preferably designed depending on the type and / or frequency of expected overvoltage events, so that several overvoltage events can be accumulated in the storage cell. Based on the level of an existing total charge, conclusions can be drawn regarding the frequency and / or level of overvoltage events that have occurred previously.

[0024] In an advantageous embodiment of the present invention, the device is configured to be actively operated using a voltage (supply voltage) that is below a threshold voltage required for writing to the memory cell. By ensuring that the voltage applied during active operation of the device is below the threshold voltage, unwanted writing to the memory cell, i.e., unwanted introduction of electrical charges into the memory cell during regular operation of the device, can be prevented. In this way, it is also possible to store information about overvoltage events in the memory cell during an active operating phase and / or between respective active operating phases of the device.

[0025] In a further advantageous embodiment of the present invention, the device further comprises a control transistor, in particular a normally off control transistor, wherein the control transistor is connected in series with the memory cell in parallel with the protective element and is configured to disconnect the memory cell from a supply voltage of the electrical circuit during active operation of the electrical circuit. In this way, for example, unintentional writing to the memory cell by a supply voltage that may potentially exceed the threshold voltage of the memory cell can be prevented. Alternatively or additionally, the control transistor is configured to be switched on by means of a switch-on voltage generated on the basis of an overvoltage event in order to enable overvoltage-induced charge transport into the memory cell.For this purpose, the control transistor is connected to the ESD clamp, either directly or via a level shifter. This explicitly does not preclude the use of one or more additional elements, such as sensor elements, that can generate the turn-on voltage alternatively or in addition to the protection element. These elements can respond, among other things, to the magnitude of an applied voltage or the magnitude of an edge steepness.

[0026] Further advantageously, the device is configured, for example based on additional circuitry, to switch the control transistor off again at the latest after a predefined on-time has elapsed, in order to limit the amount of charge introduced into the memory cell by a single overvoltage event. This offers the advantage that a large number of overvoltage events can be stored in the memory cell in an accumulative manner, since a single overvoltage event with a correspondingly long duration and / or a correspondingly high voltage does not cause the memory cell to saturate.

[0027] On the other hand, this offers the advantage that a number of overvoltage events that have occurred in the past can be better estimated, since by interrupting the charge carrier uptake in the memory cell after the switch-on time has elapsed, a form of quantization of the respective charge carrier quantities per overvoltage event is achieved, so that the number of overvoltage events can be estimated particularly accurately based on a total charge present in the memory cell and information about the level of quantization of the charge quantity uptake per overvoltage event.

[0028] Further advantageously, the device according to the invention comprises a plurality of memory cells, on the basis of which the device is configured to redundantly store information about overvoltage events. This allows, for example, greater reliability to be achieved by mutually verifying the plausibility of the respective charge quantities in the respective memory cells. Alternatively or additionally, the device is configured, based on the plurality of memory cells, to write to respective memory cells at different voltage levels. This can be achieved, for example, by a different design of the respective memory cells and / or by a different wiring of the memory cells and / or the transistors that activate the respective memory cells.In this way, it is possible to ensure that, in the event of an overvoltage event, only those memory cells whose preset minimum voltage level is exceeded by the overvoltage event are charged. By appropriately staggering the different voltage levels of the respective memory cells, it is possible to determine the voltage level up to which the memory cells have been written by reading the memory cells, allowing a voltage range of the overvoltage event to be estimated on this basis.

[0029] In a further advantageous embodiment of the present invention, the device further comprises a programmable reference memory cell, which is configured to be programmed using a predefined amount of charge and to be read out via a readout terminal of the reference memory cell. For this purpose, the reference memory cell is preferably designed to be identical to the memory cell provided for storing the overvoltage information. Based on the reference memory cell, for example, fluctuations caused by the manufacturing process can be determined, which can then be used to correct the measurement results of the memory cell in which the information about the overvoltage event is stored. In this way, correspondingly more precise results can be achieved when determining information about previous overvoltage events.According to a second aspect of the present invention, a readout device is proposed which is provided for reading out a memory cell of a device according to the first aspect of the invention. For this purpose, the readout device is configured to be electrically connected to a readout terminal of the memory cell of the device and to determine, on the basis of a conductivity measurement of the memory cell of the device, a level and / or a frequency of overvoltage loads in an electrical circuit connectable or connected to the device. The readout device is preferably a device formed separately from the device and which can be connected to the device, for example, during a manufacturing process, in particular at the end of a manufacturing process of the device and the electrical circuit.In a case where the detected overvoltage load of the electrical circuit exceeds a predefined threshold, for example, it is possible to classify the electrical circuit as faulty or insufficiently reliable. Furthermore, it is also conceivable for the readout device to be housed together with the device and / or the electrical circuit in a single unit, for example, in a housing, in order to evaluate the overvoltage load internally (e.g., by applying a supply voltage to the unit) and to output information about the overvoltage load status of the unit externally via an output signal.Preferably, the readout device is further configured to carry out a readout process on the basis of a readout voltage which is below a threshold voltage for writing to the memory cell, so that the information stored in the memory cell about the overvoltage events is not inadvertently overwritten or corrupted during a readout process.

[0030] Short description of the drawings

[0031] Embodiments of the invention are described in detail below with reference to the accompanying drawings. In the drawing:

[0032] Figure 1 is a block diagram of an exemplary embodiment of a device according to the invention in conjunction with a readout device according to the invention; and

[0033] Figure 2 shows exemplary current / voltage relationships for different

[0034] Overvoltage events in a memory cell according to the invention; and Figure 3 shows exemplary conductivity values ​​of a memory cell according to the invention as a function of a number of overvoltage events.

[0035] Embodiments of the invention

[0036] Figure 1 shows a block diagram of an exemplary embodiment of a device according to the invention for storing information about an overvoltage event in conjunction with a readout device 60 according to the invention.

[0037] The device according to the invention comprises a protective element 10, a memory cell 20 formed on the basis of a floating gate transistor and a control transistor 50.

[0038] The protective element 10 is electrically connected to a terminal 32 of an electrical circuit 30, which is designed here as an ASIC, and is thus configured to protect the electrical circuit 30 from an overvoltage Ul occurring at the terminal 32 due to an overvoltage event, in particular due to an ESD event.

[0039] It should be noted that the device according to the invention can also be designed to be integrated with the electrical circuit 30, for example by integrating it into the ASIC described here.

[0040] The memory cell 20 is connected in parallel with the protection element 10 and is configured to store electrical charges generated by an overvoltage event in a non-volatile and accumulative manner. The memory cell 20 is further configured to be read via a readout terminal 40.

[0041] The control transistor 50, which is a normally blocking control transistor 50 and which is connected in series with the memory cell 20 in parallel with the protection element 10, is configured to disconnect the memory cell 20 from a supply voltage of the electrical circuit 30 during active operation of the electrical circuit 30 and to be switched on by means of a switch-on voltage U2 generated on the basis of an overvoltage event, which is provided by the protection element 10, in order to enable an overvoltage-induced charge transport into the memory cell 20.

[0042] A readout device 60 according to the invention, which is electrically connected here to the readout terminal 40, is configured to read out electrical charges stored in the memory cell 10. Based on a conductivity measurement of the memory cell 10, the readout device 60 determines the magnitude and / or frequency of overvoltage loads on the electrical circuit 30 connected to the device.

[0043] Figure 2 shows exemplary current / voltage relationships for different overvoltage events in a memory cell 20 according to the invention (see Figure 1).

[0044] Curve 70 represents an exemplary current / voltage relationship of the memory cell 20 in a case in which no charges have yet been introduced into the memory cell 20 due to an overvoltage event.

[0045] Curve 72 represents an exemplary current / voltage relationship of the memory cell 20 in a case where charges were introduced into the memory cell 20 due to an overvoltage event, wherein the overvoltage event was applied to the memory cell 20 with a precharge voltage of 7 V for a duration of 100 ns.

[0046] Curve 73 represents an exemplary current / voltage relationship of the memory cell 20 in a case in which charges were introduced into the memory cell 20 due to two overvoltage events, wherein the overvoltage events were each applied to the memory cell 20 with a precharge voltage of 7V and each for a duration of 100ns.

[0047] Curve 73 represents an exemplary current / voltage relationship of the memory cell 20 in a case in which charges were introduced into the memory cell 20 due to three overvoltage events, wherein the overvoltage events were each applied to the memory cell 20 with a precharge voltage of 7V and each for a duration of 100ns.

[0048] Figure 3 shows exemplary conductivity values ​​of a memory cell according to the invention as a function of a number of overvoltage events. Figure 3 shows that the conductivity of the memory cell 20 (see Figure 1), which is indicated on the vertical axis in the diagram in Figure 3, increases with an increasing number of ESD events, which are indicated on the horizontal axis of the diagram, until saturation of the memory cell 20 is reached.

[0049] The conductivity values ​​were determined here, for example, by means of a readout voltage or a measuring voltage of 100 mV, which can be applied to the memory cell 20 by means of a readout device 60 (see Figure 1).

Claims

Claims 1. Device for storing information about an overvoltage event, comprising: - a protective element (10), and - a memory cell (20), wherein - the protective element (10) is arranged, - to be electrically connected to a terminal (32) of an electrical circuit (30), and - to protect the electrical circuit (30) from an overvoltage (Ul) occurring at the terminal (32) due to an overvoltage event, - the memory cell (20) is connected in parallel to the protective element (10) and is arranged - to store electrical charges generated by an overvoltage event in a non-volatile manner, and - to be read out via a readout connection (40).

2. Device according to claim 1, wherein the device - is designed as an integrated circuit, and / or - is encapsulated by a housing.

3. Device according to one of the preceding claims, wherein the memory cell (20) is designed as a floating-gate transistor and in particular as an OTP or EEPROM.

4. Device according to one of the preceding claims, wherein the memory cell (20) is arranged to accumulate charges generated by a plurality of overvoltage events.

5. Device according to one of the preceding claims, wherein the device is arranged to be actively operated by means of a voltage which is below a threshold voltage required to write to the memory cell (20).

6. Device according to one of the preceding claims, further comprising a control transistor (50), in particular a normally blocking control transistor (50), wherein the control transistor (50) is connected in series with the memory cell (20) in parallel to the protective element (10) and is arranged, - to separate the memory cell (20) from a supply voltage of the electrical circuit (30) during active operation of the electrical circuit (30), and / or - to be switched on by means of a switch-on voltage (U2) generated on the basis of an overvoltage event in order to enable an overvoltage-induced charge transport into the storage cell (20).

7. The device according to claim 6, wherein the device is configured to switch the control transistor (50) off again at the latest after a predefined switch-on time has elapsed in order to limit an amount of charge that is introduced into the memory cell (20) by a single overvoltage event.

8. Device according to one of the preceding claims, wherein the device comprises a plurality of memory cells (20) on the basis of which the device is arranged, - redundantly store information about overvoltage events, and / or - to write respective memory cells at different voltage levels.

9. Device according to one of the preceding claims further comprising a programmable reference memory cell which is arranged - to be programmed using a predefined amount of charge, and - to be read out via a readout connection of the reference memory cell.

10. Read-out device (60) for reading a memory cell (10) of a device according to one of the preceding claims, wherein the read-out device (60) is arranged - to be electrically connected to a readout terminal (40) of a memory cell (10) of the device, and - to determine, on the basis of a conductivity measurement of the storage cell (10) of the device, a level and / or a frequency of overvoltage loads of an electrical circuit (30) connectable to the device.

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