Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor in which flux can be easily removed by a flux cleaning liquid. A multilayer ceramic capacitor 1 according to the present invention comprises: a laminate 2 having a plurality of dielectric layers 14 and a plurality of internal electrodes 15 stacked alternately on top of each other, a first main surface A1 and a second main surface A2 opposing each other in the stacking direction, two lateral surfaces B opposing each other in a width direction orthogonal to the stacking direction, and two end surfaces C opposing each other in a length direction orthogonal to the stacking direction and the width direction; and two external electrodes 3 respectively disposed on the end surfaces, wherein, in a cross section of the laminate 2 along the length and stacking directions at a central portion in the width direction, the dimension in the stacking direction between the first main surface A1 and the second main surface A2 in a central portion in the length direction is smaller than the dimension in the stacking direction between the first main surface A1 and the second main surface A2 at two end portions in the length direction.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors, which include a laminate in which dielectric layers and internal electrodes are alternately stacked, and external electrodes electrically connected to the internal electrodes, are mounted on a substrate for use. The multilayer ceramic capacitor is mounted on the substrate using solder, but flux components contained in the solder paste may cause malfunctions in the multilayer ceramic capacitor. To reduce the possibility of such malfunctions, flux is removed from the multilayer ceramic capacitor using a flux cleaning solution after mounting on the substrate (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-202335

[0004] However, in conventional multilayer ceramic capacitors, the space between the substrate and the laminate is narrow, making it difficult for the defluxing solution to penetrate, which can result in insufficient flux removal by the defluxing solution.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor from which flux can be easily removed using a defluxing solution.

[0006] In order to solve the above-described problems, the present invention provides a multilayer ceramic capacitor comprising: a laminate having a plurality of dielectric layers and a plurality of internal electrodes stacked alternately with one another; first and second main surfaces opposing each other in a stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction, wherein the plurality of internal electrodes have first internal electrodes extended to the first end surfaces and second internal electrodes extended to the second end surfaces; and a first external electrode disposed on the first end surface and a second external electrode disposed on the second end surface, wherein, in a cross section of the laminate taken along the length direction and the stacking direction at a center part in the width direction, the dimension in the stacking direction between the first and second main surfaces at the center part in the length direction is smaller than the dimension in the stacking direction between the first and second main surfaces at both ends in the length direction.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor from which flux can be easily removed using a defluxing solution.

[0008] FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. FIG. 2 is a WT cross-sectional view at the center in the length direction L, taken along line II-II in FIG. 1. FIG. 3 is an LT cross-sectional view at the center in the width direction W, taken along line III-III in FIG. 1. FIG. 4 is a table showing the results of investigating the occurrence of appearance defects and short-circuit defects for multilayer ceramic capacitors of embodiments and comparative embodiments. FIG. 5 is a view showing a multilayer ceramic capacitor 1A of a first modified embodiment of the present invention. FIG. 6 is a view showing a multilayer ceramic capacitor 1B of a second modified embodiment of the present invention. FIG. 7 is a view showing a multilayer ceramic capacitor 1C of a third modified embodiment of the present invention. FIG. 8 is a view showing a multilayer ceramic capacitor 1D of a fourth modified embodiment of the present invention.

[0009] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described. FIG. 1 is a schematic perspective view of the multilayer ceramic capacitor 1.

[0010] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 is a substantially rectangular parallelepiped and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2. The laminate 2 includes an inner layer portion 11 in which a plurality of dielectric layers 14 and a plurality of internal electrodes 15 are stacked, and an outer layer portion 12.

[0011] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are: a length direction L, which is the direction in which a pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; a stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked; and a width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0012] Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, taken along the width direction W and the stacking direction T at the center of the length direction L. Hereinafter, this cross-section will be referred to as a WT cross-section. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1, taken along the length direction L and the stacking direction at the center of the width direction W. Hereinafter, this cross-section will be referred to as an LT cross-section.

[0013] 2 , a pair of outer peripheral surfaces facing each other in the stacking direction T will be referred to as a first main surface A1 and a second main surface A2, and when there is no need to distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A. A pair of outer peripheral surfaces facing each other in the width direction W will be referred to as a first side surface B1 and a second side surface B2, and when there is no need to distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B. A pair of outer peripheral surfaces facing each other in the length direction L will be referred to as a first end surface C1 and a second end surface C2, and when there is no need to distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0014] The multilayer ceramic capacitor 1 of the embodiment has a dimension in the length direction L that is shorter than the dimension in the width direction W. The dimensions of the multilayer ceramic capacitor 1 of the embodiment are, for example, but not limited to, 0.2 mm to 0.6 mm in the length direction L, 0.4 mm to 1 mm in the width direction W, and 0.1 mm to 0.9 mm in the stacking direction T.

[0015] (Laminate 2) It is preferable that the corners and ridges of the laminate 2 are rounded. The corners are portions where three surfaces of the laminate 2 intersect, and the ridges are portions where two surfaces of the laminate 2 intersect. Furthermore, fine irregularities different from the recesses 20 described below may be formed on part or all of the main surface A, side surface B, and end surface C.

[0016] As shown in Figure 3, the laminate 2 of the embodiment is approximately a rectangular parallelepiped, but in the LT cross section, the dimension T1 in the stacking direction T between the first main surface A1 and the second main surface A2 at the center in the longitudinal direction L is smaller than the dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 at both ends in the longitudinal direction L.

[0017] In other words, in the laminate 2 of the embodiment, in the LT cross section, the dimension T1 in the stacking direction T between the first main surface A1 and the second main surface A2 at the center in the longitudinal direction L is smaller than both the dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 at the first end face C1 and the dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 at the second end face C2.

[0018] Here, the central portion of the laminate 2 in the longitudinal direction L refers to the central portion between the first end face C1 and the second end face C2 of the laminate 2. In other words, it refers to a position that is half the distance between the first end face C1 and the second end face C2 in the longitudinal direction L from one end face C.

[0019] Similarly, the central portion of the laminate 2 in the width direction W is basically the central portion between the first side surface B1 and the second side surface B2 of the laminate 2. That is, it refers to a position half the distance between the first side surface B1 and the second side surface B2 in the width direction W from one side surface B. However, this is not limited to a position half the dimension in the width direction W, and may be any position between a position one-third the dimension in the width direction W and a position two-thirds the dimension in the width direction W.

[0020] In the embodiment, the first main surface A1 of the laminate 2 is flat, and therefore a recess 20 is formed on the second main surface A2 of the laminate 2, the central portion of which is recessed in the stacking direction T, so that T1 < T2 holds. However, in the WT cross section shown in Fig. 2, the outline of the second main surface A2 of the laminate 2 along the width direction W is a straight line.

[0021] The recess 20 on the second main surface A2 side is formed by gradually increasing the dimension from the first main surface A1 to the second main surface A2 in at least a portion from the center in the longitudinal direction L to both ends in the longitudinal direction L in the LT cross section shown in Fig. 3. In the embodiment, the dimension from the first main surface A1 to the second main surface A2 gradually increases over the entire length from the center in the longitudinal direction L to the positions of the ends of the external electrodes 3 on the main surface side.

[0022] Further, T2 / T1 is preferably 1.01 or more, and more preferably 1.033 or more and 1.201 or less.

[0023] Furthermore, T2-T1 is preferably larger than the sum ΣTE of the dimensions TE (thickness of the internal electrode 15) of the first internal electrode 15A or the second internal electrode 15B in the stacking direction T (T2-T1)>ΣTE).

[0024] 1 , in the laminate 2, at the first side surface B1 and the second side surface B2, a dimension t1 in the stacking direction T between the first main surface A1 and the second main surface A2 at the center in the longitudinal direction L is smaller than a dimension t2 in the stacking direction T between the first main surface A1 and the second main surface A2 at both end portions in the longitudinal direction L. The ratio t2 / t1 is also preferably 1.01 or greater, and more preferably 1.033 or greater and 1.201 or less.

[0025] (Observation Method) <Method for Measuring T1 and T2> Measurement of T1 and T2 can be carried out as follows.

[0026] (1) The multilayer ceramic capacitor 1 is polished along the LT cross section to expose the LT cross section at 1 / 2 of the dimension in the width direction W. Then, the exposed LT cross section is observed using a microscope.

[0027] (2) In this LT cross section, the shortest dimension in the stacking direction T between the first main surface A1 and the second main surface A2 is measured and designated as T1.

[0028] (3) In this LT cross section, the dimension in the stacking direction T between the first main surface A1 and the second main surface A2 at the first end face C1 and the second end face C2 is measured. Then, the average value of the dimension in the stacking direction T between the first main surface A1 and the second main surface A2 at the first end face C1 and the dimension in the stacking direction T between the first main surface A1 and the second main surface A2 at the second end face C2 is defined as T2.

[0029] Regarding the measurement of t2 and t1, the side surface is exposed by polishing, and then the same operation as for T1 and T2 is carried out, whereby t2 and t1 can be obtained in the same manner as T1 and T2.

[0030] (Dielectric Layer 14) The dielectric layer 14 is mainly composed of a ceramic material containing at least one of Ca, Sr, Zr, and Ti. Specifically, for example, a ceramic material containing Ca and Zr and having the general formula ABO ３ The ceramic material having such a perovskite structure is, for example, CaZrO ３ (calcium zirconate) and TiO ２ Examples of suitable ceramic materials for forming the dielectric layer 14 include, but are not limited to, titanium oxide (TiO). The ceramic material for forming the dielectric layer 14 may contain all of Ca, Zr, and Ti as its main components. ３ In the formula, ZrO ３ Alternatively, Ca(Zr0.9Ti0.1)O3, in which part of Zr is replaced with Ti, may be used.

[0031] The ceramic material for forming the dielectric layer 14 is (Ca1-x-y, Srx, Bay)m(Zr1-z-α, Tiz, Hfα)O ３ (where x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) may also be used.

[0032] Depending on the purpose, additives may be added to the ceramic material forming the dielectric layer 14. Examples of such additives include oxides of rare earth elements such as Mn, Mg, Dy, and Cr, or V, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, and Y, or oxides of Co, Ni, Li, B, Na, K, and Si, or glass.

[0033] The thickness of the dielectric layer 14 can be determined by measuring the distance between two adjacent first internal electrodes 15A or the distance between two adjacent second internal electrodes 15B, and is, for example, 1 μm or more and 100 μm or less.

[0034] (Internal electrodes 15) The multiple internal electrodes 15 include first internal electrodes 15A extended to the first end face C1 and second internal electrodes 15B extended to the second end face C2. The number of first internal electrodes 15A and second internal electrodes 15B is, for example, 1 to 50, but is not limited to this.

[0035] In the embodiment, as shown in FIG. 3 , the first internal electrode 15A and the second internal electrode 15B do not overlap in the stacking direction T, and the sum of the dimensions of the first internal electrode 15A and the second internal electrode 15B in the length direction L is smaller than the dimension of the laminate 2 in the length direction L.

[0036] The first internal electrode 15A and the second internal electrode 15B are present on the same plane. That is, the dimension of each of the first internal electrode 15A and the second internal electrode 15B in the length direction L is smaller than half the dimension of the length direction L of the laminate 2, and they are arranged side by side in approximately the same plane (in the LW cross section) along the length direction L and the width direction W. That is, the multilayer ceramic capacitor 1 of the embodiment has a so-called butt-joint structure in which there is a gap between the first internal electrode 15A and the second internal electrode 15B in the length direction L.

[0037] Furthermore, the dimension L15 of the internal electrode 15 in the length direction L may be shorter than the average dimension L3 of the external electrodes 3 (folded portions) arranged on the principal surface A. Specifically, the dimension L15A of the first internal electrode 15A in the length direction L may be smaller than the average dimension L3A of the first external electrodes 3A arranged on the first principal surface A1 and the second principal surface A2 in the length direction L in the LT cross section. And the dimension L15B of the second internal electrode 15B in the length direction L may be smaller than the average dimension L3B of the second external electrodes 3B arranged on the first principal surface A1 and the second principal surface A2 in the length direction L.

[0038] By making the dimension of the internal electrode 15 in the length direction L shorter than the average dimension in the length direction L of the external electrodes 3 arranged on the main surface A, it is possible to minimize the possibility of the first internal electrode 15A coming into contact with the second external electrode 3B, and the second internal electrode 15B coming into contact with the first external electrode 3A, thereby reducing the possibility of short-circuit defects.

[0039] In the LT cross section shown in Figure 3, the distance L1 between the end of the first internal electrode 15A on the second end face C2 side and the end of the second internal electrode 15B on the first end face C1 side is preferably, for example, not less than 5 µm and not more than 400 µm.

[0040] The internal electrodes 15 are conductive thin films containing at least one of metals such as Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and Au. Cu is preferably used for the internal electrodes 15 to improve the frequency characteristics of the multilayer ceramic capacitor 1. The internal electrodes 15 may further contain dielectric particles having the same composition as the ceramic contained in the dielectric layers 14.

[0041] More specifically, the internal electrode 15 may contain Cu and the underlying electrode of the external electrode 3 described later may contain Cu, or the internal electrode 15 may contain Ni and the underlying electrode of the external electrode 3 described later may contain Ni.

[0042] The thickness of each of the internal electrodes 15 is preferably, for example, 0.5 μm or more and 10 μm or less.

[0043] (Outer Layer Portion 12) The outer layer portion 12 is an assembly of a plurality of dielectric layers 14 made of the same dielectric ceramic material as the dielectric layers 14 of the inner layer portion 11. However, without being limited thereto, the outer layer portion 12 may be made of a dielectric ceramic material different from that of the dielectric layers 14.

[0044] (External electrode 3) The external electrode 3 includes a first external electrode 3A and a second external electrode 3B. The first external electrode 3A covers the first end face C1 of the laminate 2 and is arranged so as to be connected to the first internal electrode 15A extended to the first end face C1. The first external electrode 3A is preferably provided so as to extend to parts of the first principal face A1 and the second principal face A2, and parts of the first side face B1 and the second side face B2. However, it may be arranged only on the first end face C1.

[0045] The second external electrode 3B is disposed so as to cover the second end face C2 of the laminate 2 and to be connected to the second internal electrode 15B extended to the second end face C2. The second external electrode 3B is preferably provided so as to extend to parts of the first principal face A1 and the second principal face A2, and parts of the first side face B1 and the second side face B2. However, the second external electrode 3B may be disposed only on the second end face C2.

[0046] Hereinafter, unless it is necessary to particularly distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively referred to as the external electrode 3. The external electrode 3 includes a base electrode layer 31 and a plating layer 32.

[0047] (Base electrode layer 31) The base electrode layer 31 includes at least one selected from a baked layer, a resin layer, a thin film layer, etc. The base electrode layer 31 covers the end face C of the laminate 2 and is arranged so as to be connected to the internal electrode 15 extended to the end face C.

[0048] (When the base electrode layer 31 includes a baking layer) The baking layer includes a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal of the baking layer includes at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer may be a multi-layered layer. The baking layer is formed by applying a conductive paste containing glass and a metal to the laminate 2 and baking it. The baking layer may be co-fired with the internal electrodes 15 and the dielectric layers 14, or may be baked after the internal electrodes 15 are baked. Note that when the baking layer is co-fired with the internal electrodes 15 and the dielectric layers 14, it is preferable to form the baking layer by adding a dielectric material instead of the glass component. The thickness of the thickest part of the baking layer is preferably, for example, approximately 5 μm to 50 μm.

[0049] (When the base electrode layer 31 includes a resin layer) The resin layer may be multiple layers. The resin layer includes, for example, conductive particles and a thermosetting resin. When forming a resin layer, it may be formed directly on the laminate 2 without forming a baked electrode layer, or it may be formed so as to cover the baked layer. The resin layer may be formed on the surface of the baked layer, or it may be formed directly on the surface of the end face C without forming a baked layer. The thickness of the resin layer (at its thickest point) is preferably 5 μm or more and 150 μm or less.

[0050] (When the Base Electrode Layer 31 Includes a Thin Film Layer) The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0051] (Plating Layer 32) The plating layer 32 is disposed so as to cover the base electrode layer 31. The plating layer 32 contains, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The plating layer 32 may be formed of multiple layers.

[0052] Preferably, the base electrode layer 31 has a two-layer structure of Ni plating 321 and Sn plating 322. The Ni plating layer 321 prevents the base electrode layer 31 from being eroded by solder when mounting ceramic electronic components, and the Sn plating layer 322 improves the wettability of solder when mounting ceramic electronic components, facilitating mounting. The thickness of each plating layer 32 is preferably 0.5 μm or more and 10 μm or less.

[0053] (Method for Manufacturing Multilayer Ceramic Capacitor 1) The multilayer ceramic capacitor 1 of the embodiment can be manufactured, for example, by the following steps.

[0054] (1) Ceramic Green Sheet Preparation Process First, a conductive material such as a conductive paste that will become the internal electrodes 15 is printed on a ceramic material such as a ceramic green sheet that will become the dielectric layer 14, to prepare a ceramic green sheet on which an internal electrode pattern is formed.

[0055] (2) Lamination Step: Ceramic green sheets on which internal electrode patterns have been formed are laminated, and ceramic green sheets on and above them that do not have internal electrode patterns and that will become outer layer portions 12 are laminated to form a mother block.

[0056] (3) Pressing Step Next, the mother block is pressed. When pressing, rubber or the like is used to press from the surface that will become the second main surface A2 toward the first main surface A1. At this time, by applying a greater pressure near the center of the laminate 2 in the length direction L than at the ends in the length direction L, recesses 20 can be formed in the second main surface A2.

[0057] Here, the multilayer ceramic capacitor 1 of the embodiment has a butt-jointed structure of the internal electrodes 15. Therefore, the number of laminated internal electrodes 15 and dielectric layers 14 at the center in the length direction L is smaller than the number of laminated internal electrodes 15 and dielectric layers 14 at the end face C where the first internal electrode 15A and the second internal electrode 15B are drawn out. In addition, in the pressing process, the pressure near the center in the length direction L of the laminate 2 is made greater than the pressure at the end portions in the length direction L.

[0058] Therefore, in this pressing process, the dimension in the stacking direction T of the central part of the longitudinal direction L of the laminate 2 is made smaller than the dimension in the stacking direction T at the end face C, making it easy to form a recess 20 in the central part of the longitudinal direction L of the second main surface A2.

[0059] In addition to this manufacturing method, the recess 20 may be formed by reducing the thickness of the dielectric layer 14 in the portion where the recess 20 is to be formed, or by hollowing out the portion of the dielectric layer 14 for the outer layer portion where the internal electrode 15 is not printed.

[0060] (4) Cutting Step The pressed mother block is cut to a predetermined size to obtain an unfired laminate 2.

[0061] (5) Firing Step Next, the laminate 2 is fired.

[0062] (6) External Electrode Formation Step Next, the external electrodes 3 are formed by baking, plating, etc. Note that the external electrodes 3 may be formed by baking a part or all of them, excluding plating, simultaneously with the firing of the laminate 2.

[0063] Through the above steps, the multilayer ceramic capacitor 1 of the embodiment is manufactured.

[0064] (Mounting of Multilayer Ceramic Capacitor 1) In the multilayer ceramic capacitor 1, one external electrode 3 (first external electrode 3A) is connected to one land 51 via solder 52, and the other external electrode 3 (second external electrode 3B) is connected to the other land 51 via solder 52. In this way, the multilayer ceramic capacitor 1 of the embodiment is mounted on a substrate. The surface of the substrate 50 excluding the lands 51 is covered with an insulating film made of solder resist, leaving a predetermined mounting area.

[0065] Here, flux is used to promote soldering when the multilayer ceramic capacitor 1 is soldered to the substrate 50. After being mounted on the substrate, the multilayer ceramic capacitor 1 is washed to remove the flux.

[0066] However, insufficient cleaning may leave flux behind. If residual flux remains, migration may occur, an electrochemical phenomenon in which, when a voltage is applied between the electrodes of the multilayer ceramic capacitor 1, the anode metal ionizes, migrates to the cathode, and receives electrons at the cathode, depositing and growing as a metal, which may result in poor appearance or short circuits.

[0067] 3 , in the LT cross section of the multilayer ceramic capacitor 1 of the embodiment, a dimension T1 in the stacking direction T between the first main surface A1 and the second main surface A2 at the center in the longitudinal direction L is smaller than a dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 at both ends in the longitudinal direction L. Since the first main surface A1 of the laminate 2 is flat, a recess 20 is formed in the second main surface A2 of the laminate 2, with the center recessed in the stacking direction T, such that T1<T2.

[0068] Therefore, the space S between the portion of the laminate 2 on the second main surface A2, which is the surface on which the laminate 2 is mounted on the substrate, where the external electrodes 3 are not formed, and the substrate 50 becomes larger. This makes it easier for the flux cleaning solution to enter between the multilayer ceramic capacitor 1 and the substrate, reducing residue due to insufficient cleaning. As a result, problems caused by residual flux can be suppressed.

[0069] In this case, when T2 / T1 is 1.01 or more, the cleaning property using a cleaning liquid becomes good, and when it is 1.033 or more and 1.201 or less, the cleaning property becomes even better.

[0070] Furthermore, as shown in Figure 1, in the first side B1 and the second side B2 of the laminate 2, the dimension t1 in the stacking direction T between the first main surface A1 and the second main surface A2 at the center in the longitudinal direction L is smaller than the dimension t2 in the stacking direction T between the first main surface A1 and the second main surface A2 at both ends in the longitudinal direction L.

[0071] Therefore, the inlet and outlet of the deflux solution into the space S are enlarged on the first side surface B1 and the second side surface B2. This makes it easier for the deflux solution from the outside to flow into and out of the space S, improving the cleaning effect on the flux. As a result, problems caused by residual flux can be further suppressed.

[0072] As described above, in the multilayer ceramic capacitor 1 of the embodiment, the flux cleaning solution easily penetrates between the multilayer ceramic capacitor 1 and the substrate, so that residue due to insufficient cleaning is reduced. As a result, defects caused by residual flux can be suppressed.

[0073] (Verification of cleaning effect of multilayer ceramic capacitor 1 of embodiment) In order to verify the above effect, the multilayer ceramic capacitor 1 of the embodiment and a multilayer ceramic capacitor of a comparative embodiment were prepared, and the occurrence of appearance defects and short-circuit defects due to migration defects was examined.

[0074] (Verification Method) (1) As shown in Fig. 3, multilayer ceramic capacitors 1 according to Examples 1, 2, 3, 4, 5, 6, and 7 of the embodiment, in which the dimension T1 in the stacking direction T between the first main surface A1 and the second main surface A2 at the center in the length direction L in the LT cross section at the center in the width direction W is smaller than the dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 at both ends in the length direction L, with T2 / T1 being 1.01 or greater, and a multilayer ceramic capacitor according to Comparative Example 1, in which T1 is slightly larger than T2 and T2 / T1 is 0.998, were fabricated using the manufacturing method described above. The dimensions T1 and T2 and T2 / T1 of each capacitor are shown in the table of Fig. 4.

[0075] However, in the multilayer ceramic capacitor 1 of Comparative Example 1, the ceramic green sheets were stacked so that adjacent internal electrodes 15 in the stacking direction T overlapped with each other at the center of the length direction L, and the entire stacked sheets were pressed uniformly during pressing.

[0076] (2) 72 pieces of each of the multilayer ceramic capacitors of Comparative Example 1 and the multilayer ceramic capacitors 1 of Examples 1, 2, 3, 4, 5, 6, and 7 were randomly selected and the presence or absence of structural defects in appearance was observed using an optical microscope. The number of multilayer ceramic capacitors with structural defects was counted, and the structural defect rate was calculated using the total number of multilayer ceramic capacitors 1 used in the verification as the modulus. The results are shown in "Structural Defect Defect Rate" in Figure 4.

[0077] In Example 7, where the T2 / T1 value was 1.53, the structural defect rate was 2 / 72, but the structural defect rate was 0 / 72 in Comparative Example 1 and Examples 1, 2, 3, 4, 5, and 6. The reason why the structural defect rate in Example 7 was higher than in the other Examples is thought to be that the dielectric layer 14 was excessively stretched during the pressing process, and was fired in this state, causing cracks and fissures.

[0078] (3) Next, 72 of each of the multilayer ceramic capacitors used in (2) were mounted on a substrate, and a humidity resistance test was performed in which a voltage of 25 V was applied to the substrate on which the multilayer ceramic capacitors were mounted for 200 hours at a humidity of 95% and a temperature of 120°C.

[0079] (4) The appearance of the multilayer ceramic capacitor mounted on the substrate in (3) was observed with an optical microscope, and multilayer ceramic capacitors in which metal had precipitated on the surface of the laminate 2 where the first external electrode 3A and the second external electrode 3B were not formed were counted as migration defective products, and the migration defect rate was calculated using the total number of multilayer ceramic capacitors used in the verification as the modulus. The results are shown in "Migration Defect Rate" in Figure 4.

[0080] The migration defect rate of Comparative Example 1 was as high as 32 / 72. The migration defect rate of Example 1 was 9 / 72. The migration defect rate of Examples 2, 3, 4, 5, 6, and 7 was 0 / 72.

[0081] The judgment results based on the above verification results are shown in Figure 4. In Figure 4, a double circle (◎) indicates a migration defect rate of 0 / 72 and a structural defect defect rate of 0 / 72, a single circle (◯) indicates a migration defect rate or a structural defect defect rate of 0 / 72 and the other defect rate of 10 / 72 or less, and a cross (×) indicates a migration defect rate or a structural defect defect rate of more than 10 / 72.

[0082] As shown in Figure 4, when the T2 / T1 value is less than 1.0, as in Comparative Example 1, migration defects are likely to occur. However, it was confirmed that a good effect of suppressing migration defects was achieved when T2 / T1 was in the preferred range of 1.010 or more in the embodiment. Furthermore, a good effect of suppressing structural defects was confirmed when T2 / T1 was in the more preferred range of 1.033 or more and 1.201 or less in the embodiment.

[0083] (Modifications) Although the embodiment of the multilayer ceramic capacitor 1 has been described above, the present invention is not limited to the above, and various modifications such as those described below are also within the scope of the present invention.

[0084] (First variant) In the embodiment, as shown in FIG. 2 , in the WT cross section at the center of the longitudinal direction L, the dimension in the stacking direction T between the first main surface A1 and the second main surface A2 was constant from the position at 1 / 2 of the dimension in the width direction W to both ends in the width direction W (the first and second side surfaces B2).

[0085] However, the present invention is not limited to this. Fig. 5 is a diagram showing a multilayer ceramic capacitor 1A according to a first modified embodiment of the present invention. As shown in the figure, the capacitor may have a structure in which the dimension in the lamination direction T between the first main surface A1 and the second main surface A2 gradually decreases from the center in the width direction W to both ends in the width direction W (the first side surface B1 and the second side surface B2). In this case, the center in the width direction W may be convex on both the first main surface A1 and the second main surface A2.

[0086] The multilayer ceramic capacitor 1A of the first modified embodiment can also achieve the same effects as those of the embodiment. Furthermore, in the multilayer ceramic capacitor 1A of the first modified embodiment, the inlet and outlet of the defluxing liquid into the space S are larger than those of the multilayer ceramic capacitor 1 shown in Fig. 2. Therefore, the defluxing liquid can more easily flow in and out of the space S, further improving the cleaning performance.

[0087] Furthermore, in the first modified embodiment, the first main surface A1 and the second main surface A2 have the same shape, which allows either the first or second main surface A2 to be selected as the mounting surface.

[0088] Second Modified Embodiment In the embodiment, as shown in FIG. 3, the contour of the recess 20 formed on the second main surface A2 side in the LT cross section is an arc or an elliptical arc.

[0089] However, this is not limiting. Fig. 6 is a diagram showing a multilayer ceramic capacitor 1B according to a second modified embodiment of the present invention. As shown in the figure, the contour of the recess 20 formed on the second main surface A2 side may be in the shape of two sides of a triangle with the vertex at the center in the width direction W, i.e., two straight lines. The multilayer ceramic capacitor 1B according to the second modified embodiment can also achieve the same effects as those of the embodiment.

[0090] (Third Modified Form) In the embodiment, as shown in FIG. 3 , the first main surface A1 is flat, and the second main surface A2, which is the substrate mounting side, is recessed in the stacking direction T to form the recess 20, but this is not limited to this.

[0091] 7 is a diagram showing a multilayer ceramic capacitor 1C according to a third modified embodiment. In the multilayer ceramic capacitor 1C according to the third modified embodiment, both the first main surface A1 and the second main surface A2, which is the substrate mounting side, may be recessed in the lamination direction T. The multilayer ceramic capacitor 1C according to the third modified embodiment also has the same effects as those of the embodiment.

[0092] (Fourth Variant) In the embodiment, as shown in FIG. 3 , the first main surface A1 is flat, and the second main surface A2, which is the substrate mounting side, is recessed in the stacking direction T to form a recess 20, and the outline of the recess 20 is a smooth arc or elliptical arc shape, but is not limited to this.

[0093] Fig. 8 is a diagram showing a multilayer ceramic capacitor 1D of a fourth modified embodiment. In the multilayer ceramic capacitor 1D of the fourth modified embodiment, both the first main surface A1 and the second main surface A2, which is the substrate mounting side, may be recessed in the lamination direction T. Furthermore, the outline of the recess 20 of the fourth modified embodiment may be in the shape of two sides of a triangle with the center of the width direction W as the vertex, i.e., two straight lines, in the cross section shown in Fig. 8. The multilayer ceramic capacitor 1D of the fourth modified embodiment also has the same effects as the embodiments.

[0094] Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various changes and modifications can be made as follows.

[0095] <1> A multilayer ceramic capacitor comprising: a laminate having a plurality of dielectric layers and a plurality of internal electrodes stacked alternately with one another; first and second main surfaces opposing each other in a stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction, wherein the plurality of internal electrodes have first internal electrodes extended to the first end surfaces and second internal electrodes extended to the second end surfaces; and a first external electrode disposed on the first end surface and a second external electrode disposed on the second end surface, wherein in a cross section of the laminate taken along the length direction and the stacking direction at a center part in the width direction, the dimension in the stacking direction between the first and second main surfaces at the center part in the length direction is smaller than the dimension in the stacking direction between the first and second main surfaces at both ends in the length direction.

[0096] <2> The multilayer ceramic capacitor according to <1>, wherein the length of the laminate is shorter than the width of the laminate.

[0097] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein, in the first side surface and the second side surface, the dimension in the stacking direction between the first main surface and the second main surface at a center portion in the longitudinal direction of the laminate is smaller than the dimension in the stacking direction between the first main surface and the second main surface at both end portions in the longitudinal direction.

[0098] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein in a cross section of the laminate taken along the length direction and the lamination direction at a center portion in the width direction, a dimension between the first main surface and the second main surface gradually increases in at least a part from the center portion in the length direction to both end portions in the length direction.

[0099] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first internal electrodes and the second internal electrodes do not overlap with each other in the stacking direction.

[0100] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the sum of the lengthwise dimensions of the first internal electrodes and the second internal electrodes is smaller than the lengthwise dimension of the laminate.

[0101] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the first external electrode is arranged from the first end surface to a portion of the first main surface and a portion of the second end surface, the second external electrode is arranged from the second end surface to a portion of the first main surface and a portion of the second end surface, the lengthwise dimension of the first internal electrode is shorter than the average lengthwise dimension of the first external electrodes arranged on the first main surface and the second main surface, and the lengthwise dimension of the second internal electrode is shorter than the average lengthwise dimension of the second external electrodes arranged on the first main surface and the second main surface.

[0102] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein the first internal electrode and the second internal electrode are present on the same plane along the width direction and the length direction.

[0103] <9> The multilayer ceramic capacitor according to any one of <1> to <8>, wherein the dielectric layers contain at least one of Ca, Sr, Zr, and Ti.

[0104] <10> The multilayer ceramic capacitor according to any one of <1> to <9>, wherein the first internal electrode, the second internal electrode, the first external electrode, and the second external electrode contain at least one of Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and Au.

[0105] <11> The multilayer ceramic capacitor according to any one of <1> to <10>, wherein the first internal electrodes and the second internal electrodes contain Cu.

[0106] <12> The multilayer ceramic capacitor according to any one of <1> to <11>, wherein the first external electrode and the second external electrode contain Cu and glass.

[0107] <13> The multilayer ceramic capacitor according to any one of <1> to <12>, wherein the first internal electrodes and the second internal electrodes contain Ni.

[0108] <14> The multilayer ceramic capacitor according to any one of <1> to <13>, wherein the first external electrode and the second external electrode contain Ni and a ceramic component.

[0109] <15> The multilayer ceramic capacitor according to any one of <1> to <14>, wherein T2 / T1 is 1.033 or more and 1.201 or less.

[0110] A: Main surface A1: First main surface A2: Second main surface B: Side surface B1: First side surface B2: Second side surface C: End surface C1: First end surface C2: Second end surface T: Stacking direction W: Width direction S: Space 1: Multilayer ceramic capacitor 3: External electrode 3A: First external electrode 3B: Second external electrode 11: Internal layer portion 12: External layer portion 14: Dielectric layer 15: Internal electrode 15A: First internal electrode 15B: Second internal electrode 20: Recess 50: Substrate 51: Land 52: Solder

Claims

1. A multilayer ceramic capacitor comprising: a plurality of dielectric layers and a plurality of internal electrodes alternately laminated with each other; a first main surface and a second main surface facing each other in the lamination direction; a first side surface and a second side surface facing each other in a width direction orthogonal to the lamination direction; and a first end surface and a second end surface facing each other in a length direction orthogonal to the lamination direction and the width direction, wherein the plurality of internal electrodes include a first internal electrode drawn out to the first end surface and a second internal electrode drawn out to the second end surface; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein in a cross section along the length direction and the lamination direction at the central portion in the width direction of the laminate, the dimension in the lamination direction between the first main surface and the second main surface at the central portion in the length direction is smaller than the dimension in the lamination direction between the first main surface and the second main surface at both ends in the length direction.

2. The multilayer ceramic capacitor according to claim 1, wherein the dimension of the laminate in the length direction is shorter than the dimension in the width direction.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein in the first side surface and the second side surface of the laminate, the dimension in the lamination direction between the first main surface and the second main surface at the central portion in the length direction is smaller than the dimension in the lamination direction between the first main surface and the second main surface at both ends in the length direction.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein in a cross section along the length direction and the lamination direction at the central portion in the width direction of the laminate, the dimension between the first main surface and the second main surface gradually increases at least in a part from the central portion in the length direction to both ends in the length direction.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the first internal electrode and the second internal electrode do not overlap in the lamination direction.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the total dimension of the first internal electrode and the second internal electrode in the length direction is smaller than the dimension of the laminate in the length direction.

7. The first external electrode is disposed across a part of the first main surface and a part of the second end surface from the first end surface. The second external electrode is disposed across a part of the first main surface and a part of the second end surface from the second end surface. The dimension of the first internal electrode in the length direction is shorter than the average dimension of the first external electrode disposed on the first main surface and the second main surface in the length direction. The dimension of the second internal electrode in the length direction is shorter than the average dimension of the second external electrode disposed on the first main surface and the second main surface in the length direction. The multilayer ceramic capacitor according to any one of claims 1 to 6.

8. The first internal electrode and the second internal electrode exist on the same plane along the width direction and the length direction. The multilayer ceramic capacitor according to any one of claims 1 to 7.

9. The dielectric layer contains at least one of Ca, Sr, Zr, and Ti. The multilayer ceramic capacitor according to any one of claims 1 to 8.

10. The first internal electrode, the second internal electrode, the first external electrode, and the second external electrode contain at least one of Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and Au. The multilayer ceramic capacitor according to any one of claims 1 to 9.

11. The first internal electrode and the second internal electrode contain Cu. The multilayer ceramic capacitor according to any one of claims 1 to 10.

12. The first external electrode and the second external electrode contain Cu and glass. The multilayer ceramic capacitor according to any one of claims 1 to 11.

13. The first internal electrode and the second internal electrode contain Ni. The multilayer ceramic capacitor according to any one of claims 1 to 12.

14. The first external electrode and the second external electrode contain Ni and a ceramic component. The multilayer ceramic capacitor according to any one of claims 1 to 13.

15. T2 / T1 is 1.033 or more and 1.201 or less. The multilayer ceramic capacitor according to any one of claims 1 to 14.

Images