Semiconductor device

Abstract

A semiconductor device 1 comprises a semiconductor substrate 10, an activation region-side electrode 20, an insulation layer 30, and a field plate 40. The semiconductor substrate 10 includes: a substrate region 12 of a first conductivity type; an activation region 14 of a second conductivity type that has a plurality of first corner portions 14a and a plurality of first side portions 14b; a surface semiconductor region 16 of the second conductivity type that is formed on the first main surface side so as to be in contact with the outer periphery of the activation region 14 in a plan view and has a smaller total dopant amount than the activation region 14; and a first region 18 which is formed so as to be positioned inside the corresponding first side portion 14b in the plan view and has a smaller total dopant amount than the activation region 14. With the semiconductor device 1, it is possible to reduce the size of the semiconductor device while achieving a higher breakdown voltage as compared with a semiconductor device having the guard ring structure, and to increase the breakdown resistance of the device as a whole.

Description

Semiconductor Devices Cross Reference

[0001] This application claims priority based on Japanese Patent Application No. 2024-7680, filed on January 22, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to a semiconductor device.

[0003] Conventionally, semiconductor devices having a guard ring formed in a peripheral region (semiconductor devices having a guard ring structure) have been known (see, for example, Patent Document 1). A semiconductor device 900 (hereinafter referred to as "conventional semiconductor device 900"), which is an example of a conventional semiconductor device, will be briefly described below.

[0004] As shown in FIG. 4 , the conventional semiconductor device 900 includes a semiconductor substrate 910, an active region side electrode 920 disposed on a first main surface of the semiconductor substrate 910, an insulating layer 930 in contact with the outer periphery of the active region side electrode 920 and disposed on the first main surface, a field plate 940 in contact with the outer periphery of the active region side electrode 920 and disposed on the insulating layer 930, a second electrode 950, and a channel stop electrode 960.

[0005] The semiconductor substrate 910 is ＋ type semiconductor regions 912a and n － and a p-type base region 912 having an n-type semiconductor region 912b and a p-type electrode 920 formed on the first main surface side so that at least a portion of the p-type base region 912b overlaps with an active region side electrode 920 when viewed in plan. ＋ The semiconductor device has an active region 914, a plurality of guard rings 916 formed to surround the periphery of the active region 914 at a distance in plan view, and a channel stopper 919. The active region side electrode 920 and the field plate 940 constitute a first electrode.

[0006] In conventional semiconductor device 900, semiconductor substrate 910 has multiple guard rings 916 in the peripheral region, which allows the depletion layer that spreads from the pn junction between activation region 914 and substrate region 912 to spread to the peripheral region when reverse bias is applied, and also makes it possible to reduce the curvature of the depletion layer. Therefore, conventional semiconductor device 900 can increase the breakdown voltage compared to a semiconductor substrate 910 that does not have guard rings 916.

[0007] Japanese Patent Application Publication No. 10-173174

[0008] In order to obtain a high breakdown voltage in a semiconductor device with a guard ring structure such as conventional semiconductor device 900, it is necessary to increase the number of guard rings, but increasing the number of guard rings requires increasing the area of ​​the peripheral region. As a result, it is difficult to miniaturize a semiconductor device with a guard ring structure while achieving a high breakdown voltage.

[0009] Furthermore, in semiconductor devices with a guard ring structure, the breakdown voltage at the corners is often lower than that at the edges when reverse bias is applied. For example, at the apex of the corner of guard ring 916 in conventional semiconductor device 900, the depletion layer is less likely to extend due to charge balance. Note that, when the outer edge of the corner of the guard ring is an arc shape with a central angle of 90° in plan view, as in conventional semiconductor device 900, the apex of the corner of the guard ring is a point at a central angle of 45°.

[0010] In semiconductor devices with a guard ring structure, avalanche breakdown occurs near the apex of the corners of the guard ring before it occurs at the edges of the guard ring, resulting in a high current density at the corners, which results in a problem of reduced breakdown resistance for the entire device.

[0011] The present invention has been made to solve the above-mentioned problems, and has as its object to provide a semiconductor device that can be made smaller while achieving a higher breakdown voltage than semiconductor devices with a guard ring structure, and that can increase the breakdown resistance of the device as a whole.

[0012] The semiconductor device of the present invention comprises a semiconductor substrate, an activation region side electrode disposed on a first main surface of the semiconductor substrate, an insulating layer in contact with the outer periphery of the activation region side electrode and disposed on the first main surface, and a field plate in contact with the outer periphery of the activation region side electrode and disposed on the insulating layer, wherein the semiconductor substrate has a first conductivity type substrate region, a second conductivity type activation region formed on the first main surface side so as to overlap at least a portion of the activation region side electrode in a planar view and having a plurality of first corner portions and a plurality of first side portions, a second conductivity type surface semiconductor region formed on the first main surface side so as to contact the outer periphery of the activation region in a planar view and having a smaller total impurity content than the activation region, and a first region formed so as to be located inside the corresponding first side portion in a planar view and having a smaller total impurity content than the activation region.

[0013] In the semiconductor device of the present invention, the semiconductor substrate has a surface semiconductor region of a second conductivity type formed on the first main surface side so as to contact the periphery of the active region in plan view, and the surface semiconductor region has a smaller total impurity concentration than the active region. In the semiconductor device of the present invention, both the substrate region and the surface semiconductor region can be depleted under reverse bias, eliminating the need to increase the area of ​​the peripheral region to achieve a high breakdown voltage. Therefore, the semiconductor device of the present invention can be made smaller while still achieving a higher breakdown voltage than semiconductor devices with a guard ring structure.

[0014] In the semiconductor device of the present invention, the semiconductor substrate has a first region formed so as to be located inside the corresponding first edge portion in a plan view, and having a smaller total impurity concentration than the active region. While the breakdown voltage is determined by the area of ​​the extension of the depletion layer, in the semiconductor device of the present invention, the first region is formed inside the first edge portion of the active region, thereby narrowing the extension of the depletion layer near the first region and reducing the breakdown voltage in the edge portion. Therefore, with the semiconductor device of the present invention, avalanche breakdown is more likely to occur in the edge portion when reverse biased, thereby increasing the breakdown voltage of the entire device.

[0015] Therefore, the semiconductor device of the present invention can be made smaller while achieving a higher breakdown voltage than semiconductor devices with a guard ring structure, and can also be made to have a higher breakdown resistance as a whole.

[0016] 1A and 1B are diagrams illustrating a semiconductor device 1 according to a first embodiment. FIG. 1A is a plan view of the semiconductor device 1. FIG. 1B is a cross-sectional view (including a first corner portion 14a) of FIG. 1A taken along A1-A1. FIG. 1C is a cross-sectional view (including a first side portion 14b) of FIG. 1A taken along A2-A2. The term "plan view" used herein refers to a view of the semiconductor device as seen from the first main surface of the semiconductor substrate (the side on which the active region-side electrode is disposed). In FIG. 1A, the active region-side electrode 20, insulating layer 30, and field plate 40 are not shown in order to show the shapes of the active region 14, surface semiconductor region 16, and first region 18. The method of depicting each component is the same as in FIG. 1A in plan views according to embodiments other than FIG. 1A, which will be described later. A diagram illustrating a semiconductor device 2 according to a second embodiment. FIG. 2A is a plan view of the semiconductor device 2. 2(b) is a cross-sectional view taken along A3-A3 in FIG. 2(a) (a cross-sectional view including the first corner portion 14a). FIG. 2(c) is a cross-sectional view taken along A4-A4 in FIG. 2(a) (a cross-sectional view including the first side portion 14b). It is a plan view for explaining a semiconductor device 3 according to a modified example. It is a diagram for explaining a conventional semiconductor device 900. FIG. 4(a) is a plan view of the semiconductor device 900. FIG. 4(b) is a cross-sectional view taken along A-A in FIG. 4(a). In FIG. 4(a), the active region side electrode 920, the insulating layer 930, and the field plate 940 are not shown in order to show the shapes of the active region 914 and the guard ring 916.

[0017] The semiconductor device of the present invention will be described below based on the embodiments shown in the drawings. In each embodiment described below, components having the exact same or substantially the same functions will be designated by common reference numerals in each embodiment, even if their shapes are slightly different, and descriptions already given may be omitted. The embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in each embodiment are necessarily essential to the solution of the present invention.

[0018] [Embodiment 1] A semiconductor device 1 according to embodiment 1 is a planar diode. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 10, an active region side electrode 20, an insulating layer 30, a field plate 40, and a second electrode 50. The active region side electrode 20 and the field plate 40 form a first electrode. The semiconductor device 1 may include components other than those described above. Note that, among the drawings including FIG. 1, those showing the configuration of the semiconductor device are schematic diagrams, and the sizes of the illustrated components do not necessarily correspond to the sizes of the actual components. Each component will be described below.

[0019] The semiconductor substrate 10 has a substrate region 12, an active region 14, a surface semiconductor region 16, a first region 18, and a channel stopper 19. The material of the semiconductor substrate 10 is, for example, Si.

[0020] The substrate region 12 is n ＋ type semiconductor regions 12a and n － The n-type semiconductor region 12b is a region of the first conductivity type (n-type in the semiconductor device 1). ＋ The surface impurity concentration of the type semiconductor region 12a is, for example, 1×10 ２０ cm －３ In addition, n ＋ The depth (n ＋ The thickness of the n-type semiconductor region 12a can be set to, for example, 5 to 90 μm. － The surface impurity concentration of the n-type semiconductor region 12b is ＋lower than the type semiconductor region 12a, for example, 5.0×10 １３ ~4.0 x 10 １４ cm －３ In addition, n － The thickness of the type semiconductor region 12b can be set to, for example, 40 to 200 μm.

[0021] The activation region 14 is a second conductivity type (p-type in the semiconductor device 1) region formed on the first main surface so that at least a portion of the activation region electrode 20 overlaps the activation region electrode 20 in a plan view. The activation region 14 has multiple first corners 14a and multiple first side portions 14b. In this specification, "plan view" refers to viewing the target component from the first main surface side of the semiconductor substrate (the side on which the activation region electrode is located). In this specification, the term "first corner" refers to a corner portion of the outer edge of the activation region, which can also be considered as a portion connecting two first side portions with different orientations. In this specification, the term "first side portion" refers to a straight portion of the outer edge of the activation region. In this specification, the "outer edge" of a region of the semiconductor substrate refers to the outer edge of a portion where the depth (thickness) of the region is approximately constant, rather than the tip of a side diffusion portion where the depth of the region rapidly decreases.

[0022] In this specification, when the term "corner portion" is used without referring to a specific region, it refers to the portion of the semiconductor device extending from the activation region including the first corner portion to the outer periphery. For example, FIG. 1B can be considered a cross-sectional view showing the corner portion of semiconductor device 1. In addition, when the term "side portion" is used without referring to a specific region, it refers to the portion of the semiconductor substrate extending from the activation region including the first side portion to the outer periphery. For example, FIG. 1C can be considered a cross-sectional view showing the side portion of semiconductor device 1.

[0023] The activation region 14 in the semiconductor device 1 is a region having an outer periphery in which a plurality of first corners 14a and a plurality of first sides 14b are alternately arranged. The activation region 14 has four first corners 14a and four first sides 14b, and the first corners 14a are arc-shaped with a central angle of 90°. Therefore, the activation region 14 has a substantially rectangular shape with rounded corners when viewed in plan. The surface impurity concentration of the activation region 14 is, for example, 1×10 １６ ~5 x 10 １９ cm －３ The total impurity concentration in the active region 14 can be, for example, 1.7×10 １２ cm －２ The depth of the active region 14 can be set to, for example, 4 to 10 μm.

[0024] The maximum depth of the activation region 14 is deeper than the maximum depth of the surface semiconductor region 16. Note that the "depth" of a region of the semiconductor substrate is based on the first main surface unless otherwise specified.

[0025] The surface semiconductor region 16 is formed on the first main surface side so as to contact the outer periphery of the activation region 14 in plan view, and is a region of the second conductivity type (p-type in the semiconductor device 1) having a smaller total impurity concentration than the activation region 14. In this specification, the "total impurity concentration" refers to the value obtained by integrating the impurity concentration distribution in the depth direction from the surface (the amount of activated impurity per unit area). Note that the total impurity concentration is also related to the dose amount (the amount of impurity implanted), but there are cases in which an appropriate correlation is not necessarily obtained between the breakdown voltage and the dose amount. This is due to the fact that the amount of impurity can change due to heat treatment, etc.

[0026] The surface semiconductor region 16 has a generally rectangular shape with rounded corners when viewed from above. The total impurity concentration of the surface semiconductor region 16 is, for example, 0.5×10 １２ ~1.25 x 10 １２ cm －２ The depth of the surface semiconductor region 16 can be set to, for example, 3 to 6 μm.

[0027] The first region 18 is formed so as to be located inside the corresponding first side portion 14b in plan view, and is a region having a smaller total impurity concentration than the activation region 14. The first region 18 can also be said to be a region formed so as to be located inside the first side portion 14b, in which the activation region 14 is not formed. Note that "inside the first side portion" can also be said to be the activation region side when the first side portion is used as a reference.

[0028] The first region 18 in the semiconductor device 1 is a region of the second conductivity type (p-type in the semiconductor device 1) having a smaller total impurity concentration than the activation region 14. The maximum depth of the first region 18 is shallower than the maximum depth of the activation region 14. The total impurity concentration and maximum depth of the first region 18 can be, for example, approximately the same as the total impurity concentration and maximum depth of the surface semiconductor region 16. The first region 18 in the semiconductor device 1 has a rectangular shape extending in a direction along the first side portion 14b when viewed in a plan view. Four first regions 18 are formed in the semiconductor device 1 corresponding to the four first side portions 14b. Furthermore, the first regions 18 are not formed inside the first corner portions 14a.

[0029] Here, when the semiconductor device 1 is viewed in cross section, the contact edge is the location where the three components, the semiconductor substrate 10, the active region-side electrode 20, and the insulating layer 30, meet. The contact edge is a location where crystal distortion is likely to occur, weakening the breakdown voltage. Therefore, it is preferable to increase the surface impurity concentration of the semiconductor substrate 10 at the contact edge to alleviate the depletion layer. For this reason, the first region 18 is formed more inward than the contact edge. To ensure a high surface impurity concentration at the contact edge, the distance between the first region 18 and the contact edge is preferably 5 μm or more, and more preferably 10 μm or more. Furthermore, from the viewpoint of reducing the breakdown voltage of the edge, the distance between the first region 18 and the contact edge is preferably 50 μm or less.

[0030] The width of the first region 18 in plan view is the width of the side diffusion portion (curvature portion) of the activation region 14 and the base region 12 (n －In order to ensure sufficient contact between first region 18 and active semiconductor region 12b to reduce the breakdown voltage at the edges, the width of first region 18 is preferably at least twice the depth of activation region 14. Furthermore, if first region 18 is too wide, the area of ​​activation region 14 will be small, so the width of first region 18 is preferably no more than 10 times the depth of activation region 14.

[0031] The channel stopper 19 is a region formed on the first main surface side of the outermost periphery of the semiconductor substrate 10 when viewed from above. ＋ The first conductivity type (n-type in the semiconductor device 1) has a higher impurity concentration than the first conductivity type semiconductor region 12a.

[0032] The active region side electrode 20 is disposed on the first main surface of the semiconductor substrate 10 .

[0033] The insulating layer 30 is disposed on the first main surface and in contact with the outer periphery of the active region-side electrode 20. The insulating layer 30 in the semiconductor device 1 is disposed so as to cover a part of the active region 14 including the outer periphery, the surface semiconductor region 16, the base region 12 on the outer periphery side of the surface semiconductor region 16, and a part of the channel stopper 19 including the inner periphery.

[0034] The field plate 40 is in contact with the outer periphery of the active region side electrode 20 and is disposed on the insulating layer 30. In the semiconductor device 1, the active region side electrode 20 and the field plate 40 are integrated as a first electrode, but in a plan view, the inner side of the inner periphery of the insulating layer 30 is the boundary, and the field plate 40 is the outer side. The field plate 40 in the semiconductor device 1 is disposed so as to overlap with a portion of the active region 14 and the surface semiconductor region 16 in a plan view.

[0035] The second electrode 50 is disposed on a second major surface of the semiconductor substrate 10 opposite to the first major surface.

[0036] The effects of the semiconductor device 1 according to the first embodiment will be described below.

[0037] In the semiconductor device 1 according to the first embodiment, the semiconductor substrate 10 has a surface semiconductor region 16 of the second conductivity type formed on the first main surface side so as to contact the outer periphery of the activation region 14 in a plan view, and having a smaller total impurity concentration than the activation region 14. In the semiconductor device 1 according to the first embodiment, both the substrate region 12 and the surface semiconductor region 16 can be depleted under reverse bias, so there is no need to increase the area of ​​the peripheral region in order to obtain a high breakdown voltage. Therefore, the semiconductor device 1 according to the first embodiment can be made smaller while achieving a higher breakdown voltage than a semiconductor device with a guard ring structure.

[0038] Furthermore, in the semiconductor device 1 according to the first embodiment, the semiconductor substrate 10 has a first region 18 formed so as to be located inside the corresponding first side portion 14b in plan view, and having a smaller total impurity concentration than the activation region 14. While the breakdown voltage is determined by the area of ​​the extension of the depletion layer, in the semiconductor device 1 according to the first embodiment, the first region 18 is formed inside the first side portion 14b of the activation region 14, so the extension of the depletion layer near the first region 18 is narrowed, and the breakdown voltage at the side portion can be reduced. Therefore, according to the semiconductor device 1 according to the first embodiment, avalanche breakdown is more likely to occur at the side portion when reverse bias is applied, thereby increasing the breakdown voltage of the entire device.

[0039] Therefore, the semiconductor device 1 according to the first embodiment can be made smaller while achieving a higher breakdown voltage than a semiconductor device with a guard ring structure, and can also increase the breakdown resistance of the entire device.

[0040] Furthermore, in the semiconductor device 1 according to the first embodiment, the maximum depth of the activation region 14 is deeper than the maximum depth of the surface semiconductor region 16. According to the semiconductor device 1 according to the first embodiment, a high breakdown voltage can be obtained without forming the surface semiconductor region 16 deep, which makes it possible to improve the productivity of the semiconductor device 1 and reduce the production cost.

[0041] In the semiconductor device 1 according to the first embodiment, the first region 18 is a second conductivity type region having a smaller total impurity concentration than the activation region 14, and the maximum depth of the first region 18 is shallower than the maximum depth of the activation region 14. Therefore, the presence of the first region 18 forms a cylindrical low total impurity portion in the activation region 14, and the side diffusion portion (curvature portion) of the activation region 14 near this portion and the base region 12 (n － The side diffusion portion (curvature portion) of the active region 14 near the first region 18 and the base region 12 (n-type semiconductor region 12b) come into contact with each other. － Therefore, the semiconductor device 1 according to the first embodiment can further reduce the breakdown voltage at the side portions, making it easier for avalanche breakdown to occur at the side portions when a reverse bias is applied, thereby further increasing the breakdown resistance of the device as a whole.

[0042] [Embodiment 2] A semiconductor device 2 according to embodiment 2 has a configuration similar to that of the semiconductor device 1 according to embodiment 1, but differs in the shape of the surface semiconductor region from that of the semiconductor device 1 according to embodiment 1. Specifically, in the semiconductor device 2, the surface semiconductor region 66 in the semiconductor substrate 60 has a rectangular outer periphery in a planar view (see FIG. 2). That is, the outer edges of the corners of the surface semiconductor region 66 are angular in a planar view. Furthermore, the channel stopper 69 in the semiconductor substrate 60 has a rectangular inner periphery in a planar view, corresponding to the shape of the surface semiconductor region 66. The configuration of the semiconductor substrate 60 is similar to that of the semiconductor substrate 10 according to embodiment 1, except for the shapes of the surface semiconductor region 66 and the channel stopper 69. Due to the shapes of the surface semiconductor region 66 and the channel stopper 69, the insulating layer 32 in the semiconductor device 2 also has a rectangular outer periphery in a planar view.

[0043] The semiconductor device 2 according to the second embodiment has a surface semiconductor region whose shape is different from that of the semiconductor device 1 according to the first embodiment, but the semiconductor substrate 60 in the semiconductor device 2 has a surface semiconductor region 66 and a first region 18. Therefore, like the semiconductor device 1 according to the first embodiment, the semiconductor device 2 according to the second embodiment can be made smaller while achieving a higher breakdown voltage than a semiconductor device with a guard ring structure, and can also be made to have a higher breakdown voltage tolerance as a whole.

[0044] Furthermore, in the semiconductor device 2 according to the second embodiment, the surface semiconductor region 66 has a rectangular outer periphery in plan view, which facilitates the extension of a depletion layer from the corners of the surface semiconductor region 66 under reverse bias, thereby reducing the electric field strength at the apexes of the corners of the surface semiconductor region 66 and increasing the breakdown voltage at the corners. As a result, the semiconductor device 2 according to the second embodiment makes it easier for avalanche breakdown to occur at the edges under reverse bias, thereby further increasing the breakdown voltage of the entire device.

[0045] The semiconductor device 2 according to the second embodiment also has the same effects as the semiconductor device 1 according to the first embodiment, except for the above effects.

[0046] Although the present invention has been described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments. The present invention can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0047] (1) The positions, sizes, etc. of the components described in the above embodiments are merely examples and may be changed within the scope that does not impair the effects of the present invention.

[0048] (2) In the second embodiment, the activation region 14 has the same shape as the activation region 14 in the first embodiment, but the present invention is not limited to this. The activation region 74 of the semiconductor substrate 70 in the semiconductor device 3 according to the modification is a second conductivity type region whose outer periphery is rectangular in plan view and has multiple first corner portions 74 a and multiple first side portions 74 b (see FIG. 3 ). Like the activation region 74 in the modification, the activation region may have a rectangular outer periphery in plan view. Note that, when the outer periphery of the activation region is rectangular, the corner portions of the field plate preferably have arc shapes centered on the vertices of the corner portions of the activation region.

[0049] (3) In the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this. The first conductivity type may be p-type and the second conductivity type may be n-type.

[0050] (4) Although the semiconductor devices 1 and 2 according to the above embodiments are planar diodes, the present invention is not limited to this. The present invention can also be applied to diodes other than planar diodes, transistors (e.g., MOSFETs), thyristors, and the like.

[0051] REFERENCE SIGNS LIST 1, 2, 3... semiconductor device, 10, 60, 70... semiconductor substrate, 12... substrate region, 14, 74... active region, 14a, 74a... first corner portion, 14b, 74b... first side portion, 16, 66... ​​surface semiconductor region, 18... first region, 20... active region side electrode, 30, 32... insulating layer, 40... field plate, 50... second electrode

Claims

1. A semiconductor device comprising a semiconductor substrate, an activation region side electrode disposed on a first main surface of the semiconductor substrate, an insulating layer disposed on the first main surface and in contact with an outer periphery of the activation region side electrode, and a field plate disposed on the insulating layer and in contact with the outer periphery of the activation region side electrode, wherein the semiconductor substrate includes a substrate region of a first conductivity type, an activation region of a second conductivity type formed on the first main surface side so as to at least partially overlap the activation region side electrode in a plan view and having a plurality of first corner portions and a plurality of first side portions, a surface semiconductor region of a second conductivity type formed on the first main surface side so as to be in contact with an outer periphery of the activation region in a plan view and having a smaller total impurity sum than the activation region, and a first region formed so as to be located inside a corresponding one of the first side portions in a plan view and having a smaller total impurity sum than the activation region.

2. The semiconductor device according to claim 1, wherein a maximum depth of the activation region is deeper than a maximum depth of the surface semiconductor region.

3. The semiconductor device according to claim 1 or 2, wherein the first region is a region of a second conductivity type having a smaller total impurity sum than the activation region, and a maximum depth of the first region is shallower than a maximum depth of the activation region.

4. The semiconductor device according to any one of claims 1 to 3, wherein an outer peripheral shape of the surface semiconductor region in a plan view is a rectangular shape.

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