Apparatus and method for changing refresh rate in adaptive synchronization operation

Abstract

According to various embodiments of the present disclosure, an operating method of a source apparatus is provided, the operating method comprising the steps of: receiving a hot plug detection (HPD) signal from a sink apparatus; receiving, from the sink apparatus, first information related to extended display identification (EDID) or DisplayID (DPID); identifying, on the basis of the first information from the sink apparatus, information about the minimum number of frames related to an adaptive synchronization (Adaptive-Sync) operation; performing rendering such that video information, in which a refresh rate is changed from a first refresh rate to a second refresh rate, is maintained at a number of frames greater than or equal to the information about the minimum number at a third refresh rate between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink apparatus.

Description

Device and method for performing injection rate change in adaptive synchronization operation

[0001] The present disclosure relates to a device and method for performing a refresh rate change in an adaptive sync operation. Specifically, the present disclosure relates to a device and method for setting a minimum number of frames to be maintained when changing a refresh rate in an adaptive sync operation.

[0002]

[0003] The Successive Frame Duration Increase / Decrease Tolerance parameter in the DisplayID's Adaptive-Sync Data block can control the amount of refresh rate change based on the Max Single Frame Duration. However, because this method only operates on individual frames, the brightness gradient can change rapidly.

[0004] However, if the adaptive-sync operation is performed through the minimum frame operation setting based on the minimum adaptive-sync frame number suggested in various embodiments of the present invention, the gradient of the brightness change according to the frame can be made gentler than the existing function, so that the user can perceive less brightness change when switching frame rates. The minimum frame operation setting based on the minimum adaptive-sync frame number suggested in various embodiments of the present invention can be used together with the successive frame duration increase / decrease, and can also exhibit technical effects alone.

[0005] The minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention can be used together with the successive frame duration increase / decrease or can be used alone.

[0006]

[0007] To solve the above-described problems, the present disclosure provides a device and method for performing a refresh rate change in an adaptive-sync operation.

[0008] The present disclosure provides a device and method for setting a minimum number of frames to be maintained when changing a refresh rate in an adaptive synchronization operation.

[0009] The technical problems to be achieved in the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present disclosure belongs from the description below.

[0010]

[0011] According to various embodiments of the present disclosure, a method of operating a source device is provided, comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or a DisplayID (DPID) from the sink device; identifying information on a minimum number of frames related to an adaptive-sync operation based on the first information of the sink device; performing rendering to maintain frames corresponding to a number greater than or equal to the minimum number information at a third refresh rate corresponding to a between the first refresh rate and the second refresh rate for video information whose refresh rate is changed from a first refresh rate to a second refresh rate; and transmitting the rendered video information to the sink device.

[0012] According to various embodiments of the present disclosure, a source device is provided, comprising: a processor; a memory; and a transceiver, wherein the memory stores instructions for performing operations based on what is executed by the processor, the operations comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or a DisplayID (DPID) from the sink device; identifying information on a minimum number of frames related to an adaptive-sync operation based on the first information of the sink device; performing rendering for video information whose refresh rate is changed from a first refresh rate to a second refresh rate so as to maintain a number of frames that is greater than or equal to the minimum number information at a third refresh rate corresponding to a range between the first refresh rate and the second refresh rate; and transmitting the video information on which the rendering has been performed to the sink device.

[0013] According to various embodiments of the present disclosure, a computer-readable medium storing one or more commands is provided, wherein the one or more commands perform operations based on being executed by one or more processors, the operations comprising: receiving a hot plug detection (HPD) signal from a sink device; receiving first information related to an Extended Display Identification (EDID) or a DisplayID (DPID) from the sink device; identifying information on a minimum number of frames related to an Adaptive-Sync operation based on the first information of the sink device; performing rendering for video information whose refresh rate is changed from a first refresh rate to a second refresh rate so as to maintain a number of frames that is greater than or equal to the minimum number of frames at a third refresh rate corresponding to a range between the first refresh rate and the second refresh rate; and transmitting the rendered video information to the sink device.

[0014]

[0015] To solve the above-described problem, the present disclosure can provide a device and method for performing a change in injection rate in an adaptive-sync operation.

[0016] The present disclosure may provide a device and method for setting a minimum number of frames to be maintained when changing a refresh rate in an adaptive synchronization operation.

[0017]

[0018] The accompanying drawings are intended to aid in understanding the present disclosure and, together with detailed descriptions, may provide embodiments of the present disclosure. However, the technical features of the present disclosure are not limited to specific drawings, and the features disclosed in each drawing may be combined with each other to form new embodiments. Reference numerals in each drawing may indicate structural elements.

[0019] FIG. 1 is a block diagram illustrating a system according to various embodiments of the present disclosure.

[0020] FIG. 2 is a diagram illustrating an example of Adaptive-Sync SDP transmission timing according to various embodiments of the present disclosure.

[0021] FIG. 3 is a diagram illustrating an example of the structure of a Display Range Limit Block in EDID1.4 according to various embodiments of the present disclosure.

[0022] FIG. 4 is a diagram illustrating an example of the structure of an Adaptive-Sync Data Block in DisplayID 2.0 / 2.1 / 2.1a according to various embodiments of the present disclosure.

[0023] Figure 5 is a diagram showing an example of brightness change according to frame when neither the Maximum Single Frame Duration Increase function nor the Minimum Frame number function is applied.

[0024] Figure 6 is a drawing showing an example of brightness change according to frame when the Maximum Single Frame Duration Increase function is applied and the Minimum Frame number function is not applied at all.

[0025] Figure 7 is a diagram showing an example of brightness change according to frame when both the Maximum Single Frame Duration Increase function and the Minimum Frame number function are applied.

[0026] Figure 8 is a diagram illustrating an example of a process for determining a Frame Range when a Source device performs Adaptive-Sync operation.

[0027] FIG. 9 is a diagram illustrating an example of a process for determining a Frame Range when a Source device performs an Adaptive-Sync operation according to various embodiments of the present disclosure.

[0028] FIG. 10 is a diagram illustrating an example of a signal flow diagram between a source device and a sink device according to various embodiments of the present disclosure.

[0029] FIG. 11 is a diagram illustrating an example of a signal flow diagram between a source device and a sink device according to various embodiments of the present disclosure.

[0030] FIG. 12 is a diagram illustrating an example of an operation method of a source device according to various embodiments of the present disclosure.

[0031]

[0032] In various embodiments of the present disclosure, “A or B” may mean “only A,” “only B,” or “both A and B.” In other words, in various embodiments of the present disclosure, “A or B” may be interpreted as “A and / or B.” For example, in various embodiments of the present disclosure, “A, B or C” may mean “only A,” “only B,” “only C,” or “any combination of A, B and C.”

[0033] In various embodiments of the present disclosure, a slash ( / ) or a comma may mean "and / or." For example, "A / B" may mean "A and / or B." Accordingly, "A / B" may mean "only A," "only B," or "both A and B." For example, "A, B, C" may mean "A, B, or C."

[0034] In various embodiments of the present disclosure, “at least one of A and B” may mean “only A,” “only B,” or “both A and B.” Furthermore, in various embodiments of the present disclosure, the expressions “at least one of A or B” or “at least one of A and / or B” may be interpreted as equivalent to “at least one of A and B.”

[0035] Additionally, in various embodiments of the present disclosure, “at least one of A, B and C” can mean “only A,” “only B,” “only C,” or “any combination of A, B and C.” Additionally, “at least one of A, B or C” or “at least one of A, B and / or C” can mean “at least one of A, B and C.”

[0036]

[0037] FIG. 1 is a block diagram illustrating a system according to various embodiments of the present disclosure.

[0038] Hereinafter, devices that transmit and receive video / audio / control data will be collectively referred to as an AV (audio / video) system. Examples of AV systems include HDMI and DisplayPort.

[0039] Referring to FIG. 1, an AV system may include a source device (100) and a sink device (200). In particular, a device transmitting audio / video data in the AV system may correspond to the source device (100), and a device receiving video / audio data may correspond to the sink device (200). In this case, cables and connectors may be provided as physical devices that connect the two devices to support data transmission and reception.

[0040] Cables and connectors can pair four channels, each providing a Transition Minimized Differential Signaling (TMDS) data channel and a TMDS clock channel. The TMDS data channels can be used to carry video data, audio data, and auxiliary data.

[0041] Additionally, the AV system provides the Video Electronics Standards Association (VESA) Display Data Channel (DDC). DDC is used to exchange configuration and status information between source and sink devices. The CEC protocol can provide high-level control functions between various audiovisual products in the user environment and can also be used optionally. In addition, the optional HEAC (HDMI Ethernet and Audio Return Channel) can provide ARC (Audio Return Channel) and Ethernet-compatible data networking between connected devices in the opposite direction from TMDS.

[0042] Video data, audio data, and additional data can be transmitted / received over three TMDS data channels. The TMDS clock, which typically runs the video pixel rate, is transmitted over the TMDS clock channel. The TMDS clock can be used as a frequency reference for data recovery on the three TMDS data channels at the receiver. At the source device, 8 bits of data per TMDS data channel can be converted into a 10-bit DC-balanced, transition-minimized sequence that can be serially transmitted at a rate of 10 bits per TMDS clock period.

[0043] To transmit audio data and additional data over TMDS channels, AV systems use a packet structure. To achieve high reliability for audio and control data, data can be transmitted as 10-bit words generated using BCH error correction and error reduction coding.

[0044] A source device can read the Enhanced Extended Display Identification Data (E-EDID) of a Display Data Channel (DDC) sink device to determine the sink device's configuration information and capabilities. E-EDID may also be referred to as EDID information hereinafter.

[0045] The utility line can be used for optional extensions such as HEAC.

[0046] The source device (100) can receive EDID (Extended Display Identification Data) information from the sink device (200) via a DDC channel. The source device (100) can parse the received EDID information to recognize configuration information and supported functions of the sink device (200). The EDID information can include at least one block containing various information regarding the sink device (200).

[0047] In particular, EDID information according to one embodiment of the present invention may include information on the function and power supply capability of the sink device (200) in power transmission and reception. The source device (100) recognizes the power transmission / reception capability of the sink device (200) through this EDID information, and accordingly transmits power to the sink device (200) or receives power from the sink device (200).

[0048] The source device (100) includes at least one of a display unit (110), a user input interface unit (120), a control unit (180), a transmitter (Tx), a memory unit (140), a storage unit (150), a multimedia unit (160), a power control unit (130), and a power supply unit (170).

[0049] The sink device (200) includes at least one of an EDID EEPROM (210), a power control unit (220), a display unit (230), a user input interface unit (240), a receiver (Rx), a control unit (280), a power supply unit (250), a memory unit (260), and a multimedia unit (270). Hereinafter, descriptions of units performing the same operation will not be repeated.

[0050] The source device (100) represents a physical device that transmits or streams content stored in the storage unit (150) to the sink device (200). The source device (100) can send a request message to the sink device (200) or receive and process a request message received from the sink device (200). The source device (100) can provide a UI that processes and transmits a response message transmitted by the sink device (200) in response to the transmitted request message to the user, and when the source device (100) includes a display unit (110), this UI can be provided as a display. In addition, the source device (100) can request the sink device (200) to supply power.

[0051] The sink device (200) receives content from the source device (100) and can transmit a request message to the source device (100) or process a message received from the source device (100) and transmit a response message. The sink device (200) can also provide a UI (User Interface) that processes the response message received from the source device (100) and transmits it to the user. If the sink device (200) includes a display unit, this UI can be provided as a display. In addition, the sink device (200) can supply power requested by the source device (100) to the source device (100).

[0052] The user input interface unit (120, 240) can receive a user's action or input, and as an example, the user input interface (120, 240) can correspond to a remote controller, a voice receiving / recognition device, a touch input sensing / receiving device, etc.

[0053] The control unit (180, 280) can control the overall operation of each device. In particular, the control unit (180, 280) can perform communication between units included in each device and control the operation of each unit.

[0054] The memory unit (140, 260) represents a volatile physical device in which various types of data are temporarily stored.

[0055] The storage unit (150) represents a non-volatile physical device capable of storing various types of data.

[0056] EDID EEPROM (210) represents an EEPROM that stores EDID information.

[0057] The above-described memory unit (140, 260), storage unit (150), and EDID EEPROM (210) all serve to store data, and they may all be collectively referred to as memory units.

[0058] The display unit (110, 230) can display received data or content, data stored in the memory unit, UI, etc. under the control of the control unit (180, 280).

[0059] The multimedia unit (160, 270) can play various types of multimedia. The multimedia unit (160, 270) may be implemented separately from the control unit (180, 280), or may be implemented as a single physical configuration with the control unit (180, 280).

[0060] The power supply unit (170, 250) can supply power required for the operation of the source device (100), the sink device (200) and the units included therein.

[0061] A transmitter (Tx) is a unit equipped in a source device (100) that transmits and receives data, and performs data transmission and reception including not only audio / video data but also messages such as commands, requests, actions, and responses between devices.

[0062] The receiver (Rx) is a unit equipped in the sink device (200) that transmits and receives data, and performs data transmission and reception including not only audio / video data but also messages such as commands, requests, actions, and responses between devices.

[0063] The power control unit (130, 220) can manage and control power transmission and reception between devices via a transmitter and receiver.

[0064] Among the above-described units, units other than the transmitter (Rx), receiver (Tx), and control unit (180, 280) may be optionally included in the source device (100) or the sink device (200) depending on the embodiment, and may not be essential component units.

[0065] Previously, AV systems did not support power transfer between source and sink devices. As a result, when operating portable devices for extended periods, the inconvenience of always having to connect an external power cable for optimal operation existed. To address this issue, this specification proposes a method for ensuring optimal AV system operation without the need for external devices by enabling the wired interface to support power transfer.

[0066] For convenience of explanation, below, a device that supplies (or transmits) power will be referred to as a P-source device, and a device that supplies (or receives) power will be referred to as a P-sync device. Additionally, a device that simultaneously supports the functions of a P-source device and a P-sync device will be referred to as a dual device.

[0067]

[0068] Background to various embodiments of the present disclosure

[0069] Adaptive-Sync operation

[0070] Adaptive-Sync is a technology used in computer graphics that synchronizes graphics cards and monitors to eliminate screen flickering and tearing. Adaptive-Sync was standardized by the Video Electronics Standards Association (VESA) along with DisplayPort Adaptive-Sync and HDMI VRR (Variable Refresh Rate) technologies.

[0071] Adaptive-Sync technology includes a communication protocol for communication between the graphics card and the monitor, as well as time-splitting technology for synchronization between the two. Therefore, Adaptive-Sync technology encompasses the following technical areas:

[0072] - Graphics Card Technology: To support Adaptive-Sync, the graphics card must support Variable Refresh Rate (VRR) technology. AMD offers FreeSync, and NVIDIA offers G-Sync, each with their own VRR technology.

[0073] - Communication Protocol Technology: Display connection interfaces supporting Adaptive-Sync require DisplayPort 1.2a or higher and HDMI 2.1 or higher. Furthermore, to use Adaptive-Sync, the graphics card and monitor must use the same communication protocol.

[0074] Monitor Technology: A monitor that supports Adaptive-Sync must support the graphics card's VRR technology. Additionally, a monitor that supports Adaptive-Sync must support the protocol for communicating with the graphics card.

[0075] - Time-slicing technology: Adaptive-Sync uses time-slicing technology to synchronize the monitor and graphics card. To achieve this, both the graphics card and monitor must use the same time-slicing technology.

[0076] Adaptive-Sync technology encompasses a variety of technologies, including graphics cards, communication protocols, monitors, and time-slicing technology, all of which work together to make Adaptive-Sync possible.

[0077]

[0078] Source device operation during live frame transmission

[0079] A source device that has both the PANEL REPLAY ENABLE register (DPCD 001B0h[0] = 1) set to enable the panel replay mode of the sink device and the ALPM enable bit (DPCD 00116h[0] = 1) set in the RECEIVER_ALPM_CONFIGURATION register transmits an Adaptive-Sync SDP on the VBlank line that corresponds to one of the following:

[0080] (1) Leading edge of VSync pulse -or-

[0081] (2) One line before the leading edge of the VSync pulse starting from the first video frame as shown in Figure 2-155.

[0082] If the source device does not set both bits (DPCD 001B0h[0] = 0 and / or DPCD 00116h[0] = 0), the source device may transmit on or before the lines specified above during the VBlank period.

[0083] Source Device Operation during Live Frame Transmission

[0084] A Source device that has set both the Source Device Enables Panel Replay Mode in Sink Device bit in the PANEL REPLAY ENABLE register (DPCD 001B0h[0] = 1) and ALPM Enable bit in theRECEIVER_ALPM_CONFIGURATION register (DPCD 00116h[0] = 1) shall transmit the Adaptive-Sync SDP at the VBlank line that corresponds to either of the following:

[0085] (1) The VSync pulse's leading edge, -or-

[0086] (2) One line before the VSync pulse's leading edge, starting with the first video frame, as illustrated in Figure 2-155

[0087] When a Source device has not set both bits (DPCD 001B0h[0] = 0 and / or DPCD 00116h[0] = 0), the Source device may transmit at the line specified above -or- earlier during the VBlank period.

[0088]

[0089] FIG. 2 is a diagram illustrating an example of Adaptive-Sync SDP transmission timing according to various embodiments of the present disclosure.

[0090] The following requirements apply to the source device regarding whether to transmit the Adaptive-Sync SDP one line before or on the leading edge of the VSync pulse:

[0091] (1) When DPCD 02214h[1] of the sink device is 0, the source device shall maintain DPCD 0011Bh[7] = 0 and transmit Adaptive-Sync SDP on the line corresponding to the leading edge of the VSync pulse in the first half line or in the first 3,840 pixel cycle, whichever comes first.

[0092] (2) When DPCD 02214h[1] of the Sink device = 1, the Source device can do one of the following:

[0093] (3) During video mode setup, set DPCD 0011Bh[7] = 1 and then transmit the entire Adaptive-Sync SDP one line early at any time during the line.

[0094] (4) Clear DPCD 0011Bh[7] = 0 during video mode setup and transmit Adaptive-Sync SDP in the first half of the line corresponding to the leading edge of the VSync pulse or in the first 1,920 pixel cycle, whichever comes first.

[0095] As for whether to transmit the Adaptive-Sync SDP on the VSync pulse's leading edge or one line earlier, the following mandates apply for the Source device:

[0096] (1) When the Sink device's DPCD 02214h[1] = 0, the Source device shall keep DPCD 0011Bh[7] = 0 and transmit the Adaptive-Sync SDP in the first half line -or- the first 3,840 pixel cycles, whichever comes first, on the line that corresponds to the VSync pulse's leading edge

[0097] (2) When the Sink device's DPCD 02214h[1] = 1, the Source device may perform either of the following:

[0098] (3) Set DPCD 0011Bh[7] = 1 during video mode set, and then transmit the entire Adaptive-Sync SDP one line earlier, at any time during the line, -or-

[0099] (4) Clear DPCD 0011Bh[7] = 0 during video mode set, and then transmit the Adaptive-Sync SDP in the first half line -or- the first 1,920 pixel cycles, whichever comes first, on the line that corresponds to the VSync pulse's leading edge

[0100]

[0101] Adaptive-Sync 동작 관련 DPCD

[0102] DPCD (DisplayPort Configuration Data Channel) is part of the DisplayPort connection interface and is a data channel for communication between a display device and a graphics card. DPCD is used by the graphics card to recognize the display device, configure its features, and share the DP connection status with the monitor. The following configurations are related to Adaptive-Sync DPCD operation.

[0103] (1) Source device adaptive synchronization operation requirements

[0104] This section defines the source device rules for the following Adaptive-Sync policies:

[0105] (1-1) Before and during video mode setting

[0106] (1-2) Transmitting live frames

[0107] Before working on setting the video mode, the source device must check the following:

[0108] (1-3) The Stream Sink of the connected Sink device meets the following VESA AdaptiveSync requirements:

[0109] (1-3-1) DisplayID Adaptive-Sync data block support

[0110] (1-3-2) Supports detailed timing with CVT v2.0 RB v3 timing or 350ppm offset exposed in DisplayID.

[0111] (1-4) The DPRX of the connected sink device complies with the VESA AdaptiveSync specification.

[0112] (1-4-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0113] (1-4-2) DPCD 02214h[0] = 1

[0114] (1) Source Device Adaptive-Sync Operation Mandates

[0115] This section defines Source device mandates for the following Adaptive-Sync policies:

[0116] (1-1) Before and during video mode set

[0117] (1-2) During live frame transmission

[0118] Before video mode set operation, a Source device shall verify the following:

[0119] (1-3) Stream Sink in the connected Sink device meets the following VESA AdaptiveSync mandates:

[0120] (1-3-1) Supports the DisplayID Adaptive-Sync data block

[0121] (1-3-2) Supports the CVT v2.0 RB v3 timing -or- detailed timing with 350-ppm offset exposed in the DisplayID

[0122] (1-4) DPRX in the connected Sink device meets the VESA AdaptiveSync mandates:

[0123] (1-4-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0124] (1-4-2) DPCD 02214h[0] = 1

[0125]

[0126] (2) Requirements for adaptive synchronization operation of sink devices

[0127] This section defines the sink device rules for the following Adaptive-Sync policies:

[0128] (2-1) Before and during video mode setting

[0129] (2-2) Transmitting live frames

[0130] VESA AdaptiveSync sync devices must meet the following:

[0131] (2-3) DisplayID Adaptive-Sync data block support

[0132] (2-4) CVT v2.0 RB v3 timing support or detailed timing support with 350ppm offset exposed in DisplayID

[0133] (2-5) Adaptive-Sync SDP v2 support (HB2[4:0] = 02h)

[0134] (2-6) Set the following Adaptive-Sync DPCD function register bits to their default values.

[0135] (2-6-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0136] (2-6-2) DPCD 02214h[0] = 1

[0137] (2-7) Set DPCD 02214h[1] = 1 as needed

[0138] (2-8) Arm for Adaptive-Sync operation when the source device writes DPCD 00107h[7] = 1 while video mode is set.

[0139] (2-9) Since the sink device may be connected to a legacy source device that sets DPCD 00107h[7] = 1 and starts receiving the video stream after the video mode setting operation, it must check for the presence of an Adaptive-Sync SDP, but it does not transmit an Adaptive-Sync SDP. As long as all of the following conditions are met, the VESA AdaptiveSync Sink device must parse the Adaptive-Sync SDP payload data bytes and display the image within the latency constraints while meeting the Adaptive-Sync display CTS visual performance requirements (e.g., flicker performance greater than -50 dB, panel overdrive compensation, and responsive gray-to-gray transitions that do not cause ghosting):

[0140] (2-10) The source device follows the frame period increase and decrease limits of the sink device listed in the Adaptive-Sync data block (bytes 1 and 5, respectively).

[0141] (2-11) The Adaptive-Sync SDP payload content is true. VESA AdaptiveSync sink devices must also meet the minimum visual performance requirements (e.g., -45 dB flicker performance) as long as the source device adheres to the min-max refresh range. This also applies if the Adaptive-Sync SDP payload content is false for one frame during the Adaptive-Sync operating mode transition.

[0142] (2) Sink Device Adaptive-Sync Operation Mandates

[0143] This section defines Sink device mandates for the following Adaptive-Sync policies:

[0144] (2-1) Before and during video mode set

[0145] (2-2) During live frame transmission

[0146] A VESA AdaptiveSync Sink device shall:

[0147] (2-3) Support the DisplayID Adaptive-Sync data block

[0148] (2-4) Support the CVT v2.0 RB v3 timing -or- detailed timing with 350-ppm offset exposed in the DisplayID

[0149] (2-5) Support Adaptive-Sync SDP v2 (HB2[4:0] = 02h)

[0150] (2-6) Set the following Adaptive-Sync DPCD capability register bits as default:

[0151] (2-6-1) DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1

[0152] (2-6-2) DPCD 02214h[0] = 1

[0153] (2-7) Set DPCD 02214h[1] = 1, as needed

[0154] (2-8) Arm for Adaptive-Sync operation when a Source device writes DPCD 00107h[7] = 1 during video mode set

[0155] (2-9) Sink device shall check for the presence of an Adaptive-Sync SDP as the Sink device starts receiving a video stream after video mode set operation because the Sink device may be connected to a legacy Source device that sets DPCD 00107h[7] = 1 but does not transmit an Adaptive-Sync SDP A VESA AdaptiveSync Sink device shall parse Adaptive-Sync SDP payload data bytes and display an image within a latency limit while meeting Adaptive-Sync Display CTS visual performance mandates (e.g., flicker performance of -50 dB or better, a responsive gray-to-gray transition without causing panel overdrive compensation ghosting), as long as both of the following conditions are met:

[0156] (2-10) Source device honors the Sink device's Frame Duration Increase and Decrease Limits that are enumerated in the Adaptive-Sync data block (Bytes 1 and 5, respectively)

[0157] (2-11) Adaptive-Sync SDP payload content is true

[0158] The VESA AdaptiveSync Sink device shall also meet the minimum visual performance mandates (e.g., a flicker performance of -45 dB) as long as the Source device honors the minimum-to-maximum refresh range even when the Adaptive-Sync SDP payload content is false for one frame during an Adaptive-Sync operation mode transition.

[0159]

[0160] (3) Adaptive-Sync에 사용되는 DPCD 레지스터

[0161] (3) DPCD Registers used for Adaptive-Sync

[0162] 다음의 표 1은 Table 2-220: DPCD Registers Used for Adaptive-Sync를 나타낸다.

[0163] TypeDPCD Register AddressNameCapability0007h[6]DOWN_STREAM_PORT_COUNT register,MSA_TIMING_PAR_IGNORED bitExtended Capability02207h[6]DOWN_STREAM_PORT_COUNT register,MSA_TIMING_PAR_IGNORED bit02215h[2,1,0]DPRX_FREATURE_ENUMERATION_LIST_CONT_1 register,FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED,AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED, andADAPTIVE_SYNC_SDP_SUPPORTED bits, respectively02218h[6]DPRX_FEATURE_ENUMERATION_LIST_CONT_2 register,ADAPTIVE SYNC SDP T2 SUPPORTED IN ALL PR ACTIVE STATES bitConfiguration00107h[7,6]DOWNSPREAD_CTRL register, MSA_TIMING_PAR_IGNORE_EN andFIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE bits0011Ah[7:6]PANEL REPLAY CONFIGURATION 3 register,AS_SDP_SETUP_CONFIG_PR_ACTIVE field0011Bh[7]ADAPTIVE_SYNC_SDP_TRANSMISSION_TIMING_CONFIG register,AS_SDP_ONE_LINE_EARLIER_ENABLE bit

[0164] Adaptive-Sync 동작 관련 EDID - DisplayID에서의 Adaptive-Sync Data Block

[0165] FIG. 3 is a diagram illustrating an example of the structure of a Display Range Limit Block in EDID1.4 according to various embodiments of the present disclosure.

[0166] EDID (Extended Display Identification Data) is a data structure used by a source device (e.g., GPU) to read information embedded in a sink device (e.g., monitor). When a sink device (e.g., monitor) provides EDID information, the source device (e.g., GPU) can automatically recognize and set the sink device's (e.g., monitor's) optimal resolution, refresh rate, and other basic settings.

[0167] EDID contains information about how the Sink device (e.g., monitor) was manufactured, including the manufacturer, model name, manufacturing date, resolution, and supported refresh rates. The Source device (e.g., GPU) that reads this information can automatically set the optimal resolution and refresh rate for the Sink device (e.g., monitor), or the user can manually set them.

[0168] Blocks related to Adaptive-Sync operation can be expressed as shown in Table 2 below.

[0169] Table 2 below shows Table 3.26: Display Range Limits & Timing Descriptor Block Definition.

[0170] Byte #ValueDisplay Range Limits Definitions0, 1(00 00)hIndicates that this 18 byte descriptor is a Display Descriptor200hReserved: Set to 00h when 18 byte descriptor is used as a Display Descriptor3FDhTag Number for Display Range Limits Descriptor47 6 5 4 3 2 1 0Display Range Limits Offsets: FLAGs0 0 0 0_ _ 0 0Vertical Rate Offsets are zero0 0 0 0_ _ 1 0Max. Vertical Rate + 255 Hz Offset; Min. Vertical Rate is not offset0 0 0 0_ _ 1 1Max. Vertical Rate + 255 Hz Offset; Min. Vertical Rate + 255 Hz Offset0 0 0 00 0Horizontal Rate Offsets are zero0 0 0 01 0 _ _Max. Horizontal Rate + 255 kHz Offset; Min. Horizontal Rate is not offset0 0 0 01 1 _ _Max. Horizontal Rate + 255 kHz Offset; Min. Horizontal Rate + 255 kHz Offset01h, 04h → 07h, 09h,0Dh 10h → FFhReserved: Do not use501h → FFhMinimum Vertical Rate: (for interlace this refers to the field rate)[Byte 4, Bits 1, 0] ≠ 11Binary coded rate in Hz, integer only (range is 1 Hz to 255 Hz)[Byte 4, Bits 1, 0] = 11Binary coded rate in Hz,integer only (range is 256 Hz to 510 Hz)00hReserved: Do not use601h → FFhMaximum Vertical Rate: (for interlace this refers to the field rate)[Byte 4, Bit 1] ≠ 11Binary coded rate in Hz, integer only (range is 1 Hz to 255 Hz)[Byte 4, Bit 1] = 11Binary coded rate in Hz, integer only (range is 256 Hz to 510 Hz)Note: Minimum rate value shall be less than or equal to maximum rate value00hReserved: Do not use701h → FFhMinimum Horizontal Rate:[Byte 4, Bits 3, 2] ≠ 11Binary coded rate in kHz, integer only (range is 1 kHz to 255 kHz)[Byte 4, Bits 3, 2] = 11Binary coded rate in kHz, integer only (range is 256 kHz to 510 kHz)00hReserved: Do not use801h → FFhMaximum Horizontal Rate:[Byte 4, Bit 3] ≠ 11Binary coded rate in kHz, integer only (range is 1 kHz to 255 kHz)[Byte 4, Bit 3] = 11Binary coded rate in kHz,integer only (range is 256 kHz to 510 kHz)Note: Minimum rate value shall be less than or equal to maximum rate value00hReserved: Do not use901h → FFhMaximum Pixel Clock:Binary coded clock rate in MHz / 10, Example: 130MHz is '0Dh'Note: Maximum Pixel Clock shall be rounded to the nearest multiple of 10 MHz00hReserved: Do Not Use10Video Timing Support Flags: Bytes 10 → 17 indicate support for additional video timings00hDefault GTF supported if bit 0 in Feature Support Byte at address 18h = 101hRange Limits Only --- no additional timing information is provided02hSecondary GTF supported --- requires support for Default GTF04hCVT supported if bit 0 in Feature Support Byte at address 18h = 103h,05h → FFhReserved for future timing definitions --- Do Not Use110AhLine Feed (if Byte 10 = 00h or 01h)00h → FFhVideo Timing Data (if Byte 10 = 02h or 04h) --- Refer to Tables 3.27 → 3.281220hSpace (if Byte 10 = 00h or 01h)00h → FFhVideo Timing Data (if Byte 10 = 02h or 04h) --- Refer to Tables 3.27 → 3.28,

[0171] Adaptive-Sync Data Block in DisplayID 2.0 / 2.1 / 2.1a

[0172] FIG. 4 is a diagram illustrating an example of the structure of an Adaptive-Sync Data Block in DisplayID 2.0 / 2.1 / 2.1a according to various embodiments of the present disclosure.

[0173] Table 3 below shows Table 4.51: Adaptive-Sync Data Block.

[0174] In Table 3, N represents the number of detailed timing descriptors in the data block. M represents the value of offset 01h[6:4]. The source device implementation should accommodate varying fields for future extensibility. (N represents the number of detailed timing descriptors in the data block. M represents the value of offset 01h[6:4]. The source device implementation should accommodate varying fields for future extensibility.)

[0175] OffsetBit #Definition / Priority00h7:0Adaptive-Sync Data Block2Bh01hBlock Revision and Other Data2:0Block RevisionRevision ranges from 0 through 7000b=Revision 0All other values are RESERVED3RESERVEDCleared to 06:4Number of Payload Bytes (M) in an Adaptive-Sync Operation ModeAnd Range DescriptorWhere M (bytes) = 6 (initial descriptor size) + field value000b = 6 + 0 bytes / descriptor (defined as part of Adaptive0Sync, Revision 0)All other values are RESERVED7RESERVEDCleared to 002h7:0Number of Payload Bytes in BlockNumber of payload bytes within the block is based on the number of descriptors (N) * size of each descriptor (M) bytesAll other values are RESERVED03h through03h+M-1(M*8-1):0First Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor03h+M through 03h + 2M - 1(M*8-1):0Second Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor, if present......03h +(N-1) * M through03h+ (N*M) - 1(M*8-1):0Nth Adaptive-Sync Operation Mode and Range DescriptorM-byte descriptor, if present.

[0176] 다음의 표 4은 Table 4.52: Adaptive-Sync Operation Mode and Range Descriptor를 나타낸다.

[0177] Byte #Bit #Definition0Adaptive-Sync Operation and Range Information0Adaptive-Sync Range0 = Non-native panel range. (The display implements buffering to support the declared Adaptive-Sync range, and may repeat frames as necessary.)1 = Native panel range. (The display does not implement buffering to support the declared Adaptive-Sync range, and does not repeat frames.)1Successive Frame Duration Increase Tolerance for Meeting VESA Adaptive Sync Flicker Performance0 = Flicker performance is met in any duration increase within the refresh rate range, but may cause up to a single base video frame period jitter impact.1 = Flicker performance is met in any duration increase within Byte 1.Note: Flicker performance is met in any duration increase within the refresh rate range without jitter impact when either of the following conditions are met:(1) Byte 1 = 00h,-or-(2) Byte 1 >= the delta between the maximum frame duration ( = minimum refresh rate) and the minimum frame duration (= maximum refresh rate)3:2Supported Adaptive-Sync Modes00b = Fixed-Average VTotal (FAVT) mode is supported01b = Both Fixed-Average VTotal and Adaptive VTotal modes (FAVT and AVT, respectively) are supportedAll other values are RESERVED4Seamless Transition of Adaptive-Sync Mode and Range Not Supportd0 = Seamless transition to and from current Adaptive-Sync mode and range is supported1 = Seamless transition to and from current Adaptive-Sync mode and range is not supported5Successive Frame Duration Decrease Tolerance for Meeting VESA Adaptive Sync Flicker Performance0 = Flicker performance is met in any duration decrease within the refresh rate range,but may cause up to a single base video frame period jitter impact1 = Flicker performance is met in any duration decrease within Byte 5Note: Flicker performance is met in any duration decrease within the refresh rate range without jitter impact when either of the following conditions are met:(1) Byte 5 = 00h, -or-(2) Byte 5 >= the delta between the maximum frame duration(= minimum refresh rate) and the minimum frame duration (= maximum refresh rate)7:6RESERVEDCleared to all 0s17:0Maximum Single Frame Duration Increase Allowed for Meeting VESA Adaptive Sync Flicker Performance6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive00h = Flicker performance is met in any duration increase within the refresh rate range without jitter impact27:0Minimum Refresh RateMinimum refresh rate ranges from 0 through 255 Hz,divided by 1.00100h = 0 Hz01h = (1 / 1.001) Hz...FFh = (255 / 1.001) Hz4:3Maximum Refresh RateMaximum refresh rate ranges from 1 through 1,024 Hz, plus 350 ppm. Note that the value stored in this field shall match that of at least one CVT v2.0 RB Timing v3 timing supported by the Sink device000h = (1*1.00035) Hz...3FFh = (1,024 * 1.00035) Hz37:0Maximum Refresh Rate 7:041:0Maximum Refresh Rate 9:87:2RESERVEDCleared to all 0s57:0Maximum Single Frame Duration Decrease Allowed for Meeting VESA Adaptive Sync Flicker Performance6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive00h = Flicker performance is met in any duration decrease within the refresh rate range without jitter impact,

[0178] Adaptive-Sync SDP

[0179] The Adaptive-Sync Second data packet is used for communication between the graphics card and the display. The graphics card sends the Adaptive-Sync Second data packet to the display, which then informs the graphics card of its supported refresh rate range and VRR mode. Based on this information, the graphics card synchronizes with the display, preventing screen tearing and stutter, and enabling smoother display. The information and size of the Adaptive-Sync SDP may vary depending on the Adaptive-Sync operation parameters for each EDID block.

[0180] The Adaptive-Sync SDP operation and the information on Header and Payload Data Bytes are as follows.

[0181] In addition to setting the MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register (DPCD), an Adaptive-Sync capable DP protocol converter indicates Adaptive-Sync SDP support by setting the ADAPTIVE_SYNC_SDP_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST_CONT_1 register (DPCD 02214h[0] = 1, 00007h[6] = 1 and DPCD 02207h[6] = 1). An Adaptive-Sync capable DP protocol converter must support SDP splitting in SST and MST modes and indicate the splitting capability by setting the SST_SPLIT_SDP_CAP bit in the DPRX_FEATURE_ENUMERATION_LIST register (DPCD 02210h[1] = 1). An Adaptive-Sync-capable DP source device can enable Adaptive-Sync video transmission to a connected DP protocol converter only after verifying the following:

[0182] (1) The connected DP protocol converter has DPCD 00007h[6] = 1 and DPCD 02214h[0] = 1.

[0183] (2) A stream sink connected to a DP protocol converter indicates support for the Adaptive-Sync refresh rate range in its DisplayID or legacy EDID. As always for Adaptive-Sync video transmission, an Adaptive-Sync capable DP source device must use an AUX write transaction to set the MSA_TIMING_PAR_IGNORE_EN bit in the DOWNSPREAD_CTRL register (DPCD 00107h[7] = 1) before enabling Adaptive-Sync video transmission. If the connected DP device has DPCD 02214h[0] = 1, the DP source device must transmit an Adaptive-Sync SDP before enabling Adaptive-Sync video transmission.

[0184] When transmitting Adaptive-Sync SDP, the DP source device must:

[0185] (3) Transmit Adaptive-Sync SDP in every video frame. For multi-field video modes such as interlaced and 3D, Adaptive-Sync SDP must be transmitted in every video field.

[0186] (4) Ensure that the start and end of the Adaptive-Sync SDP transmission occur within the first half of the line corresponding to the start of the VSync pulse (indicated by the BS symbol sequence).

[0187] (5) Send valid HTotal[15:0], HStart[15:0], HSyncPolarity[0](HSP), HSyncWidth[14:0].

[0188] (HSW), VStart[15:0], VSyncPolarity[0](VSP) 및 VSyncWidth[14:0](VSW)는 Adaptive-Sync SDP를 전송하는 동안 유효한 HWidth[15:0] 및 VHeight[15:0]. 즉, Adaptive-Sync 가능 DP 프로토콜 변환기는 Adaptive-Sync SDP를 수신하는 동안 VTotal[15:0]만 무시해야 한다.

[0189] An Adaptive-Sync-capable DP protocol converter shall indicate Adaptive-Sync SDP support by setting the ADAPTIVE_SYNC_SDP_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST_CONT_1 register (DPCD 02214h[0] = 1) in addition to setting the MSA_TIMING_PAR_IGNORED bit in the DOWN_STREAM_PORT_COUNT register(s) (DPCD 00007h[6] = 1 and DPCD 02207h[6] = 1). An Adaptive-Sync-capable DP protocol converter shall support SDP splitting in SST and MST modes, and indicates its splitting capability by setting the SST_SPLIT_SDP_CAP bit in the DPRX_FEATURE_ENUMERATION_LIST register (DPCD 02210h[1] = 1). An Adaptive-Sync-capable DP Source device may enable an Adaptive-Sync video transmission to a plugged DP protocol converter only after verifying the following:

[0190] (1) Plugged DP protocol converter has DPCD 00007h[6] = 1 and DPCD 02214h[0] = 1

[0191] (2) Stream sink plugged to the DP protocol converter indicates support for the Adaptive-Sync refresh rate range in the DisplayID or legacy EDID As is always the case with Adaptive-Sync video transmission, an Adaptive-Sync-capable DP Source device shall use an AUX write transaction to write 1 to the MSA_TIMING_PAR_IGNORE_EN bit in the DOWNSPREAD_CTRL register (DPCD 00107h[7] = 1) prior to enabling an Adaptive-Sync video transmission. When the plugged DP device has DPCD 02214h[0] = 1, a DP Source device shall transmit an Adaptive-Sync SDP before enabling an Adaptive-Sync video transmission.

[0192] When transmitting an Adaptive-Sync SDP, a DP Source device shall do the following:

[0193] (3) Transmit an Adaptive-Sync SDP on every video frame. For multi-field video modes such as Interlaced and 3D, the Adaptive-Sync SDP shall be transmitted on every video field.

[0194] (4) Ensure that the start and end of the Adaptive-Sync SDP transmission occur within the 1st half of the line (marked by BS symbol sequences) that corresponds to the start of the VSync pulse.

[0195] (5) Transmit valid HTotal[15:0], HStart[15:0], HSyncPolarity[0] (HSP), HSyncWidth[14:0]

[0196] (HSW), VStart[15:0], VSyncPolarity[0] (VSP), and VSyncWidth[14:0] (VSW) while transmitting an Adaptive-Sync SDP, as well as valid HWidth[15:0] and VHeight[15:0]. That is, an Adaptive-Sync-capable DP protocol converter shall ignore only VTotal[15:0] while receiving an Adaptive-Sync SDP.

[0197]

[0198] 표 5은 Table 2-126: Adaptive-Sync SDP Header Bytes를 나타낸다.

[0199] Byte #Bit #ContentHB07:0Secondary-data Packet IDSpecific to stream (usually 00h)HB17:0Secondary-data Packet Type22h = Adaptive-SyncHB24:0Version Number01h = Version 1. No payload data bytes (same as DP v2.0, as released in June 2019).02h = Version 2. VESA AdaptiveSync shall support both the DisplayID Adaptive-Sync data block and Adaptive-Sync SDP data structure version 2.All other values are RESERVED for future versions.7:5RESERVEDRead all 0sHB35:0Number of Valid Data BytesVersion 100h = No payload data bytes.Version 209h = Nine payload data bytes.The Adaptive-Sync SDP has 32 payload data bytes. Unused data bytes shall be zero-padded.7:6RESERVEDRead all 0s.

[0200] 표 6은 Table 2-127: Adaptive-Sync SDP Version 2 Payload Data Bytes를 나타낸다.

[0201] Byte #Bit #ContentDB0Timing Options01VARIABLE_FRAME_RATE_DISABLEAdaptive Sync Operation ModeWhen a Source device sets the MSA_TIMING_PAR_IGNORE_EN and FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE bits in the DOWNSPREAD_CTRL register (DPCD 00107h [7,6] = 11b, respectively):00b = AVT mode, and video frame duration is bound to change from frame-to-frame.01b = AVT mode; however, video frame duration is currently fixed.10b = FAVT mode, and TRR is yet to be reached.11b = FAVT mode, and TRR is reached.When a Source device programs DPCD 00107h[7,6] = 01b (see Section 2.18 for details):01b = Adaptive-Sync operation is disabled and the VTotal line count is fixed.00b, 10b, and 11b = RESERVED.2Adaptive Sync SDP Transmission Disable in PR Active StateCleared to 0 when the Sink device does not support PR.0 = Source-to-Sink device timing sync using the Adaptive-Sync SDP is enabled.1 = Source-to-Sink device timing sync using the Adaptive-Sync SDP is disabled.3Remote Frame Buffer (RFB) Update in PR Active StateValid only during a PR Active state. Shall be driven to 0 in PR_State 0_0 (Disabled) -or-PR_State 0_1 (Inactive). Cleared to 0 when the Sink device does not support PR.0 = No RFB update in the current active video image time interval.1 = Update the RFB - Capture the incoming video frame / Sus to the RFB.7:4RESERVEDRead all 0s.DB17:0Minimum Vertical Total7:0Minimum Vertical Total15:8Source device shall program DB2:DB1 to the VTotal value that corresponds to the enabled base timing. The value is statically programmed and is valid in both FAVT mode and AVT mode.DB27:0DB37:0Target Refresh Rate7:0Target Refresh Rate9:8AVT modeSource device shall clear DB4[1:0] = 00b and DB3 = 00h.FAVT modeSource device shall program DB4[1:0] and DB3 and DV4[5] to match the average video frame rate.DB41:04:2RESERVEDRead all 0s.5Target Refresh Rate DividerValid only in FAVT mode. Sink device ignores the bit in AVT mode.0 = 1.000.1 = 1.001.6Successive Frame Duration Increase ConfigurationIf the Source device engages in a bounded transition for low-flicker performance by using information in the DisplayID Adaptive-Sync data block and setting this bit to 1, the Source device shall:(1) Use the CVT v2.0 RB Timing v3 -or- detailed timing descriptor with 350-ppm offset exposed in the DisplayID, and(2) Constrain the duration increase to the value reported in the DisplayID Adaptive-Sync data block for a guarantee of low-flicker performance0 = Video frame duration increase transitions are unbounded.1 = Video frame duration increase transitions are bounded by the time specified in DB5.7Successive Frame Duration Decrease ConfigurationIf the Source device engages in a bounded transition for low-flicker performance by using the information in the DisplayID Adaptive-Sync data block and setting this bit to 1, the Source device shall:(1) Use the CVT v2.0 RB Timing v3 -or- detailed timing descriptor with 350-ppm offset exposed in the DisplayID, and(2) Constrain the duration decrease to the value reported in the DisplayID Adaptive-Sync data block for a guarantee of low-flicker performance0 = Video frame duration decrease transitions are unbounded.1 = Video frame duration decrease transitions are bounded by the time specified in DB6.DB57:0Duration Increase Constraint Value in ms Unit6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive.When the Source device clears DB4[6] = 0, the Source device shall clear DB5 = 00h.When the Source device sets DV4[6] = 1, the Source device shall program DB5 to the value that the Source device is using for the maximum duration increase. The value does not indicate the instantaneous video frame-to-frame duration delta.A 0.00 value indicates that the Source device may invoke a maximum-to-minimum refresh rate transition across a single video frame boundary.To attain optimum flicker performance without jitter impact, the Source device shall keep the DB5 value less than or equal to the limit value reported by the Sink device in the Max Single Frame Duration Increase Allowed for Attaining the Low Flicker Performance byte (Byte 1) of the DisplayID Adaptive-Sync data block's Operation Mode and Range descriptor.DB67:0Duration Decrease Constraint Value in ms Unit6.2 format (six integer bits and two fractional bits) that results in a value range of 0.00 to 63.75 ms, inclusive.When the Source device clears DB4[7] = 0, the Source device shall clear DB6 = 00h.When the Source device sets DB4[7] = 1, the Source device shall program DB6 to the value that the Source device is using for the maximum duration decrease. The value does not indicate the instantaneous video frame-to-frame duration delta.A 0.00 value indicates that the Source device may invoke a maximum-to-minimum refresh rate transition across a single video frame boundary.To attain optimum flicker performance without jitter impact, the Source device shall keep the DB6 value less than or equal to the limit value reported by the Sink device in the Max Single Frame Duration Decrease Allowed for Attaining the Low Flicker Performance byte (Byte 5) of the DisplayID Adaptive-Sync data block's Operation Mode and Range descriptor.DB77:0Coasting VTotal7:0 in PR Active StateShall be programmed to the Coasting Vtotal LSB value that the Sink device shall use to maintain the refresh rate when the DPTX has suspended transmission of the Adaptive-Sync SDP in a PR Active state.DB7 = 00h when the Sink device does not support PR.DB87:0Coasting VTotall15:8 in PR Active StateShall be programmed to the Coasting VTotal MSB value that the Sink device shall use to maintain the refresh rate when the DPTX has suspended transmission of the Adpative-Sync SDP in a PR Active state.DB8 = 00h when the Sink device does not support PR.DB9throughDB31191:0RESERVEDRead all 0s.

[0202]

[0203] Problems with prior art

[0204] Figure 5 is a diagram showing an example of brightness change according to frame when neither the Maximum Single Frame Duration Increase function nor the Minimum Frame number function is applied.

[0205] Figure 6 is a drawing showing an example of brightness change according to frame when the Maximum Single Frame Duration Increase function is applied and the Minimum Frame number function is not applied at all.

[0206] Figure 7 is a diagram showing an example of brightness change according to frame when both the Maximum Single Frame Duration Increase function and the Minimum Frame number function are applied.

[0207] The Successive Frame Duration Increase / Decrease Tolerance parameter in the DisplayID's Adaptive-Sync Data block can control the amount of refresh rate change based on the Max Single Frame Duration. However, because this method only operates on individual frames, the brightness gradient can change rapidly.

[0208] However, if the adaptive-sync operation is performed through the minimum frame operation setting based on the minimum adaptive-sync frame number suggested in various embodiments of the present invention, the gradient of the brightness change according to the frame can be made gentler compared to the existing function, as in the embodiment of FIG. 7 of Example 1, so that the user can perceive less brightness change when switching frame rates. The minimum frame operation setting based on the minimum adaptive-sync frame number suggested in various embodiments of the present invention can be used together with the successive frame duration increase / decrease, and can also exhibit technical effects alone.

[0209] The minimum frame operation setting based on the minimum adaptive-sync frame number proposed in various embodiments of the present invention can be used together with the successive frame duration increase / decrease or can be used alone.

[0210] Example 1) When changing from 240Hz to 60Hz

[0211] - Maximum Single Frame Duration Increase = 8ms

[0212] - Minimum Multi Frame number = 3 Frame rate

[0213]

[0214] Figure 5 illustrates a case where neither the Maximum Single Frame Duration Increase nor the Minimum Frame Number function is applied. In this case, the brightness changes abruptly when the frame rate changes. This demonstrates that the user can clearly perceive the brightness change when the frame rate changes from 240Hz to 60Hz.

[0215] Figure 6 shows the case where the Maximum Single Frame Duration Increase feature is applied. In this case, the single frame duration increases, making the gradient of brightness changes somewhat gentler. However, since there is no minimum frame rate setting, the overall brightness change is still not smooth.

[0216] Figure 7 illustrates a case where both the Maximum Single Frame Duration Increase and Minimum Frame Number functions are applied. In this case, the minimum frame count setting is additionally applied during the frame rate conversion process, resulting in a more gradual gradient of brightness changes. This allows the user to perceive less brightness changes due to frame rate changes.

[0217] The examples in Figures 5, 6, and 7 demonstrate that the proposed features can improve the impact of brightness changes on the user experience when switching frame rates. In particular, the method in Figure 7 maximizes the technical effectiveness by combining increased continuous frame duration with a minimum frame rate setting.

[0218]

[0219] Composition and operation of the invention

[0220] The purpose of various embodiments of the present disclosure is to reduce abrupt luminance changes when changing the frame rate by maintaining the minimum number of frames indicated in the Sink information block whenever the frame rate is changed during the adaptive-sync operation.

[0221] Sink specifies the minimum number of frames that must be processed each time the refresh rate changes in the Block for communication between Sources (e.g. EDID, DisplayID, and DPCD Blocks). Sources must refer to this information when performing video rendering tasks when the frame rate changes.

[0222] Due to the nature of the display, there is a difference in luminance depending on the change in frame rate. Using this invented function, even if there is a sudden change in frame rate, the brightness changes gradually, reducing the user's eye fatigue and providing a better experience.

[0223] A Sink specifies a minimum number of frames to be maintained when changing refresh rates (both when the refresh rate increases and when it decreases) in blocks for communication between Sources (e.g., EDID, DisplayID, and DPCD blocks). The minimum number of frames can be specified in any way through the Video Capability block. A Source must read the information blocks in the Sink and perform video rendering tasks based on this information.

[0224]

[0225] Table 7 shows, as an example, the case where the minimum number of frames is indicated as a parameter for EDID, DisplayID, and CTA Block.

[0226] Byte #NameDefinitionX ByteMinimum Adaptive-Sync Frame numberThe minimum number of frames that must remain for each refresh rate change.

[0227] Table 8 shows, as an example, a case where the minimum number of frames is specified as a parameter for a DPCD Block.

[0228] DPCD RegisterAddressNameDescriptor0xxxxh[X]Minimum Adaptive-Sync Frame number The minimum number of frames that must remain at each refresh rate change.

[0229]

[0230] The process by which the source device performs Adaptive-Sync operation.

[0231] Figure 8 is a diagram illustrating an example of a process for determining a Frame Range when a Source device performs Adaptive-Sync operation.

[0232] Figure 8 shows the flow of the process of determining the Frame Range when the Source device performs Adaptive-Sync operation.

[0233] The source device receives a Hot Plug Detect (HPD) signal from the sink device. Reception of the HPD signal confirms the connection with the sink device.

[0234] The source device reads the EDID, DisplayID, or DPCD data from the sink device. The EDID, DisplayID, or DPCD data may contain information related to Adaptive-Sync operation.

[0235] The source device checks whether the EDID, DisplayID, or DPCD data contains blocks related to Adaptive-Sync operation.

[0236] If the EDID, DisplayID, or DPCD data contains blocks related to Adaptive-Sync operation, the source device operates in Frequency Variable Mode. Frequency Variable Mode is used to reduce power consumption and optimize display performance through variable frame rates.

[0237] If there is no Adaptive-Sync information in the EDID, DisplayID, or DPCD data, the source device operates in Frequency Fixed Mode. Frequency Fixed Mode ensures stable screen output while maintaining a fixed frame rate.

[0238]

[0239] FIG. 9 is a diagram illustrating an example of a process for determining a Frame Range when a Source device performs an Adaptive-Sync operation according to various embodiments of the present disclosure.

[0240] Figure 9 illustrates in more detail the process of determining the Frame Range when the Source device performs Adaptive-Sync operation.

[0241] The source device receives a Hot Plug Detect (HPD) signal from the sink device. Reception of the HPD signal confirms the connection with the sink device.

[0242] The source device reads the EDID, DisplayID, or DPCD data from the sink device. The EDID, DisplayID, or DPCD data may contain information related to Adaptive-Sync operation.

[0243] The source device checks whether the EDID, DisplayID, or DPCD data contains blocks related to Adaptive-Sync operation.

[0244] If there is no block related to Adaptive-Sync operation in the EDID, DisplayID, or DPCD data, the source device operates in Frequency Fixed Mode. Frequency Fixed Mode provides stable screen output while maintaining a fixed frame rate.

[0245] If the EDID, DisplayID, or DPCD data contains Adaptive-Sync related blocks, the source device additionally checks whether the EDID, DisplayID, or DPCD data contains a block indicating the minimum number of frames to change when changing the respective refresh rate.

[0246] If the EDID, DisplayID, or DPCD data does not contain a block indicating the minimum number of frames to change when changing each refresh rate, the source device operates in Frequency Variable Mode. Frequency Variable Mode is used to reduce power consumption and optimize display performance by varying the frame rate.

[0247] If the EDID, DisplayID, or DPCD data contains a block indicating the minimum number of frames to be used when changing each refresh rate, the source device will operate in variable frequency mode while maintaining the minimum number of frames when changing each refresh rate. In other words, the source device operates in variable frequency mode and maintains the minimum number of frames when changing the refresh rate. This provides a smoother user experience when changing frames.

[0248] Figure 9 is an improvement over Figure 8 in that it handles the Adaptive-Sync operation conditions in greater detail. In particular, the additional requirement of maintaining a minimum frame rate more effectively reduces unnatural brightness changes and frame loss that can occur during screen transitions. This significantly improves the user experience.

[0249]

[0250] Flow chart for exchanging data between source and sink devices

[0251] FIG. 10 is a diagram illustrating an example of a signal flow diagram between a source device and a sink device according to various embodiments of the present disclosure.

[0252] The source device confirms its connection with the sink device via a Hot Plug Detect (HPD) signal. The HPD signal detects the connection status and acts as a trigger to initiate the next step of the process.

[0253] The source device reads the EDID, DisplayID, or DPCD data from the sink device. The EDID, DisplayID, or DPCD data contains information related to the display settings (resolution, frequency, etc.) and plays a crucial role in coordinating display operation.

[0254] The source device checks the Adaptive-Sync block information in the EDID, DisplayID, or DPCD data. The Adaptive-Sync block contains information about whether the Sink device supports Adaptive-Sync and what conditions are followed when switching frame rates.

[0255] If there is an Adaptive-Sync block in the EDID, DisplayID, or DPCD data, check the minimum frame rate information that must be maintained when changing each refresh rate in the EDID, DisplayID, or DPCD data. This is a critical factor in ensuring smooth rendering during screen transitions.

[0256] The source device renders and outputs video data by referencing the information blocks in the EDID, DisplayID, or DPCD data of the sink device. This process focuses on optimizing display performance and improving the user experience.

[0257]

[0258] FIG. 11 is a diagram illustrating an example of a signal flow diagram between a source device and a sink device according to various embodiments of the present disclosure.

[0259] Figure 11 illustrates the signal flow between a Source device and a Sink device, specifically detailing frame processing and data transmission / reception processes based on Adaptive-Sync operation. This flowchart illustrates specific processes related to screen switching and frame rate maintenance.

[0260] The source device confirms its connection with the sink device via a Hot Plug Detect (HPD) signal. The HPD signal detects the connection status and acts as a trigger to initiate the next step of the process.

[0261] The source device checks the Adaptive-Sync block information in the EDID, DisplayID, or DPCD data. The Adaptive-Sync block contains information about whether the Sink device supports Adaptive-Sync and what conditions are followed when switching frame rates.

[0262] If there is an Adaptive-Sync block in the EDID, DisplayID, or DPCD data, check the minimum frame rate information that must be maintained when changing each refresh rate in the EDID, DisplayID, or DPCD data. This is a critical factor in ensuring smooth rendering during screen transitions.

[0263] The Source device performs the video rendering task by referencing the information block in the EDID, DisplayID, or DPCD data of the Sink device, and sends the information of the minimum frame rate that must be maintained to the Sink device along with the video data in the Secondary Data Packet (SDP). The minimum frame rate information included in the SDP plays an important role in conveying the frame maintenance criteria to the Sink device during the refresh rate change process during Adaptive-Sync operation. This information provides the Sink device with the reference data necessary to maintain screen quality and synchronization performance, and ensures a smooth and consistent screen output experience for the user. The Source device transmits the minimum frame rate information along with the video data to help the Sink device output the video according to the Adaptive-Sync setting. This is an important step in optimizing the user experience by enabling smooth frame rate transitions.

[0264]

[0265] [Source device claim related description]

[0266] The embodiments described below are specifically described with reference to FIG. 12 in terms of terminal operation. The methods described below are distinguished for convenience of explanation, and it is understood that some components of one method may be substituted for or combined with some components of another method, as long as they are not mutually exclusive.

[0267] FIG. 12 is a diagram illustrating an example of an operation process of a source device according to various embodiments of the present disclosure.

[0268] According to various embodiments of the present disclosure, a method is provided that is performed by a source device.

[0269] The source device includes a processor; a memory; and a transceiver. The memory stores instructions for performing operations based on those executed by the processor.

[0270] At step S1201, the source device receives a hot plug detection (HPD) signal from the sink device.

[0271] In step S1202, the source device receives first information related to EDID (Extended Display Identification) or DPID (DisplayID) from the sink device.

[0272] In step S1203, the source device identifies the minimum number of frames related to an adaptive-sync operation based on the first information of the sink device.

[0273] In step S1204, the source device performs rendering so as to maintain a number of frames that is greater than or equal to the minimum number of information at a third refresh rate corresponding to a range between the first refresh rate and the second refresh rate for video information whose refresh rate changes from the first refresh rate to the second refresh rate.

[0274] At step S1205, the source device transmits the video information on which the rendering has been performed to the sink device.

[0275]

[0276] According to various embodiments of the present disclosure, a secondary data packet (SDP) may be transmitted to the sink device along with the rendered video information. The SDP may include information on the third refresh rate that must be maintained for the number of frames corresponding to the minimum number of information by the rendering.

[0277] According to various embodiments of the present disclosure, the minimum number of pieces of information may be equal to or greater than 3 or 5.

[0278] According to various embodiments of the present disclosure, the first injection rate may correspond to a first luminance, the second injection rate may correspond to a second luminance, and the third injection rate may correspond to a third luminance. The third luminance may fall between the first luminance and the second luminance.

[0279] According to various embodiments of the present disclosure, the first information may be related to support for the adaptive synchronization operation of the sink device.

[0280] According to various embodiments of the present disclosure, if the first information is not related to support for the adaptive synchronization operation, the video information may be rendered with the refresh rate fixed.

[0281] According to various embodiments of the present disclosure, when the first information is not related to the minimum number information, the video information can be rendered while the injection rate is fixed.

[0282]

[0283] According to various embodiments of the present disclosure, a source device is provided. The source device includes a processor; a memory; and a transceiver, wherein the processor may be configured to perform a method of operating the source device according to FIG. 7.

[0284]

[0285] According to various embodiments of the present disclosure, a device for controlling a source device is provided. The device includes at least one processor and at least one memory operably connected to the at least one processor. The at least one memory may be configured to store instructions for performing an operating method of the source device according to FIG. 7 based on instructions executed by the at least one processor.

[0286]

[0287] According to various embodiments of the present disclosure, one or more non-transitory computer-readable media (CRM) storing one or more commands are provided. The one or more commands, when executed by one or more processors, perform operations, and the operations may include an operating method of a source device according to FIG. 7.

[0288]

[0289] The claims described in the various embodiments of the present disclosure may be combined in various ways. For example, the technical features of the method claims of the various embodiments of the present disclosure may be combined and implemented as a device, and the technical features of the device claims of the various embodiments of the present disclosure may be combined and implemented as a method. Furthermore, the technical features of the method claims of the various embodiments of the present disclosure may be combined and implemented as a device, and the technical features of the method claims of the various embodiments of the present disclosure may be combined and implemented as a method.

Claims

1. In the method of operating the source device, A step of receiving a hot plug detection (HPD) signal from a sink device; A step of receiving first information related to EDID (Extended Display Identification) or DPID (DisplayID) from the sink device; A step of identifying information on the minimum number of frames related to an adaptive-sync operation based on the first information of the sync device; A step of performing rendering so as to maintain frames corresponding to a number greater than or equal to the minimum number of information at a third refresh rate corresponding to a range between the first refresh rate and the second refresh rate for video information in which the refresh rate changes from a first refresh rate to a second refresh rate; A step of transmitting the video information on which the rendering has been performed to the sink device, method.

2. In paragraph 1, A secondary data packet (SDP) is transmitted to the sink device along with the rendered video information, The above SDP includes information of the third injection rate that must be maintained for frames corresponding to the minimum number of information by the above rendering. method.

3. In paragraph 1, The minimum number of information above is greater than or equal to 3 or 5, method.

4. In paragraph 1, The first injection rate corresponds to a first luminance, the second injection rate corresponds to a second luminance, and the third injection rate corresponds to a third luminance. The third luminance is between the first luminance and the second luminance. method.

5. In paragraph 1, The first information relates to support for the adaptive synchronization operation of the sink device, method.

6. In paragraph 1, If the first information is not related to support for the adaptive synchronization operation, the video information is rendered with the refresh rate fixed. method.

7. In paragraph 1, If the first information is not related to the minimum number information, the video information is rendered while the injection rate is fixed. method.

8. In the source device, A processor; memory; and a transceiver, The above memory stores instructions for performing operations based on what is executed by the processor, The above actions are, A step of receiving a hot plug detection (HPD) signal from a sink device; A step of receiving first information related to EDID (Extended Display Identification) or DPID (DisplayID) from the sink device; A step of identifying information on the minimum number of frames related to an adaptive-sync operation based on the first information of the sync device; A step of performing rendering so as to maintain frames corresponding to a number greater than or equal to the minimum number of information at a third refresh rate corresponding to a range between the first refresh rate and the second refresh rate for video information in which the refresh rate changes from a first refresh rate to a second refresh rate; A step of transmitting the video information on which the rendering has been performed to the sink device, Source device.

9. In paragraph 8, A secondary data packet (SDP) is transmitted to the sink device along with the rendered video information, The above SDP includes information of the third injection rate that must be maintained for frames corresponding to the minimum number of information by the above rendering. Source device.

10. In paragraph 8, The minimum number of information above is greater than or equal to 3 or 5, Source device.

11. In paragraph 8, The first injection rate corresponds to a first luminance, the second injection rate corresponds to a second luminance, and the third injection rate corresponds to a third luminance. The third luminance is between the first luminance and the second luminance. Source device.

12. In paragraph 8, The first information relates to support for the adaptive synchronization operation of the sink device, Source device.

13. In paragraph 8, If the first information is not related to support for the adaptive synchronization operation, the video information is rendered with the refresh rate fixed. Source device.

14. In paragraph 8, If the first information is not related to the minimum number information, the video information is rendered while the injection rate is fixed. Source device.

15. In one or more non-transitory computer-readable media storing one or more instructions, The one or more instructions perform operations based on being executed by one or more processors, The above actions are, A step of receiving a hot plug detection (HPD) signal from a sink device; A step of receiving first information related to EDID (Extended Display Identification) or DPID (DisplayID) from the sink device; A step of identifying information on the minimum number of frames related to an adaptive-sync operation based on the first information of the sync device; A step of performing rendering so as to maintain frames corresponding to a number greater than or equal to the minimum number of information at a third refresh rate corresponding to a range between the first refresh rate and the second refresh rate for video information in which the refresh rate changes from a first refresh rate to a second refresh rate; A step of transmitting the video information on which the rendering has been performed to the sink device, Computer readable medium.

Images