Method and device for encoding and decoding data in communication or broadcasting system

Abstract

The present disclosure provides an efficient encoding and decoding method and device, the method and device: reducing a decoding latency; providing algebraic characteristics to be satisfied by a parity check matrix of a low density parity check (LDPC) code for reducing encoding complexity; and using the LDPC code having the algebraic characteristics.

Description

Method and device for encoding and decoding data in a communication or broadcasting system

[0001] The present disclosure relates to a method and device for encoding and decoding data in a communication or broadcasting system.

[0002] Looking back at the evolution of wireless communication over successive generations, technologies have primarily been developed for human-facing services such as voice, multimedia, and data. With the commercialization of the 5G (5th Generation) communication system, an explosive increase in connected devices is expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction equipment, and factory equipment. Mobile devices are also expected to evolve into diverse form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6G (6th Generation) era, efforts are being made to develop improved 6G communication systems to connect hundreds of billions of devices and objects and provide diverse services. For this reason, 6G communication systems are often referred to as "beyond 5G."

[0003] The 6G communication system, expected to be realized around 2030, will have a maximum transmission speed of terabytes (i.e., 1,000 gigabits) per second (bps) and a wireless latency of 100 microseconds (μsec). In other words, compared to 5G, the transmission speed in a 6G communication system will be 50 times faster and the wireless latency will be reduced to one-tenth.

[0004] To achieve these high data rates and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz (THz) band (e.g., from 95 gigahertz (GHz) to 3 terahertz (THz)). Compared to the millimeter wave (mmWave) band introduced in 5G, the terahertz band is expected to have more severe path loss and atmospheric absorption, making it more important to develop technologies that can guarantee signal reach, or coverage. Key technologies to ensure coverage include Radio Frequency (RF) components, antennas, new waveforms that offer better coverage than Orthogonal Frequency Division Multiplexing (OFDM), beamforming, and multiple antenna transmission technologies such as massive Multiple-Input and Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing using Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surface (RIS) are being discussed to improve the coverage of terahertz band signals.

[0005] In addition, in order to improve frequency efficiency and system network, 6G communication systems are developing full duplex technology that utilizes the same frequency resources at the same time for uplink and downlink; network technology that integrates satellites and HAPS (High-Altitude Platform Stations); network structure innovation technology that supports mobile base stations and enables optimization and automation of network operation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes AI (Artificial Intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services with complexity that exceeds the limits of terminal computing capabilities by utilizing ultra-high-performance communication and computing resources (Mobile Edge Computing (MEC), cloud, etc.). In addition, efforts are being made to further strengthen connectivity between devices, further optimize networks, promote softwareization of network entities, and increase the openness of wireless communications through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe use of data, and the development of technologies for maintaining privacy.

[0006] Research and development of these 6G communication systems are expected to enable a new level of hyper-connected experience through the hyper-connectivity of 6G communication systems, which encompass not only connections between things but also connections between people and things. Specifically, 6G communication systems are expected to enable services such as truly immersive eXtended Reality (XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems through enhanced security and reliability, will be applied in diverse fields such as industry, medicine, automobiles, and home appliances.

[0007] The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC (Low Density Parity Check) code must satisfy in order to reduce decoding latency and encoding complexity. In addition, an efficient encoding and decoding method and device using an LDPC code having the above algebraic characteristics are provided.

[0008] The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy in order to reduce the Block Error Rate (BLER) or block error probability. In addition, an efficient encoding and decoding method and device using an LDPC code having the algebraic characteristics are provided.

[0009] The present disclosure provides algebraic characteristics that a parity check matrix of an LDPC code must satisfy by appropriately combining the aforementioned algebraic characteristics to simultaneously reduce decoding latency, encoding complexity, and BLER. In addition, the present disclosure provides an efficient encoding and decoding method and device using an LDPC code having the combined algebraic characteristics.

[0010] The present disclosure provides a method for variably applying puncturing to LDPC encoded bits to support a trade-off between encoding performance and decoding latency. Furthermore, an efficient encoding and decoding method and device supporting the variable puncturing method are provided.

[0011] The present disclosure provides a device and method for efficiently decoding a low-density parity-check (LDPC) code in a communication or broadcasting system.

[0012] In addition, the present invention provides an LDPC decoding device and method for improving decoding performance without increasing decoding complexity by applying appropriate decoding scheduling according to the LDPC code encoding method when performing decoding of an LDPC code using layered scheduling or a corresponding method.

[0013] In a communication system according to one embodiment of the present disclosure, a data transmission method of a base station or a terminal may include a step of LDPC encoding data bits based on a basic matrix and / or a parity check matrix, a step of applying rate matching to the encoded bits, a step of modulating the rate-matched encoded bits, and a step of transmitting the modulated signal through a transmission device, wherein the encoded bits are variably applied so that some of the data bits are not included or are included depending on a setting of the system.

[0014] In a communication system according to one embodiment of the present disclosure, a data receiving method of a base station or a terminal may include the steps of receiving a modulated signal corresponding to at least a part of encoded bits through a receiving device, performing demodulation to determine values ​​for decoding based on the received signal, performing LDPC decoding based on the determined values ​​and a basic matrix and / or a parity check matrix, appropriately applying rate dematching to the LDPC decoded result, and determining data bits from the rate dematched result, wherein the encoding bits are variably applied so that some of the data bits are not included or included depending on a setting of the system.

[0015] In a method performed by a transmitter in a communication system according to one embodiment of the present disclosure, the method comprises the steps of: determining a number of input bits; determining a basic matrix based on the number of input bits; determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix; determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); performing encoding based on the parity check matrix and the input bits to determine encoded bits; and transmitting at least a portion of the encoded bits to a receiver, wherein when a first setting is indicated, input bits of a first length among the input bits are not included in the encoded bits, and when a second setting is indicated, input bits of a second length among the input bits are not included in the encoded bits, and the second length is 0 or less than the first length.

[0016] A method performed by a receiver in a communication system according to one embodiment of the present disclosure, comprising the steps of: receiving a signal corresponding to at least a portion of coding bits; determining a number of input bits based on the signal; determining a basic matrix based on the number of input bits; determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix; determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); and performing decoding of the signal based on the parity check matrix, wherein when a first setting is indicated, input bits of a first length among the input bits are not included in the coding bits, and when a second setting is indicated, input bits of a second length among the input bits are not included in the coding bits, and the second length is 0 or less than the first length.

[0017] In a communication system according to one embodiment of the present disclosure, a transmitter comprises: a transmitting unit; and a control unit connected to the transmitting unit, wherein the control unit determines a number of input bits, determines a basic matrix based on the number of input bits, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), performs encoding based on the parity check matrix and the input bits to determine encoded bits, and transmits at least a portion of the encoded bits to a receiver, wherein when a first setting is indicated, input bits of a first length among the input bits are not included in the encoded bits, and when a second setting is indicated, input bits of a second length among the input bits are not included in the encoded bits, and the second length is 0 or less than the first length.

[0018] In a communication system according to one embodiment of the present disclosure, a receiver comprises: a receiving unit; and a control unit connected to the transmitting unit, wherein the control unit receives a signal corresponding to at least a portion of coded bits, determines a number of input bits based on the signal, determines a basic matrix based on the number of input bits, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), and performs decoding of the signal based on the parity check matrix, wherein when a first setting is indicated, an input bit of a first length among the input bits is not included in the coded bits, and when a second setting is indicated, an input bit of a second length among the input bits is not included in the coded bits, and the second length is 0 or less than the first length.

[0019] A method performed by a receiver in a communication system according to one embodiment of the present disclosure, comprising the steps of: receiving a signal corresponding to at least a portion of coding bits; determining a number of input bits based on the signal; determining a basic matrix based on the number of input bits; determining a lifting size (Z) based on at least one of the number of input bits or the basic matrix; determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); and performing decoding of the signal based on the parity check matrix, wherein for a first setting, an input bit of a first length among the input bits is not included in the coding bits, and for a second setting, an input bit of a second length among the input bits is not included in the coding bits, and the second length is 0 or less than the first length, and wherein a layered decoding order associated with the first setting and a layered decoding order associated with the second setting are different from each other.

[0020] In a communication system according to one embodiment of the present disclosure, a receiver comprises: a receiving unit; and a control unit connected to the transmitting unit, wherein the control unit receives a signal corresponding to at least a portion of coded bits, determines a number of input bits based on the signal, determines a basic matrix based on the number of input bits, determines a lifting size (Z) based on at least one of the number of input bits or the basic matrix, determines a parity check matrix based on at least one of the basic matrix or the lifting size (Z), and performs decoding of the signal based on the parity check matrix, wherein for a first setting, an input bit of a first length among the input bits is not included in the coded bits, and for a second setting, an input bit of a second length among the input bits is not included in the coded bits, and the second length is 0 or less than the first length, and a layered decoding order associated with the first setting and a layered decoding order associated with the second setting are different from each other.

[0021] The present disclosure applies a method for variably applying data bit puncturing when determining encoding bits. The present disclosure can support an efficient LDPC encoding method and device by enabling the variably applying a method for maximizing encoding gain or minimizing decoding latency depending on system conditions.

[0022] Figure 1 is a diagram of a systematic LDPC codeword structure.

[0023] Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.

[0024] Figure 3a is an example diagram for explaining the cycle characteristics of a QC-LDPC code.

[0025] Figure 3b is an example diagram for explaining the cycle characteristics of a QC-LDPC code.

[0026] FIG. 4 is a transmission block structure diagram according to an embodiment of the present disclosure.

[0027] FIG. 5 is an exemplary diagram of an LDPC encoding process according to an embodiment of the present disclosure.

[0028] FIG. 6 is an exemplary diagram of an LDPC decoding process according to an embodiment of the present disclosure.

[0029] Figure 7 is a block diagram of a transmitter device according to an embodiment of the present disclosure.

[0030] Figure 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.

[0031] FIG. 9 is a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.

[0032] Figure 10 is an example diagram of the structure of a parity check matrix of an LDPC code.

[0033] FIG. 11a is an example diagram of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.

[0034] FIG. 11b is an example diagram of a parity check matrix for an LDPC code satisfying the characteristics proposed in the present disclosure.

[0035] Figure 12a is an example diagram showing a case where one or two perforated bit nodes are connected to one inspection node.

[0036] Figure 12b is an example diagram showing a case where one or two perforated bit nodes are connected to one inspection node.

[0037] FIG. 13 is a diagram illustrating a rate matching method according to the present disclosure.

[0038] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, in describing the present disclosure, if a detailed description of a related known function or configuration is deemed to unnecessarily obscure the gist of the present disclosure, such detailed description will be omitted. The terms described below are defined based on the functions of the present disclosure and may vary depending on the intent or custom of the user or operator. Therefore, their definitions should be based on the contents of this specification.

[0039] The main gist of this disclosure can be applied to other systems with similar technical backgrounds, with minor modifications, without significantly departing from the scope of this disclosure. This can be accomplished at the discretion of those skilled in the technical field of this disclosure. While the term "communication system" generally encompasses the meaning of a broadcasting system, in this disclosure, a communication system whose primary service is broadcasting may be more clearly termed a broadcasting system.

[0040] The advantages and features of the present disclosure, and methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present disclosure is complete and to fully inform those skilled in the art of the scope of the invention, and the present disclosure is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

[0041] Low Density Parity Check (LDPC) codes, first introduced by Gallager in the 1960s, were long forgotten due to their complexity, which was difficult to implement with the technology of the time. However, in 1993, the turbo code proposed by Berrou, Glavieux, and Thitimajshima showed performance approaching the Shannon channel capacity, which led to many analyses of the performance and characteristics of turbo codes, and much research on iterative decoding and graph-based channel coding was conducted. This led to a restudy of LDPC codes in the late 1990s, and it was discovered that when decoding is performed using iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC code, the LDPC code also achieves performance approaching the Shannon channel capacity.

[0042] LDPC codes are generally defined as a parity-check matrix and can be represented using a bipartite graph, commonly referred to as a Tanner graph. LDPC codes are generally a type of parity-check code, and are called "low-density" parity-check codes because they have the characteristic that the ratio of the number of 1s (i.e., density) in the parity-check matrix for very long codes is very low. Therefore, the techniques proposed in this disclosure based on LDPC codes for convenience can be easily extended to general parity-check matrix codes.

[0043] Figure 1 is a diagram illustrating a systematic LDPC codeword structure.

[0044] According to Fig. 1, the device in which LDPC encoding is performed is K ldpcInput information word (102) composed of dog bits or symbols and perform encoding to N ldpc Generate a codeword (100) consisting of bits or symbols. For convenience of explanation below, K ldpc Input information word (102) containing dog bits and N ldpc It is assumed that a codeword (100) consisting of dog bits is generated. That is, K ldpc Information word which is the input bit of a dog When (102) is encoded, the codeword (100) is generated. That is, the information word and the code word are bit strings composed of multiple bits, and the information word bit and the code word bit mean each bit that constitutes the information word and the code word. Typically, the LDPC coded bit

[0045]

[0046] If it contains information words such as , it is called a systematic code. Here, is the parity bit (104), and the number of parity bits N parity is N parity = N ldpc - K ldpc can be expressed as

[0047] LDPC code is a type of linear block code and includes a process of determining a codeword that satisfies the conditions in mathematical expression 1 below.

[0048] [Mathematical Formula 1]

[0049]

[0050] Here, am.

[0051] In mathematical expression 1, H is a parity check matrix, c is a codeword, and c i is the i-th bit of the codeword, N ldpc means the LDPC codeword length, means the i-th column of the parity check matrix (H).

[0052] The parity check matrix H has N, which is equal to the number of bits in the LDPC codeword. ldpc It consists of columns. Mathematical expression 1 is the i-th column of the parity check matrix. ) and the i-th code word bit c i This means that the sum of the products of is '0', so the i-th column ( ) is the i-th code word bit c i It means that there is a relationship with .

[0053] Figure 2 is a diagram illustrating a method for representing a graph of an LDPC code.

[0054] Referring to Fig. 2, a method for representing a graph of an LDPC code will be described.

[0055] Fig. 2 is a diagram illustrating an example of a parity check matrix H1 of an LDPC code consisting of 4 rows and 8 columns, and its representation as a Tanner graph. Referring to Fig. 2, since the parity check matrix H1 has 8 columns, a codeword of length 8 is generated, and the code generated through H1 means an LDPC code, and each column corresponds to 8 encoded bits.

[0056] Referring to Fig. 2, the Tanner graph of an LDPC code that encodes and decodes based on a parity check matrix H1 is composed of eight variable nodes, namely x1 (202), x2 (204), x3 (206), x4 (208), x5 (210), x6 (212), x7 (214), x8 (216), and four check nodes (218, 220, 222, 224). Here, the i-th column and the j-th row of the parity check matrix H1 of the LDPC code are each a variable node x icorresponds to the j-th check node. In addition, the meaning of the value of 1, that is, a non-zero value, at the point where the i-th column and the j-th row of the parity check matrix H1 of the LDPC code intersect is the variable node x on the Tanner graph, as shown in Fig. 2. i This means that there is an edge connecting the j-th inspection node.

[0057] In the Tanner graph of an LDPC code, the degree of a variable node and a check node refers to the number of line segments connected to each node, which is the same as the number of non-zero elements (entries) in the column or row corresponding to the node in the parity check matrix of the LDPC code. For example, in Fig. 2, the degrees of variable nodes x1 (202), x2 (204), x3 (206), x4 (208), x5 (210), x6 (212), x7 (214), and x8 (216) are 4, 3, 3, 3, 2, 2, 2, 2, respectively, and the degrees of check nodes (218, 220, 222, 224) are 6, 5, 5, 5, respectively, in that order. In addition, the number of non-zero elements in each column of the parity check matrix H1 of FIG. 2 corresponding to the variable nodes of FIG. 2 matches the degrees of the above-described variable nodes, which are 4, 3, 3, 3, 2, 2, 2, 2, in that order, and the number of non-zero elements in each row of the parity check matrix H1 of FIG. 2 corresponding to the check nodes of FIG. 2 matches the degrees of the above-described check nodes, which are 6, 5, 5, 5, in that order. For this reason, the degree of each variable node is also called the column degree or column weight, and the degree of the check node is also called the row degree or row weight.

[0058] LDPC encoded codeword bits can be decoded based on an iterative decoding algorithm based on a sum-product algorithm on a bipartite graph as shown in Fig. 2. Here, the sum-product algorithm is a type of message passing algorithm, and the message passing algorithm represents an algorithm that exchanges messages through edges on a bipartite graph and calculates and updates an output message from messages input to a variable node or a test node.

[0059] Here, the value of the ith coding bit can be determined based on the message of the ith variable node. Both hard decision and soft decision methods are possible to determine the value of the ith coding bit. Therefore, the ith bit of the LDPC codeword, c i The performance of corresponds to the performance of the ith variable node of the Tanner graph, which can be determined by the position and number of 1s in the ith column of the parity check matrix. In other words, the N of the codeword ldpc The performance of the LDPC code bits can be affected by the position and number of 1s in the parity check matrix, which means that the performance of an LDPC code is greatly affected by the parity check matrix. Therefore, in order to design an LDPC code with excellent performance, a method for designing a good parity check matrix is ​​required.

[0060] The parity check matrix used in communication and broadcasting systems is usually a quasi-cyclic LDPC code (or QC-LDPC code, hereinafter referred to as QC-LDPC code), which uses a quasi-cyclic parity check matrix for ease of implementation. Depending on the communication and broadcasting system, there are cases where a parity check matrix that has a structure that is not a complete quasi-cyclic structure but is almost similar to a quasi-cyclic structure is used. Such LDPC codes may not be strictly classified as QC-LDPC codes algebraically, but they are sometimes categorized as QC-LDPC codes for convenience.

[0061] A typical QC-LDPC code is characterized by having a parity check matrix composed of zero matrices or circulant permutation matrices (or circular permutation matrices) in the form of small square matrices. Here, a permutation matrix refers to a matrix in which each row or column contains only one 1, and all remaining elements are 0. In addition, a circulant permutation matrix refers to a matrix in which each element of the identity matrix is ​​cyclically shifted to the right or left. Generally, the identity matrix itself is also included in the circulant permutation matrix, because each element of the identity matrix is ​​regarded as having been cyclically shifted 0 times. Therefore, a circulant permutation matrix basically includes the identity matrix, but for the convenience of explanation, an identity matrix and a circulant permutation matrix that is not an identity matrix can be expressed separately.

[0062] Below, the QC-LDPC code is described in detail.

[0063] First, as in mathematical equation 2 Circular permutation matrix of size is defined here means the entry of the i-th row and j-th column in the matrix P above. ( )

[0064] [Equation 2-1]

[0065]

[0066] For the permutation matrix P defined as above, (0 ≤ i < Z) is It is a cyclic permutation matrix in the form of a circular shift of each element of the identity matrix of size i to the right. The cyclic permutation matrix can also be defined as in [Mathematical Formula 2-2], in which case go It is a cyclic permutation matrix in the form of each element of the identity matrix of size shifted to the left by i times:

[0067] [Equation 2-2]

[0068]

[0069] In the present disclosure, for convenience, various embodiments are described using a cyclic permutation matrix defined based on [Mathematical Formula 2-1]. However, the cyclic permutation matrices defined in [Mathematical Formula 2-1] and [Mathematical Formula 2-2] have the same basic algebraic properties, although their expressions are different. Therefore, a cyclic permutation matrix defined based on Mathematical Formula 2-2 can be used in the embodiments of the present disclosure, or various types of cyclic permutation matrices having the same algebraic properties can be used.

[0070] The parity check matrix H of the simplest QC-LDPC code can be expressed in the following mathematical expression 3.

[0071] [Equation 3]

[0072]

[0073] For convenience second When defined as a 0-matrix of size , each index of the cyclic permutation matrix or 0-matrix in the above mathematical expression 3 has one of the values ​​{-1, 0, 1, 2, ..., Z-1}. The identity matrix is or can be expressed as , and the 0-matrix is or can be expressed as . In addition, the parity check matrix H of the above mathematical expression 3 is a column block. Dog, row block Since it is a dog, the size of the above parity check matrix H is am.

[0074] If the parity check matrix of the above mathematical expression 3 has the maximum rank (full rank, or complete coefficient), the length of the information word bit of the QC-LDPC code corresponding to the parity check matrix is For convenience, the information bits correspond to The ten blocks of the dog are called information word ten blocks and the number of information word bits is , corresponding to the remaining parity bits. The ten blocks of the dog can be called parity ten blocks. In this case, the number of parity bits is . For reference, if the parity check matrix of the above mathematical expression 3 does not have the maximum rank, the above information word bits is larger, and the number of information bits is The larger the value, the more parity bits has a smaller value.

[0075] Typically, in the parity check matrix of the above mathematical expression 3, each cyclic permutation matrix and 0-matrix are replaced with 1 and 0, respectively. A binary matrix of size H is called the mother matrix or base matrix or base graph of the parity check matrix H, and M(H) or It is expressed as follows. Also, by selecting the index of each cyclic permutation matrix or 0-matrix, it is obtained as in mathematical formula 4. An integer matrix of size H is the exponent matrix of the parity check matrix H. It is said.

[0076] [Equation 4]

[0077]

[0078] Of course, the names of these matrices are just examples and are exponential matrices. can be called by different names. For example, since the indices of each cyclic permutation matrix correspond to values ​​that circularly shift the identity matrix, as in [Mathematical Formula 2-1] or [Mathematical Formula 2-2], each indices is called a circular shift value (or circular shift value). It can also be called a circular shift value matrix or shift value matrix. It is generally equivalent to the size of the exponential matrix or shift value matrix and the circular permutation matrix or 0-matrix. Given a value, a parity check matrix can be determined or identified. For this reason, according to the mathematical definition, a parity check matrix means a binary matrix H that satisfies the condition of Equation 1, but in some cases, for convenience, an exponential matrix or a shift value matrix can also be called a parity check matrix.

[0079] Since one integer included in the exponential matrix or the shift value matrix corresponds to a cyclic permutation matrix in the parity check matrix, the exponential matrix may be conveniently expressed as a sequence of integers. In general, the parity check matrix can be expressed not only as an exponential matrix but also as various sequences that can express algebraically identical characteristics. In the present disclosure, the parity check matrix is ​​conveniently expressed as a sequence indicating the position of 1 in the exponential matrix or the parity check matrix, but there are various sequence notations that can distinguish the positions of 1 or 0 included in the parity check matrix, and thus the present disclosure is not limited to the method expressed in the present specification and may be expressed in the form of various sequences or matrices that exhibit the algebraically identical effect. The sequence may be called in various ways, such as an LDPC sequence, an LDPC code sequence, an LDPC sequence, a parity check matrix sequence, or a (cyclic) shift value sequence, in order to distinguish it from other sequences.

[0080] In addition, a transceiver may directly generate a parity check matrix to perform LDPC encoding and decoding, but depending on implementation characteristics, LDPC encoding and decoding may also be performed based on an exponential matrix, a shift value matrix, or a sequence that has the same effect algebraically as the parity check matrix. Therefore, although encoding and decoding using a parity check matrix is ​​described for convenience in this disclosure, in an actual transceiver, encoding and decoding can be implemented through various methods that can obtain the same effect as the parity check matrix.

[0081] For reference, the algebraically equivalent effect means that two or more different representations can be described or transformed as being completely equivalent to each other logically or mathematically. In particular, in the case of codes that can be defined by matrices, such as LDPC codes, it can mean that algebraic values ​​that can be defined by matrices, such as minimum distance, rank, and cycle characteristics in the Tanner graph, are identical. It can also mean that the basic structure or operation during the encoding / decoding process is identical. For example, if the same matrix is ​​obtained through appropriate column permutations and row permutations, the two matrices can be considered algebraically equivalent from a code perspective. Furthermore, various transpose transformations that do not change the actual characteristics of the code can also provide algebraically equivalent effects.

[0082] As a concrete example, given the following matrix A, examples of various transformations that provide algebraically identical effects are shown in A1 through A8.

[0083]

[0084] (step, Is and coprime integers)

[0085] silver This is an example of a block-by-block permutation that permutes the second and third row blocks. silver In addition, here is an example of a block-by-block permutation in which the first and third row blocks are permuted. silver This is an example of applying cyclic permutation only to the first and third column blocks. Is In addition, this is an example in which the cyclic permutation is applied only to the second and fourth row blocks. Is This is an example of applying transpose to . silver This is an example of applying block-wise transposition transformation. silver Here is an example of reversing the signs of each index (or cyclic shift value) (for convenience only) A 0-matrix of size When expressing as , using negative exponents (or shift values) can be confusing, so Is ) can also be expressed as a positive value. silver This is an example of applying an affine transformation with a constant term of 0 (it can also be applied to cases where the constant term is not 0 in general). For reference, the above examples are for convenience. go Although we have described the case where there are no elements that are 0-matrix of size 0, when a 0-matrix is ​​included, the part corresponding to the 0-matrix is ​​always a 0-matrix regardless of the transformation. For example, at If is a 0-matrix, , and In , too is a 0-matrix, and In each and is a 0-matrix, and at is a 0-matrix, at is a 0-matrix.

[0086] The above transformations are merely examples, and various other transformations may exist. Furthermore, while each transformation can be applied independently, they can also be applied in combination and overlapping. The characteristic of each transformation or combination of transformations is that they can be converted back to the original matrix through an appropriate invertible transform process.

[0087] The above-described various transformations or combinations of transformations are essentially reversible transformations in which the arrangement of bits (or variable nodes) or check nodes on the Tanner graph is simply changed, or symmetrical transformations or specific structures are maintained. Therefore, in terms of code performance, instantaneous performance may vary depending on the given channel conditions, but on average, the same performance can be provided. In this way, in the present disclosure, all parity check matrices that can be obtained through transformations that can achieve the same algebraic effect are considered to be the same parity check matrix.

[0088] For convenience, one so far Although only one cyclic permutation matrix corresponding to a square block of size has been described, the same invention can be applied to a case where a single block includes multiple cyclic permutation matrices. For example, as in the following mathematical expression 5, two cyclic permutation matrices are located at the positions of one i-th row block and one j-th column block. , When it corresponds, simply It can be expressed in the form of a sum such as , and the exponential matrix (or cyclic shift value matrix) can be expressed as in mathematical expression 6. Looking at mathematical expression 6, it can be seen that it is a matrix in which two integers correspond to the i-th row and j-th column corresponding to the row block and column block including the sum of the plurality of cyclic permutation matrices.

[0089] [Equation 5]

[0090]

[0091] [Equation 6]

[0092]

[0093] As in the above embodiment, in general, a QC-LDPC code can have one or more cyclic permutation matrices corresponding to one row block and one column block in a parity check matrix, and for reference, multiple cyclic permutation matrices are duplicated in one row block and one column block. A matrix of size is called a circulant matrix (or circulant matrix or circular matrix). In general, each element (entry) of a circulant matrix has not only binary numbers but also arbitrary numbers as elements. However, in this disclosure, for convenience, a binary code is described, so the circulant matrix means a binary circulant matrix. Of course, the algebraic structure and features proposed in this disclosure can be extended in a similar manner to the case of non-binary codes, but details are omitted in this disclosure.

[0094] Meanwhile, the basic matrix (or parent matrix or basic graph) for the parity check matrix and the index matrix (or cyclic shift value matrix) of the above mathematical expressions 5 and 6 means a binary matrix obtained by replacing each cyclic permutation matrix and 0-matrix with 1 and 0, respectively, similar to the definition used in the above mathematical expression 3, and the cyclic matrix included in one block (i.e., the sum of multiple cyclic permutation matrices) can also be replaced with 1.

[0095] A simple example of the relationship between the parity check matrix, the exponential matrix (or the cyclic shift matrix), and the fundamental matrix is ​​shown in the following [Mathematical Formula 7].

[0096] [Equation 7]

[0097]

[0098] In the above [Equation 7] The notation of the index (or shift value) of a 0-matrix of size -1 is just an example, and can be expressed in various ways. In addition, the matrix representation method of the above [Mathematical Formula 7] can be expressed in various other ways, and as a specific example, the representation method of the parity check matrix of the LDPC code defined in 3GPP TS 38.212, which is a 3GPP 5G standard specification, can be used. In 3GPP TS 38.212, the sizes of the parity check matrices of the LDPC code corresponding to BG1 (Base Graph 1) and BG2 (Base Graph 2) are too large, so they are represented using a table. When the corresponding representation method is applied to the matrices of the above [Mathematical Formula 7], the result is as follows [Table 1].

[0099] Is is a matrix of size, silver is a matrix of size. The entries of the basic matrix (or basic graph) and parity check matrices not expressed in Table 1 below are 0 or A 0-matrix of size 0 corresponds.

[0100] [Table 1]

[0101]

[0102] If the basic matrix and exponential matrix in the above [Mathematical Formula 7] are expressed using a sequence, they can be expressed in the following manner.

[0103] :

[0104] 0 2 3

[0105] 0 1 3 4

[0106] 1 2 4 5

[0107] 0 1 2 5

[0108] :

[0109] 159 0 0

[0110] 117 109 0 0

[0111] 225 1 0 0

[0112] 84 211 0 0

[0113] Exponential matrix as above When expressed as a sequence, it can be conveniently named in various ways, such as shift sequence, shift value sequence, LDPC sequence, etc. In the sequence expression method above, is a method of listing the positions of columns where the elements are not 0 for each row, is a method of listing the indices or shift values ​​of each cyclic permutation matrix, not a 0-matrix, for each row. From the above sequences, the exponent matrix (or shift value matrix) can be defined exactly, and if If we obtain information about the values, the parity check matrix can also be defined exactly.

[0114] Another simple example of the relationship between the parity check matrix and the exponential matrix (or cyclic shift matrix), the fundamental matrix, etc. is shown in the following [Equation 8]. In the example of [Equation 8], at least one It illustrates a case where a block of size contains a circulant matrix corresponding to two or more circulant permutation matrices.

[0115] [Equation 8]

[0116]

[0117] For reference, in the above [Equation 8] is a weight matrix for the fundamental matrix, exponential matrix, or parity check matrix, and is a matrix that expresses how many cyclic permutation matrices correspond to the ith row, the jth column in the fundamental matrix and exponential matrix, or the ith row block, the jth column block in the parity check matrix. For example, corresponds to the i-th row block and j-th column block in the parity check matrix. It refers to a matrix that represents the number of circulant permutation matrices that constitute a circulant matrix of size as an element of the i-th row and j-th column. That is, is a matrix that represents 0 as an element when a 0-matrix corresponds, and w as an element when w cyclic permutation matrices correspond. (Note that a 0-matrix can be viewed as a cyclic matrix in a broad sense, but it is not a cyclic 'permutation' matrix.)

[0118] If the basic matrix or parity check matrix or circular shift value matrix (or exponential matrix) defined in [Mathematical Formula 8] is expressed by applying the method of expressing parity check matrices of LDPC codes in 3GPP TS 38.212 as in [Table 1], it can be expressed as in [Table 2] below.

[0119] Is is a matrix of size, silver is a matrix of size . The elements of the basic matrix (or basic graph) and parity check matrix not expressed in Table 2 below are 0 or A 0-matrix of size 0 corresponds.

[0120] [Table 2]

[0121]

[0122] If the basic matrix and exponential matrix of the above [Mathematical Formula 8] are expressed using a sequence, they can be expressed in the following manner.

[0123] :

[0124] 0 1 2 3

[0125] 0 1 2 3

[0126] :

[0127] (117, 159) 109 0 0

[0128] 84 (211, 225) (1, 3) 0

[0129] As another way of expressing it, we can use a weight matrix to express it in a form consisting only of a sequence, as follows:

[0130] :

[0131] 0 1 2 3

[0132] 0 1 2 3

[0133] :

[0134] 2 1 1 1

[0135] 1 2 2 1

[0136] :

[0137] 117 159 109 0 0

[0138] 84 211 225 1 3 0

[0139] In the above expression is a method of listing the positions of columns where the elements are not 0 for each row, is a matrix defined based on the number of circulant permutation matrices that constitute the circulant matrices corresponding to the fundamental matrix, the exponential matrix, or the parity check matrix. is a method of listing the indices or shift values ​​of each non-zero circulant matrix by row. The exponential matrix can be defined exactly from the above sequences, and if If we obtain information about the values, the parity check matrix can also be defined exactly.

[0140] Since the performance of an LDPC code is determined by its parity check matrix, designing a parity check matrix is ​​essential for achieving high-performance LDPC codes. Furthermore, an LDPC encoding or decoding method capable of supporting various input lengths and code rates is required.

[0141] Lifting can be used not only for the efficient design of QC-LDPC codes, but can also mean a method for generating parity check matrices of various lengths or generating LDPC codewords using given base matrices and exponent matrices. That is, the lifting can be applied to efficiently design a very large parity check matrix by setting the Z value, which determines the size of a cyclic permutation matrix or a 0-matrix from a given small parent matrix, according to a specific rule, or can mean a method for generating parity check matrices of various lengths or generating LDPC codewords by applying an appropriate Z value to a given exponent matrix or its corresponding sequence.

[0142] The characteristics of the existing lifting method and the QC-LDPC code designed through lifting are briefly explained with reference to the following reference [Myung2006].

[0143] Reference [Myung2006]

[0144] S. Myung, K. Yang, and Y. Kim, “Lifting Methods for Quasi-Cyclic LDPC Codes,” IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.

[0145] First, given an LDPC code C0, S QC-LDPC codes to be designed using the lifting method are C1, ..., C S And, the values ​​corresponding to the sizes of the row blocks and column blocks of the parity check matrix of each QC-LDPC code are L k Here, C0 is C1, ..., C S It corresponds to the smallest LDPC code with the parent matrix of the code as the parity check matrix, and the Z0 value corresponding to the size of the row block and column block is 1. Also, for convenience, each code C k Parity check matrix of Is exponential matrix of size and each index are {-1, 0, 1, 2, ..., Z k - 1} is selected as one of the values.

[0146] The existing lifting method is C0-> C1->...-> C S It consists of steps such as Z k+1 = q k+1 Z k (q k+1 It has the characteristic of satisfying the conditions such as positive integer, k=0,1,..., S-1). Also, due to the characteristics of the lifting process, C s Parity check matrix of If only storing is performed, the QC-LDPC codes C0, C1, ..., C can be obtained by using the following mathematical formula 9 or mathematical formula 10 depending on the lifting method. S can all be expressed.

[0147] [Equation 9]

[0148]

[0149] or

[0150] [Equation 10]

[0151]

[0152] In this way, larger QC-LDPC codes C1, ..., C from C0 S How to design the back as well as the big sign C k From the small sign C using an appropriate method such as Equation 9 or Equation 10 i The method of generating (i=k-1, k-2, … 1, 0) can also be called lifting. For reference, in 3GPP TS 38.212, LDPC codes of various lengths can be generated using the lifting method of [Mathematical Formula 10].

[0153] The lifting method of the above mathematical expression 9 or 10 is for each QC-LDPC code Ck Z corresponding to the size of a row block or column block in the parity check matrix k Since they have a multiple relationship with each other, the exponent matrix is ​​also selected in a specific way. This existing lifting method helps to easily design QC-LDPC codes with improved error floor characteristics by improving the algebraic or graphical properties of each parity check matrix designed through lifting.

[0154] Figures 3a and 3b are examples to simply explain that the cycle characteristics of a QC-LDPC code can vary greatly depending on the exponential matrix.

[0155] Figure 3a is a diagram for explaining the cycle characteristics of a QC-LDPC code.

[0156] The exponential matrix in Fig. 3a is , and in this case, there may be many 4-cycles in the Tanner graph. Codes with many short cycles like this may cause serious degradation in decoding performance.

[0157] Figure 3b is a diagram for explaining the cycle characteristics of a QC-LDPC code.

[0158] The exponential matrix in Fig. 3b is , and in this case, the length of the shortest cycle on the Tanner graph is 12. Since the cycle characteristics on the Tanner graph can change significantly just by changing a single index of the cyclic permutation matrix, the selection of the index matrix plays an important role in improving the performance of the LDPC code. The lifting method can be viewed as one of the design methods that takes these cycle characteristics into account.

[0159] In general, lifting can be thought of as using the exponential matrix of Equation 4 for LDPC encoding and decoding by changing the values ​​of its elements for various Z values. For example, the exponential matrix of Equation 4 above and the transformed exponential matrix according to the Z value In this case, the following conversion formula, such as mathematical formula 11, can be generally applied.

[0160] [Equation 11]

[0161]

[0162] In the above mathematical formula 11 can be defined in various forms, for example, the above [Mathematical Formula 9] It corresponds to ( ), the above [Mathematical Formula 10] is may correspond to (mod(a,b) means modulo-b operation for a). In addition, can be defined in various ways, as shown in the following mathematical expression 12.

[0163] [Equation 12]

[0164]

[0165] or

[0166]

[0167] or

[0168]

[0169] In the above mathematical expression 12, D means a constant that is a positive integer defined in advance.

[0170] For reference, in the conversion formula of the above mathematical expression 11, the reference value (or, and To distinguish the application of The reference value) is represented as 0 for convenience, but the reference value is the lifting size Z value to be supported or It can be set differently depending on how the 0-matrix of size is expressed. For example, If the 0-matrix of size is defined as a number or symbol other than the negative integer -1 and is not determined in advance, the reference value for applying the conversion formula f can be defined differently. In addition, if the expression of the exponent matrix or LDPC sequence is based on a method of not expressing the exponent corresponding to the 0-matrix by excluding it from the beginning, the rule for values ​​whose exponent is less than 0 in mathematical expression 11 can be omitted. Since the conversion formula f is applied to a circulant permutation matrix or a circulant matrix other than a 0-matrix, in general There are various ways to omit transformations for a 0-matrix of size.

[0171] As an embodiment of the present disclosure, a case of applying LDPC encoding and decoding based on a plurality of exponential matrices or LDPC sequences based on a single determined base matrix is ​​described. That is, the base matrix is ​​fixed to one, and an exponential matrix or (cyclic) shift value matrix or LDPC sequence of an LDPC code defined based on the base matrix can be determined, and variable-length LDPC encoding and decoding is performed by applying lifting according to a lifting size included in each lifting size group from the matrix or sequence. This method has a characteristic that elements or numbers constituting the exponential matrix or LDPC sequence of an LDPC code can have different values, but the positions of the corresponding elements or numbers are exactly the same on the base matrix.

[0172] The LDPC code defined in TS 38.212, the 3GPP 5G standard, is also a code designed in the same way, with two basic matrices. This is defined and 8 exponent matrices (or circular shift value matrices) for each base matrix ( ) is defined and can be used for LDPC encoding. That is, according to the standard, a total of two base matrices and 16 exponent matrices, and an appropriate lifting size Based on this, the parity check matrix of various LDPC codes can be determined. However, in the TS 38.212 standard, The matrix corresponding to is called the parity check matrix, and the matrix corresponding to the normal parity check matrix is ​​matrix- It was named as. is a matrix of integers with lifting size A parity check matrix in the strict sense can be constructed if given, but for convenience as explained above, can also be called a parity check matrix.

[0173] In the following, for the convenience of explanation, the LDPC code and its representation method defined in the 3GPP 5G standard specification TS 38.212 are used as much as possible, but in some cases, it can be expressed in a conventional mathematical expression or in another way. First, the parity check matrix or matrix- of the LDPC code In order to determine the lifting size (Z) to be supported, the following [Table 3] is shown. (Hereinafter, the set index i for each lifting size set LS is just an example and can be reversed in a different order.)

[0174] [Table 3]

[0175]

[0176] In the present disclosure, lifting sizes or block sizes are basically expressed in the same manner as in [Table 3] above, but they can also be expressed in the same manner as in [Table 4] below, and various other expression methods are also possible.

[0177] [Table 4]

[0178]

[0179] In 3GPP 5G, lifting sizes or block sizes Z can be divided into multiple sets (or groups) as shown in [Table 3] or [Table 4]. (Hereinafter, for convenience, they are referred to as lifting size sets (or groups) or block size sets (or groups))

[0180] In the 3GPP 5G standard, an exponential matrix can be obtained using the lifting method of [Mathematical Formula 10]. Parity check matrix or matrix-based It decides. This is and When , for each i and j This means that (for reference, the 3GPP 5G standard specification TS 38.212 states that Simply put ) was expressed as

[0181] As explained previously in [Mathematical Formula 11], in the present disclosure, from the basic matrix and the exponential matrix Note that no special transformation is applied to the part corresponding to the 0-matrix of size. That is, In cases where there is no special explanation, no special transformation is performed on the part corresponding to the 0-matrix. Depending on the value, only the size of the 0-matrix can change. As a specific example, in the expression method used in the 3GPP 5G standard specifications, as in [Table 1] and [Table 2], Since the part corresponding to the 0-matrix of size is not indicated from the beginning, it is included in [Table 1] or [Table 2]. If we perform a predefined transformation such as modulo appropriately only for , the part corresponding to the 0-matrix is ​​naturally not transformed, which is equivalent to defining a 0-matrix with a different size. The above expression is an example for the convenience of explanation, and various other expression methods may exist.

[0182] For a given exponential matrix (or circularly shifted value matrix), a parity check matrix or matrix- Since the lifting sizes defined in [Table 3] above can be transformed in various ways, the set of lifting sizes required for a system can be defined differently. That is, the above [Table 3] and [Table 4] are only examples, and all lifting size (Z) values ​​included in the lifting size (or block size) group (or set) of [Table 3] and [Table 4] above can be used, and some of the appropriate lifting sizes can be selected and used depending on the situation required by the system, and more diverse lifting size values ​​can be added as needed.

[0183] For example, if the minimum transport block size (TBS) is 24, Z = 2, 3, 4, 5, 6, 9, and 13 are virtually never used in the system. In this case, some Z values ​​can be defined by excluding them, as shown in [Table 5].

[0184] [Table 5]

[0185]

[0186] In a communication system based on LDPC codes that applies [Table 5] as the lifting size, the minimum lifting size is 7, so each column block that constitutes the parity check matrix of the LDPC code used for LDPC encoding and decoding can be composed of at least 7 columns.

[0187] If the minimum value of TBS is greater than 8 for future scalability, and additional values ​​such as 8 or 16 are used, the lifting size set (or block size group) may be changed as shown in [Table 6].

[0188] [Table 6]

[0189]

[0190] The above [Table 6] excludes only the cases where Z = 2 or 3 in the above [Table 3] or [Table 4], because the minimum value of Z that can be determined when TBS is 8 or more is 4 or more.

[0191] As an example of setting another lifting size set, let us call the lifting size set A sets , , , … , When classified, it can be classified in the following way: ( )

[0192]

[0193]

[0194] ...

[0195]

[0196] ...

[0197]

[0198] For example, the case where A = 4 and A = 8 can be represented as in the following [Table 7-1] and [Table 7-2]. ( )

[0199] [Table 7-1]

[0200]

[0201] [Table 7-2]

[0202]

[0203] When the lifting size sets are defined in the manner shown in [Table 7-1] and [Table 7-2] above, there is an advantage in that the distribution of Z values ​​can be set relatively uniformly. The lifting size sets defined in [Table 7-1] and [Table 7-2] above all contain the same number of Z values, but appropriate Z values ​​can be added or subtracted for each set as needed. For example, it is possible to define the lifting size sets of [Table 3] to [Table 6] above based on the lifting size sets of [Table 7-2] above.

[0204] Also, in [Table 7-1] and [Table 7-2] By appropriately setting the range of values, you can also set Z values ​​suitable for your system. For example, The value Setting this to , we obtain a set of lifting sizes with 7 different Z values ​​in each set, The value If set to , a lifting size set with four different Z values ​​is obtained in each set. However, the above The value is an example and the above An example of a value does not limit the scope of the present disclosure. In addition, in some cases, it is also possible to add or exclude some appropriate Z values ​​from the lifting size sets. For example, if the maximum value of Z set in the system is Zmax, all values ​​greater than Zmax can be removed (e.g., Zmax = 768). In addition, if all Z values ​​that can be supported by the existing 3GPP 5G standard are included, at least some of the values ​​such as 2, 3, 4, 5, 6, 7, etc. may be additionally included. Of course, even if values ​​such as TBS = 8, 16 are additionally supported in a 5G or 6G system, values ​​such as Z = 2, 3 are not used, so only values ​​such as 4, 6, 7 or 4, 5, 6, 7 may be additionally included, and values ​​that are not actually used in 5G may be excluded. The following [Table 8] shows specific examples of lifting size sets. (The numbers in () in Table 8 represent values ​​that may or may not be used as lifting sizes.)

[0205] [Table 8]

[0206]

[0207] The lifting size sets can be defined in various ways other than [Table 3] to [Table 8], but the common characteristics are that each of the multiple lifting size sets must not have overlapping lifting sizes, and the lifting sizes included in each lifting size set must be multiples or divisors of each other. [Table 3] to [Table 8] above define a continuous lifting size for the smallest lifting size in each lifting size set. ( ) are composed of multiples, but are generally ( ) can be composed of non-consecutive multiples, and can also include multiples of integers other than multiples of 2.

[0208] In new communication systems, including 6G systems, in order to support backward compatibility with existing systems (e.g., 5G systems), the existing lifting size set may be maintained as is (e.g., [Table 3] or [Table 4]), and a new lifting size set may be added (e.g., [Table 5] to [Table 8]). Alternatively, if only one lifting size set is defined, but the range of TBS used is determined differently in advance depending on the application scenario or system settings such as the target BLER, the range of Z values ​​used also varies. For example, if the first minimum TBS and the first maximum TBS values ​​are set for a service applying the first target BLER, and the second minimum TBS and / or the second maximum TBS values ​​are defined for a service applying the second target BLER, the first minimum TBS and the second minimum TBS values ​​may be different, or the first maximum TBS and the second maximum TBS values ​​may be different (both the minimum value and the maximum value may be different).

[0209] Additionally, the applicable service scenario or target BLER, etc. may be determined based on upper layer signaling information. For example, the CQI (channel quality information) table or the MCS (modulation coding scheme) table may typically be determined by considering the target service scenarios or BLERs. (For example, the first target service or BLER may be the first CQI table and / or the first MCS table, the second target service or BLER may be the second CQI table and / or the second MCS table, the third target service or BLER may be the third CQI table and / or the third MCS table, etc.)

[0210] This means that the range of lifting sizes to be used or the set of lifting sizes to be used can be determined from higher-layer signaling information, and the intermediate operations can exist in various ways depending on the system. In addition, the set of lifting sizes to be used can be indicated through physical layer signaling or higher-layer signaling. Based on the indicated set of lifting sizes and the determined lifting size Z value, the parity check matrix can be determined.

[0211] For reference, in the present invention, the target BLER means the minimum BLER to be achieved in the system, and is typically set so that the average BLER of a terminal or base station does not exceed the target BLER.

[0212] Figure 4 is a transport block structure diagram according to one embodiment of the present disclosure.

[0213] Referring to FIG. 4, a transport block composed of A bits is added with L bits of CRC bits (TB-CRC bits), and one transport block can become one code block. In addition, if the value B = A + L is greater than a specific threshold value, it can be divided into multiple code blocks through an appropriate segmentation process. At this time, the size K of the code blocks is all the same, and for this purpose, specific bits called null bits or filler bits can be added to each code block. The null bits or filler bits typically correspond to a value of 0, but are not necessarily limited to this, and can be composed of any specific bits determined in advance. The operation of adding predetermined bits such as null bits or fillers in this way is typically called shortening because the size of the actual pure information word bits is reduced, and if the values ​​are 0, it can also be called zero-padding.

[0214] After the size of the transport block to be transmitted (TBS, transport block size) is determined, one of the basic matrices of two different LDPC codes used for LDPC encoding or decoding can be determined based on the code rate indicated in the TBS size and MCS through a method such as the [basic matrix determination method] below.

[0215] [How to determine the basic matrix]

[0216] The LDPC basic matrix for LDPC encoding and decoding of a transport block with TBS = A can be determined based on the TBS size and the code rate indicated by the MCS as follows:

[0217] - When A ≤ 292 (or 288), or A ≤ 3824 and R ≤ 0.67, or R ≤ 0.25, LDPC encoding can be performed using LDPC basic matrix 2.

[0218] - In addition, LDPC encoding can be performed using LDPC basic matrix 1. For reference, basic matrix 1 defined in the 3GPP 5G standard and basic matrix 2 is as follows.

[0219] :

[0220] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

[0221] 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

[0222] 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

[0223] 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

[0224] 0 1 26

[0225] 0 1 3 12 16 21 22 27

[0226] 0 6 10 11 13 17 18 20 28

[0227] 0 1 4 7 8 14 29

[0228] 0 1 3 12 16 19 21 22 24 30

[0229] 0 1 10 11 13 17 18 20 31

[0230] 1 2 4 7 8 14 32

[0231] 0 1 12 16 21 22 23 33

[0232] 0 1 10 11 13 18 34

[0233] 0 3 7 20 23 35

[0234] 0 12 15 16 17 21 36

[0235] 0 1 10 13 18 25 37

[0236] 1 3 11 20 22 38

[0237] 0 14 16 17 21 39

[0238] 1 12 13 18 19 40

[0239] 0 1 7 8 10 41

[0240] 0 3 9 11 22 42

[0241] 1 5 16 20 21 43

[0242] 0 12 13 17 44

[0243] 1 2 10 18 45

[0244] 0 3 4 11 22 46

[0245] 1 6 7 14 47

[0246] 0 2 4 15 48

[0247] 1 6 8 49

[0248] 0 4 19 21 50

[0249] 1 14 18 25 51

[0250] 0 10 13 24 52

[0251] 1 7 22 25 53

[0252] 0 12 14 24 54

[0253] 1 2 11 21 55

[0254] 0 7 15 17 56

[0255] 1 6 12 22 57

[0256] 0 14 15 18 58

[0257] 1 13 23 59

[0258] 0 9 10 12 60

[0259] 1 3 7 19 61

[0260] 0 8 17 62

[0261] 1 3 9 18 63

[0262] 0 4 24 64

[0263] 1 16 18 25 65

[0264] 0 7 9 22 66

[0265] 1 6 10 67

[0266] :

[0267] 0 1 2 3 6 9 10 11

[0268] 0 3 4 5 6 7 8 9 11 12

[0269] 0 1 3 4 8 10 12 13

[0270] 1 2 4 5 6 7 8 9 10 13

[0271] 0 1 11 14

[0272] 0 1 5 7 11 15

[0273] 0 5 7 9 11 16

[0274] 1 5 7 11 13 17

[0275] 0 1 12 18

[0276] 1 8 10 11 19

[0277] 0 1 6 7 20

[0278] 0 7 9 13 21

[0279] 1 3 11 22

[0280] 0 1 8 13 23

[0281] 1 6 11 13 24

[0282] 0 10 11 25

[0283] 1 9 11 12 26

[0284] 1 5 11 12 27

[0285] 0 6 7 28

[0286] 0 1 10 29

[0287] 1 4 11 30

[0288] 0 8 13 31

[0289] 1 2 32

[0290] 0 3 5 33

[0291] 1 2 9 34

[0292] 0 5 35

[0293] 2 7 12 13 36

[0294] 0 6 37

[0295] 1 2 5 38

[0296] 0 4 39

[0297] 2 5 7 9 40

[0298] 1 13 41

[0299] 0 5 12 42

[0300] 2 7 10 43

[0301] 0 12 13 44

[0302] 1 5 11 45

[0303] 0 2 7 46

[0304] 10 13 47

[0305] 1 5 11 48

[0306] 0 7 12 49

[0307] 2 10 13 50

[0308] 1 5 11 51

[0309] The above basic matrix 1 and basic matrix 2 The sizes of the parity check matrices are 46×68 and 42×52, respectively, and the sizes of the parity check matrices determined from the basic matrices are 46Z×68Z and 42Z×52Z.

[0310] Also, according to the above-determined TBS, the number of CRC bits to be added to the transport block (L) is as follows: TB ) can be determined.

[0311] [Method for determining the number of transport block CRC bits]

[0312] CRC bit size L for transport blocks with TBS = A TB The values ​​can be set differently depending on the TBS value as follows:

[0313] L if A > 3824 TB = 24, otherwise L TB = 16.

[0314] Based on the TBS size (A) determined in this way or the total number of bits B (A + L) with the CRC appended to the transport block, an appropriate code block is determined from the transport block, and LDPC encoding and decoding can be performed for each code block. The process of determining the code block length (CBS) is described in more detail as follows:

[0315] [How CBS decides]

[0316] Input bit sequence for code block segmentation is b0, b1, …, b B-1 can be expressed as (B > 0) if B is the maximum code block size K cb If it is larger than , segmentation of the input bit sequence is performed, and a CRC of L = 24 bits is additionally appended to each code block. For LDPC elementary matrix 1, the maximum code block size is K cb = 8448, the maximum code block size for LDPC base matrix 2 is K cb = 3840.

[0317] The specific steps are explained below.

[0318] Step 1: Number of code blocks can be decided.

[0319] - If On the other hand, And and, .

[0320] - Otherwise, , and, .

[0321] Step 2: Bit output from code block segmentation c r0 , c r1 ,…, cr (Kr - 1) When r is a code block number (0 ≤ r < C), Kr (= K) can mean the number of bits of a code block for the code block number r. Here, K, the number of bits included in each code block, can be calculated as follows:

[0322] - ;

[0323] - In the case of LDPC basic matrix 1 .

[0324] - In the case of LDPC basic matrix 2,

[0325] On the other hand, ;

[0326] On the other hand, ;

[0327] On the other hand, ;

[0328] On the other hand, .

[0329] Step 3: Table 3 Among the values The minimum value that satisfies can be determined. For LDPC basic matrix 1 , and for LDPC basic matrix 2 Set to .

[0330] In step 2 of the above [CBS Determination Method] The value corresponds to a column or column block corresponding to an LDPC information bit in the basic matrix (or basic graph) or parity check matrix of the LDPC code, and is the maximum value of the LDPC information bit without shortening or zero padding. ) can correspond to. For example, even if the number of columns (or column blocks) corresponding to information word bits in the LDPC basic matrix 2 or the parity check matrix corresponding to the basic matrix 2 is 10, if If set to , then substantially the maximum LDPC encoding / decoding is performed on the information bits of the bits, and at least The information bits corresponding to the column of the dog are shortened or zero-padded. Shortening or zero-padding here can mean that the transmitter and receiver assign a bit value promised, such as 0, or it can mean that the corresponding part is not used in the parity check matrix.

[0331] The lifting size Z value for LDPC encoding and decoding can be determined based on the lifting size sets shown in [Table 3] to [Table 8] or the lifting size sets with specific lifting size values ​​added and removed. Each Z value has an index i. LS It is included in a specific set that is determined in advance according to, and when the Z value is determined in step 3 of [CBS decision method], the set or index i of the set corresponding to the Z value LSThe value is determined, and the parity check matrix of the LDPC code corresponding to each index or the corresponding sequence can also be determined. By applying a modulo operation based on the lifting size Z to the parity check matrix of the LDPC code determined in this way or the corresponding sequence, the parity check matrix or sequence is transformed to support encoding and decoding of LDPC codes of various lengths. In the 3GPP 5G standard, each number included in the parity check matrix or sequence of the LDPC code means a value corresponding to a cyclic permutation matrix.

[0332] A flowchart for an embodiment of an LDPC encoding and decoding process based on a designed base matrix or exponential matrix is ​​shown in FIGS. 5 and 6.

[0333] Figure 5 is a diagram illustrating an embodiment of an LDPC encoding process.

[0334] First, the transmitter determines the transport block size TBS to be transmitted, as in step (510) of Fig. 5. In step (520), the transmitter determines whether the TBS is greater than, less than, or equal to max CBS.

[0335] If TBS is greater than max CBS, the transmitter can segment the transport block to determine CBS in step (530). If TBS is less than or equal to max CBS, the transmitter skips the segmentation operation and determines the TBS as CBS.

[0336] In step (540), the transmitter determines the lifting size (Z) value to be applied to LDPC encoding based on the CBS.

[0337] And the transmitter determines a parity check matrix or sequence based on the TBS or CBS or lifting size (Z) value in step (550). Alternatively, the transmitter may determine an LDPC index matrix or sequence that has an effect algebraically identical to the parity check matrix.

[0338] And the transmitter performs LDPC encoding based on the parity check matrix or sequence in step (560). Alternatively, the transmitter may perform LDPC encoding based on the exponential matrix or sequence in step (560). In addition, the transmitter may perform LDPC encoding based on the lifting size and the exponential matrix or sequence in step (560).

[0339] For reference, the step (550) above may include a process of converting the determined LDPC index matrix or sequence based on the determined lifting size, depending on the case. It is obvious that the LDPC index matrix or sequence or parity check matrix for LDPC encoding may be determined in various ways based on TBS or CBS, depending on the system. For example, the transmitter may first determine the base matrix through TBS, and then determine the LDPC index matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods may also be applied. For reference, additional operations may be included depending on the system between steps (520) and (540) or between steps (530) and (540). For example, in the case of a 3GPP 5G system, the base matrix 2 ( ) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size. The process of determining the value may be included. (For reference, The column blocks of the parity check matrix corresponding to the columns of the basic matrix of the dog are shortened.)

[0340] The LDPC decoding process can be similarly represented as in Fig. 6.

[0341] Figure 6 is a diagram illustrating an embodiment of an LDPC decoding process.

[0342] If TBS is determined in step (610), the receiver determines in step (620) whether TBS is greater than, less than, or equal to max CBS.

[0343] If TBS is greater than max CBS, the receiver determines the size of the CBS to which segmentation is applied in step (630). If TBS is determined to be less than or equal to max CBS, TBS is determined to be equal to CBS.

[0344] The receiver determines the lifting size (Z) value to be applied to LDPC decoding at step (640).

[0345] Then, the receiver determines a parity check matrix or sequence based on the TBS or CBS or lifting size (Z) value at step (650). Alternatively, the transmitter may determine an exponential matrix or sequence that has an effect algebraically identical to the parity check matrix.

[0346] And the receiver can perform LDPC decoding based on the parity check matrix or sequence in step (660). Alternatively, the receiver can perform LDPC decoding using the exponent matrix or sequence in step (660). Note that step (650) may include a process of converting the determined LDPC exponent matrix or sequence based on the determined lifting size, as the case may be. It is obvious that the LDPC exponent matrix or sequence or parity check matrix for LDPC decoding can be determined in various ways based on TBS or CBS depending on the system. For example, the receiver can first determine the base matrix through TBS, and then determine the LDPC exponent matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods can also be applied.

[0347] According to the above embodiment, the process of determining the exponent matrix or sequence of the LDPC code in steps (550) and (650) of FIGS. 5 and 6 has been described for the case where the exponent matrix or sequence is determined by one of the TBS, CBS, or lifting size (Z), but various other methods may exist. In addition, additional operations may be included between steps (620) and (640) or between steps (630) and (640) of FIG. 6 depending on the system. For example, in the case of a 3GPP 5G system, the basic matrix 2 ( ) means the number of columns to be actually used in the base matrix or the number of column blocks to be used in the parity check matrix depending on the TBS size. A process for determining the value may be included. Note that the receiver Since the bits corresponding to the column blocks of the parity check matrix corresponding to the columns of the base matrix can be known to have been shortened at the transmitter, the receiver may additionally perform appropriate operations on the shortened bits before performing LDPC decoding.

[0348] In an embodiment of the LDPC encoding and decoding process based on the basic matrix and the exponential matrix (or LDPC sequence) of the LDPC code of the above FIGS. 5 and 6, LDPC encoding and decoding of various code rates and various lengths can be supported by appropriately shortening or puncturing some of the information bits for the LDPC code and puncturing and repeating some of the code bits. For example, as in the 3GPP 5G standard technology, shortening is applied to some of the information bits in the LDPC encoding process of the above FIG. 5, and the first two of the basic matrix, i.e., the first in the parity check matrix By punching the information bits corresponding to the column of the dog, punching a portion of the parity, or repeating a portion of the LDPC codeword, various information word lengths (or code block lengths) and various code rates can be supported.

[0349] Given input bits or code block bits and the encoding bits are When expressed as (however, in the case of the basic matrix 1) , if the basic matrix is ​​2 ), part of the encoding process can be defined as shown in [Table 9] below.

[0350] [Table 9]

[0351]

[0352] According to the above encoding process, the first of the input bits or code block bits bits is not included in the encoding bits. That is, the above This means that the bits are punctured at the transmitter and not transmitted to the receiver. For reference, if a portion of the information word bits is punctured, this means that the transmitter does not transmit a portion of the information word (102) of FIG. 1. Accordingly, the receiver can decode the untransmitted information word bits by treating them as erased. In other words, since the punctured bits are regarded as if they were lost and have the same probability of being 0 or 1, the receiver can insert a corresponding value to perform decoding.

[0353] The information bits punctured during the above encoding process may not always be transmitted, even in the case of retransmission. In cases where a circular buffer is used for rate matching, if rate matching and retransmission are performed without storing the punctured information bits in the circular buffer, the punctured information bits may not always be transmitted.

[0354] On the other hand, in the case of a first transmission, some of the information bits may be punctured, and in the case of a retransmission, all or some of the punctured information bits may be transmitted. All information bits are stored in a circular buffer, but in the case of a first transmission, the RV (redundancy value) value may be appropriately set so that some of the information bits are punctured (e.g., the RV0 value is set to exclude the information bits to be punctured). Even if some of the information bits are punctured in the first transmission, since the bit values ​​are stored in the circular buffer, in the case of a retransmission, some or all of the punctured information bits may be transmitted depending on the circular buffer rate matching operation and selection of an appropriate RV value.

[0355] For convenience, in [Table 9] is called a coding bit, but the definition of a coding bit may change for convenience of explanation. For example, in [Table 9] The bit string after punching out some of the information bits can be defined as the encoded bit, but in reality, the parity bit vector in the encoding process Input bits or code block bits to generate Because this is used, it is based on the pre-perforation of the information bits.

[0356]

[0357] can also be defined as a coded bit. Also, a bit string with rate matching applied based on the allocated resource amount. This can also be defined as a coded bit, and is a bit string with interleaving applied to the rate-matched bit string. This can also be defined as a coded bit. In addition, the coded bit string can be defined in various ways for convenience of explanation, but usually, the bit string related to actual transmission in the system is Ina, related to the encoding process This can be defined by the encoding bits.

[0358] In the LDPC decoding process of FIG. 6, decoding can be performed by adding appropriate operations to the shortened information bits and the punctured bits or repeated bits in response to the transmitter operation. Typically, the shortened information bits are 0, so the receiver performs decoding by excluding the column corresponding to the shortened bits from the parity check matrix, or by setting a value preset in the system for the shortened bits to perform decoding. (Since it is certain to be 0, the highest value corresponding to 0 preset in the system is typically set.) Since the punctured parity bits are regarded as lost and have the same probability of being 0 and 1, the receiver can perform decoding by inserting a corresponding value, or, depending on the structure of the parity check matrix, decoding can be performed without using at least some of the rows corresponding to the punctured parity bits. In general, when puncturing the parity bit corresponding to a column with degree 1, the LDPC decoder can perform decoding without using part or all of the corresponding part in the parity check matrix, which has the advantage of reducing decoding complexity.

[0359] In addition, when supporting variable information word length or variable code rate by using LDPC code shortening or zero padding, the code performance can be improved depending on the shortening order or shortening method. If a shortening order is set, the encoding performance can be improved by appropriately rearranging the order of some or all of the given basic matrix. In addition, the performance can be improved by appropriately determining the number of column blocks to which the lifting size or shortening is applied for a specific information word length (or code block length CBS). Similarly, there are methods to improve the performance of LDPC codes by adjusting the puncturing order of the parity bits or the transmission order of the generated LDPC codeword. For example, better performance can be supported by appropriately puncturing some of the information word bits and the parity bits than by simply puncturing the parity bits to support a variable code rate. In addition, when repeating some of the LDPC codewords to support a lower code rate, the LDPC encoding performance can be improved by appropriately determining the order in advance.

[0360] Typically, in the LDPC encoding process, the transmitter first determines the size of the input bits (or code blocks) to which the LDPC encoding is to be applied, and then determines the lifting size (Z) to which the LDPC encoding is to be applied based on the size, determines an appropriate LDPC index matrix or sequence based on the lifting size, and then performs LDPC encoding based on the lifting size (Z) and the determined index matrix or LDPC sequence. At this time, the LDPC index matrix or sequence may be applied to LDPC encoding without transformation, or in some cases, the LDPC index matrix or sequence may be appropriately transformed based on the lifting size (Z) to perform LDPC encoding.

[0361] Similarly, in the LDPC decoding process, the receiver determines the size of the input bits (or code blocks) for the transmitted LDPC codeword, and then determines the lifting size (Z) to apply LDPC decoding based on the size, determines an appropriate LDPC exponent matrix or sequence based on the lifting size, and then performs LDPC decoding based on the lifting size (Z) and the determined exponent matrix or LDPC sequence. At this time, the LDPC exponent matrix or sequence may be applied to LDPC decoding without transformation, and in some cases, the LDPC exponent matrix or sequence may be appropriately transformed based on the lifting size (Z) to perform LDPC decoding.

[0362] In a parity check matrix, the submatrix corresponding to the parity bits often has a special structure for efficient encoding. In this case, lifting may change the encoding method or complexity. Therefore, in order to maintain the same encoding method or complexity, lifting may not be applied to some of the exponent matrices for the submatrix corresponding to the parity in the parity check matrix, or a different lifting method may be applied to the exponent matrix for the submatrix corresponding to the information word bits. In other words, the lifting method applied to the sequence corresponding to the information word bits within the exponent matrix may be set differently from the lifting method applied to the sequence corresponding to the parity bits, and in some cases, lifting may not be applied to some or all of the sequence corresponding to the parity bits, so that a fixed value may be used without sequence transformation.

[0363] Figure 7 is a block diagram of a transmitter device according to an embodiment of the present disclosure.

[0364] Specifically, as shown in FIG. 7, the transmitting device (700) may include a segmentation unit (710), a zero padding unit (720), an LDPC encoding unit (730), a rate matching unit (740), a modulation unit (750), etc., to process variable-length input bits. The rate matching unit (740) may include an interleaver (741) and a puncturing / repetition / zero removal unit (742), etc.

[0365] Here, the components illustrated in FIG. 7 are components that perform encoding and modulation for variable-length input bits, and this is only an example, and in some cases, some of the components illustrated in FIG. 7 may be omitted or changed, and other components may be added.

[0366] Meanwhile, the transmitting device (700) can determine necessary parameters (e.g., input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate / code length of LDPC code, parameters for interleaving, parameters for repetition and puncturing, and at least one of modulation methods), and encode the input bits based on the determined parameters and transmit them to the receiving device (800).

[0367] Since the number of input bits is variable, when the number of input bits is greater than a preset value, the input bits can be segmented to have a length less than or equal to the preset value. In addition, each segmented block can correspond to one LDPC coded block. However, when the number of input bits is less than or equal to the preset value, the input bits are not segmented and the input bits can correspond to one LDPC coded block.

[0368] Meanwhile, the transmitting device (700) may store various parameters used for encoding, interleaving, and modulation. Here, the parameter used for encoding may include at least one of information on a code rate, a codeword length, and a parity check matrix of an LDPC code. In addition, the parameter used for interleaving may include information on an interleaving rule, and the parameter used for modulation may include information on a modulation method. In addition, information on puncturing may include a puncturing length. In addition, information on repetition may include a repetition length. The information on the parity check matrix may include an exponent value of a circulant matrix or values ​​algebraically identical thereto when using the parity matrix presented in the present disclosure.

[0369] In this case, each component constituting the transmitting device (700) can perform an operation using these parameters.

[0370] Meanwhile, although not shown, in some cases, the transmitter (700) may further include a control unit (not shown) for controlling the operation of the transmitter (700).

[0371] Figure 8 is a block diagram of a receiving device according to an embodiment of the present disclosure.

[0372] Specifically, as shown in FIG. 8, the receiving device (800) may include a demodulation unit (810), a rate dematching unit (820), an LDPC decoding unit (830), a zero removal unit (840), and a desegmentation unit (850) to process variable length information. The rate dematching unit (820) may include an LLR (log likelihood ratio) insertion unit (822), an LLR combiner (823), a deinterleaver (824), and the like.

[0373] Here, the components illustrated in FIG. 8 are components that perform functions corresponding to the components illustrated in FIG. 8, and this is only an example, and some of them may be omitted or changed depending on the case, and other components may be added.

[0374] The parity check matrix in the present disclosure may be read using memory, may be provided in advance to a transmitting device or a receiving device, or may be directly generated by the transmitting device or the receiving device. In addition, the transmitting device may store or generate a sequence or an exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply the same to encoding. Similarly, the receiving device may store or generate a sequence or an exponential matrix corresponding to the parity check matrix, or a value algebraically identical thereto, and apply the same to decoding.

[0375] Below, a detailed description of the receiver operation is provided based on Fig. 8.

[0376] The demodulator (810) demodulates the signal received from the transmitter (700).

[0377] Specifically, the demodulator (810) is a component corresponding to the modulation unit (750) of the transmitter (700), and can demodulate a signal received from the transmitter (700) to generate values ​​corresponding to bits transmitted from the transmitter (700).

[0378] To this end, the receiving device (800) determines parameters necessary for demodulation and decoding (e.g., at least one of input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), code rate / codeword length of LDPC code, parameters for interleaving, parameters for repetition and puncturing, and modulation methods), and based on the determined parameters, the demodulation unit (810) can perform a decoding process of demodulating a signal received from the transmitting device (700) according to a mode to generate values ​​corresponding to LDPC codeword bits.

[0379] Meanwhile, the value corresponding to the bits transmitted from the transmitting device (700) may be an LR (likelihood ratio) value or an LLR (log likelihood ratio) value.

[0380] Specifically, the LR value refers to the ratio of the probability that the bit transmitted from the transmitting device (700) is 0 and the probability that it is 1, and the LLR value can be expressed as the logarithm of the ratio of the probability that the bit transmitted from the transmitting device (700) is 0 and the probability that it is 1. Alternatively, the LR or LLR value can be expressed as the bit value itself by being determined based on the probability or the ratio of the probability or the Log value for the ratio of the probability, or can be expressed as a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs. An example of a method for determining a representative value defined in advance according to the section to which the probability or the ratio of the probability or the Log value for the ratio of the probability belongs includes a method that considers quantization. In addition, various other values ​​corresponding to the probability or the ratio of the probability or the Log value for the ratio of the probability may be used.

[0381] In the present disclosure, for convenience, an operation based on an LLR value is shown to explain the operation of the receiving method and device, but it is not necessary to be limited thereto.

[0382] The above-mentioned demodulator (810) includes a function for performing multiplexing (not shown) on LLR values. Specifically, the multiplexer (not shown) is a component corresponding to the bit demuxer (not shown) of the transmitter (700) and can perform an operation corresponding to the bit demuxer (not shown).

[0383] To this end, the receiving device (800) may store information about parameters that the transmitting device (700) used for demultiplexing and block interleaving. Accordingly, the multiplexer (not shown) may perform the demultiplexing and block interleaving operations performed in the bit demuxer (not shown) in reverse order for the LLR values ​​corresponding to the cell words (information representing the received symbols for the LDPC codeword as vector values), thereby multiplexing the LLR values ​​corresponding to the cell words on a bit-by-bit basis.

[0384] The rate dematching unit (820) can additionally insert LLR values ​​into the LLR values ​​output from the demodulation unit (810). In this case, the rate dematching unit (820) can insert pre-arranged LLR values ​​between the LLR values ​​output from the demodulation unit (810).

[0385] Specifically, the rate dematching unit (820) is a component corresponding to the rate matching unit (740) of the transmitting device (700), and can perform operations corresponding to the interleaver (741), zero removal, and puncturing / repetition / zero removal unit (742).

[0386] First, the rate dematching unit (820) performs deinterleaving to correspond to the interleaver (741) of the transmitter. The LLR insertion unit (822) can insert LLR values ​​corresponding to zero bits into positions where zero bits were padded in the LDPC codeword in the output values ​​of the deinterleaver (824). In this case, the LLR value corresponding to the padded zero bits, i.e., the shortened zero bits, can be ∞ or -∞. However, ∞ or -∞ is a theoretical value, and in practice, it can be the maximum or minimum value of the LLR value used in the receiving device (800).

[0387] To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used to pad zero bits. Accordingly, the rate dematching unit (820) may determine the position where zero bits were padded in the LDPC codeword and insert an LLR value corresponding to the shortened zero bits at that position.

[0388] In addition, the LLR insertion unit (822) of the rate dematching unit (820) can insert LLR values ​​corresponding to the punctured bits into the positions of the punctured bits in the LDPC codeword. In this case, the LLR values ​​corresponding to the punctured bits can be 0 or another predetermined value. In general, when parity bits with degree 1 are punctured, there is no effect on improving the performance of the LDPC decoding process, so they may not be used in the LDPC decoding process without inserting LLRs into some or all of the corresponding punctured positions. However, in order to increase the efficiency of the LDPC decoding process based on a parallel process, the LLR insertion unit (822) can insert a predetermined LLR value into positions corresponding to some or all of the punctured bits with degree 1, regardless of the improvement in decoding performance.

[0389] To this end, the receiving device (800) can store information on parameters used for puncturing in the transmitting device (700). Accordingly, the LLR insertion unit (822) can insert an LLR value (e.g., LLR = 0) corresponding to the punctured positions of the LDPC information word bits or parity bits. However, this process may be omitted for positions of some punctured parity bits.

[0390] The LLR combiner (823) can combine, i.e., add up, the LLR values ​​output from the LLR insertion unit (822) and the demodulation unit (810). Specifically, the LLR combiner (823) is a component corresponding to the puncturing / repetition / zero removal unit (742) of the transmitter (700) and can perform an operation corresponding to the repetition unit (742). First, the LLR combiner (823) can combine the LLR values ​​corresponding to the repeated bits with another LLR value. Here, the another LLR value may be an LLR value for the bits that formed the basis for generating the repeated bits in the transmitter (700), i.e., the LDPC information word bits or parity bits that were selected as repetition targets.

[0391] That is, as described above, the transmitting device (700) selects LDPC encoded bits, repeats them between LDPC information bits and LDPC parity bits, and transmits them to the receiving device (800). Accordingly, the LLR value for the LDPC encoded bits can be composed of an LLR value for the repeated LDPC encoded bits and an LLR value for the non-repeated LDPC encoded bits. The LLR combiner (823) can combine the LLR values ​​for the same LDPC encoded bits.

[0392] To this end, the receiving device (800) can store information about parameters used for repetition in the transmitting device (700). Accordingly, the LLR combiner (823) can determine the LLR value for the repeated LDPC encoded bits and combine it with the LLR value for the LDPC encoded bits that formed the basis of the repetition.

[0393] Additionally, the LLR combiner (823) can combine the LLR value corresponding to the retransmitted or IR (increment redundancy) bits with another LLR value. Here, the other LLR value can be an LLR value for some or all of the LDPC codeword bits that formed the basis for generating the retransmitted or IR bits in the transmitting device (700).

[0394] As described above, when a NACK occurs for HARQ, the transmitting device (700) can transmit some or all of the codeword bits to the receiving device (800).

[0395] Accordingly, the LLR combiner (823) can combine the LLR values ​​for bits received through retransmission or IR with the LLR values ​​for LDPC codeword bits received through the previous frame.

[0396] To this end, the receiving device (800) can store information on parameters used by the transmitting device (700) to generate retransmission or IR bits. Accordingly, the LLR combiner (823) can determine an LLR value for the number of retransmission or IR bits and combine it with an LLR value for LDPC encoded bits that serve as the basis for generating retransmission bits.

[0397] The deinterleaver (824) can deinterleave the LLR value output from the LLR combiner (823).

[0398] Specifically, the deinterleaver unit (824) is a component corresponding to the interleaver (741) of the transmitting device (700) and can perform an operation corresponding to the interleaver (741).

[0399] To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used for interleaving. Accordingly, the deinterleaver (824) may reversely perform the interleaving operation performed by the interleaver (741) on the LLR values ​​corresponding to the transmitted LDPC coded bits, thereby deinterleaving the LLR values ​​corresponding to the transmitted LDPC coded bits.

[0400] The LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820).

[0401] Specifically, the LDPC decoding unit (830) is a component corresponding to the LDPC encoding unit (730) of the transmitting device (700) and can perform an operation corresponding to the LDPC encoding unit (730).

[0402] To this end, the receiving device (800) may store information about parameters used by the transmitting device (700) to perform LDPC encoding according to the mode. Accordingly, the LDPC decoding unit (830) may perform LDPC decoding based on the LLR value output from the rate dematching unit (820) according to the mode.

[0403] For example, the LDPC decoding unit (830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (820) based on an iterative decoding method based on a sum-product algorithm, and output bits whose errors are corrected according to the LDPC decoding. The LDPC decoding unit (830) performs LDPC decoding on the LDPC codeword based on a parity check matrix or an exponential matrix or sequence corresponding thereto. In addition, LDPC decoding can be performed using a parity check matrix defined differently according to a code rate (i.e., a code rate of the LDPC code). The LDPC decoding unit (830) can generate information word bits by performing LDPC decoding by passing the LLR value corresponding to the LDPC codeword bits through an iterative decoding algorithm. Here, the LLR value is a channel value corresponding to the LDPC codeword bits, and can be expressed in various ways.

[0404] The zero removal unit (840) can remove zero bits from the bits output from the LDPC decoding unit (830).

[0405] Specifically, the zero removal unit (840) is a component corresponding to the zero padding unit (720) of the transmitting device (700) and can perform an operation corresponding to the zero padding unit (720).

[0406] To this end, the receiving device (800) may store information about the parameters used to pad zero bits in the transmitting device (700). Accordingly, the zero removal unit (840) may remove zero bits that were padded in the zero padding unit (720) from the bits output from the LDPC decoding unit (830).

[0407] The desegmentation unit (850) is a component corresponding to the segmentation unit (710) of the transmitting device (700) and can perform an operation corresponding to the segmentation unit (710).

[0408] To this end, the receiving device (800) may store information about the parameters that the transmitting device (700) used for segmentation. Accordingly, the desegmentation unit (850) can restore the bits before segmentation by combining the bits output from the zero removal unit (840), i.e., segments for variable-length input bits.

[0409] FIG. 9 shows a structural diagram of an LDPC decoding unit according to an embodiment of the present disclosure.

[0410] Meanwhile, as described above, the LDPC decoding unit (830) can perform LDPC decoding using an iterative decoding algorithm, and in this case, the LDPC decoding unit (830) can be configured with a structure as shown in FIG. 9. However, the detailed configuration illustrated in FIG. 9 is also just an example.

[0411] According to FIG. 9, the decryption device (900) includes an input processor (901), a memory (902), a variable node operator (904), a controller (906), a check node operator (908), and an output processor (910).

[0412] The input processor (901) stores the input value. Specifically, the input processor (901) can store the LLR value of the received signal received through the channel.

[0413] The controller (906) determines the number of values ​​input to the variable node operator (904) and the address value in the memory (902), the number of values ​​input to the check node operator (908) and the address value in the memory (902), etc. based on the block size (i.e., the length of the codeword) of the received signal received through the channel and the parity check matrix corresponding to the code rate.

[0414] The memory (902) stores input data and output data of the variable node operator (904) and the inspection node operator (908).

[0415] The variable node operator (904) receives data from the memory (902) based on the address information of the input data and the number information of the input data received from the controller (906) and performs a variable node operation. Thereafter, the variable node operator (904) stores the variable node operation results in the memory (902) based on the address information of the output data and the number information of the output data received from the controller (906). In addition, the variable node operator (904) inputs the variable node operation results to the output processor (910) based on the data received from the input processor (901) and the memory (902). Here, the variable node operation has been described above based on FIG. 6.

[0416] The inspection node operator (908) receives data from the memory (902) and performs inspection node operations based on the address information of the input data and the number information of the input data received from the controller (906). Thereafter, the inspection node operator (908) stores the inspection node operation results in the memory (902) based on the address information of the output data and the number information of the output data received from the controller (906). Here, the inspection node operation has been described above based on FIG. 6.

[0417] The output processor (910) makes a hard decision on whether the information word bits of the codeword of the transmitting side are 0 or 1 based on the data input from the variable node operator (904), and then outputs the hard decision result, and the output value of the output processor (910) becomes the final decrypted value. In this case, the hard decision can be made based on the sum of all message values ​​input to one variable node in FIG. 6 (the initial message value and all message values ​​input from the check node).

[0418] Meanwhile, the memory (902) of the decoding device (900) can store information on the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC decoding unit (830) can perform LDPC decoding using this information. However, this is only an example, and the relevant information may be provided from the transmitting side.

[0419] For reference, in this disclosure, the FEC (forward error correction) technique of a communication system is explained only with respect to LDPC codes, but in general, FEC encoding and decoding of a communication system can be subdivided into concatenated codes such as outer codes and inner codes. According to the definition of outer codes and inner codes, the transmitter performs inner encoding after outer encoding, and the receiver performs inner decoding after inner decoding.

[0420] In the case of external codes, algebraic codes that enable relatively simple error detection or correction, such as CRC (cyclic redundancy check) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and Reed-Solomon (RS) codes, are often used, but they are not necessarily limited to these, and multiple codes can also be applied overlappingly.

[0421] For inner codes, relatively complex but excellent error correction capabilities encoding methods such as LDPC codes, Turbo codes, and Polar codes are widely used, but it is not necessarily limited to these. (For example, tail-biting convolutional codes or other algebraic codes can be used, and overlapping application of multiple codes is also possible.) For reference, in the 3GPP 5G system, CRC codes are used for outer codes, LDPC codes are used for inner codes for data channels, and Polar codes are used for inner codes for control channels.

[0422] Various broadcasting and communication systems use LDPC codes optimized for each system. In this disclosure, a system using an LDPC code defined based on a parity check matrix having the same structure as the LDPC code used in the 3GPP 5G system is described, but is not necessarily limited thereto. In addition, a communication system including a 5G or 6G system may apply rate matching at the transmitter and rate dematching at the receiver to support various code rates and various code lengths. However, in a system that performs encoding / decoding based on a fixed LDPC code, such as some broadcasting systems, not only rate matching or rate dematching but also all or part of other operations may be omitted.

[0423] FIG. 10 shows the general structure of a parity check matrix of an LDPC code, which is an internal code applied to an FEC encoding unit (not shown) and an FEC decoding unit (not shown) to be described in the present disclosure.

[0424] The number of columns of the parity check matrix illustrated in FIG. 10 is N, and the number of rows is (M1+ M2) (provided that M1, M2≥0, M1+ M2>0). In general, when the parity check matrix has the full rank, the number of columns corresponding to the information word bits in the parity check matrix is ​​equal to the total number of columns minus the total number of rows. That is, if the parity check matrix of FIG. 10 has the full rank (M1+ M2), it means that the number of information word bits K becomes N-(M1+ M2). In the present disclosure, for convenience, only the case where the parity check matrix of FIG. 10 has the full rank is described, but it is not necessarily limited thereto.

[0425] First, the parity-check matrix of FIG. 10 can be divided into a first part of the parity-check matrix composed of submatrices A (1010) and B (1020) and a second part of the parity-check matrix composed of submatrices C (1040), D (1050), and E (1060) (however, if either M1 or M2 is 0, the first part and the second part may not be divided). Submatrix O (1030) means a 0-matrix of the size (M1 × M2). Since the submatrix O (1030) is a 0-matrix of the size (M1 × M2), even if it is included in the first part of the parity-check matrix, it has no effect on the matrix operation. For this reason, in the present disclosure, for convenience, the first part of the parity check matrix is ​​defined as a matrix composed of submatrices A (1010) and B (1020) excluding the 0-matrix of size (M1× M2), but if necessary, the first part of the parity check matrix may also include the 0-matrix of size (M1× M2).

[0426] If the parity check matrix of the above Fig. 10 is defined as a QC LDPC code with a lifting size or block size of Z, the parity check matrix of the above Fig. 10 and , ( , ) about can correspond to a basic matrix or weight matrix having a size of . Similarly, the first part of the parity check matrix consisting of submatrices A(1010) and B(1020) is or The second part of the parity check matrix, which corresponds to a submatrix of the fundamental matrix or weight matrix of size and consists of submatrixes C(1040), D(1050) and E(1060), or It corresponds to a submatrix of the fundamental matrix or weight matrix of size.

[0427] For convenience, the parity check matrix of the above figure 10 is called H, and the information word bits (or information word bit vector) corresponding to the submatrix A (1010) or C (1040) are and the first parity bits (or first parity bit vector) corresponding to the submatrix B(1020) or D(1050) and the second parity bits (or second parity bit vector) corresponding to the submatrix E(1060) Then, from mathematical expression 1, we can obtain a relationship such as mathematical expression 13.

[0428] [Equation 13]

[0429]

[0430] Referring to the above mathematical expression 13, the first parity vector can be obtained (or calculated or determined) based on the information word bit vector i and the first part of the parity check matrix. Also, the parity vector After obtaining the information word bit vector , the above parity vector And the parity vector based on the second part of the parity check matrix can be obtained (or calculated or determined).

[0431] In this disclosure, information word bit vector Based on the first parity vector The first part of the parity check matrix consisting of A(1010) and B(1020) required to generate may be conveniently called a core part or matrix, a kernel part or matrix, or a precoding part or matrix. In addition, the information word bit vector and / or the first parity vector Based on the second parity vector The second part of the parity check matrix consisting of C(1040), D(1050) and E(1060) required to generate may be called an extension part or a single parity-check extension part.

[0432] As a concrete example, the basic matrix 1 defined in the 3GPP 5G standard described above and basic matrix 2 Each core matrix part is represented as follows.

[0433] Core matrix of:

[0434] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

[0435] 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

[0436] 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

[0437] 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

[0438] Core matrix of:

[0439] 0 1 2 3 6 9 10 11

[0440] 0 3 4 5 6 7 8 9 11 12

[0441] 0 1 3 4 8 10 12 13

[0442] 1 2 4 5 6 7 8 9 10 13

[0443] The size of the core matrix is ​​4×26, The size of the core matrix is ​​4×14. Also, the sizes of the core matrices based on the parity check matrix are 4Z×26Z and 4Z×14Z, respectively. As a specific example, in the 3GPP 5G standard TS 38.212, the lifting size set index i LS A part of the exponent matrix of the LDPC code defined for the case where = 0 is shown in Figs. 11a and 11b. The part corresponding to the core matrix of the basic matrix or parity check matrix in Figs. 11a and 11b is as follows.

[0444] , Core matrix of:

[0445] 250 69 226 159 100 10 59 229 110 191 9 195 23 190 35 239 31 1 0

[0446] 2 239 117 124 71 222 104 173 220 102 109 132 142 155 255 28 0 0 0

[0447] 106 111 185 63 117 93 229 177 95 39 142 225 225 245 205 251 117 0 0

[0448] 121 89 84 20 150 131 243 136 86 246 219 211 240 76 244 144 12 1 0

[0449] , Core matrix of:

[0450] 9 117 204 26 189 205 0 0

[0451] 167 166 253 125 226 156 224 252 0 0

[0452] 81 114 44 52 240 1 0 0

[0453] 8 58 158 104 209 54 18 128 0 0

[0454] Meanwhile, in the present disclosure, a parity check matrix based on the following conditions may be considered for the parity check matrix corresponding to the above-described FIG. 10.

[0455] Hereinafter, submatrix A(1010) and submatrix B(1020) may be referred to as the first submatrix and the second submatrix, respectively. In addition, the cyclic permutation matrix below is determined based on the lifting size Z. It may mean a cyclic permutation matrix having a size of , and may be configured as in mathematical expression 5 or mathematical expression 6, for example. In addition, in the present disclosure, a cyclic matrix may mean a matrix in which cyclic permutation matrices are overlapped.

[0456] Condition 1(a): In the parity check matrix for the QC-LDPC code of Fig. 10, the submatrix B(1020) is In the case where the circulant permutation matrices of the size do not include nested circulant matrices, the weights of all column blocks of the submatrix B(1020) are 2 or more, and at least one column block with an odd weight of 3 or more can be included in the submatrix B(1020). In addition, the basic matrix corresponding to the submatrix B(1020) All columns of the matrix have a weight of 2 or greater, and the columns with an odd weight of 3 or greater are the basic matrix. may contain at least one or more of:

[0457] Condition 1(b): In the parity check matrix for the QC-LDPC code of Fig. 10, the submatrix B(1020) is If the circulant permutation matrices of the size include at least one nested circulant matrix, the weights of all column blocks of the submatrix B(1020) are 2 or greater, and at least one column block whose weight is an odd number of 3 or greater is included in the submatrix B(1020). In addition, the weight matrix corresponding to the submatrix B(1020) In the weight matrix, the sum of the elements of all columns is 2 or more, and the column whose sum of the elements of the column is an odd number of 3 or more At least one of the above is included. The weight of the column block containing the nested circulant matrices of circulant permutation matrices of size 2 may be 2 or 3 or more.)

[0458] Condition 2: All column weights and row weights of the submatrix E(1060) of the above Fig. 10 are 1. In addition, the column weights and row weights of the submatrix of the basic matrix and the weight matrix corresponding to the above submatrix E(1060) are all 1. Therefore, E(1060) and the submatrix of the basic matrix and the weight matrix corresponding to E(1060) are identity matrices or matrices that are converted to identity matrices when appropriate column permutation or row permutation is applied. (That is, E(1060) is an identity matrix or a matrix having an equivalent algebraic property.) If the parity check matrix of the above Fig. 10 is defined as a quasi-cyclic parity check matrix, the submatrix E has multiple They can be classified into size identity matrices.

[0459] The above FIGS. 11a and 11b are examples of parity check matrices that satisfy at least one of Condition 1(a), Condition 1(b), or Condition 2. As briefly described above, FIG. 11a is an example of the case where K = 22*Z, M1 = 4*Z, and M2 = 2*Z in FIG. 10, and FIG. 11b is an example of the case where K = 10*Z, M1 = 4*Z, and M2 = 7*Z in FIG. 10. Note that since the code rate of the LDPC code corresponding to the parity check matrices of FIGS. 10, 11a, and 11b is K / N, a codeword with a lower code rate can be generated as M2 decreases. In other words, according to the present disclosure, LDPC encoding and decoding can be performed based on a parity check matrix that can support a lower code rate by further expanding columns of degree 1 while including the above-described FIGS. 11a and 11b.

[0460] When a set of lifting sizes is used for LDPC encoding or decoding for a parity check matrix of a quasi-cyclic LDPC code, the number of columns constituting one column block of the parity check matrix is ​​greater than or equal to the minimum value of the lifting size. For example, when the values ​​in Table 6 are used as the lifting sizes, the number of columns constituting one column block of the parity check matrix may be at least 4 or more. Therefore, in a communication system in which the lifting sizes in Table 6 are practically applied to a parity check matrix of an LDPC code having a structure as in FIGS. 10, 11a, and 11b that satisfies at least one of Condition 1(a), Condition 1(b), or Condition 2, this means that the number of columns with degree 3 in the submatrix B(1020) is at least 4 or more.

[0461] Note that the core matrix in the parity check matrix or base matrix or weight matrix can also be defined in a form that satisfies at least one of Condition 1(a), Condition 1(b), or Condition 2 by adding one or two more rows as follows.

[0462] Core matrix of:

[0463] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

[0464] 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

[0465] 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

[0466] 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

[0467] 0 1 26

[0468] Core matrix of:

[0469] 0 1 2 3 6 9 10 11

[0470] 0 3 4 5 6 7 8 9 11 12

[0471] 0 1 3 4 8 10 12 13

[0472] 1 2 4 5 6 7 8 9 10 13

[0473] 0 1 11 14

[0474] However, in the present disclosure, for convenience, a parity check matrix [A(1010) B(1020)] including a partial matrix B that satisfies only Condition 1(a) or Condition 1(b) is regarded as a core matrix (or kernel matrix or precoding matrix). That is, in the present invention, the first part of the basic matrix or the first part of the parity check matrix or the core matrix / part or the kernel matrix / part, etc. means a partial matrix from which columns corresponding to parity bits of degree 1 and rows directly related to the parity bits of degree 1 are excluded.

[0475] As an embodiment of the present disclosure, a method for improving the performance of an LDPC code according to a weight matrix and a method for improving the decoding convergence speed are described.

[0476] First, the basic matrix 2 defined in [How to determine the basic matrix] The core matrix consists of four rows, which can also be expressed as a weight matrix as in Equation 14. Basic matrix 1 or base matrix 2 An LDPC code defined by is one Since we define that one cyclic permutation matrix corresponds to a size block, the base matrix and the weight matrix are basically the same.

[0477] [Equation 14]

[0478]

[0479] In this way, one LDPC codes, which are designed so that at most one cyclic permutation matrix corresponds to a block of size, are suitable for performing layered decoding in units of one row block during decoding. In other words, the structure of the LDPC code is suitable for performing decoding through a Z-unit parallel processing processor. Layered decoding refers to an operation of sequentially performing decoding for each layer. Therefore, decoding may be performed sequentially for each row block, or decoding may be performed for each layer by configuring multiple row blocks as one layer. Meanwhile, although layered decoding in the present disclosure is defined as an operation of sequentially performing decoding for each layer, performing decoding sequentially only means performing decoding for each layer, and does not mean that decoding must be performed in the order of the layer indexes. In addition, performing decoding sequentially in the present disclosure may mean performing decoding sequentially according to a layered decoding order or pattern (or sequence) described below. Additionally, depending on the structure of a parity check matrix, some layers may be composed of one row block and other layers may be composed of multiple row blocks.

[0480] This layered decoding method typically performs parallel processing on a basic unit of a layer consisting of one row block or multiple row blocks, so one iteration of decoding can be considered complete when decoding is performed for the total number of row blocks. This means that if there are enough parallel processing processors, the decoding throughput through layered decoding is inversely proportional to the number of row blocks. However, if the same code length is supported using a parity check matrix with a small number of row blocks, the lifting size Z value increases further, so the amount of parallel processing processors required to simultaneously decode one row block increases.

[0481] For example, the above weight matrix It consists of 4 rows and 14 columns, and the weights of each column are 3, 3, 2, 3, 3, 2, 3, 3, 3, 3, 2, 2, 2. If it consists of 3 rows and 13 columns, and the weight distribution is similar to the weight matrix It consists of 2 rows and 12 columns. and the weight distribution is similar to the weight matrix It can be structured as follows:

[0482]

[0483] If each weight matrix , , LDPC codes with the same code length can be generated using , and the lifting size corresponding to each parity check matrix can be , , If so, , There is a relationship between . Also, in the LDPC decoder, each If the number of parallel processing processors allowed, the approximate throughput of decryption information is Is 1.5 times of Is It can be twice as much.

[0484] In this way, when sufficient parallel processing processors are available, reducing the number of row blocks can increase the decryption information processing capacity inversely. Therefore, for systems requiring extremely high decryption information processing capacity, if more parallel processing processors are available, it is advantageous to keep the number of rows in the base or weight matrix, or in other words, the number of row blocks in the parity check matrix, small.

[0485] While keeping the number of rows in the base matrix or weight matrix, or in other words, the number of row blocks in the parity check matrix, small may be beneficial from the perspective of decoding information processing capacity, setting the number of row blocks too small can severely limit the algebraic properties of the LDPC code, such as its cycle characteristics or minimum distance characteristics, and can result in performance degradation. Therefore, the base matrix or weight matrix must be determined by simultaneously considering the system's target information processing capacity and target error correction capability.

[0486] As an embodiment of the present disclosure, a method for improving code performance while achieving high decoding throughput is proposed. In particular, the present disclosure proposes algebraic properties that a core matrix portion of a basic matrix or a weight matrix, which is closely related to the maximum decoding throughput or peak data rate of a system, must satisfy. Of course, if the parity check matrix does not include a second part of the parity check matrix composed of submatrices C (1040), D (1050), and E (1060) of FIG. 10, the core matrix may be identical to the basic matrix or the weight matrix.

[0487] One of the conditions that the core matrix of the parity check matrix must satisfy is that when two columns with only one non-zero element are selected from the weight matrix corresponding to the core matrix, ( ) should not contain non-zero elements in only one row. As a simple example, , , , , …, etc. are applicable. The minimum distance of the parity check matrix corresponding to the weight matrix or the core matrix including this structure is Since it is below, there is a high possibility that the error floor phenomenon will easily occur. Therefore, , , , …, in any two columns with only one non-zero element, the non-zero elements must be located in different rows. This means that for the elementary matrix, all non-zero elements in columns with weight 1 are located in different rows. The above can be defined as conditions 3(a) and 3(b) below.

[0488] Condition 3(a): All columns of the basic matrix or weight matrix corresponding to the core matrix have weights greater than or equal to 2, or the number of columns with weight 1 is at most 1.

[0489] Condition 3(b): If there are two or more columns with weight 1 among the columns of the basic matrix or weight matrix corresponding to the core matrix, the non-zero elements included in the columns with weight 1 are located in different rows.

[0490] The above conditions 3(a) and 3(b) are satisfied when the number of column blocks consisting of only one circulating permutation matrix or circulating matrix included in the core matrix is ​​at most 1, or when the core matrix includes two or more circulating permutation matrix or circulating matrix-only column blocks. It means that the size cyclic permutation matrix or cyclic matrices are necessarily included in different row blocks. In addition, the above conditions 3(a) and (3b) are structures to prevent serious error floor phenomenon, but if an even better error floor characteristic is to be obtained, the following condition 4 may be additionally added. As described above, the above cyclic permutation matrix or cyclic matrix It can have any size.

[0491] Condition 4: The weight of the column corresponding to the information bit (or input bit or code block) in the parity check matrix corresponding to the core matrix is ​​3 or greater.

[0492] The above condition 4 is the basic matrix 2 of mathematical expression 14. The encoding gain may be reduced by ensuring that the weight of the column corresponding to the information bit is not 2, as in the corresponding parity check matrix, but it can be applied when trying to improve the error floor phenomenon.

[0493] The above condition 4 is that the submatrix A(1010) in the parity check matrix for the QC-LDPC code If the circulant permutation matrices of the size do not contain nested circulant matrices, the weight of all column blocks of the submatrix A(1010) is 3 or more, and the fundamental matrix corresponding to the submatrix A(1010) It means that the weight of all columns is 3 or more. Also, in the parity check matrix for QC-LDPC code, the submatrix A(1010) If the circulant permutation matrices of the size include at least one nested circulant matrix, the weight of all column blocks of the submatrix A(1010) is 3 or more, and the weight matrix corresponding to the submatrix A(1010) It means that the sum of all the elements of the column is 3 or more.

[0494] Another condition that the core matrix of the parity check matrix must satisfy is that the weight matrix corresponding to the core matrix does not contain an element greater than or equal to 3. In general, if the core matrix of the weight matrix contains an element greater than or equal to 3, it means that three or more cyclic permutation matrices correspond to the corresponding position. If there are three or more circulant permutation matrices that constitute a circulant matrix of size that overlap, Regardless of the value, the maximum length of the cycle is limited to 6. Since the performance improvement effect by iterative decoding is reduced when the cycle length is short, the parity check matrix corresponding to the weight matrix or core matrix including values ​​of 3 or more as elements is suitable for use when the code length is short or the code rate is relatively high. Since this disclosure deals with a design method of an LDPC code supporting various code rates and various code lengths, the core matrix of the weight matrix does not include elements of 3 or more. (Of course, it may be included in the part corresponding to the single parity check extension part.) The above can be defined as Condition 5 below.

[0495] Condition 5: The weight matrix corresponding to the core matrix consists of only 0 and 1, or only 0, 1, and 2.

[0496] Another condition that the core matrix must satisfy is the first parity vector The submatrix B(1020) of Fig. 10 corresponding to must have a maximum rank to enable efficient encoding, and the following restrictive structure is desirable to prevent serious degradation of cycle characteristics.

[0497] Condition 6(a): If the weight matrix corresponding to the core matrix has four rows, then the submatrix corresponding to B(1020) in the weight matrix and the fundamental matrix is ​​one of the following:

[0498]

[0499] Condition 6(b): If the weight matrix corresponding to the core matrix consists of three rows, the submatrix of the fundamental matrix corresponding to the submatrix B(1020) is , and the weight matrix is ​​one of:

[0500]

[0501] Condition 6(c): If the weight matrix corresponding to the core matrix consists of two rows, the submatrix of the fundamental matrix corresponding to the submatrix B(1020) is , and the weight matrix is ​​one of: , .

[0502] For reference, the above condition 6(a) shows the case where the weight matrix and the base matrix are the same, and condition 6(b) shows the case where the weight matrix is It has the same form as the fundamental matrix only if 0 is in the fundamental matrix or weight matrix shown in Conditions 6(a), 6(b), and 6(c). It means 0-matrix of size 1, identity matrix of size or cyclic permutation matrix (v > 0). Also, 2 is Circular matrix of size It means ( ).

[0503] In general, an upper bound on the cycle length can be predicted from the base matrix or weight matrix, but the cycle characteristics of the parity check matrix corresponding to the base matrix or weight matrix are unknown. For example, if the submatrix B(1020) or In each case, regardless of the values ​​of v1 and v2, the base matrix or weight matrix is or Although they are the same, their cycle characteristics are very different. If at least one of v1 or v2 is 0, or (or ) will generate a large number of 4-cycles, so basically v1, v2 , (or ) is set to an integer satisfying . Similarly In the case where v1 = 0, a large number of 4-cycles are generated, so basically v1 is An integer satisfying v2 is is set to an integer satisfying . The above is only a method to remove 4-cycles, and the values ​​of v1 and v2 can be limited in various ways to obtain longer cycles.

[0504] If the communication system applies the perforation of the information bits described in [Table 9], the following conditions that the core matrix must satisfy may be added.

[0505] Condition 7: In an LDPC encoding system where puncturing of information bits is applied, a submatrix of a core matrix composed only of columns corresponding to the punctured information bits has at least one row with a row weight of 1.

[0506] Since the bits punctured at the receiver are regarded as bits lost during the reception process, the probability that the punctured bits are 0 and 1 is determined to be the same. This usually means 1 when decoding is performed using the LR value, and 0 when decoding is performed using the LLR value, but it may be determined in a different form based on the values ​​used in the decoding process. When LDPC decoding is performed based on a parity check matrix that does not satisfy Condition 7, the punctured information bits may not be decoded unless ML (maximum likelihood) decoding or pseudo ML decoding is used. Since ML or pseudo ML decoding is not commonly used due to its complexity, the parity check matrix may be determined to satisfy Condition 7 to ensure decoding success.

[0507] If the LDPC code is a QC-LDPC code, the parity check matrix can be expressed based on the lifting size Z value and the basic matrix and / or weight matrix and / or exponent matrix, etc., and thus can be expressed as in the following condition 8.

[0508] Condition 8: In a QC-LDPC encoding system in which puncturing of information bits is applied in units of a lifting size Z or its multiples, a submatrix of a basic matrix composed of only a columns corresponding to a submatrix of a core matrix composed of only a*Z columns corresponding to the punctured a*Z (a: integer greater than or equal to 1) information bits has at least one row with weight 1. In addition, a submatrix of a weight matrix composed of only a columns corresponding to a submatrix of a core matrix composed of only a*Z columns has at least one row with weight 1 and an element 1.

[0509] For example, in a QC-LDPC encoding system where puncturing of the information bits of 2Z bits is always applied, condition 8 implies that a = 2.

[0510] Meanwhile, in the present disclosure, at least one of the above conditions may be used to construct a parity check matrix. That is, the parity check matrix may be determined to satisfy one of the above conditions or a combination of at least two of the above conditions.

[0511] As an embodiment of the present disclosure, a method for improving the error floor performance of an LDPC code is proposed. In general, the error floor phenomenon of an LDPC code is greatly affected by the cycle characteristics of the Tanner graph. However, since the cycle characteristics of a QC LDPC code on the Tanner graph are determined by the relationship between the base matrix and the indices or cyclic shift values ​​of the cyclic permutation matrix, not only the positions of the cyclic permutation matrix constituting the parity check matrix but also the cyclic shift values ​​must be appropriately selected.

[0512] In the present disclosure, first parity bits (or first parity bit vector) in the first part of the parity check matrix composed of sub-matrices A (1010) and B (1020) in FIG. 10 We propose an algebraic property that the submatrix B(1020) corresponding to must satisfy.

[0513] The size of the above submatrix B(1020) is (or ), and the submatrix B(1020) is (or ) corresponds to the basic matrix or weight matrix of the size. In addition, the first column block of the submatrix B(1020) is composed of three cyclic permutation matrices. At this time, the cyclic permutation matrix may include an identity matrix. That is, in the present disclosure, the cyclic permutation matrix is ​​defined as a matrix in which each element of the identity matrix is ​​cyclically shifted by i, and when the value of i is 0, the cyclic permutation matrix may be an identity matrix. This can be applied throughout the detailed description of the present disclosure. In addition, the remaining column blocks of the submatrix B(1020) are composed of two cyclic permutation matrices or identity matrices. In the present invention, for convenience, the remaining column blocks are expressed only when the identity matrix is ​​composed of a double diagonal structure, but in general, it is not necessary to be limited thereto.

[0514] A specific example of the partial matrix B(1020) is shown in Mathematical Expression 15. The partial matrix B(1020) can be determined based on at least one of the matrices included in Mathematical Expression 15 below. However, the embodiment of the present disclosure is not limited thereto, and various matrices satisfying the above characteristics (the first column block is composed of three cyclic permutation matrices, and the remaining column blocks are composed of two cyclic permutation matrices or an identity matrix) can be considered.

[0515] [Equation 15]

[0516]

[0517] In the above mathematical formula 15 , , , The first column block contains three different cyclic permutation matrices , , It consists of . Also, in mathematical expression 15, for convenience, Although only the cases where the values ​​are 3, 4, and 5 are shown, a submatrix B(1020) can be similarly defined for integers greater than those. Furthermore, matrices that can be transformed into a submatrix B(1020) of the above form through an appropriate invertible transform process can be considered as algebraically identical matrices.

[0518] In the present disclosure, the mathematical expression 15 above , , , In addition, we propose a method for improving the cycle characteristics for larger submatrix B(1020) of similar form. For convenience, details on the method for analyzing the cycle characteristics of QC LDPC codes and some algebraic properties are omitted in this disclosure, but reference is made to the reference [Myung2005].

[0519] [Myung2005]

[0520] S. Myung, K. Yang, and J. Kim, “Quasi-Cyclic LDPC Codes for Fast Encoding,” IEEE Transactions on Information Theory, vol. 51, No. 8, pp. 2894-2901, Aug. 2005.

[0521] If, as in Equation 15, the submatrix B(1020) has a dual diagonal structure with the size of the remaining column blocks excluding the first column block, which is composed of identity matrices, the indices (or cyclic shift values) of the cyclic permutation matrix of the first column block were used for encoding convenience. , , At least two values ​​among them were set to the same value. In this case, the values ​​used in the encoding process are Size of The matrix is ​​an identity matrix or a simple cyclic permutation matrix It becomes, Inverse matrix of is the identity matrix or It is simplified together, so the encoding process becomes simpler. (For detailed encoding process of QC LDPC code, refer to [Myung2005]) As a specific example, If set to Is and become Is Therefore, efficient encoding can be performed. Similarly, If set to Is and become Is Therefore, efficient encoding can be performed.

[0522] however In this case, the length on the Tanner graph is according to the structure shown in the following mathematical expression 16. In cycle The dog always exists. In other words, if If the value of is fixed, the lifting size and index Regardless of the value, the length There is always a cycle in the QC LDPC code. (For detailed information on the cycle characteristics of QC LDPC codes, see [Myung2005].)

[0523] [Equation 16]

[0524]

[0525] Not only that In this case, due to the structure as in the following mathematical expression 17, the lifting size and index Regardless of the value There are always shorter cycles than that.

[0526] [Equation 17]

[0527]

[0528] should When the value is appropriately large, the cycle characteristics of the Tanner graph corresponding to structures such as Equations 16 and 17 may not significantly affect the performance of the LDPC code. However, When the value is relatively small, the BLER may increase due to the error floor phenomenon, which becomes a non-negligible problem as the target BLER of the system is lower.

[0529] In order to solve this problem, in the present invention, the indices (or cyclic shift values) of the cyclic permutation matrices constituting the first column block of the submatrix B(1020) having the structure as in mathematical expression 15 , , We propose a method to improve cycle characteristics by limiting the LDPC encoding process to satisfy certain algebraic conditions. In addition, the method improves cycle characteristics while also providing the necessary It explains that the computational complexity associated with matrices increases to a reasonable level.

[0530] If the lifting size for the parity check matrix of the QC LDPC code cast , ( is odd, When is an integer greater than or equal to 0, the indices (or circular shift values) of the cyclic permutation matrices that constitute the first column block of the submatrix B(1020) , , are distinct integers, satisfying at least some or all of the following conditions:

[0531] Index condition 1a: At least one of the differences between two indices (circular shift values) is a lifting magnitude. The greatest common divisor with is 1 or greater than 1 is the smallest number among the divisors of (i.e., and are mutually prime or greater than 1 ) has the least divisor as the greatest common divisor.

[0532] Index condition 1b: Two of the differences between the two indices are the lifting magnitudes. The common divisor with is 1 or greater than 1 It is the smallest number among the divisors of .

[0533] Index Condition 2a: At least one of the differences between the two exponents is ( )am.

[0534] Index Condition 2b: At least one of the differences between the two exponents is is 1 In this case ( ) and is an odd number greater than or equal to 3 In this case ( )am.

[0535] For reference, the difference between the exponents used in the above exponent conditions is , , It means back.

[0536] According to the above index condition 1a, the difference between the two indices is If and are relatively prime, the length of the cycle determined by the cyclic permutation matrix associated with the two indices is maximized. For example, The value of In the case where and are relatively prime, mathematical expression 17 The length of a cycle on a Tanner graph is determined by becomes. If and The greatest common divisor of The ramen cycle length is becomes. As a result As the value increases, the length of the cycle also increases.

[0537] As another example, The value of In the case where and are relatively prime, the cycle length determined by the structure of mathematical expression 16 is becomes. If and The greatest common divisor of The ramen cycle length is As a result, it can be seen that the cycle length is not fixed regardless of the Z value, but rather increases as the Z value increases. Considering only the cycle characteristics, the difference between the exponents is Although it is desirable that they are relatively prime, depending on the situation, the exponents may be chosen so that the greatest common divisor D is small (for example, so that it is the smallest divisor of Z greater than 1) by other conditions. For example, if the difference between the exponents cannot satisfy the property of being relatively prime to Z, the greatest common divisor It is desirable to select an exponent that makes the value smaller.

[0538] The above index condition 1b is a condition for further improving cycle characteristics by restricting the index condition more than index condition 1a. For example, and The value And in case they are mutually prime Not only are the cycle characteristics related to the indices a and b unique, but Likewise, the cycle characteristics related to the indices b and c are also improved. (The same holds true for other forms of submatrix B extended based on Equation 15 and Equation 15.)

[0539] Another form of submatrix B based on equation 15 and equation 15 is , , When all are different, the encoding process requires The matrix is defined as follows. The matrix is It is not easy to obtain, The density of weights of a matrix also often has a high density characteristic rather than a low density characteristic. That is, it has a low density characteristic. The matrix It has the characteristic that it does not guarantee the low density characteristic of the matrix. Because the high density nature of the matrix increases the encoding complexity, It is desirable that the density of the matrix be as low as possible, It is desirable for matrices to have a simple structure.

[0540] The above index conditions 2a and 2b are for efficient LDPC encoding. It is a condition for simplifying the matrix as much as possible. For example, in the above index condition 2a, In that case

[0541]

[0542] Become This is it. Here silver

[0543]

[0544] since can be determined relatively simply, but As the value increases It can be seen that the computational complexity increases. Therefore, depending on the complexity that is acceptable in the system, The values ​​can be used by appropriately limiting them. Typically, The value is It is recommended to use a range, but larger values ​​may be used depending on the system's allowable range.

[0545] For reference, the length is An arbitrary bit string About Circular permutation matrix of size Multiplying operation is a bit string operation rather than an actual matrix multiplication operation. About It is equivalent to performing a circular shift by a bit. In other words, the above operation means an operation or action with very low complexity, as it can be implemented as a bit shift operation rather than a matrix multiplication. In addition, Even in the process of calculating Rather than expanding and calculating each term, Computational complexity can be minimized through step-by-step calculations, as in the following example:

[0546]

[0547] In the above index condition 2a me In the same way, if Encoding can be performed by determining the difference between all two indices. However, In the case of the form, the cycle characteristics are likely to be poor. Therefore, for efficient encoding and good cycle characteristics, at least one of the differences between the two indices should be ( ) and the remaining exponent differences satisfy the exponent condition 1a or exponent condition 1b. In addition, the difference between the two exponents The above indices can be selected if at least one of the index conditions 1a or 1b is satisfied.

[0548] Index condition 2b is a condition that further improves cycle characteristics while enabling efficient encoding by restricting the index condition more than index condition 2a. When index condition 2b is satisfied, encoding complexity increases somewhat compared to existing 5G LDPC codes, but has the advantage of improving cycle characteristics. Of course, if there is no case that satisfies index condition 2b, the indices can be determined by considering index condition 2a. For reference, in index condition 2a, The difference between the two indices is , except that And you can always see that they are not the same. That is, The difference between the two exponents has a common divisor greater than 1. Satisfying That there is This means that the index condition 2b must be satisfied. By conditions And the difference between the two exponents is not prime, has as its common divisor.

[0549] As an embodiment of the present disclosure, a more specific example of constructing a submatrix B(1020) of FIG. 10 using the above exponential conditions is described.

[0550] First, consider a communication system or broadcasting system, such as 5G, where a set of lifting sizes is defined, as shown in Tables 3 through 8, and only lifting sizes included in the set can be applied. Furthermore, a separate parity check matrix or index matrix can be defined for each lifting size set. That is, in the cases of Tables 3 through 8, a parity check matrix or index matrix can be defined for each of the eight set indices.

[0551] In Equation 15 and another form of submatrix B extended based on Equation 15, , , Let us decide as follows. In general, to ( ) index for the submatrix B of the corresponding parity check matrix , , For convenience, since the values ​​may all be different , , It was expressed as .

[0552] Example 1 of selecting an index ( )

[0553] - is an arbitrary integer

[0554] - Is and here Is is an integer satisfying , that is, among the indices corresponding to the submatrix B, , Is is an integer satisfying . Here, Is , It means the greatest common divisor of Is It means any lifting size that belongs to the set of lifting sizes corresponding to .

[0555] - Is and here Is The largest lifting size among the lifting size values ​​belonging to the corresponding lifting size set It is one of the smaller lifting sizes.

[0556] If we calculate the difference between each index for the submatrix B determined through the above index selection example 1, an arbitrary lifting size About Therefore, it satisfies the index condition 1a, at Is One of the values, each of which Since the values ​​are multiples of each other ( drainage relationship), According to the definition of This is established and the index condition 1b is also satisfied. However, Therefore, index condition 2a and index condition 2b are the lifting size Satisfaction varies depending on the situation. For example, In this case, the index condition 2a and the index condition 2b are always satisfied, but In this case is established Circular permutation matrix of size and Since they are virtually the same, they may not satisfy the exponent conditions 2a and 2b. In other words, In this case, the structure is as in mathematical expression 16, which means that the cycle characteristics are not improved. In conclusion, in order to improve the cycle characteristics for lifting sizes of various lengths, It is desirable that the value be determined as small as possible.

[0557] However, the lifting size for LDPC encoding The value If it is relatively large compared to the value (i.e., at (if the value is large) It is highly likely that the encoding complexity will increase significantly due to matrix-related operations. Therefore, The value can be selected by considering the cycle characteristics and encoding complexity. If only the cycle characteristics improvement is considered, The smallest lifting size among the lifting size values ​​belonging to the corresponding lifting size set can be selected. Also, when considering the limited increase in encoding complexity, Among the lifting size values ​​belonging to the corresponding lifting size set, a lifting size that is greater than the smallest lifting size and smaller than the largest lifting size can be selected. Typically, the lifting sizes included in the lifting size set are , , … , When ( ), The value is ( ) can be set. Generally, , , … , If the values ​​are not consecutive integers, The value is , , … may be selected as an integer other than the above embodiment. In addition to the above embodiment, for other embodiments as well As previously explained, it can be selected based on various conditions, but detailed explanation may be omitted for convenience of explanation.

[0558] For convenience, as a concrete example of the index selection method, , in other words, An example of index selection when set to is shown below.

[0559] Example 2 of selecting an index ( )

[0560] -

[0561] - ( If set to , , )

[0562] - Is (or ) and here Is The largest lifting size among the lifting size values ​​belonging to the corresponding lifting size set It is one of the smaller lifting sizes.

[0563] If we calculate the difference between each index for the submatrix B determined through the above index selection example 2, This is an arbitrary lifting size Always about This is established, Become this Since this holds, index condition 1a and index condition 1b can be satisfied. As in the above index selection example 2. In this case as well as in general ) that satisfies For this, index conditions 1a and 1b can be satisfied. That is, In Jeong-su About, , , , the submatrix B set as satisfies the index condition 1a and the index condition 1b. In addition, Therefore, index condition 2a and index condition 2b are the lifting size Satisfaction varies depending on the situation. (or ) can be selected based on various conditions, taking into account cycle characteristic improvement and encoding complexity, as explained above.

[0564] A specific example related to index selection example 2 is described below.

[0565] Given a set of lifting sizes as in Table 8, a specific example of the submatrix B is given in the following mathematical expression 18. Mathematical expression 18 is An example of a submatrix B in the parity check matrix for is shown. (Matrix of Equation 15) Here is an example of setting the submatrix B. The submatrix B can be determined based on at least one of the matrices included in the following mathematical expression 18. However, the embodiments of the present disclosure are not limited thereto. That is, the following embodiment is an example of a case where 32 is selected among the lifting sizes, but any one of the lifting sizes included in Table 8 above can be selected. Accordingly, various matrices can be considered based on c determined according to the lifting size.

[0566] [Equation 18]

[0567] - (Choose 32 from lifting sizes)

[0568]

[0569] In the case of mathematical expression 18, the lifting size in the 0th lifting size set If the value is selected as 32 or less, such as 8, 16, or 32, From This has become a reality The matrix is ​​an identity matrix Become Also the identity matrix Since the encoding process becomes simpler, there is a disadvantage that the cycle characteristic is not improved. If the cycle characteristic is improved while considering the limited increase in encoding complexity, in the submatrix having the structure of the above mathematical expression 18, The corresponding exponent pair The following combinations may be possible:

[0570] [Table 10]

[0571]

[0572] The above Table 10 is only an example and is generally one of the lifting size values ​​smaller than Zmax. By selecting can be decided by

[0573] As one embodiment of the present disclosure, the above The value may be determined based on the largest lifting size among lifting sizes smaller than a specific reference value. Specifically, if the reference value is set to 96, in a system using lifting size sets such as [Table 3] to [Table 8], the numbers less than or equal to 96 in each lifting size set are 64, 96, 80, 56, 72, 88, 52, and 60 in that order. Therefore, in each lifting size set, based on the given reference value, the parity check matrix corresponding to the index of each lifting size set is defined. If the value is determined, the above The values ​​can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to each lifting size set index. If the reference value is set to 48, the above method can be used in the same way. The values ​​can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to the index of each lifting size set. For reference, when using the lifting size set excluding the numbers in () in [Table 3] or [Table 8], i LS = If the i-th largest lifting size among the lifting sizes included in the 1-person lifting size set is determined as the reference value, the corresponding parity check matrix defined according to each lifting size set index is The value has the characteristic that it is determined as an integer that adds 1 to the ith largest lifting size in each set.

[0574] In addition, for the uniformity of the encoding method, the ith largest lifting size in each lifting size set may be selected (i = 2, 3, 4, …). For example, in a system using lifting size sets as in [Table 3], the fifth largest numbers in each lifting size set are 16, 24, 20, 14, 18, 22, 13, 15. Therefore, based on the fifth largest number in each lifting size set, the corresponding parity check matrix defined according to each lifting size set index is If the value is determined (i=5), the above The values ​​can be defined as 17, 25, 21, 15, 19, 23, 14, 16 in order according to each lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values ​​can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values ​​can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set. If the value is determined (i=2), The values ​​can be defined as 129, 193, 161, 113, 145, 177, 105, 121 in order of lifting size set index.

[0575] In a system that uses the lifting size sets of values ​​excluding the values ​​in () in [Table 8], the fifth largest numbers in each lifting size set are 32, 48, 40, 28, 36, 44, 26, and 30. Therefore, based on the fifth largest number in each lifting size set, the corresponding parity check matrix defined according to each lifting size set index is If the value is determined (i=5), the above The values ​​can be defined as 33, 49, 41, 29, 37, 45, 27, 31 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values ​​can be defined as 65, 97, 81, 57, 73, 89, 53, 61 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values ​​can be defined as 129, 193, 161, 113, 145, 177, 105, 121 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set. If the value is determined (i=2), The values ​​can be defined as 257, 385, 321, 225, 289, 353, 209, 241 in order of the lifting size set index.

[0576] Also, as shown in the above mathematical formula 18 and the above table 10 and the corresponding examples, According to the pair, The matrix This is done, and the lifting size is determined according to the above index selection example 2. The value If less than or equal to This was established and eventually Therefore, the cycle characteristics are not improved, This establishment allows efficient LDPC encoding. Lifting size The value In larger cases Satisfying exists ( ) This becomes, and therefore By using the human nature, efficient LDPC encoding is possible, although the encoding complexity increases. Here, and The cycle length determined by the existing at It increases to . and or and The cycle length determined by satisfies exponential condition 1a and exponential condition 1b. It increases significantly in proportion to the value.

[0577] For convenience, as a concrete example of the index selection method, , in other words, An example of index selection when set to is shown below.

[0578] Example 3 of selecting an index ( )

[0579] -

[0580] - ( If set to , , )

[0581] - Is (or ) and here Is The largest lifting size among the lifting size values ​​belonging to the corresponding lifting size set It is one of the smaller lifting sizes.

[0582] If we calculate the difference between each index for the submatrix B determined through the above index selection example 3, This is an arbitrary lifting size Always about This is established, Become this Since this holds, index condition 1a and index condition 1b can be satisfied. As in the above index selection example 3. In this case as well as in general ) that satisfies For this, index conditions 1a and 1b can be satisfied. That is, In Jeong-su About, , , , the submatrix B set as satisfies the index condition 1a and the index condition 1b. In addition, Therefore, index condition 2a and index condition 2b are the lifting size Satisfaction varies depending on the situation. (or ) can be selected based on various conditions, taking into account cycle characteristic improvement and encoding complexity, as explained above.

[0583] Specific examples related to index selection example 3 are described below.

[0584] Given a set of lifting sizes as in Table 8, a specific example of the submatrix B is given in Equation 19 below. Equation 19 is given in Table 8. An example of a submatrix B in the parity check matrix for is shown. (Matrix of Equation 15) Here is an example of setting the submatrix B. The submatrix B can be determined based on at least one of the matrices included in the following mathematical expression 19. However, the embodiments of the present disclosure are not limited thereto. That is, the following embodiment is an example of a case where 32 is selected among the lifting sizes, but any one of the lifting sizes included in Table 8 above can be selected. Accordingly, various matrices can be considered based on c determined according to the lifting size.

[0585] [Equation 19]

[0586] - (Choose 32 from lifting sizes)

[0587]

[0588] In the case of mathematical expression 19, the lifting size in the 0th lifting size set If the value is selected as 32 or less, such as 8, 16, or 32, From This has become a reality The matrix is ​​a cyclic permutation matrix Become is a cyclic permutation matrix Since the encoding process becomes simpler, there is a disadvantage that the cycle characteristic is not improved. If the cycle characteristic is improved while considering the limited increase in encoding complexity, in the submatrix having the structure of the above mathematical expression 18, The corresponding exponent pair The following combinations may be possible:

[0589] [Table 11]

[0590]

[0591] The above Table 11 is only an example and is generally one of the lifting size values ​​smaller than Zmax. By selecting can be decided by

[0592] As one embodiment of the present disclosure, the above The value may be determined based on the largest lifting size among the lifting sizes smaller than a specific reference value. Specifically, if the reference value is set to 96, in a system using lifting size sets such as [Table 3] to [Table 8], the numbers less than or equal to 96 in each lifting size set are 64, 96, 80, 56, 72, 88, 52, and 60 in that order. Therefore, in each lifting size set, based on the given reference value, the parity check matrix corresponding to the index of each lifting size set is defined. If the value is determined, the above The values ​​can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to each lifting size set index. If the reference value is set to 48, the above can be defined in the same way. The values ​​can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to each lifting size set index. When using a lifting size set excluding the numbers in () in [Table 3] or [Table 8], i LS = If the i-th largest lifting size among the lifting sizes included in the 1-person lifting size set is determined as the reference value, the corresponding parity check matrix defined according to each lifting size set index is The value has the characteristic that it is determined by the i-th largest lifting size in each set.

[0593] In addition, for the uniformity of the encoding method, the ith largest lifting size in each lifting size set may be selected (i = 2, 3, 4, 5, 6, …). For example, in a system using lifting size sets as in [Table 3], the fifth largest numbers in each lifting size set are 16, 24, 20, 14, 18, 22, 13, 15. Therefore, based on the fifth largest number in each lifting size set, the corresponding parity check matrix defined according to each lifting size set index is If the value is determined (i=5), The values ​​can be defined as 16, 24, 20, 14, 18, 22, 13, 15 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values ​​can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values ​​can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the second largest number in each lifting size set. If the value is determined (i=2), The values ​​can be defined as 128, 192, 160, 112, 144, 176, 104, 120 in order of the lifting size set index.

[0594] In a system that uses the lifting size sets of values ​​excluding the values ​​in () in [Table 8], the fifth largest numbers in each lifting size set are 32, 48, 40, 28, 36, 44, 26, and 30. Therefore, based on the fifth largest number in each lifting size set, the corresponding parity check matrix defined according to each lifting size set index is If the value is determined (i=5), the above The values ​​can be defined as 32, 48, 40, 28, 36, 44, 26, 30 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the fourth largest number in each lifting size set. If the value is determined (i=4), The values ​​can be defined as 64, 96, 80, 56, 72, 88, 52, 60 in order according to the lifting size set index. Similarly, the parity check matrix corresponding to the lifting size set index is defined based on the third largest number in each lifting size set. If the value is determined (i=3), The values ​​can be defined as 128, 192, 160, 112, 144, 176, 104, 120 in order according to the lifting size set index. Similarly, based on the second largest number in each lifting size set, the corresponding parity check matrix defined according to the lifting size set index If the value is determined (i=2), The values ​​can be defined as 256, 384, 320, 224, 288, 353, 208, 240 in order of the lifting size set index.

[0595] Also, as shown in the above mathematical formula 19 and the above table 11 and the corresponding examples, According to the pair, The matrix This is done, and the lifting size is determined according to the above index selection example 3. The value If less than or equal to This was established and eventually Therefore, the cycle characteristics are not improved, , This establishment allows efficient LDPC encoding. Lifting size The value In larger cases Satisfying exists ( ) This becomes, and therefore By using the human nature, efficient LDPC encoding is possible, although the encoding complexity increases. Here, and The cycle length determined by the existing at It increases to . and or and The cycle length determined by satisfies exponential condition 1a and exponential condition 1b. It increases significantly in proportion to the value.

[0596] The above index selection examples 1, 2, and 3 are index selection methods for some cyclic permutation matrices constituting the submatrix B(1020) in the parity check matrix of FIG. 10, which simultaneously consider improvement of cycle characteristics and coding complexity. The above index selection examples propose a method in which the cycle characteristics are not improved when the code length is short due to a small lifting size, but the coding complexity is very low, and the coding complexity increases somewhat as the lifting size increases, but the cycle characteristics are improved. In general, as the length of an LDPC code is longer, it can be more sensitively affected by the error floor phenomenon due to the cycle characteristic, and the above methods, in which the cycle characteristics are further improved as the code length increases along with the lifting size, can be said to be methods that can improve the error floor phenomenon according to the length of the LDPC code.

[0597] Of course, when the lifting size is small and the code length is short, the cycle characteristics do not significantly affect the error floor phenomenon, but even when the lifting size is small, a method to improve the cycle characteristics can be applied.

[0598] As one embodiment of the present disclosure, a method for improving cycle characteristics when a code length is short is described.

[0599] Example 4 of selecting an index ( )

[0600] - is an arbitrary integer

[0601] - Is and here Is is an integer satisfying , that is, among the indices corresponding to the submatrix B, , Is is an integer satisfying . Here, Is , It means the greatest common divisor of Is It means any lifting size that belongs to the set of lifting sizes corresponding to . ( , is odd, )

[0602] - Is

[0603] or

[0604] If the system supports The size of is always If it is equal to or greater than It can be simply expressed as .

[0605] Example 4 of the above index selection is a cyclic permutation matrix We describe a method in which each index is not a fixed value, but is determined variably based on at least one lifting size Z. Therefore, the method proposed in the present disclosure can be applied not only to the lifting size sets of [Table 3] to [Table 8], but also to various other lifting size sets defined.

[0606] should at In this case Since this is not an integer, in the above example can be set to be, i.e., supported by the system. Depending on the values ​​and the given J value The value can be determined variably. If the system supports The value If it is greater than or equal to Since is always an integer, It can be decided in one way as follows.

[0607] The method of the above index selection example 4 satisfies index condition 1a and index condition 1b, and the lifting size Depending on the index condition 2a and the index condition 2, the satisfaction of the index condition 2 varies. For example, if the support The range of values If it is greater than or equal to, it satisfies exponent condition 2a and exponent condition 2b, If it is less than that, it is not satisfied.

[0608] According to the embodiment of the above index selection example 4, (or ) in this case and The cycle length determined by the existing at increases to , (or ) in this case increases to ( ) does not increase in this case. and or and The cycle length determined by satisfies exponential condition 1a and exponential condition 1b. It increases significantly in proportion to the value.

[0609] also (or ) in this case The matrix

[0610]

[0611] since,

[0612]

[0613] LDPC encoding is possible using . (or ) in this case The matrix

[0614]

[0615] since,

[0616]

[0617] Integers that satisfy ( ) exists, so LDPC encoding is possible in a similar way.

[0618] The method of the above index selection example 4 has the disadvantage that the maximum value of the cycle length that can be improved depending on the J value is fixed regardless of the lifting size Z, but has the advantage that the cycle characteristics are improved even when the lifting size Z is small. In other words, the cyclic permutation matrix The cycle characteristics can be improved for various lifting sizes by determining at least one of the indices of the cyclic permutation matrix to be variably determined based on the lifting size Z rather than all of the indices being fixed integer values.

[0619] For convenience, as a specific example of the above index selection example 4, , in other words, An example of index selection when set to is shown below.

[0620] Example 5 of selecting an index ( )

[0621] -

[0622] - ( )

[0623] - Is

[0624] or .

[0625] If the system supports The size of is always If it is equal to or greater than It can be simply expressed as .

[0626] As in example 5 of the above index selection In this case yes Any arbitrary It also satisfies index condition 1a and index condition 1b. That is, In Jeong-su About, , , (or ) The submatrix B set as satisfies the index condition 1a and the index condition 1b.

[0627] According to the same method as the above index selection example 5,

[0628]

[0629] Become Efficient encoding is possible using .

[0630] For convenience, as a more specific example of the above index selection example 4, , in other words, An example of index selection when set to is shown below.

[0631] Example 6 of selecting an index ( )

[0632] -

[0633] - ( )

[0634] - Is

[0635] or )

[0636] If the system supports The size of is always If it is equal to or greater than It can be simply expressed as .

[0637] As in example 6 of the above index selection In this case yes Any arbitrary It also satisfies index condition 1a and index condition 1b. That is, In Jeong-su About, , , (or ) The submatrix B set as satisfies the index condition 1a and the index condition 1b.

[0638] According to the same method as the above index selection example 6,

[0639]

[0640]

[0641] Efficient encoding is possible based on .

[0642] The index selection methods of the above index selection examples 4, 5 and 6 are such that the cycle length is at most It can be improved by. If If the value is relatively large, the cycle characteristics can be sufficiently improved even if the J value is not large. Typically, the J value is a parameter that indicates the number of rows in the core matrix part of the parity check matrix given in the system. It can be determined by considering the values ​​and target BLER values. For example, if the target BLER is relatively high or the core matrix For large values, J = 1, 2 may be sufficient, but if the target BLER is relatively low or the core matrix is For small values, it is desirable to set J = 2, 3, 4, …, etc.

[0643] In general, since the degree to which the performance of a code is affected by the cycle characteristics varies depending on the length of the code, it is also possible to set the J value differently depending on the lifting size. That is, at least one of the exponents is determined based on the lifting size, but when the lifting size is relatively small, If the value is small and the lifting size is relatively large, You can set the value to a large value ( ). When setting the J value differently depending on the lifting size, the standard lifting size and the appropriate , The value must be determined.

[0644] Various possible index selection methods, including the index selection examples 1 to 6, can be variably applied depending on the target BLER and / or lifting size of the system. For example, if the target BLER of the system is high, encoding can be performed using an existing method with the highest encoding efficiency even if the cycle characteristics are not improved because the cycle characteristics do not have a significant impact on the decoding performance of the code. However, if the target BLER is low, the index selection methods proposed in the present disclosure can be applied. Here, the high and low of the target BLER can be relatively determined when there are multiple target BLERs applicable in the system. For example, if the first target BLER is And the second target BLER When the first target BLER is higher than the second target BLER, it can be said that the first target BLER is higher than the second target BLER. If the first target BLER is , the second target BLER And the third target BLER work (or ), the first target BLER may be determined to be higher than the second target BLER and the third target BLER, and the first target BLER and the second target BLER may be determined to be higher than the third target BLER. In this way, when there are multiple target BLERs applicable to the system, the high and low of the BLER can be determined based on a specific BLER value, and then the index selection method proposed in the present disclosure can be variably applied based on this.

[0645] However, this is an embodiment of the present invention, and the index selection method proposed in the present disclosure can be applied when the target BLER is high or regardless of the target BLER, and can be applied variably based on other factors. In addition, since the index selection method described throughout the present disclosure refers to a method of selecting an index of a cyclic permutation matrix included in a submatrix of a parity check matrix (specifically, a submatrix B), the index selection method of the present disclosure can be described as a method of determining a parity check matrix or a method of determining a submatrix included in a parity check matrix. In addition, since the lifting size is closely related to the code length or TBS, etc., all processes determined based on the lifting size among the embodiments disclosed in the present invention can be changed to a method determined based on the code length or TBS. In addition, in the above index selection examples 1 to 6, the lifting size For convenience, " , , is expressed as "odd number", but is generally expressed as " as in [Table 7-1] or [Table 7-2] , , Is "The smallest lifting size in the set of lifting sizes" The same methods for selecting exponents can be applied even when the number is not restricted to odd numbers.

[0646] As a specific example of the application of the J value in Index Selection Example 4 to Index Selection Example 6, if the system target BLER is judged to be high, the J value is If the system target BLER is judged to be low, set the J value to a relatively large value. can be set to a value ( ). Also, the method of selecting these indices or the decision on the J value can be determined by considering the lifting size together. Generally, the reference BLER and / or lifting size is set to A, and a total of (A+1) different J values ​​can be distinguished. For example, if there are the first reference value, the second reference value, etc., the J value is , , … can be subdivided into, etc. In general, J can also be set to 0, in which case It refers to the existing method that enables the simplest encoding without improving cycle characteristics.

[0647] Note that the method for determining the target BLER at the terminal or base station can vary depending on the system. For example, the system target BLER may be directly indicated by upper-layer signaling, such as configured RRC (radio resource control) information, indirectly indicated based on configured CQI tables or MCS tables, or indirectly indicated based on configured service scenarios.

[0648] As one embodiment of the present invention, a method of variably applying the puncturing to reduce the decoding delay time of a terminal or base station in a system for transmitting and receiving data by puncturing information bits corresponding to some columns of a basic matrix or a parity check matrix, such as a 3GPP 5G standard technology, is described.

[0649] A technique in which some of the input bits or code block bits are punctured by the transmitter and not transmitted to the receiver is a method typically applied to obtain high encoding gain. In addition, unlike the method of puncturing some of the parity bits corresponding to relatively light columns in the parity check matrix, the input bits or code block bits to be punctured correspond to columns with high weight. For example, as shown in [Table 9], in the encoding process of the 5G NR system, the first of the input bits or code block bits bits are bits that are not transmitted, and are the basic matrix corresponding to the above-mentioned punctured information bits. or The first two columns are columns with relatively high weights in the entire basic matrix. Specifically, in the parity check matrix, the basic matrix corresponding to the first column of The weight of the dog column is 30, corresponding to the second column The weight of the dog column is 28, and the basic matrix in the parity check matrix corresponding to the first column of The weight of the dog column is 22, corresponding to the second column The weight of the dog column is 23. As such, the basic matrix or The front of the parity check matrix corresponding to The columns of the dog are columns with significantly higher weights than other columns in the entire parity check matrix.

[0650] Typically, the punctured information bits correspond to the columns with the highest weights in the basic matrix or parity check matrix. Typically, in order to obtain a large encoding gain, the weights of the corresponding columns are preferably at least three times the average column weight of the entire parity check matrix, and in some cases, a weight exceeding five or six times the average column weight can be considered. In addition, the optimized constraints on the weights of the columns corresponding to the punctured information bits can be set differently depending on the code rate. In addition, the columns with the highest weights or degrees in the basic matrix or parity check matrix are conveniently arranged at the front, but are not necessarily limited thereto, and may be arranged in the middle or back of the parity check matrix according to the requirements of the system.

[0651] In general, when parity bits corresponding to columns with weight or degree 1 in the base matrix or parity check matrix of an LDPC code are punctured, it does not have any effect on the decoding process, so in the decoding operation, decoding is performed by excluding the columns corresponding to the corresponding parity bits and the rows directly connected to the columns, which has the effect of reducing the decoding complexity. However, even if the punctured information bits are not actually transmitted from the transmitter to the receiver, the receiver regards the punctured information bits as erased bits and necessarily performs decoding, so the decoding complexity is not reduced.

[0652] When performing LDPC decoding in a system where information bits are punctured, there may be a problem with the decoding convergence speed depending on the decoding method. To explain this problem, the characteristics of the decoding process when some of the information bits or code blocks are punctured when performing LDPC encoding and decoding using a part of the basic matrix of Equation 20 are simply shown in Figures 12a and 12b. For reference, Equation 20 is the basic matrix It is a basic matrix obtained by selecting 6 rows from the top, and it is assumed that the information bits corresponding to the first two columns are not transmitted. The method of not transmitting the information bits corresponding to the above two columns can be performed through a rate matching method, or can be performed through puncturing of the LDPC encoding bits separately from the rate matching.

[0653] [Equation 20]

[0654]

[0655] Figures 12a and 12b are examples showing cases where one and two perforated bits are connected to one inspection node, respectively.

[0656] The above Fig. 12a is a diagram showing a Tanner graph corresponding to the first row in the basic matrix of the above mathematical expression 20. In the above Fig. 12a, 8 variable nodes and one check node (1210) are shown for convenience, but since the basic matrix of the above mathematical expression 20 represents a quasi-cyclic LDPC code with a block size of Z, the first row actually means that 8*Z variable nodes are connected to Z check nodes.

[0657] If two or more variable nodes, such as (1201) and (1202) in Fig. 12a, are connected to a single test node, the LLR values ​​corresponding to the variable nodes are set to 0, and these values ​​are transmitted to the test nodes (1210) along each line (1220) connected to the variable nodes. For an explanation of the decoding process in Figs. 12a and 12b, reference is made to 『Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 47, NO. Referring to the decoding algorithm presented in 『Proceedings of the Invention of the Invention on the Reliability of Variable Nodes』 (Proceedings of the Invention of the Invention on the Reliability of Variable Nodes, vol. 2, FEBRUARY 2001, pp498-519), when applying the decoding update formula based on the multiplication rule using the tanh(.) function to the check node, since tanh(0) = 0, there will inevitably be at least one case where tanh(0) = 0 in the update formula, and therefore the multiplication formula will always be 0, so no matter how the update process is performed for any variable node, the LLR value of the variable node (i.e., bit) will not be updated. In other words, if two or more punctured variable nodes (i.e., bits) are connected to one check node, the LLR values ​​for all variable nodes will not be updated by the update rule based on the multiplication rule. Although the multiplication rule and the update rule for the LLR value are described here for convenience, the reliability of the variable node will not be updated no matter what update rule and message value (i.e., the value obtained through demodulation to perform decoding, meaning the decoder input value) is applied.

[0658] The above Fig. 12b is a diagram showing a Tanner graph corresponding to the second row block in the basic matrix of mathematical expression 20. In the above Fig. 12b, 10 variable nodes and one check node (1240) are shown for convenience, but since the basic matrix of mathematical expression 20 represents a quasi-cyclic LDPC code with a block size of Z, this means that in reality, the second row has 10*Z variable nodes connected to Z check nodes.

[0659] If only one perforated variable node, such as (1231) in FIG. 12b, is connected to a single inspection node, the LLR value corresponding to the variable node is set to 0, and this value is transmitted to the inspection node (1240) along the line (1250). In other words, if the inspection node processor applies an update method based on the multiplication rule in the process of calculating the updated LLR values ​​corresponding to the remaining lines excluding the line (1250), the LLR values ​​corresponding to the variable nodes excluding (1231) connected to other lines excluding the line (1250) are not updated due to the LLR = 0 value corresponding to the line (1250). However, since the update of the LLR value corresponding to the variable node corresponding to the line (1250) is performed based on the values ​​corresponding to the lines excluding the line (1250), the LLR value corresponding to the variable node (1231) can be updated to a value other than 0, which was set due to the perforation. And once the LLR value corresponding to the variable node (1231) is updated to a non-zero value, a meaningful confidence value (e.g., LLR value) is set for all variable nodes, so that in the subsequent iterative decoding process, the LLR values ​​for all variable nodes (i.e., bits) can be updated.

[0660] If LDPC decoding is performed using a flooding scheduling method that simultaneously decodes all rows using the basic matrix of the above mathematical expression 20, there are no updates for rows except for the second and fourth rows in the first iterative decoding process, and only the reliabilities (e.g., LLR) corresponding to the bits corresponding to the first two columns of the basic matrix are updated by the updates for the second and fourth rows. That is, in the 0th iterative decoding process, the bits other than the bits corresponding to the first two columns are not updated at all, and since updates are performed for all bits from the 1st iterative decoding process, the minimum number of essential iterative decodings required for successful LDPC decoding is 1. (The first decoding performed based on the LLR value obtained through demodulation from the first received signal is considered the 0th iteration decoding.) The number of iteration decodings for successful decoding may vary depending on the channel conditions, but it means that at least 1 iteration decoding is always required regardless of the channel conditions.

[0661] Mathematical expression 21 is the fundamental matrix This is a simple representation of the basic matrix obtained by selecting 6 rows from the top, and it is assumed that the information bits corresponding to the first two columns are not transmitted. The method of not transmitting the information bits corresponding to the above two columns can be performed through a rate matching method, or can be performed through puncturing of the LDPC encoding bits separately from the rate matching.

[0662] [Equation 21]

[0663]

[0664] In the basic matrix of the above mathematical expression 21, all rows except the second row can be connected to variable nodes corresponding to two punctured bits in one inspection node, similar to FIG. 12a, and FIG. 12 is a drawing showing a Tanner graph for this.

[0665] If LDPC decoding is performed using a flooding scheduling method that simultaneously decodes all rows using the basic matrix of the above mathematical expression 21, there are no updates for rows other than the second row in the first iterative decoding process, and only the reliability (e.g., LLR) corresponding to the bits corresponding to the first column of the basic matrix is ​​updated by the update for the second row. That is, in the 0th iterative decoding process, the bits remaining except for the bits corresponding to the first column are not updated at all.

[0666] When the 0th decoding iteration is completed, the bits corresponding to the second column are still considered as missing. Therefore, in the 1st decoding iteration, all bits connected to the bits corresponding to the second column are still not updated. However, since the bits corresponding to all columns except the second column acquire meaningful reliability (e.g., LLR value) in the 0th decoding iteration, the bits corresponding to the second column acquire meaningful reliability values ​​through the 1st decoding iteration. That is, since meaningful reliability values ​​are set for all bits when the 1st decoding iteration is completed, updates for all bits are performed from the 2nd decoding iteration, so the essential number of decoding iterations required for successful LDPC decoding is at least 2. The number of decoding iterations required for successful decoding may vary depending on the channel conditions, but this means that at least 2 decoding iterations are always required regardless of the channel conditions.

[0667] State-of-the-art communication systems, including 5G systems, support a variety of service scenarios. Among these, services that transmit high-speed, high-capacity data require rapid data processing in the decoder. Specifically, 5G systems are designed with a peak data rate of 20 Gbps in mind, and next-generation communication systems, such as 6G systems, are considering supporting services with peak data rates several to tens of times higher.

[0668] As the number of iterative decoding required to achieve the error correction performance required by the system increases, the decoder's operating time also increases linearly, so the number of iterative decoding and the size of the decoder's information processing capacity are inversely proportional. Therefore, in an environment where high information processing capacity is required, a small number of iterative decoding is required to achieve a high data rate. In this way, the smaller the number of iterative decoding required to achieve the error correction performance required by the system or the decoder's operating time required accordingly, the faster the decoding convergence speed is expressed. On the other hand, the larger the number of iterative decoding or the decoder's operating time required accordingly, the slower the decoding convergence speed is expressed.

[0669] In existing 5G systems, some of the information bits are always punctured and not transmitted to obtain excellent encoding gain. Therefore, in receivers that apply decoding algorithms such as the flooding method, at least two or more iterative decodings are required. This may be disadvantageous in terms of decoding convergence speed depending on the system's communication environment. In other words, in situations where a sufficient number of iterative decodings can be applied, puncturing the information bits provides excellent encoding gain. However, in situations where fast data decoding is required (i.e., when the number of iterative decodings is limited), the encoding gain that can be obtained from puncturing the information bits may not be sufficient.

[0670] In this disclosure, a method is proposed that enables efficient operation of the system by variably performing information word perforation according to the situation required by the system.

[0671] In the existing encoding process, in order to apply the puncturing of the information bits, a portion of the information bits were always excluded in the process of defining the encoding bits as shown in [Table 9]. Meanwhile, the present disclosure proposes a method for variably performing the puncturing of the information bits, and when the puncturing of the information bits is not applied, a simply modified operation of the operation of [Table 9] can be performed as shown in the following [Table 12].

[0672] [Table 12]

[0673]

[0674] Referring to the above [Table 12], the input bits or code block bits and the encoding bits are When expressed as , the basic matrix 1 Or if you apply a base matrix of the same size , basic matrix 2 Or if you apply a base matrix of the same size am.

[0675] Depending on the settings of the system including the terminal or base station, if the puncturing of the information bit is to be applied, [Table 9] may be applied, and if the puncturing of the information bit is not to be applied, [Table 12] may be applied. In the present disclosure, the setting indicating to perform the puncturing of the information bit as in [Table 9] may be expressed as the first setting, and the setting indicating not to apply the puncturing of the information bit as in [Table 12] may be expressed as the second setting.

[0676] The above settings may be determined based on higher layer parameters (e.g., RRC parameters). For example, in a situation where a high coding gain is required through the above parameters or a specific service corresponding thereto is set (if the first setting is indicated), the operation of [Table 9] is performed, and in a situation where a high information throughput is required or a specific service corresponding thereto is set (if the second setting is indicated), the operation of [Table 12] is performed.

[0677] In addition, situations or services requiring high coding gain or situations or services requiring high information throughput may be indicated or set based on separate signaling or parameters, but may also be indicated or set based on other existing signaling information or parameters. For example, variable puncturing of information bits may be performed based on at least one of the configured CQI or MCS indices. The MCS index indicates the spectral efficiency of the system by indicating a combination of modulation order and code rate. Typically, when high spectral efficiency is set, it means that the channel condition is good, so there is a high possibility that high information throughput is required rather than coding gain. Therefore, puncturing of information bits may be variably applied based on the configured CQI or MCS index value. In addition, puncturing of information bits may be variably applied based on the range of values ​​of at least one of the modulation order or code rate determined from the CQI or MCS index. For example, it may be set whether the first setting or the second setting is to be applied depending on the CQI or MCS index value (e.g., in the form of a table), and the setting according to the indicated CQI or MCS index value may be applied.

[0678] The above examples are merely illustrative, and the criteria for variably applying information bit perforation can be applied in various ways. For example, information bit perforation may be variably applied based on the configured UE category, or depending on whether the transmission is downlink or uplink.

[0679] Alternatively, although the present disclosure exemplifies a case where the first setting or the second setting described above is set in the terminal, as another embodiment, basically, when the puncturing of the information bit is applied as in [Table 9], but a setting indicating not to apply the puncturing of the information bit is included, the puncturing of the information bit may not be applied based on the above setting. That is, the puncturing of the information bit may not be applied depending on whether or not the setting indicating not to apply the puncturing of the information bit is included.

[0680] [Table 9] and [Table 12] can also be expressed in an integrated form as shown in [Table 13].

[0681] [Table 13]

[0682]

[0683] In the above [Table 13] means the number of information bits to be punched, and the input bits or code block bits and the encoding bits are When expressed as , the basic matrix 1 Or if you apply a base matrix of the same size , basic matrix 2 Or if you apply a base matrix of the same size As a specific example, When bit information word perforation is applied , if information word perforation is not applied can be set to .

[0684] In general, the number of the above encoding bits silver The maximum number of encoding bits determined by, i.e., It can be defined as the difference between the total number of columns of the parity check matrix determined by and the number of punctured information bits. Also, the number of parity bits that can be generated when the parity check matrix is ​​determined is The maximum number of encoding bits determined by the parity check matrix is ​​equal to the difference between the total number of columns of the parity check matrix and the number of given input bits (= code block bits), so the parity bits are equal to the basic matrix 1. Or if you apply a base matrix of the same size , basic matrix 2 Or if you apply a base matrix of the same size or expressed as, can be expressed as follows. Therefore, the encoding bit corresponding to the parity bit can be expressed as follows:

[0685]

[0686] In the above examples, for convenience, a method of applying variable perforation to the same number of information word bits regardless of the basic matrix was proposed. is based on the basic matrix , can be defined as different values. Also, cast If you set it as a multiple of , ( : 1, 2, 3, … ) can be expressed in the form of the total number of columns of the given basic matrix (= total number of column blocks of the parity check matrix). When we say, generally Because there is a relationship, or It can be expressed in various forms, such as:

[0687] Also, in the examples in [Table 9] and [Table 12] above, or Although only the cases distinguished by have been explained, the perforation of variable information bits as described above can be applied in a more detailed manner. For example, or or ( ) can be variably applied to the perforation of information bits in three stages, and can also be subdivided into more stages. Also, depending on the system, There may not be any cases where this is the case, and in such cases ( ) may be expressed as follows. That is, in the embodiment of the present disclosure, the second setting does not apply the puncturing of the information bits, or some of the information bits (e.g., the number of information bits to be punctured) This may mean a setting that instructs to puncture bits (if less than or equal to 1 bit). In other words, when the second setting is indicated, it means that at least some of the information bits to be punctured in the encoding process or rate matching process when the first setting is indicated are not punctured in the encoding process or rate matching process. Alternatively, when the second setting is indicated, it may mean that the number of information bits to be punctured in the encoding process or rate matching process is less than or equal to the number of information bits to be punctured in the encoding process or rate matching process when the first setting is indicated. Alternatively, when the first setting is indicated, it may mean that input bits of the first length among the input bits are not included in the encoding bits, and when the second setting is indicated, it may mean that input bits of the second length among the input bits are not included in the encoding bits, and the second length is 0 or less than the first length.

[0688] That is, the characteristic that the number of information bits to be punctured is zero or smaller in a situation where a high information processing amount is required or a specific service corresponding thereto is set (second setting) is maintained compared to a situation where a high encoding gain is required or a specific service corresponding thereto is set (first setting).

[0689] Depending on the puncturing of the information bits, specific rate matching and / or retransmission processes can also be affected. Referring to Figure 13, in addition to applying appropriate shortening, puncturing, and repetition techniques during the LDPC encoding process, the starting position of the transmitted bits is determined based on the RV value. As a specific example, the rate matching process in a 5G system can be expressed as follows.

[0690] [Example of the rate matching process]

[0691] (1) Encoding bits corresponding to the rth code block The length is can be stored in a circular buffer. (The circular buffer may refer to an actual physical buffer, but may also refer to a logical buffer.)

[0692] (2) For the rth code block, if LBRM (limited buffer rate-matching) is not applied ( ) in , when LBRM (limited buffer rate-matching) is applied ( ) in is set to . Here, and, , refers to the TBS calculated based on limited parameters when applying LBRM.

[0693] (3) RV number for current transmission or retransmission rv id (rv id= 0, 1, 2 or 3), the output bits after rate matching is determined based on the following process:

[0694]

[0695] Here is rv id , a value indicating the position of the bit at which transmission begins, determined according to the basic matrix and Table 14 below.

[0696] [Table 14]

[0697]

[0698] Table 14 above As the values ​​determined by considering this, it can be seen that in the case of basic matrix 1, the denominator of the calculation formula is 66 (= 68 - 2), and in the case of basic matrix 2, the denominator of the calculation formula is 50 (= 52 - 2). That is, in the current 5G system, rate matching is based on a value smaller than the number of columns of the actual basic matrix, 68 and 52, because the information word bits themselves that are punched into the circular buffer are not input. The value can be determined.

[0699] However, if the information word puncturing is not applied, all information word bits must be input into the circular buffer, so the above calculation value also changes. First, in the case of basic matrix 1, the value of the denominator in the calculation formula can be changed to 68, and in the case of basic matrix 2, the value of the denominator in the calculation formula can be changed to 52. In other words, the position of the bit where transmission starts can be determined based on the RV value and the total number of columns of the basic matrix.

[0700] As a specific example, in cases where information word perforation is not applied The method of determining the value is shown in Table 15.

[0701] [Table 15]

[0702]

[0703] If the RV value is 1, 2, 3 The value is calculated based on the total number of columns in the base matrix. Also, for at least RV values ​​2 and 3, the same base matrix, , When this is applied, if information word perforation is applied In case information word perforation is not applied to the value A larger value is desirable. For certain parameters, the two values ​​may be the same, but in general, when no perforation is applied, The value cannot be smaller, and there must be a larger case.

[0704] If the information word perforation is applied to only one column of the base matrix, i.e., Likewise, in the case of the calculation formula in Table 15, the denominator must be the total number of columns of the basic matrix minus 1, and for at least RV values ​​2 and 3, the same basic matrix, , When this applies It is desirable that the value satisfies the feature that is equal to or greater than when applying Table 14, and equal to or less than when applying Table 15.

[0705] or The value of can be determined based on a higher layer parameter (e.g., an RRC parameter). For example, in a situation where a high encoding gain is required through the parameter or a specific service corresponding thereto is set (if the first setting is indicated), the number of first puncture bits ( ) is set to a value of , and in situations where high information processing is required or when a specific service corresponding to it is set (when the second setting is indicated), Or, it may be set to a value smaller than the number of first punch bits corresponding to the first setting (the number of second punch bits).

[0706] However, the embodiments of the present disclosure are not limited thereto. or The value of may not be set separately and may be predetermined for the first setting or the second setting. Accordingly, when the terminal receives the first setting or the second setting, it may determine the number of information bits to be punctured corresponding thereto (also, it may be expressed that it is determined not to puncture when the number of bits to be punctured is 0).

[0707] In addition, situations or services requiring high coding gain or situations or services requiring high information throughput may be indicated or set based on separate signaling or parameters, but may also be indicated or set based on other existing signaling information or parameters. For example, puncturing of information bits may be variably applied based on at least one of the set CQI or MCS indices. In addition, puncturing of information bits may be variably applied according to the range of values ​​of at least one of the modulation order or code rate determined from the CQI or MCS index. For example, whether the first setting or the second setting is to be applied may be set (e.g., in the form of a table) depending on the CQI or MCS index value. Or, the number of information bits to be punctured may be set (e.g., in the form of a table) depending on the CQI or MCS index value, and the setting may be applied or puncturing of information bits may be performed depending on the indicated CQI or MCS index value.

[0708] In addition, the puncturing of the information bits may be applied variably depending on the CQI or MCS table being set. In other words, among the multiple CQI or MCS tables, some CQI or MCS tables correspond to a method of applying puncturing of the information bits, and other some CQI or MCS tables correspond to a method of not applying puncturing of the information bits or of puncturing a smaller number of information bits. Accordingly, the base station or terminal can determine whether to apply puncturing of the information bits based on the CQI or MCS table being set. As a specific example, when the first CQI or the first MCS table is set in the base station or terminal, it is determined that puncturing is applied to a part of the information bits, and the encoding process of [Table 9] is performed or in [Table 13] The encoding process can be performed. If the second CQI or the second MCS table is set, the encoding process is performed without applying the puncturing of the information word bits as in [Table 12] or as in [Table 13]. Alternatively, encoding may be performed by applying perforation to a number of information bits smaller than the number of information bits to be perforated when the first CQI or first MCS table is set.

[0709] The above examples are merely examples, and the criteria for variably applying the perforation of information bits can be applied in various ways. For example, when a specific CQI or MCS table is set, the perforation of information bits may be variably applied according to the CQI or MCS index, the perforation of information bits may be variably applied based on the set UE category, and the perforation of information bits may be variably applied depending on whether it is downlink or uplink.

[0710] In the case where the puncturing of the information bits is variably applied as in the examples above, the receiver may apply a flooding decoding method or a layered decoding method. The performance of the layered decoding method may vary depending on the order of the layers or row blocks in which decoding is performed. For example, assuming that layered decoding is performed based on a parity check matrix corresponding to the basic matrix of Equation 21, and each of the six row blocks is divided into six layers, layered decoding can be performed in the order of [0, 1, 2, 3, 4, 5] from the 0th row block (= layer) to the 5th row block. In this case, the numbers included in the above order may correspond to the indices of the row blocks of the parity check matrix or the row indices of the basic matrix, and the same applies below. However, if the information bits corresponding to the first two column blocks are punctured, the decoding update is not performed even if layered decoding is performed first on the 0th, 2nd, 3rd, 4th, and 5th row blocks. Therefore, when information word perforation is applied, it is desirable to first perform layered decoding on the first row block. As a specific example, when layered decoding is performed in an order such as [1, 4, 5, 0, 2, 3], a faster decoding convergence effect can be obtained compared to performing layered decoding in an order such as [0, 1, 2, 3, 4, 5]. Therefore, better decoding performance can be obtained when a smaller number of iterative decodings are applied.

[0711] On the other hand, if no perforation is applied to the information word bit, there is no case where decoding updates do not proceed regardless of which row block or which layer is selected to perform layered decoding, so performing decoding on a row block other than the first row block can support better performance and decoding convergence speed.

[0712] Layered decoding scheduling, which refers to the order of row blocks or layers that perform decoding, can be applied differently depending on whether or not puncturing of information bits is applied or the size of the punctured information bits.

[0713] The present invention proposes a method for determining the order of layers (or row blocks, if a layer consists of a single row block) to perform decoding to optimize the performance of layered decoding, as well as specific embodiments thereof. To this end, we examine various factors that should be considered when determining the order of layers to perform decoding, and propose a specific method for combining these factors to establish an appropriate decoding schedule. Furthermore, for convenience of explanation, the present invention presents specific embodiments only for the case of using a quasi-cyclic LDPC code, but it should be noted that the present invention can be easily extended to general LDPC codes.

[0714] <Conditions for determining layered decoding scheduling>

[0715] When applying higher-order modulation schemes such as 16-QAM, 64-QAM, 256-QAM, 1024-QAM, etc., each bit that constitutes the modulation symbol has a different reliability. For example, in each modulation symbol, the MSBs (most significant bits) typically have a low bit error rate, i.e., high reliability, and the LSBs (least significant bits) typically have a high bit error rate, i.e., low reliability. Therefore, there may be a large difference in LDPC decoding performance depending on how the LDPC codeword bits to be transmitted are mapped to the modulation symbols. If the mapping rules to the modulation symbols are determined in advance, the order of the layers that are initially decoded may vary in order to maximize performance depending on the modulation scheme (or order) and the mapping rules.

[0716] Condition 1) When a portion of the information word bit (or code block) is transmitted with a puncture, the initial decoding is prioritized for the row block corresponding to the row with a degree or weight of 0 or 1 within the submatrix consisting only of the columns or column blocks corresponding to the punctured information word bits in the basic matrix. If there is no information word puncture, Condition 1) is ignored.

[0717] Condition 2) Prioritize decoding for row blocks that maximize theoretical decoding performance by considering the degree or weight distribution or modulation order or methods. In many cases, in the initial decoding process, the lower the check node degree, i.e., the lower the row weight, the greater the improvement in decoding performance. In addition, since the reliability or bit error rate of each bit that constitutes the modulation symbol differs depending on the modulation method, the optimized scheduling method may differ depending on the modulation method. The theoretical performance can be applied to various methods, such as density evolution analysis or EXIT chart (extrinsic information transfer chart) analysis.

[0718] Condition 3) Prioritize the row blocks to be decoded by considering the portion of the base matrix or parity check matrix of the LDPC code that is actually used in decoding or that affects performance, depending on the code rate or rate matching. That is, the order of layers to be decoded may change depending on the code rate or rate matching.

[0719] Condition 4) Prioritize the row blocks to be decoded based on the portion of the base matrix or parity check matrix of the LDPC code that is actually used or affects performance, depending on the TBS or CBS. That is, the order of layers to be decoded may change depending on the TBS size.

[0720] The above condition 1) is a condition for fast decoding convergence, considering the limited number of iterative decodings depending on whether or not the information word is punctured. In the case of LDPC codes, not only is the puncturing of the parity portion variable, but if the parity of degree 1 is punctured, the corresponding parity check matrix portion can be excluded from the decoding process and decoding can be performed.

[0721] When applying higher-order modulation schemes such as 16-QAM, 64-QAM, 256-QAM, 1024-QAM, etc., each bit that constitutes the modulation symbol has a different reliability. For example, in each modulation symbol, the MSBs (most significant bits) typically have a low bit error rate, i.e., high reliability, and the LSBs (least significant bits) typically have a high bit error rate, i.e., low reliability. Therefore, there may be a large difference in LDPC decoding performance depending on how the LDPC codeword bits to be transmitted are mapped to the modulation symbols. If the mapping rules to the modulation symbols are determined in advance, the order of the layers that are initially decoded may vary in order to maximize performance depending on the modulation scheme (or order) and the mapping rules.

[0722] In a communication system that applies appropriate rate matching to support variable code rates, the submatrix of the parity check matrix corresponding to the rate matching may substantially affect performance, so the above condition 3) may be considered to reflect this characteristic. For example, in an LDPC encoding / decoding system that uses a parity check matrix corresponding to the basic matrix of the above mathematical expression 21, if a high code rate close to 1 is supported, some parity bits corresponding to the last one or two column blocks in the core part of the parity check matrix may be punctured due to rate matching. In this case, it is obvious that initial decoding should be performed on the first row block to minimize invalid decoding processes.

[0723] On the other hand, when the code rate is relatively low, the best encoding / decoding performance can be supported by preferentially applying initial decoding to row blocks other than the 1st row block. For example, the 6th row block, the 10th row block, etc. of the parity check matrix corresponding to M(BG1) correspond to row blocks whose degree or weight is 0 or 1 within the submatrix composed only of columns or column blocks corresponding to the punctured information word bits. Therefore, when applying LDPC encoding based on M(BG1), when the code rate is lower than 22 / (22 + 6 - 2) or 22 / (22 + 7 - 2), performing decoding first on row blocks other than the 1st row block can support good encoding / decoding performance. Likewise, when applying LDPC encoding based on M(BG2), if the code rate is equal to or greater than 10 / (10 + 6 - 2), it is desirable to first perform decoding on one of the 1st or 4th row blocks in the parity check matrix. However, if the code rate is lower than 10 / (10 + 6 - 2) or 10 / (10 + 7 - 2), first performing decoding on a row block other than the 1st or 4th row block may support good encoding / decoding performance. When performing LDPC encoding based on M(BG2), the number of columns used among the 10 columns corresponding to the information word bits varies depending on the size of the TBS, so the standard for the code rate may vary, and for convenience, it may be distinguished by the number of rows of the basic matrix used or the number of row blocks of the parity check matrix.For example, if the number of rows actually used for decoding in M(BG2) is 6 or 7 or less, it is preferable to first perform decoding on one of the 1st or 4th row blocks, and if the number of rows actually used for decoding is 6 or 7 or more, it may be preferable to first perform decoding on a row block other than the 1st or 4th row block. Similarly, when applying LDPC encoding / decoding using M(BG1), the number of rows of the basic matrix or the number of row blocks of the parity check matrix may be determined based on 6 or 7. If the code rate supported by the system is not variable, the order of optimal decoding scheduling may be determined as one.

[0724] Since the size and range of the sub-matrix that affects the performance in the parity check matrix vary depending on whether puncturing is applied and / or the code rate, applying a single fixed layered decoding scheduling method may be easy to implement but may result in some performance loss. Therefore, if implementation is possible, applying a variable decoding scheduling based on whether puncturing is applied, the maximum or minimum code rate that can be supported or the code rate actually supported, the modulation order, etc. will improve the encoding / decoding performance.

[0725] For reference, the code rate used in the above condition 3) may be an effective code rate that divides the number of information word bits or the code block size by the number of transmitted bits. Alternatively, a code rate defined from system information related to MCS or CQI (channel quality indicator) (e.g., MCS index or CQI index) may be used. Using an effective code rate has the advantage of defining a scheduling order or pattern that enables more accurate performance prediction, but an additional process for calculating the effective code rate may be required. When using a code rate defined in MCS or CQI, additional calculations may not be required, but performance degradation may occur because it may be different from the code rate optimized for the predetermined scheduling order or pattern.

[0726] The above condition 4) can be applied when a part of the basic matrix or parity check matrix of the LDPC code that is actually used for decoding or affects the performance is different depending on the TBS or CBS. In fact, according to the 3GPP 5G standard specification TS 38.212 document, when mapping a code block (or information word bit) to a submatrix corresponding to the information word in the parity check matrix, the range is set differently depending on the CBS. For example, when encoding is performed based on the second basic matrix BG2 defined in TS 38.212 (in TS 38.212, the basic matrix is ​​expressed as a basic graph), if the CBS or TBS length is greater than 640, K b = 10 heat blocks, K if less than 640 and greater than 560 b = 9 column blocks, K if less than 560 but more than 192 b = 8 column blocks, K if less than 192 b = Select 6 heat blocks, then the above K bEncoding is performed based on the K column blocks. Therefore, in the submatrix of the parity check matrix corresponding to the information word bits or code blocks, b Except for the 10-column block, the remaining 10-column blocks may not be used during the encoding process. This omission of a portion of the given parity check matrix during the encoding process is a shortening operation, which means that the degree distribution, which affects actual performance, changes. Therefore, as mentioned in condition 2) above, this can have a significant impact on the theoretical performance of the LDPC code. Therefore, the optimal scheduling order or pattern may vary depending on the TBS or CBS length.

[0727] The optimal layered decoding order or pattern may differ depending on the number of row blocks actually utilized for decoding in the parity check matrix. However, when the code rate is low, the performance difference decreases, and when the code rate is high, the performance difference is relatively large. Therefore, by optimizing the layered decoding order or pattern for a high code rate using a greedy algorithm and then optimizing the order or pattern for a low code rate based on the result, a semi-optimized order or pattern can be derived as a simple sequence. In the present invention, as a method for maximizing performance even if the complexity increases somewhat, the length of the rate-matched bit string, i.e., the total transmitted codeword length We propose a NSA (Nested-Sequence Approach) layered decoding method that stores a layered decoding order or pattern based on RV values ​​using a sequence having a nested structure (or a superposition structure) and then performs decoding.

[0728] The receiving unit of the terminal or base station determines the TBS or CBS value and the basic matrix or After performing the desegmentation process, including the process of determining which basic matrix was used, the process of determining the block size (Z), etc., the number of codeword bits transmitted after rate matching for the r-th code block is determined by considering the determined values, allocated resources, modulation method, etc. can be determined. However, in the 3GPP 5G communication system, when transmission is required for cases where the number of ACK or NACK bits, which are acknowledgement signals, is 1 or 2, an effect such as some of the CSI-part2 (channel state information part2) and / or UL-SCH (Uplink Shared Channel) data bits being punctured may occur. Some of the bits may not actually be transmitted. However, the receiver may consider the corresponding transmitted codeword bits to have been transmitted, but may treat the codeword bits in those positions as punctured bits by setting LLR = 0.

[0729] In other words, the number of transmitted code bits The value may refer to the number of bits physically transmitted by the transmitter, but in some cases it may refer to the number of codeword bits that the receiver can determine to have been transmitted.

[0730] The number of row blocks of the parity check matrix that are valid (or actually affect performance) during the encoding / decoding process, or the number of rows of the base matrix. is the number of bits of the above code word can be determined based on, for example, the number of row blocks of a parity check matrix or the number of rows of a base matrix. It can be determined based on mathematical expression 22.

[0731] [Equation 22]

[0732]

[0733] Here is the number of column blocks actually used and corresponding to the information word bits in the parity check matrix for LDPC encoding of the code block given in the basic matrix, means the number of column blocks corresponding to the bits to which the perforation is applied among the information word bits or code blocks.

[0734] As a concrete example, referring to 3GPP standard specification document TS 38.212, TBS = 5632 bits (including 16 bits of CRC), code rate according to MCS index is greater than 2 / 3, = 7632. Under these conditions, as the basic matrix for LDPC encoding, This is determined, and the block size is also determined as Z = 5632 / 22 = 256. In the case of the above 3GPP standard specification TS 38.212, is fixed as, When this is used is always 22, so This means that a total of 10 row blocks in the parity check matrix actually affect the LDPC encoding / decoding performance.

[0735] If retransmission is performed, it is done by RV values. This may be determined differently. For example, if the initial transmission was based on RV0 and the retransmission was based on RV2 or RV3, some of the bits between RV1 and RV2 or between RV1 and RV3 may not have actually been transmitted. If the parity bits corresponding to the second part of the parity check matrix are not transmitted, the rows corresponding to the parity bits do not have any effect on the LDPC decoding process, so the receiver may perform LDPC decoding by excluding the rows. However, for the convenience of implementation, the parity bit corresponding to the last column and row among the transmitted parity bits is used as the standard. can be determined. That is, the total number of columns from the 0th column of the parity check matrix to the last column of the actually transmitted parity bits. It can also be determined as follows. The value required to obtain the number of row blocks required for LDPC decoding, as in Equation 22. may be determined differently depending on the RV value applied during transmission.

[0736] does not exceed the total number of columns of the parity check matrix of the LDPC code. For example, Or, if a base matrix of the same size or a corresponding parity check matrix is ​​applied. The value is Does not exceed, Or, if a base matrix of the same size or a corresponding parity check matrix is ​​applied. The value is Does not exceed . The values ​​are each at or at In this case, it means that LDPC decoding is performed using all rows of the basic matrix or all row blocks of the parity check matrix from Equation 22.

[0737] By appropriately utilizing the greedy algorithm while considering all of Conditions 1), 2), 3), and 4) of <Conditions for Determining Layered Decoding Scheduling>, it is possible to determine the decoding order or pattern of a nested structure that exhibits stable performance by considering whether to apply perforation or at least some of the modulation order or TBS or code rate.

[0738] As a concrete example, for the case where perforation is applied, the basic matrix 1 We define the following sequence as a layered decoding order or pattern based on:

[0739] Pattern-1:

[0740] [42, 40, 26, 34, 37, 45, 30, 32, 22, 28, 38, 44, 41, 20, 27, 25, 31, 36, 39, 13, 33, 35, 24, 29, 43, 17, 23, 18, 21, 14, 6, 10, 16, 1, 4, 19, 7, 12, 15, 9, 5, 11, 8, 0, 2, 3]

[0741] Similarly, the basic matrix 2 We define the following sequence as a layered decoding order or pattern based on:

[0742] Pattern-2:

[0743] [22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15, 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3]

[0744] However, the decoding order or pattern of the nested structure of the present invention is not limited to the above order or pattern. That is, it is obvious that the embodiments of the present invention can be applied to the decoding order or pattern of the nested structure generated using the greedy algorithm.

[0745] Additionally, the numbers included in the above sequence or pattern may correspond to indices of row blocks of a parity check matrix or row indices of a base matrix.

[0746] Below, the usage method of the above pattern-1 and pattern-2 is specifically described.

[0747] The receiver first receives the given fundamental matrix or and the number of row blocks that are actually used or affect performance in the corresponding parity check matrix. . And, the receiver determines the sequence of pattern-1 or pattern-2. A sequence with smaller values ​​is selected and applied as a layered decoding sequence or pattern for the actual decoding. This method is conveniently called the NSA layered decoding method.

[0748] As a concrete example, basic matrix 2 For the case of performing LDPC decoding based on , the input bits (TB+CRC) are 3840 bits (including 16 bits of CRC), and the code rate according to the MCS index is less than 2 / 3, Let's assume that. In the case of 3GPP standard specification TS 38.212, under these conditions, as the basic matrix for LDPC encoding, is determined, and the block size is determined as Z = 384. is fixed. Also, when the number of input bits is 3840, K b = 10, so This is. That is, a total of 21 row blocks in the parity check matrix actually affect the LDPC encoding / decoding performance. At this time, the receiver Select a sequence consisting only of numbers less than 21. That is, the receiver can determine a sequence (or pattern) consisting only of indices of valid row blocks in the pattern-2 sequence.

[0749] The indices of valid row blocks in the above pattern-2 sequence are as shown below.

[0750] [22, 37, 40, 31, 24, 29,20,12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39,17,16, 36, 21, 33,18,15,9,14, 30,11,19,6,7,8, 26,10,13,1,4,5,0,2,3]

[0751] Therefore, the order or pattern determined based on the index of the valid row block in the above pattern-2 sequence is as follows.

[0752] [20, 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3]

[0753] The above-mentioned selected sequence [20, 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3] represents a layered decoding pattern to be applied in an LDPC decoder, which means that one cycle of iterative decoding is performed by sequentially performing layered decoding starting from the 20th row block up to the 3rd row block.

[0754] The NSA layered decryption method can be modified in various forms, not just the above-mentioned embodiment. For example, If the value is not a multiple of Z, the last Since some of the parity bits corresponding to the th row block correspond to the value LLR = 0, the receiver uses the NSA layered decoding method. Select a sequence consisting of only smaller numbers and perform the layered decryption, The second row block can also perform layered decoding based on a predefined order. For example, If we assume that the layered decoding is always applied to the i(>0)th row block, In a sequence or pattern consisting of only smaller numbers, between the (i-1)th number and the ith number Values ​​can be applied.

[0755] As a concrete example, the last Assume that the system promises that the th row block is always applied to the 1st after the 0th layered decoding. As in the above-described embodiment, TBS = 3840 bits (including 16 bits of CRC), and the code rate according to the MCS index is less than 2 / 3. In this case, rather than applying [20, 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3] as a layered decoding order or pattern, In order to apply row block 20, which is the th row block, to the 1st, the position of 20 may be changed, such as [12,20, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3]. As another example, if the last Assume that the system promises that the second row block will be applied to the second. As in the above-described embodiment, TBS = 3840 bits (including 16 bits of CRC), and the code rate according to the MCS index is less than 2 / 3. In this case, rather than applying [20, 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3] as a layered decoding order or pattern, In order to apply row block 20, which is the th row block, to the 2nd, the position of 20 may be swapped with 17, which is the 2nd, as in [17, 12,20, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3]. Or, 20 may be positioned in the 2nd, and the order of 12 and 17 may be moved forward by one, as in [12, 17,20, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3].

[0756] The method described above is only an example, and there may be NSA layered decoding methods that are appropriately combined with other techniques based on a sequence of various nested structures.

[0757] If implementation complexity is not a major issue, the receiver can apply a layered decoding scheme using multiple optimized sequences or patterns based on the base matrix or code rate or modulation order of each LDPC code.

[0758] For example, the basic matrix 2 For systems that use the LDPC fundamental matrix corresponding to and employ some of the modulation schemes such as QPSK, 16QAM, 64QAM, 256QAM, and 1024QAM, LDPC decoding can be performed by applying the following sub-optimal layered decoding order or pattern (or sequence) according to each modulation scheme:

[0759] Pattern-2-1-4Q: Sequence or pattern for QPSK or 4QAM

[0760] [37, 40, 29, 27, 25, 22, 31, 28, 36, 33, 32, 34, 24, 41, 38, 21, 20, 35, 18, 12, 23, 39, 17, 30, 16, 15, 9, 14, 7, 11, 19, 6, 8, 26, 13, 10, 1, 4, 5, 0, 2, 3]

[0761] Pattern-2-1-16Q: Sequence or pattern for 16-QAM

[0762] [37, 40, 29, 27, 25, 22, 31, 34, 28, 33, 36, 24, 21, 32, 39, 20, 41, 38, 35, 18, 12, 23, 17, 16, 30, 15, 9, 14, 6, 11, 7, 19, 10, 8, 26, 1, 4, 5, 13, 0, 2, 3]

[0763] Pattern-2-1-64Q: Sequence or pattern for 64-QAM

[0764] [37, 40, 33, 29, 25, 27, 32, 23, 22, 36, 31, 28, 24, 26, 34, 20, 18, 21, 39, 12, 41, 38, 35, 17, 30, 16, 14, 11, 15, 6, 7, 9, 19, 10, 8, 13, 1, 4, 5, 0, 2, 3]

[0765] Pattern-2-1-256Q: Sequence or pattern for 256-QAM

[0766] [40, 37, 33, 32, 30, 29, 28, 41, 27, 26, 25, 39, 23, 22, 24, 38, 36, 21, 20, 18, 12, 35, 31, 17, 15, 9, 14, 34, 16, 6, 11, 7, 19, 10, 8, 1, 4, 5, 13, 0, 2, 3]

[0767] Pattern-2-1-1024Q: Sequence or pattern for 1024-QAM

[0768] [41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 18, 15, 12, 17, 11, 9, 16, 14, 6, 7, 1, 19, 10, 13, 4, 8, 5, 0, 2, 3]

[0769] A transmitter can transmit data bits according to each modulation scheme or order. Furthermore, a receiver can appropriately demodulate a received signal according to each modulation scheme or order, determine an LLR value for each received data bit, and then perform layered decoding based on the LLR value and the patterns.

[0770] Meanwhile, for the convenience of explanation, the above pattern or pattern-2-1-4Q to pattern-2-1-1024Q is described as being defined for each specific modulation method, but the embodiments of the present invention are not limited thereto. That is, it is obvious that the above pattern or order pattern-2-1-4Q to pattern-2-1-1024Q can be applied to each modulation method or order depending on the settings of the transmitter or receiver. For example, this means that the above pattern-2-1-4Q can be applied not only to the modulation method QPSK, but also to 16QAM, 64QAM, 256QAM, and 1024QAM.

[0771] Meanwhile, as described above, the embodiment of the present invention can also be applied to a case where decoding is performed based on a layer composed of two or more row blocks. If a row block adjacent to a row block determined to apply layered decoding has a characteristic of being orthogonal or quasi-orthogonal to the row block, decoding can be performed based on a layer including the row blocks. In addition, it is self-evident that layered decoding can be performed by forming a layer with row blocks having orthogonality or quasi-orthogonality when performing sequential decoding or reverse decoding thereafter. When at least one layer is composed of two or more row blocks, the layered decoding order or patterns can be defined as a sequence shorter than the total number of row blocks, and additional information may be required regarding which row blocks are combined for a layer in which the plurality of row blocks are combined.

[0772] Meanwhile, the layered decoding described above may be implemented in various ways, such as block parallel decoding, row-block parallel decoding (or row-parallel decoding).

[0773] Here, block parallel decoding is a layered decoding method that is typically performed based on one or more blocks in a parity check matrix, i.e., a cyclic permutation matrix of size Z*Z. In addition, row block parallel decoding (or row parallel decoding) is a layered decoding method that is typically performed based on one row block.

[0774] Row-block parallel decoding can be viewed as an extension of block-parallel decoding in a broad sense, as it performs decoding on all blocks (cyclic permutation matrices) contained in a given row block or a layer composed of multiple row blocks. While implementation complexity may increase compared to block-parallel decoding based on a single block (cyclic permutation matrix), it can support higher decoding throughput.

[0775] Block parallel decoding can be performed based on a single block (a cyclic permutation matrix), but more commonly, it can be performed based on multiple blocks. Furthermore, it can also be performed based on criteria smaller than a single block, in which case block parallel decoding is typically performed based on a divisor of the block size Z. When implementing layered decoding based on multiple blocks in block parallel decoding, implementation complexity increases, but so does the amount of decoded information processed.

[0776] The operation of the receiver according to the embodiment of the present invention is summarized as follows. That is, the receiver can receive a signal corresponding to input bits transmitted from a transmitter, and check the number of input bits based on the signal. In addition, the receiver can check the size of a code block based on the number of input bits, and perform layered decoding based on a parity check matrix corresponding to the size of the code block. In this case, the layered decoding can be decoded with priority for a layer corresponding to at least one of the row blocks having an order of 1 within a submatrix corresponding to a column block to be punctured. In addition, the layered decoding can be performed in combination with various embodiments of the present invention described above.

[0777] In addition, the receiver can receive a signal corresponding to the input bits transmitted from the transmitter, and check the number of input bits based on the signal. In addition, the receiver can check the size of a code block based on the number of input bits, and perform layered decoding based on a parity check matrix corresponding to the size of the code block. The layered decoding can be performed based on a decoding order or pattern, such as Pattern-1 or Pattern-2. In addition, if different decoding scheduling is applied according to the modulation method, a process of judging or determining the modulation method or modulation order applied to the encoding may be included, and the receiver can perform layered decoding based on a pattern (or sequence) corresponding to the decoding scheduling among Pattern-2-1-4Q to Pattern-2-1-1024Q according to the modulation method or modulation order.

[0778] The above modulation order may be determined based on the MCS index. Furthermore, the code rate may be determined based on the MCS index. Alternatively, the code rate may be determined based on an effective code rate value, which may be determined based on the number of bits actually transmitted, Er, through the allocated resources.

[0779] Additionally, the receiver can determine a base matrix based on the number of input bits and the code rate, and determine a parity check matrix based on the determined base matrix and the lifting size.

[0780] The above embodiments have been described assuming that some of the information bits (or code blocks) are always punctured. However, in some cases, the information bit puncturing may not be applied in the system. In such cases, the proposed layered decoding scheduling order or pattern may not be optimal. Therefore, when information bit puncturing is not applied, a layered decoding order or pattern different from that when information bit puncturing is applied may be applied.

[0781] For example, if perforation is not applied, the LLR value is updated regardless of which layer is decoded first, so reverse-order layered decoding is performed (considering condition 2 of <Conditions for determining layered decoding scheduling>), and if perforation is applied, various methods suggested in the above embodiments can be applied.

[0782] In conclusion, the first pattern or the second pattern can be applied depending on whether or not part of the information word bits or code blocks are perforated. Specifically, if at least part of the information word bits or code blocks are perforated, the first pattern is applied, and if not perforated, layered decoding is applied based on the second pattern different from the first pattern, so that performance can be improved.

[0783] Meanwhile, the present invention may be used by determining an order or pattern for determining a layered decoding order based on the basic matrix (or parity check matrix) of an LDPC code, a code rate (or the number of row blocks used), a modulation order, whether or not information bits are punctured, or the number of punctured information bits, but the order or pattern may also be determined based on two or more conditions. In addition, the embodiments of the present invention may be applied independently or in combination with each other. In addition, when different decoding orders or patterns are applied based on at least some of each basic matrix, modulation order, code rate (or the number of row blocks used), whether or not information bits are punctured, or the number of punctured information bits, performance may be optimized, but complexity may increase, and therefore, in some cases, the same pattern may be applied.

[0784] For example, in the layered decoding pattern for the above modulation order, one of the patterns or sequences set for each modulation order may be set to be used for cases where the modulation order is lower or higher than a predetermined modulation order. Furthermore, the method of the present invention may be implemented by combining some or all of the contents included in each embodiment, as long as it does not harm the essence of the invention.

[0785] While the present invention has been described in terms of preferred embodiments, various modifications and variations may occur to those skilled in the art. Such modifications and variations are intended to be encompassed by the appended claims. Furthermore, it should be understood that operations represented as separate blocks in the flowchart of the present invention for convenience of explanation may be implemented separately across multiple processors in an actual system, but may also be implemented integrated into a single processor.

[0786] Meanwhile, the electronic devices according to various embodiments disclosed in this document may be devices of various forms. The electronic devices may include, for example, at least one of a portable communication device (e.g., a smartphone), a TV, a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. The electronic devices according to embodiments of this document are not limited to the aforementioned devices. Furthermore, the act of transmitting a frame does not only mean that it is transmitted via a wireless channel or the like, but may also mean that various electronic devices include an interface for outputting the frame for transmission. For example, a processor may output a frame to an RF front-end for transmission via a bus interface. Similarly, the act of receiving a frame from another device may mean that various electronic devices have an interface for obtaining a frame received from another device. For example, a processor may receive or obtain a frame from an RF front-end via a bus interface.

[0787] It should be understood that the various embodiments and terminology used in this document are not intended to limit the technology described in this document to a specific embodiment, but rather to encompass various modifications, equivalents, and / or alternatives of the embodiments.

[0788] In connection with the description of the drawings, similar reference numerals may be used for similar components. The singular expression may include the plural expression unless the context clearly indicates otherwise. In this document, expressions such as "A or B", "at least one of A and / or B", "A, B, or C", or "at least one of A, B, and / or C" may include all possible combinations of the items listed together. Expressions such as "first", "second", "first", or "second" may modify the corresponding components without regard to order or importance, and are only used to distinguish one component from another component and do not limit the corresponding components. When one (e.g., a first) component is said to be "(functionally or communicatively) connected" or "connected" to another (e.g., a second) component, the one component may be directly connected to the other component, or may be connected via another component (e.g., a third component).

[0789] Also, the word "determining" can have many different meanings, such as identifying, calculating or computing, processing, deriving, investigating, estimating, looking up (e.g., from a database or other data structure), and ascertaining, depending on the context.

[0790] Meanwhile, the order of description in the drawings explaining the method of the present disclosure does not necessarily correspond to the order of execution, and the order of precedence may be changed or executed in parallel.

[0791] Alternatively, the drawings illustrating the method of the present disclosure may omit some components and include only some components without detracting from the essence of the present disclosure.

[0792] In addition, the method of the present disclosure may be implemented by combining some or all of the contents included in each embodiment within a scope that does not harm the essence of the invention.

[0793] While the present disclosure has been described with preferred embodiments in mind, various modifications and variations may occur to those skilled in the art. Such modifications and variations are intended to be encompassed by the appended claims. Furthermore, it should be understood that operations represented by different blocks in the flowchart of the present disclosure for convenience of explanation may be implemented separately across multiple processors in an actual system, but may also be implemented integrated into a single processor.

Claims

1. In a method performed by a receiver in a communication system, A step of receiving a signal corresponding to at least a part of the coding bits; A step of determining the number of input bits based on the above signal; A step of determining a basic matrix based on the number of input bits; A step of determining a lifting size (Z) based on at least one of the input bit number or the basic matrix; A step of determining a parity check matrix based on at least one of the basic matrix or the lifting size (Z); A step of performing decryption of the signal based on the parity check matrix, For the first setting, an input bit of the first length among the input bits is not included in the coded bit, and for the second setting, an input bit of the second length among the input bits is not included in the coded bit, The second length is characterized in that it is 0 or less than the first length, A method characterized in that the layered decoding order related to the first setting and the layered decoding order related to the second setting are different from each other.

2. In paragraph 1, A method characterized in that the first setting or the second setting is determined based on upper layer parameters.

3. In paragraph 1, A method characterized in that the first setting or the second setting is determined based on at least one of a CQI (channel quality information) or an MCS (modulation and coding scheme) index.

4. In paragraph 1, A method characterized in that the first setting or the second setting is determined based on at least one of a modulation order or a code rate.

5. In paragraph 1, A method characterized in that the first setting or the second setting is determined based on UE (user equipment) category information.

6. In a receiver in a communication system, Receiver; and Includes a control unit connected to the above transmitter, The above control unit, Receive a signal corresponding to at least a portion of the coding bits, Determine the number of input bits based on the above signal, Determine the basic matrix based on the number of input bits, Determine the lifting size (Z) based on at least one of the input bit number or the basic matrix, Determine a parity check matrix based on at least one of the above basic matrix or the above lifting size (Z), Decoding of the signal is performed based on the above parity check matrix, For the first setting, an input bit of the first length among the input bits is not included in the coded bit, and for the second setting, an input bit of the second length among the input bits is not included in the coded bit, The second length is characterized in that it is 0 or less than the first length, A receiver characterized in that the layered decoding order related to the first setting and the layered decoding order related to the second setting are different from each other.

7. In paragraph 6, A receiver characterized in that the first setting or the second setting is determined based on upper layer parameters.

8. In paragraph 6, A receiver characterized in that the first setting or the second setting is determined based on at least one of a CQI or an MCS index.

9. In paragraph 6, A receiver characterized in that the first setting or the second setting is determined based on at least one of a modulation order or a code rate.

10. In paragraph 6, A receiver characterized in that the first setting or the second setting is determined based on UE (user equipment) category information.

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