Chip for ultrasonic transducer, ultrasonic transducer, device, and manufacturing method

Abstract

Embodiments of the present application provide a chip for an ultrasonic transducer, an ultrasonic transducer, a device, and a chip manufacturing method. The chip is provided under an acoustic layer. The chip comprises: a substrate; a circuit module, provided in the substrate; and a conductive shielding layer, provided between the circuit module and the acoustic layer, wherein the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate, and the conductive shielding layer is grounded. The embodiments of the present application reduce the situation in which a high voltage generated during polarization of an acoustic layer could easily cause breakdown in closely-spaced metal blocks and floating metal blocks within a circuit module, thereby improving the yield rate of chips.

Description

Chip for ultrasonic transducer, ultrasonic transducer, device, and preparation method Technical Field

[0001] The embodiments of the present application relate to the field of sensor technology, and in particular to a chip, ultrasonic transducer, device, and preparation method for an ultrasonic transducer. Background Art

[0002] An ultrasonic transducer consists of an acoustic layer and a chip. The acoustic layer includes a piezoelectric layer, an electrode on the piezoelectric layer, and a protective layer. In transmit mode, the chip drives the piezoelectric layer to vibrate, emitting ultrasonic waves toward the target. In receive mode, the chip uses the acoustic wave signals reflected from the acoustic path to identify the surface structure of the detected object.

[0003] In the actual application of ultrasonic transducers, since the circuit module of the chip is set in the substrate below the acoustic layer, the polarization of the acoustic layer of the ultrasonic transducer requires a higher voltage. Therefore, the higher voltage will make the small-pitch metal blocks and suspended metal blocks in the circuit module easily broken down, affecting the yield of the chip.

[0004] Summary of the Invention

[0005] In view of this, embodiments of the present application provide a chip, an ultrasonic transducer, a device, and a preparation method for an ultrasonic transducer, which at least partially solve the above technical problems.

[0006] According to the first aspect of the present application, an embodiment provides a chip for an ultrasonic transducer, wherein the chip is arranged below an acoustic layer, and the chip includes: a substrate; a circuit module, wherein the circuit module is arranged in the substrate; a conductive shielding layer, wherein the conductive shielding layer is arranged between the circuit module and the acoustic layer, and the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate, and the conductive shielding layer is grounded.

[0007] According to the second aspect of the present application, an embodiment provides an ultrasonic transducer, including: the above chip and an acoustic layer.

[0008] According to a third aspect of the present application, an electronic device is provided, comprising: a screen and the above-mentioned ultrasonic transducer, wherein the ultrasonic transducer is attached to the screen via a substrate of the ultrasonic transducer.

[0009] According to a fourth aspect of the present application, an embodiment provides a method for preparing a chip for controlling an ultrasonic transducer. The method includes: when the acoustic layer of the ultrasonic transducer is polarized, the induced charge from above the acoustic layer is connected to the ground through a conductive shielding layer, the conductive shielding layer is arranged between the circuit module and the acoustic layer, and the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate.

[0010] Embodiments of the present application provide a chip, ultrasonic transducer, device, and preparation method for an ultrasonic transducer. A conductive shielding layer is disposed between a circuit module and an acoustic layer within a substrate, with the projection of the conductive shielding layer on the substrate at least covering the projection of the circuit module on the substrate. The conductive shielding layer directs induced charge from above the acoustic layer of the ultrasonic transducer to ground. Embodiments of the present application reduce the risk of breakdown of small-pitch metal blocks and suspended metal blocks within the circuit module due to the high voltage generated during polarization of the acoustic layer, thereby improving the chip's yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0012] FIG1 is a top view of an embodiment of an ultrasonic transducer according to the present application;

[0013] FIG2 is a cross-sectional view taken along line AA in FIG1 ;

[0014] FIG3 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0015] FIG4 is a cross-sectional view taken along line AA in FIG3 ;

[0016] FIG5 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0017] FIG6 is a cross-sectional view taken along line AA in FIG5 ;

[0018] FIG7 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0019] FIG8 is a cross-sectional view taken along line AA in FIG7 ;

[0020] FIG9 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0021] FIG10 is a cross-sectional view taken along line AA in FIG9 ;

[0022] FIG11 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0023] FIG12 is a cross-sectional view taken along line AA in FIG11 ;

[0024] FIG13 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0025] FIG14 is a cross-sectional view taken along line AA in FIG13;

[0026] FIG15 is a cross-sectional view taken along line AA in FIG13;

[0027] FIG16 is a cross-sectional view taken along line AA in FIG13;

[0028] FIG17 is a cross-sectional view taken along line AA in FIG13;

[0029] FIG18 is a schematic diagram of an embodiment of an electronic device;

[0030] FIG19 is a flow chart of a chip preparation method.

[0031] Explanation of the accompanying drawings: Chip 1000; pixel circuit area 100; pixel electrode 110; chip ground module 200; circuit module 300; metal pad area 400; substrate 500; metal layer 510; top metal layer 5101; multi-layer metal layer 5102; passivation layer 520; first window 5201; second window 5202; conductive shielding layer 600; conductive layer 610; dielectric layer 620; redistribution 700; excitation electrode 800; acoustic layer 2000; piezoelectric layer 2100; piezoelectric layer upper electrode 2200; protective layer 2300. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0033] The structure of the chip 1000 according to the embodiment of the present application is described in detail below with reference to Figures 1 to 17. To facilitate observation of the structure of the chip 1000, the acoustic layer 2000 is omitted in Figures 1, 3, 5, 7, 9, 11, and 13.

[0034] Referring to Figures 1 and 2, Figure 2 is a lateral structural illustration of Figure 1 cut along the AA section. The ultrasonic transducer includes an acoustic layer 2000 and a chip 1000. The acoustic layer 2000 includes a piezoelectric layer 2100, an electrode 2200 on the piezoelectric layer, and a protective layer 2300. The chip 1000 is arranged below the piezoelectric layer 2100 of the acoustic layer 2000. The chip 1000 includes: a substrate 500, a pixel circuit area 100, a chip ground module 200, a circuit module 300, a metal pad area 400, and an excitation electrode (not shown in the figure). The metal layer 510 above the metal pad area 400 in Figure 2 is a metal pad, and the passivation layer above the metal pad area 510 is provided with a window to expose part of the metal pad.

[0035] Specifically, substrate 500 is a silicon-based substrate, and includes a top metal layer 5101 above substrate 500, and a passivation layer 520 above top metal layer 5101. Substrate 500 includes a number of transistor units (such as N-type or P-type metal oxide semiconductor field effect transistors, and complementary metal oxide semiconductor field effect transistors composed of both), intra-layer metal traces for interconnection, inter-layer vias, and multi-layer metal layers 5102. In the figure, only "..." is used to represent the above-mentioned transistor units, metal traces, inter-layer vias, and multi-layer metal layers 5102.

[0036] Referring to Figures 3 and 4, Figure 4 is a schematic diagram of the lateral structure of Figure 3 cut along the AA section. The passivation layer 520 of the pixel circuit area 100 is provided with a second window 5202 to form the pixel electrode 110. The pixel circuit area 100 is an area of ​​the ultrasonic transducer imaging array composed of a plurality of pixel electrodes 110, referred to as the Active Area (abbreviated as AA area). The chip ground module 200 is located outside the pixel circuit area 100 and is used to isolate the pixel circuit area 100 to prevent the pixel circuit area 100 from being interfered with by peripheral signals. The chip ground module 200 and the circuit module 300 are arranged side by side in the substrate 500. The circuit module 300 is provided with a large number of metal traces and functional circuits, such as power management, clock, ADC circuit, etc.

[0037] When the ultrasonic transducer is applied to the field of fingerprint recognition, the finger is placed on the screen cover, the ultrasonic transducer is in the transmitting mode, the pixel electrode 110 generates a lower voltage V1, the excitation electrode drives the upper electrode 2200 of the piezoelectric layer to generate an upper voltage V2, the upper voltage V2 minus the lower voltage V1 to obtain a differential voltage, and the differential voltage drives the piezoelectric layer 2100 to vibrate and emit ultrasonic waves. The ultrasonic wave passes through the screen cover to the surface of the finger, and the intensity of the transmitted echo signal of the sound wave at the fingerprint-cover interface varies due to the "valley" and "ridge" structure of the fingerprint. When the ultrasonic transducer is in the receiving mode, the pixel electrode 110 receives the reflected echo signal carrying the fingerprint information and transmits the received reflected echo signal to the circuit module 300. The circuit module 300 is used to perform signal processing on the reflected echo signal collected by the pixel electrode.

[0038] Specifically, the circuit module includes: an analog-to-digital conversion circuit for performing analog-to-digital conversion on the reflected echo signal collected by the pixel electrode; a storage circuit for storing the reflected echo signal after the analog-to-digital conversion; and a fingerprint recognition circuit for processing the reflected echo signal to confirm whether it is the target fingerprint. The analog-to-digital conversion circuit, storage circuit, and fingerprint recognition circuit are not shown in the figure. In some embodiments, the fingerprint recognition circuit can also be implemented by another chip, which can be provided in connection with the ultrasonic transducer.

[0039] In the embodiment of the present application, an ultrasonic transducer is placed inside a display device, and biometric identification and recognition are performed through the above process for user authentication.

[0040] In the embodiment of the present application, the pixel electrode 110 is grounded through the metal wiring, interlayer vias and multi-layer metal layer 5102 below the pixel electrode 110 , thereby preventing the pixel electrode 110 from being interfered by the voltage signal of the acoustic layer 200 .

[0041] In order to make the piezoelectric layer 2100 emit ultrasonic waves, it is usually necessary to apply a high-voltage signal of tens to hundreds of volts to the electrode 2200 on the piezoelectric layer. Since a higher voltage is required to polarize the piezoelectric layer 2100, the higher voltage will make the small-pitch metal blocks and suspended metal blocks of the circuit module 300 easily broken down, affecting the yield of the chip.

[0042] In addition, the circuit module 300 and the acoustic layer 2000 overlap in their projected areas on the substrate 500. The circuit module 300 is easily interfered with by the high-voltage signal generated by the electrode 2200 on the piezoelectric layer, resulting in an increase in the time domain noise of the signal in the circuit module and a reduction in the signal-to-noise ratio.

[0043] Referring to Figures 5 and 6, Figure 6 is a lateral structural illustration of Figure 5 cut along the AA section. A chip 1000 according to an embodiment of the present application is arranged below the acoustic layer 2000. The acoustic layer 2000 includes a piezoelectric layer 2100, an electrode 2200 on the piezoelectric layer, and a protective layer 2300. The chip 1000 includes: a substrate 500, a circuit module 300, and a conductive shielding layer 600. The conductive shielding layer 600 is arranged between the circuit module 300 and the acoustic layer 2000, and the projection of the conductive shielding layer 600 on the substrate 500 at least covers the projection of the circuit module 300 on the substrate 500, and the conductive shielding layer 600 is grounded.

[0044] According to an embodiment of the present application, the chip 1000 is provided with a conductive shielding layer 600, which is disposed between the circuit module 300 and the acoustic layer 2000. The projection of the conductive shielding layer 600 on the substrate 500 at least covers the projection of the circuit module 300 on the substrate 500, and the conductive shielding layer 600 is connected to the chip ground module 200. During the polarization process of the acoustic layer 2000, the presence of the conductive shielding layer 600 also effectively reduces the occurrence of breakdown of the fine-pitch metal blocks and the suspended metal blocks in the circuit module 300, thereby ensuring the chip manufacturing yield.

[0045] In other specific implementations of the present invention, the circuit module 300 is disposed within the substrate 500, with at least a portion of the circuit module 300 located below the acoustic layer. When the acoustic layer 2000 generates an ultrasonic signal, the induced charge above the acoustic layer 2000 is connected to ground through the conductive shielding layer 600. This reduces interference with the circuit module 300 from the high voltage signal generated by the electrode 2200 on the piezoelectric layer of the chip 1000, thereby improving the signal-to-noise ratio.

[0046] In some specific implementations of the embodiments of the present application, referring to Figures 5 and 6, the chip ground module 200 and the circuit module 300 are arranged side by side in the substrate 500, and a first window 5201 is set in the passivation layer 520 above the chip ground module 200, through which the metal layer 510 above the chip ground module 200 is exposed, and at least part of the conductive shielding layer 600 passes through the first window 5201 to connect to the metal layer 510 above the chip ground module 200, and the conductive shielding layer 600 is grounded through the metal layer 510 above the chip ground module 200.

[0047] In the embodiment of the present application, a first window 5201 is simply provided on the passivation layer above the chip ground module 200 , so that the conductive shielding layer 600 can be grounded through the metal layer 510 of the chip ground module 200 , which simplifies the manufacturing process.

[0048] In some embodiments of the present invention, the thickness of the conductive shielding layer 600 is no greater than 10 microns. Specifically, the thickness of the conductive shielding layer 600 is preferably less than 1 micron. This can prevent the thick conductive shielding layer 600 from affecting the uniformity of the piezoelectric layer 2100.

[0049] In some embodiments of the present invention, the conductive shielding layer 600 may include one of a metal material, a metal oxide semiconductor material, an organic conductive material, a nano-metal conductive material, or a carbon nano-conductive material.

[0050] Specifically, the metal material can be a common metal material such as aluminum, titanium, copper, tungsten, etc. Metal oxide semiconductor materials can be tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). Organic conductive materials can be polythiophene and poly (p-phenylene glycol) (PEDOT), poly (3,4-ethylenedioxythiophene)-polystyrene sulfonic acid (PEDOT:PSS). Nanometal conductive materials can be silver nanowires (AgNWs) and metal mesh. Carbon nanoconductive materials can be graphene and carbon nanotubes.

[0051] In some further specific implementations of the present application, referring to Figures 7 and 8 , Figure 8 illustrates the lateral structure of Figure 7 taken along the AA cross-section. Chip 1000 further includes a redistribution layer (RDL) 700. One end of the RDL 700 is connected to the conductive shielding layer 600, and the other end of the RDL 700 is electrically connected to the excitation electrode 800 during the polarization of the acoustic layer.

[0052] Specifically, the redistribution 700 can be a metal redistribution and is disposed on the side of the conductive shielding layer 600. To facilitate connection of the other end of the redistribution 700 with the excitation electrode 800, the redistribution 700 is disposed on the side of the conductive shielding layer 600 near the excitation electrode 800.

[0053] During the polarization process of the acoustic layer 2000, the excitation electrode 800 is electrically connected to the conductive shielding layer 600 through the rewiring 700. The excitation electrode 800 can be a suspended metal structure. The polarization induced charge accumulated by the excitation electrode 800 during the polarization process of the acoustic layer 2000 is discharged to the ground, thereby avoiding the excitation electrode 800 from being broken down due to the accumulation of polarization induced charge.

[0054] Since the excitation electrode 800 provides an excitation voltage to the piezoelectric layer upper electrode 2200 during operation of the ultrasonic transducer, grounding the excitation electrode 800 prevents the excitation voltage from being provided to the piezoelectric layer upper electrode 2200. Therefore, after chip fabrication is completed, the connection between the excitation electrode 800 and the redistribution wiring 700 is severed, thereby disconnecting the excitation electrode 800 from the conductive shielding layer 600, and the excitation electrode 800 is no longer grounded.

[0055] After the multiple chips on the wafer are prepared, they can be tested. After the multiple chips on the wafer are prepared or tested, the wafer containing the multiple chips is cut to form individual chips. In this embodiment, the length of the rewiring 700 exceeds the boundary of the individual chips to be cut on the wafer, and at least a portion of the rewiring is arranged within the dicing lane on the wafer corresponding to the individual chips. This facilitates severing the connection between the excitation electrode 800 and the rewiring 700 when the wafer is cut, and the excitation electrode 800 can be disconnected from the ground without adding other steps.

[0056] Specifically, the materials and manufacturing processes of the redistribution layer 700 and the conductive shielding layer 600 are consistent, thereby simplifying the manufacturing process.

[0057] In order to further simplify the manufacturing process, the redistribution layer 700 and the conductive shielding layer 600 are formed simultaneously.

[0058] In some specific implementations of the embodiments of the present application, as shown in Figures 9 and 10, Figure 10 is a lateral structural illustration of Figure 9 cut along the AA section. The conductive shielding layer 600 includes a conductive layer 610 and a dielectric layer 620 with a shape adaptation. The conductive layer 610 is arranged between the circuit module 300 and the dielectric layer 620, and the dielectric layer 620 is arranged between the conductive layer 610 and the acoustic layer 2000 (piezoelectric layer 2100). It can be understood that at least part of the conductive layer 610 is connected to the chip ground module 200 and separates the circuit module 300 from the acoustic layer 2000, so that when the acoustic layer 2000 generates an ultrasonic signal, the induced charge above the acoustic layer 2000 can be connected to the ground through the conductive shielding layer, thereby reducing interference with the circuit module 300. The dielectric layer 620 covers the conductive layer 610 , and the shape of the dielectric layer 620 is adapted to the conductive layer 610 . The dielectric layer 620 can avoid problems such as poor bonding between the piezoelectric layer 2100 of the acoustic layer 2000 and the conductive layer 610 .

[0059] Specifically, dielectric layer 620 may be at least one of silicon oxide, silicon nitride, a high-K dielectric constant material, and a polymer dielectric material. The high-K dielectric constant of a high-K dielectric constant material is defined relative to the relative dielectric constant of the material. High-K dielectric constant materials may include titanium oxide, zirconium oxide, hafnium oxide, etc. Polymer dielectric materials may include polyimide, etc.

[0060] Specifically, the redistribution 700 is formed simultaneously with the conductive shielding layer 600 . When the conductive shielding layer 600 includes a conductive layer 610 and a dielectric layer 620 , the redistribution 700 also includes a conductive layer 610 and a dielectric layer 620 .

[0061] In some specific implementations of the embodiments of the present application, as shown in Figures 11 and 12, Figure 12 is a lateral structural description of Figure 11 cut along the AA section. The conductive shielding layer 600 is at least a portion of the top metal layer 5101 above the circuit module 300, and the conductive shielding layer 600 is grounded through the inner layer routing (not shown in the figure) of the substrate 500. The embodiments of the present application reuse the top metal layer 5101 above the circuit module 300. The conductive shielding layer 600 is formed synchronously with the top metal layer 5101 above the circuit module 300, and there is no need to set up a separate conductive shielding layer 600, which makes the process simpler, improves manufacturing efficiency, and reduces costs. In addition, the conductive shielding layer 600 is at least a portion of the top metal layer 5101 above the circuit module 300, and there is no need to set up a dielectric layer to avoid problems such as poor bonding between the piezoelectric layer 2100 of the acoustic layer 2000 and the conductive layer 610.

[0062] In some further specific implementations of the present application, as shown in Figures 13 to 17 , and Figures 14 to 17 are side structural illustrations taken along the AA section of Figure 13 , the conductive shielding layer 600 comprises at least a portion of the multi-layer metal layer 5102 in the substrate 500 . The multi-layer metal layer 5102 is grounded via a portion of at least one metal layer 510 therein, and the multi-layer metal layer 5102 is located in a plurality of parallel planes.

[0063] The projection of the multi-layer metal layer 5102 on the substrate 500 covers the projection of the circuit module 300, thereby increasing the flexibility of the layout of the multi-layer metal layer 5102 according to the actual design of the chip 1000. In other words, the multi-layer metal layer 5102 is arranged at different positions on the chip 1000, which not only ensures the protection of the circuit module 300 but also allows for flexible layout.

[0064] Specifically, at least one of the multi-layer metal layers 5102 in the embodiment of the present application is grounded through an intra-layer routing (not shown in the figure), and the remaining ones are connected to the grounded metal layer 5102 through intra-layer routing (not shown in the figure), or each metal layer 5102 is grounded through an intra-layer routing (not shown in the figure).

[0065] If a single metal layer 5102 cannot cover the circuit module 300, another metal layer 5102 can be arranged to overlap the projection area of ​​the previous metal layer 5102 on the substrate 500, so that the projections of the two metal layers 5102 on the substrate 500 can cover the projection of the circuit module 300 on the substrate 500. Similarly, the arrangement of three metal layers 5102 and four metal layers 5102 has the same effect.

[0066] Furthermore, as shown in Figures 14-17 , the projections of the multiple metal layers 5102 on the substrate 500 overlap with each other. Therefore, the projections of the multiple metal layers 5102 on the substrate 500 can completely cover the projection of the circuit module 300 on the substrate 500, thereby preventing gaps between the projections of the multiple metal layers 5102 on the substrate 500, which would reduce the protection effect on the circuit module 300.

[0067] In some embodiments of the present invention, the number of metal layers 5102 can be any number and can be adjusted according to the actual structural layout of the chip 1000.

[0068] As shown in FIG14 , the conductive shielding layer 600 includes five metal layers 5102, and a portion of the five metal layers 5102 is grounded (the grounding location is not shown in the figure). Furthermore, the projected area on the substrate formed by the grounded portions of each metal layer 5102 completely covers the projection of the circuit module 300 on the substrate. Thus, through this arrangement, the conductive shielding layer 600, composed of the five metal layers 5102, protects the circuit module 300. As shown in FIG15 , the conductive shielding layer 600 can also include four metal layers 5102. As shown in FIG16 , the conductive shielding layer 600 can also include three metal layers 5102. As shown in FIG17 , the conductive shielding layer 600 also includes three metal layers 5102. However, the layout of the three metal layers 5102 in FIG17 differs from the layout of the three metal layers 5102 in FIG16 . As can be seen, the layout of the multiple metal layers 5102 can be diverse, thereby achieving structural diversity in the chip 1000.

[0069] In addition, the number of metal layers 5102 is not limited to five or three in the above embodiments, and can be arranged in different numbers according to actual usage requirements, specifically depending on the design of the chip 1000.

[0070] Specifically, when the conductive shielding layer 600 is part of the multi-layer metal layer 5102 in the substrate 500, a dielectric layer (not shown in the figure) is set between the conductive shielding layer 600 and the passivation layer 520. The dielectric layer in the substrate can be a silicon oxide layer.

[0071] Furthermore, the conductive shielding layer 600 includes at least a portion of the multi-layer metal layer 5102 in the substrate 500 , and there is no need to provide a dielectric layer to avoid problems such as poor bonding between the piezoelectric layer 2100 of the acoustic layer 2000 and the conductive layer 610 .

[0072] In some embodiments of the present invention, the sheet resistance of the conductive shielding layer 600 is between 0.1Ω / □ and MΩ / □. Specifically, the sheet resistance of the conductive shielding layer 600 can be selected based on actual use to ensure effective shielding of the induced charge of the operating voltage of the acoustic layer 2000.

[0073] In addition, the film forming method of the conductive shielding layer 600 of the chip 1000 of the embodiment of the present application can be, for example, using a metal material or a metal oxide semiconductor material, which can be formed by physical deposition (PVD), such as sputtering or evaporation. It can also be formed by chemical assisted deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), etc. It can also be formed by atomic layer deposition (ALD). If an organic conductive material, a nano-metal conductive material or a carbon nano-material is selected, it can also be formed by a series of solution coating methods such as spin coating, spray coating, roller coating, and slit coating. The patterning of the conductive shielding layer 600 can be achieved by lift-off, dry etching or wet etching. The lift-off method can be understood as a lift-off process. A patterned photoresist structure or metal shadow mask is obtained on a substrate using a photolithography process. A target coating is then applied to the mask using a coating process. A stripping solution (also known as a stripping solution) is then used to dissolve the photoresist or mechanically remove the metal hard mask to obtain a target pattern structure consistent with the pattern. Rewiring 700 can also be formed using the same method.

[0074] 1 to 17 , an embodiment of the present application further provides an ultrasonic transducer, comprising: a chip 1000 and an acoustic layer 2000 , wherein the chip 1000 is the chip 1000 described in any of the above embodiments.

[0075] 18 , an embodiment of the present application further provides an electronic device, including: a screen 180 and the above-mentioned ultrasonic transducer, wherein the ultrasonic transducer is attached to the screen 180 via a substrate 500 of the ultrasonic transducer.

[0076] Referring to FIG. 19 , an embodiment of the present application further provides a method for preparing a chip, wherein the chip is used to control an ultrasonic transducer, and the method comprises:

[0077] Step S1. When the acoustic layer of the ultrasonic transducer is polarized, the induced charge from above the acoustic layer is connected to the ground through a conductive shielding layer. The conductive shielding layer is arranged between the circuit module and the acoustic layer, and the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate.

[0078] According to an embodiment of the present application, a chip is provided with a conductive shielding layer, which is disposed between the circuit module and the acoustic layer. The projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate, and the conductive shielding layer is connected to the chip ground module. During the acoustic layer polarization process, the presence of the conductive shielding layer effectively reduces the occurrence of breakdown of small-pitch metal blocks and suspended metal blocks in the circuit module, ensuring the chip process yield.

[0079] Specifically, step S1 further includes: connecting the charge accumulated in the excitation electrode to the ground through the rewiring and the conductive shielding layer, wherein one end of the rewiring is connected to the conductive shielding layer, and the other end of the rewiring is electrically connected to the excitation electrode.

[0080] The method further comprises:

[0081] When the chip is prepared, the connection between the excitation electrode and the rewiring is disconnected.

[0082] During the polarization process of the acoustic layer, the excitation electrode is electrically connected to the conductive shielding layer through rewiring. The excitation electrode can be a suspended metal structure. The polarization induced charge accumulated on the excitation electrode during the polarization process of the acoustic layer is discharged to the ground, thereby avoiding the excitation electrode from being broken down due to the accumulation of polarization induced charge.

[0083] Since the excitation electrode provides an excitation voltage to the upper electrode of the piezoelectric layer during operation of the ultrasonic transducer, grounding the excitation electrode prevents it from providing an excitation voltage to the upper electrode of the piezoelectric layer. Therefore, after the acoustic layer is polarized, the connection between the excitation electrode and the redistribution wiring is severed, disconnecting the excitation electrode from the conductive shielding layer and removing the ground connection.

[0084] Since the excitation electrode provides an excitation voltage to the upper electrode of the piezoelectric layer during operation of the ultrasonic transducer, grounding the excitation electrode prevents the upper electrode of the piezoelectric layer from receiving an excitation voltage. Therefore, after chip fabrication, the connection between the excitation electrode and the redistribution wiring is severed, disconnecting the excitation electrode from the conductive shielding layer and removing the ground connection.

[0085] After the multiple chips on the wafer are prepared, they can be tested. After the multiple chips on the wafer are prepared or tested, the wafer containing the multiple chips is cut to form individual chips. In this embodiment, the length of the rewiring exceeds the boundary of the individual chips to be cut on the wafer, and at least a portion of the rewiring is arranged within the dicing lane on the wafer corresponding to the individual chips. This facilitates severing the connection between the excitation electrode and the rewiring when the wafer is cut, thereby achieving the goal of disconnecting the excitation electrode from grounding without adding other steps.

[0086] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A chip for an ultrasonic transducer, wherein the chip is arranged below an acoustic layer, characterized in that: The chip includes: substrate; a circuit module, wherein the circuit module is disposed in the substrate; A conductive shielding layer is provided between the circuit module and the acoustic layer, and the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate, and the conductive shielding layer is grounded.

2. The chip according to claim 1, characterized in that At least a portion of the circuit module is located below the acoustic layer.

3. The chip according to claim 1, characterized in that The chip further comprises: a chip ground module, wherein the chip ground module and the circuit module are arranged in parallel in the substrate; A first window is set in the passivation layer above the chip ground module, and the metal layer above the chip ground module is exposed through the first window. At least part of the conductive shielding layer passes through the first window to connect to the metal layer above the chip ground module, and the conductive shielding layer is grounded through the metal layer above the chip ground module.

4. The chip according to claim 1, characterized in that The chip further includes a redistribution wiring and an excitation electrode. One end of the redistribution wiring is connected to the conductive shielding layer, and the other end of the redistribution wiring is electrically connected to the excitation electrode during the polarization process of the acoustic layer.

5. The chip according to claim 4, characterized in that The length of the redistribution wiring exceeds the boundary of the chip, and at least a portion of the redistribution wiring is arranged within the saw path of the chip.

6. The chip according to claim 5, characterized in that After the chip is prepared, the connection between the rewiring and the excitation electrode is disconnected.

7. The chip according to claim 1, characterized in that The conductive shielding layer includes a conductive layer and a dielectric layer with adapted shapes. The conductive layer is arranged between the circuit module and the dielectric layer, and the dielectric layer is arranged between the conductive layer and the acoustic layer.

8. The chip according to claim 7, characterized in that The redistribution wiring is formed simultaneously with the conductive shielding layer.

9. The chip according to claim 1, characterized in that The conductive shielding layer is at least a portion of the top metal layer above the circuit module, and the conductive shielding layer is grounded through an intra-layer routing of the substrate.

10. The chip according to claim 1, characterized in that The conductive shielding layer is at least a part of the multi-layer metal layer above the circuit module. The multi-layer metal layer is grounded through a part of at least one of the metal layers. The multi-layer metal layer is in multiple planes parallel to each other. A dielectric layer in the substrate is arranged between the conductive shielding layer and the passivation layer above it.

11. The chip according to claim 10, characterized in that The projections of the multiple metal layers onto the substrate overlap with each other.

12. The chip according to claim 4, characterized in that The chip further includes: The pixel circuit area, the passivation layer above the pixel circuit area is provided with a second window, through the second window exposing the metal layer above the pixel circuit area to form a pixel electrode, and the chip ground is arranged at the periphery of the pixel circuit area; In the transmitting mode, the pixel electrode outputs a driving signal to drive the piezoelectric layer to vibrate and emit ultrasonic waves. In the receiving mode, the pixel electrode receives a reflected echo signal and transmits the reflected echo signal to the circuit module for signal processing.

13. The chip according to claim 12, characterized in that The circuit module includes: an analog-to-digital conversion circuit, configured to perform analog-to-digital conversion on the reflected echo signal collected by the pixel electrode; The circuit module further includes a storage circuit for storing the reflected echo signal after the analog-to-digital conversion; The circuit module further includes a fingerprint recognition circuit for processing the reflected echo signal to determine whether it is a target fingerprint.

14. The chip according to claim 13, characterized in that The acoustic layer includes a piezoelectric layer, an upper electrode of the piezoelectric layer and a protective layer. The chip is arranged below the piezoelectric layer. The excitation electrode drives the upper electrode of the piezoelectric layer to generate an upper voltage, and the pixel electrode generates a lower voltage. The upper voltage minus the lower voltage obtains a differential voltage. The differential voltage drives the piezoelectric layer to vibrate and emit ultrasonic waves to the outside.

15. The chip according to claim 1, characterized in that The sheet resistance of the conductive shielding layer is between 0.1Ω / □ and MΩ / □.

16. The chip according to claim 1, characterized in that The thickness of the conductive shielding layer is less than 1 micron.

17. An ultrasonic transducer, characterized in that: include: A chip and an acoustic layer, wherein the chip is the chip according to any one of claims 1 to 16.

18. An electronic device, characterized in that: include: A screen and the ultrasonic transducer according to claim 17, wherein the ultrasonic transducer is attached to the screen via a substrate of the ultrasonic transducer.

19. A method for preparing a chip for controlling an ultrasonic transducer, characterized in that: The method comprises: When the acoustic layer of the ultrasonic transducer is polarized, the induced charge from above the acoustic layer is connected to the ground through the conductive shielding layer, and the conductive shielding layer is arranged between the circuit module and the acoustic layer, and the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate.

20. The method according to claim 19, characterized in that When the acoustic layer of the ultrasonic transducer is polarized, the induced charge from above the acoustic layer is connected to the ground through the conductive shielding layer, and further includes: Leading the charge accumulated in the excitation electrode to the ground through the rewiring and the conductive shielding layer, wherein one end of the rewiring is connected to the conductive shielding layer, and the other end of the rewiring is electrically connected to the excitation electrode; The method further comprises: When the chip is prepared, disconnecting the excitation electrode from the rewiring; The length of the redistribution wiring exceeds the boundary of the chip, and at least a portion of the redistribution wiring is arranged within the saw path of the chip.

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