Display panel and display module

Abstract

Provided in the present application are a display panel and a display module. The display panel comprises a display area and a virtual terminal area, wherein a plurality of sub-pixels of the display panel are located in the display area, and each sub-pixel comprises at least one first transistor; and a photosensitive sensor is located in the virtual terminal area, and part of a film layer of the photosensitive sensor and part of a film layer of the first transistor are arranged in the same layer. The technical problem of an existing externally mounted photosensitive sensor not facilitating the increase of the screen-to-body ratio of a display is ameliorated.

Description

Display panels and display modules Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display module. Background Art

[0002] With the development of display technology, light-emitting diode (LED) displays have become a hot topic in the display industry due to their high reliability, small light-emitting unit size, and high brightness. To reduce display power consumption, a light sensor is often mounted on the upper bezel. The display uses the light sensor to sense the intensity of the external light and adjust the brightness in real time. For example, when the external light is low, the display will automatically adjust to a low brightness, thereby reducing power consumption. However, the use of an external light sensor occupies a larger bezel, which is not conducive to improving the display's screen-to-body ratio. SUMMARY OF THE INVENTION

[0003] The present application provides a display panel and a display module to alleviate the technical problem that existing external light sensors are not conducive to improving the screen-to-body ratio of the display.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, an embodiment of the present application provides a display panel comprising a display area and a binding area located on one side of the display area, wherein the binding area comprises a terminal area and virtual terminal areas located on opposite sides of the terminal area; the display panel further comprises:

[0006] substrate;

[0007] a plurality of sub-pixels arranged in an array on the substrate and located within the display area, each of the sub-pixels comprising at least one first transistor; and

[0008] At least one light sensor is located within the virtual terminal area, and a portion of the film layer of the light sensor is provided on the same layer as a portion of the film layer of the first transistor.

[0009] In a second aspect, an embodiment of the present application further provides a display module, comprising a light-emitting device and a display panel, wherein the light-emitting device is disposed on the display panel, the display panel comprising a display area and a binding area located on one side of the display area, the binding area comprising a terminal area and virtual terminal areas located on opposite sides of the terminal area; the display panel further comprising:

[0010] substrate;

[0011] a plurality of sub-pixels arranged in an array on the substrate and located within the display area, each of the sub-pixels comprising at least one first transistor; and

[0012] At least one light sensor is located within the virtual terminal area, and a portion of the film layer of the light sensor is provided on the same layer as a portion of the film layer of the first transistor;

[0013] Each of the light-emitting devices corresponds to a sub-pixel on the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] FIG1 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present application.

[0016] FIG2 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application.

[0017] FIG3 is a circuit diagram of a temperature sensor provided in an embodiment of the present application.

[0018] FIG4 is a schematic diagram of another cross-sectional structure of a display panel provided in an embodiment of the present application.

[0019] FIG5 is a schematic diagram of another cross-sectional structure of a display panel provided in an embodiment of the present application.

[0020] FIG6 is a schematic diagram of another cross-sectional structure of a display panel provided in an embodiment of the present application.

[0021] FIG7 is another circuit diagram of a temperature sensor provided in an embodiment of the present application.

[0022] FIG8 is a schematic diagram of a planar structure of a display module provided in an embodiment of the present application.

[0023] FIG9 is a schematic diagram of a partial cross-sectional structure of a display module provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0024] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0025] In response to the technical problem that existing external light sensors are not conducive to improving the screen-to-body ratio of displays, the present application provides a display panel and a display module to alleviate the technical problem that existing external light sensors are not conducive to improving the screen-to-body ratio of displays.

[0026] In one embodiment, the present application provides a display panel comprising a display area and a binding area located on one side of the display area, wherein the binding area comprises a terminal area and virtual terminal areas located on opposite sides of the terminal area; the display panel further comprises:

[0027] substrate;

[0028] a plurality of sub-pixels arranged in an array on the substrate and located within the display area, each of the sub-pixels comprising at least one first transistor; and

[0029] At least one light sensor is located within the virtual terminal area, and a portion of the film layer of the light sensor is provided on the same layer as a portion of the film layer of the first transistor.

[0030] In one embodiment, the first transistor includes a first active layer arranged on the substrate, and the display panel also includes a first stack and a first source and drain layer arranged on the side of the first active layer away from the substrate; the light sensor includes a first semiconductor layer, a second semiconductor layer and a first protective layer arranged in a stacked manner, the first semiconductor layer and the first active layer are arranged in the same layer, the first stack is provided with a first via hole at a position corresponding to the first semiconductor layer, the second semiconductor layer is filled in the first via hole and is in contact with the first semiconductor layer, and the first protective layer covers the side of the second semiconductor layer away from the first semiconductor layer.

[0031] In one embodiment, the light sensor further includes a third semiconductor layer disposed on a side of the first protective layer away from the second semiconductor layer, the first protective layer is provided with a second via hole at a position corresponding to the second semiconductor layer, and the third semiconductor layer is connected to the second semiconductor layer through the second via hole.

[0032] In one embodiment, the display panel also includes a second stack and a first electrode, the second stack is arranged on a side of the first source and drain layer away from the first stack, and the first electrode is arranged on a side of the second stack away from the first source and drain layer; the second stack is provided with a third via at a position corresponding to the first protective layer, and part of the third semiconductor layer is located in the third via.

[0033] In one embodiment, the display panel further includes a light-shielding layer and a second protective layer arranged on a side of the first electrode away from the second stack, the second protective layer is located on a side of the light-shielding layer away from the second stack, the light-shielding layer and the second protective layer are provided with a first opening at a position corresponding to the first electrode, the light-shielding layer is provided with a second opening at a position corresponding to the third via hole, the second protective layer is also located in the second opening and the third via hole, and is provided with a third opening at a position corresponding to the second via hole, and the third semiconductor layer covers the second opening and the second protective layer in the third via hole.

[0034] In one embodiment, the display panel further includes a reflective layer, which is located in the third via hole and has a fourth opening provided at a position corresponding to the second via hole, and the third semiconductor layer covers the reflective layer in the third via hole.

[0035] In one embodiment, the second stack includes a first flat layer, a first passivation layer, a second flat layer and a second passivation layer arranged in a stacked manner, the first flat layer is arranged on the first stack and the first source and drain layer, and the first electrode is arranged on the second passivation layer; the display panel also includes a second source and drain layer arranged between the first passivation layer and the second flat layer, the second source and drain layer is formed with a first auxiliary electrode, and the first auxiliary electrode is connected between the first transistor and the first electrode; the first stack includes a first gate insulating layer, a second gate insulating layer and a first interlayer insulating layer arranged in a stacked manner, the first gate insulating layer is arranged on the first active layer and the first semiconductor layer, and the first source and drain layer is arranged on the first interlayer insulating layer; the display panel also includes a first gate layer and a second gate layer, the first gate layer is located between the first gate insulating layer and the second gate insulating layer, and the second gate is located between the second gate insulating layer and the first interlayer insulating layer.

[0036] In one embodiment, the second stack includes a first flat layer and a second flat layer arranged in a stacked manner, the first flat layer is arranged on the first stack and the first source-drain layer, and the first electrode is arranged on the second flat layer; the display panel also includes a second source-drain layer arranged between the first flat layer and the second flat layer, the second source-drain layer is formed with a first auxiliary electrode, and the first auxiliary electrode is connected between the first transistor and the first electrode; the first stack includes a first gate insulating layer, a second gate insulating layer and a first interlayer insulating layer arranged in a stacked manner, the first gate insulating layer is arranged on the first active layer and the first semiconductor layer, and the first source-drain layer is arranged on the first interlayer insulating layer; the display panel also includes a first gate layer and a second gate layer, the first gate layer is located between the first gate insulating layer and the second gate insulating layer, and the second gate is located between the second gate insulating layer and the first interlayer insulating layer.

[0037] In one embodiment, the display panel further includes a plurality of temperature sensors located within the display area, wherein a portion of a film layer of the temperature sensors is provided on the same layer as a portion of a film layer of the first transistor, and an arrangement density of the temperature sensors close to the binding area is greater than an arrangement density of the temperature sensors far from the binding area;

[0038] There is a gap between two adjacent sub-pixels, and the temperature sensor is disposed in at least a portion of the gap.

[0039] In one embodiment, each of the sub-pixels further includes at least one second transistor connected to the first transistor, the first transistor is a polysilicon transistor, and the second transistor is an oxide transistor; and a material of the second semiconductor layer includes a metal oxide semiconductor material.

[0040] In one embodiment, the temperature sensor includes a third transistor and a fourth transistor connected to the third transistor, the third transistor is disposed on the same layer as the first transistor, and the fourth transistor is disposed on the same layer as the second transistor.

[0041] In one embodiment, the present application also provides a display module, which includes a light-emitting device and a display panel of one of the aforementioned embodiments, wherein the light-emitting device is arranged on the display panel, and each of the light-emitting devices corresponds to a sub-pixel on the display panel.

[0042] In the display panel and display module provided in the embodiments of the present application, the display panel includes a display area and a binding area located on one side of the display area, the binding area includes a terminal area and virtual terminal areas located on opposite sides of the terminal area; the display panel also includes a substrate and a plurality of sub-pixels and at least one light sensor arranged on the substrate, the plurality of sub-pixels are located within the display area, and each of the sub-pixels includes at least one first transistor; the light sensor is located within the virtual terminal area, and part of the film layer of the light sensor is arranged on the same layer as part of the film layer of the first transistor; the present application integrates the light sensor in the virtual terminal area of ​​the display panel, thereby allowing a smaller light sensor to be set without occupying additional space on the display panel, thereby improving the technical problem that the existing external light sensor is not conducive to improving the screen-to-body ratio of the display.

[0043] The display panel and display module of the present application will be described in detail below with reference to the accompanying drawings and specific implementations.

[0044] Please refer to Figures 1 and 2. Figure 1 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present application. Figure 2 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application. Figure 3 is a schematic diagram of a circuit of a temperature sensor provided in an embodiment of the present application. Referring to Figure 1, the display panel 100 includes a display area AA and a binding area BA located on one side of the display area AA. The binding area BA includes a terminal area PA and virtual terminal areas DPA located on opposite sides of the terminal area PA. The terminal area PA and the dummy terminal area DPA are both provided with binding terminals. The difference is that the terminals of the terminal area PA are used to connect the internal and external circuits of the display panel 100, while the terminals of the dummy terminal area DPA are not used to connect the internal and external circuits of the display panel 100. For example, a chip-on-film (COF) and / or a flexible circuit board (FPC) are bound to the display panel 100 through the terminals of the terminal area PA and the binding terminals of the dummy binding area BA, and are connected to the internal circuits of the display panel 100 through the terminals of the terminal area PA, while the terminals of the dummy terminal area DPA are in a floating state, which is used to improve the appearance consistency of the binding area BA and enhance the binding stability between the chip-on-film (COF) and the flexible circuit board (FPC) and the display panel 100. A first driver chip IC1 is provided on the chip-on-film (COF), and a second driver chip IC2 is provided on the flexible circuit board (FPC).

[0045] The display panel 100 also includes a substrate 10 and a plurality of sub-pixels SP, a plurality of temperature sensors 30, and at least one light sensor 20 disposed on the substrate 10. The plurality of sub-pixels SP are arranged in an array on the substrate 10 within the display area AA, with gaps between adjacent sub-pixels SP. The plurality of sub-pixels SP include red sub-pixels R, green sub-pixels G, and blue sub-pixels B. A plurality of temperature sensors 30 are disposed within some of the gaps. The temperature sensors 30 are configured to detect the temperature of the display panel 100 in real time, convert the detected temperature changes into electrical signals, and transmit them to a controller MT via a flexible printed circuit board (FPC) for calculation. The controller MT adjusts the heat dissipation device in real time based on the calculated results to change the temperature of the display panel 100. Optionally, the arrangement density of the temperature sensors 30 near the binding area BA is greater than that of the temperature sensors 30 farther from the binding area BA, thereby improving the reliability of the temperature measurement by the temperature sensors 30.

[0046] At least one light sensor 20 is located within the virtual terminal area DPA. The light sensor 20 is used to collect ambient light intensity, convert the collected light signal into an electrical signal, and transmit it to the controller MT via a flexible printed circuit board (FPC) for calculation. The controller MT then adjusts the screen brightness in real time based on the calculation result. By integrating the light sensor 20 within the virtual terminal area DPA of the display panel 100, without occupying additional space on the display panel 100, the technical problem of existing external light sensors 20 being detrimental to improving the display's screen-to-body ratio is addressed.

[0047] Referring to Figure 2 , each sub-pixel SP includes at least one first transistor T1 disposed on the substrate 10. Optionally, a buffer layer 11 may be disposed between the first transistor T1 and the substrate 10. The buffer layer 11 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON) to prevent unwanted impurities or contaminants (such as moisture and oxygen) from diffusing from the flexible substrate 10 into devices that could be damaged by these impurities or contaminants. The buffer layer 11 also provides a flat top surface, facilitating the fabrication of other film structures thereon.

[0048] Part of the film layer of the light sensor 20 is arranged on the same layer as part of the film layer of the first transistor T1, and part of the film layer of the temperature sensor 30 is arranged on the same layer as part of the film layer of the first transistor T1. That is, the light sensor 20 and the temperature sensor 30 are both formed under the same process as the first transistor T1 of the sub-pixel SP, so that the light sensor 20 and the temperature sensor 30 are integrated on the display panel 100, so that the light sensor 20 and the temperature sensor 30 can be arranged with a smaller volume, avoiding the use of an external sensor solution that occupies a larger frame.

[0049] The first transistor T1 includes a first active layer AS1 disposed on the substrate 10. The display panel 100 also includes a first stacked layer 40 and a first source-drain layer SD1 disposed on a side of the first active layer AS1 away from the substrate 10. The first stacked layer 40 is located between the first active layer AS1 and the first source-drain layer SD1. The first source-drain layer SD1 is a metal conductive layer. The first source-drain layer SD1 forms the first source S1 and the first drain D1 of the first transistor T1. The light sensor 20 includes a stacked first semiconductor layer 21, a second semiconductor layer 22, and a first protective layer 23. The first semiconductor layer 21 is disposed on the same layer as the first active layer AS1, that is, the first semiconductor layer 21 and the first active layer AS1 are made of the same material, such as polycrystalline silicon or other semiconductor materials.

[0050] It should be noted that "co-layer arrangement" in this application means that, during the manufacturing process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are co-layered. For example, in this embodiment, the first semiconductor layer 21 and the first active layer AS1 are obtained by patterning the same semiconductor material layer, and the first semiconductor layer 21 and the first active layer AS1 are co-layered.

[0051] The first stack 40 is provided with a first via 401 at a position corresponding to the first semiconductor layer 21. The second semiconductor layer 22 is filled in the first via 401 and is in contact with the first semiconductor layer 21. The material of the second semiconductor layer 22 includes amorphous silicon, etc. Of course, the first stack 40 is also provided with vias in a portion of the area corresponding to the first active layer AS1. The first source S1 and the first drain D1 of the first transistor T1 are respectively connected to the first active layer AS1 through corresponding vias. Specifically, the first active layer AS1 includes a channel region and a source region and a drain region located on opposite sides of the channel region. The first source S1 is connected to the source region through a corresponding via, and the first drain D1 is connected to the drain region through a corresponding via. The source region and the drain region are formed by ion doping of semiconductor material, and the first semiconductor layer 21 is also formed by ion doping of semiconductor layer material.

[0052] A first protective layer 23 covers the side of the second semiconductor layer 22 facing away from the first semiconductor layer 21. The first protective layer 23 protects the second semiconductor layer 22 from damage during etching of the first source / drain layer SD1. The first protective layer 23 is made of an etch-resistant inorganic material, such as silicon oxide. Optionally, the first protective layer 23 also fills the first via 401, in which case the upper surface of the first protective layer 23 is flush with the upper surface of the first stack 40. The upper surface refers to the surface of each structure facing away from the substrate 10.

[0053] The first stack 40 includes a first gate insulating layer 41, a second gate insulating layer 42 and a first interlayer insulating layer 43 which are stacked together. The first gate insulating layer 41 is arranged on the first active layer AS1 and the first semiconductor layer 21, and the first source and drain layer SD1 is arranged on the first interlayer insulating layer 43. The first gate insulating layer 41, the second gate insulating layer 42 and the first interlayer insulating layer 43 are all inorganic insulating layers, such as silicon nitride layers.

[0054] The display panel 100 further includes a first gate layer GL1 and a second gate layer GL2. The first gate layer GL1 is located between the first gate insulating layer 41 and the second gate insulating layer 42, and the second gate G21 is located between the second gate insulating layer 42 and the first interlayer insulating layer 43. The first gate layer GL1 and the second gate layer GL2 are both metal conductive layers. The first gate layer GL1 forms the first gate G11 of the first transistor T1 and the first signal line SL1, and the second gate layer GL2 forms the second signal line SL2.

[0055] The temperature sensor 30 includes a third transistor T3, which is disposed on the same layer as the first transistor T1. Specifically, the third transistor T3 includes a third active layer AS3, a third gate G12, a third source S3, and a third drain D3. The third active layer AS3 is disposed on the same layer as the first active layer AS1, the third gate G12 is disposed on the same layer as the first gate G11, and the third source S3 and the third drain D3 are disposed on the same layer as the first source S1. That is, the first source-drain layer SD1, while forming the first source S1 and the first drain D1 of the first transistor T1, also forms the third source S3 and the third drain D3 of the third transistor T3. Optionally, the first source-drain layer SD1 also forms the connecting electrode 25 of the light sensor 20. It should be noted that Figure 2 only schematically shows part of the film layer structure of the sub-pixel SP, the light sensor 20 and the temperature sensor 30. The present application is not limited to this. For example, each of the sub-pixels SP in the present application may also include a storage capacitor and more transistors, the light sensor 20 may also include at least one transistor connected to the first semiconductor layer 21 through the connecting electrode 25, and the temperature sensor 30 may also include a capacitor and more transistors. For example, as shown in Figure 3, the temperature sensor 30 includes 4 transistors (such as T31, T32, T33, T34) and a capacitor (such as C1).

[0056] Continuing with Figure 2 , the light sensor 20 further includes a third semiconductor layer 24 disposed on a side of the first protective layer 23 away from the second semiconductor layer 22. The first protective layer 23 is provided with a second via 230 at a position corresponding to the second semiconductor layer 22. The third semiconductor layer 24 is connected to the second semiconductor layer 22 through the second via 230. Optionally, the opening area of ​​the second via 230 accounts for 80%-100% of the upper surface area of ​​the second semiconductor layer 22, thereby increasing the contact area between the third semiconductor layer 24 and the second semiconductor layer 22. Among them, the opening area of ​​the second via 230 refers to the area of ​​the opening of the second via 230 close to the second semiconductor layer 22, that is, the area of ​​the bottom of the second via 230. More specifically, the opening area of ​​the second via 230 refers to the area of ​​the positive projection of the second opening 230 on the second semiconductor layer 22; the upper surface area of ​​the second semiconductor layer 22 refers to the area of ​​the upper surface of the second semiconductor layer 22. The upper surface of the second semiconductor layer 22 refers to the surface of the second semiconductor layer 22 away from the substrate, that is, the surface of the second semiconductor layer 22 in contact with the first protective layer 23.

[0057] The display panel 100 also includes a second stack 50 and a first electrode 61. The second stack 50 is disposed on a side of the first source / drain layer SD1 away from the first stack 40, and the first electrode 61 is disposed on a side of the second stack 50 away from the first source / drain layer SD1. A third via 501 is disposed in the second stack 50 at a location corresponding to the first protective layer 23, and a portion of the third semiconductor layer 24 is located within the third via 501. The first semiconductor layer 21 is an N-type semiconductor layer, the second semiconductor layer 22 is an intrinsic semiconductor layer, and the third semiconductor layer 24 is a P-type semiconductor layer. The third semiconductor layer 24 has high light transmittance.

[0058] The display panel 100 further includes a light shielding layer 70 and a second protective layer 80 disposed on the side of the first electrode 61 away from the second stack 50. The second protective layer 80 is located on the side of the light shielding layer 70 away from the second stack 50. The light shielding layer 70 is used to shield the transistors and signal traces on the display panel 100 from light. The material of the light shielding layer 70 includes a light shielding material such as a black matrix (BM). The second protective layer 80 is used to protect and flatten the display panel 100. The material of the second protective layer 80 includes an inorganic material such as silicon nitride.

[0059] The light shielding layer 70 and the second protective layer 80 are provided with a first opening 802 at a position corresponding to the first electrode 61. The light shielding layer 70 is provided with a second opening 701 at a position corresponding to the third via 501. The second protective layer 80 is also located within the second opening 701 and the third via 501, and is provided with a third opening 801 at a position corresponding to the second via 230. In other words, the second protective layer 80 covers the sidewalls of the light shielding layer 70 forming the second opening 701, the sidewalls of the second stack 50 forming the third via 501, and the upper surface of the first protective layer 23. The third semiconductor layer 24 covers the second opening 701 and the second protective layer 80 within the third via 501.

[0060] Optionally, the display panel 100 further includes a second electrode 62 disposed in the same layer as the first electrode 61. The first electrode 61 and the second electrode 62 are separated by a second protective layer 80 to achieve mutual insulation. The second protective layer 80 and the light shielding layer 70 are further provided with a fifth opening 803 at a position corresponding to the second electrode 62. The first opening 802 and the fifth opening 803 of the light shielding layer 70 are connected.

[0061] The second stack 50 includes a first planarization layer 51, a first passivation layer 52, a second planarization layer 53, and a second passivation layer 54. The first planarization layer 51 is disposed on the first stack 40 and the first source / drain layer SD1, and the first electrode 61 is disposed on the second passivation layer 54. The display panel 100 also includes a second source / drain layer SD2 disposed between the first passivation layer 52 and the second planarization layer 53. The second source / drain layer SD2 is a metal conductive layer. A first auxiliary electrode AE1 and a second auxiliary electrode AE2 are formed on the second source / drain layer SD2. The first auxiliary electrode AE1 is connected between the first transistor T1 and the first electrode 61 to electrically connect the first electrode 61 to the first transistor T1. Specifically, the first electrode 61 is electrically connected to the first drain D1 of the first transistor T1. The second auxiliary electrode AE2 is connected to the second electrode 62.

[0062] The first planarization layer 51 and the second planarization layer 53 are organic planarization layers, and the first passivation layer 52 and the second passivation layer 54 are inorganic insulating layers. The first passivation layer 52 and the second passivation layer 54 are used to protect the first planarization layer 51 and the second planarization layer 53, respectively, to prevent damage to the first planarization layer 51 and the second planarization layer 53 during dry etching. It should be noted that when the second source / drain layer SD2, the first source / drain layer SD1, and the first electrode 61 in this embodiment are made of the same material, for example, a titanium-aluminum-titanium laminate, to avoid side etching, this embodiment can use a dry etching process to etch the second source / drain layer SD2 and the first electrode 61. However, dry etching carries the risk of damaging the organic planarization layers. Therefore, in this embodiment, an inorganic insulating layer is provided on the organic planarization layers as protection to prevent damage to the first planarization layer 51 and the second planarization layer 53 during dry etching.

[0063] In one embodiment, please refer to Figures 1 to 4. Figure 4 is another schematic cross-sectional structure diagram of a display panel 100 provided in an embodiment of the present application. Referring to Figure 4, unlike the above embodiment, the first semiconductor layer 21 is a P-type semiconductor layer, and the third semiconductor layer 24 is an N-type semiconductor layer. The first semiconductor layer 21 and the first active layer AS1 are arranged in the same layer, and the first semiconductor layer 21 and the first active layer AS1 can use the same doping process to save the number of masks and reduce costs. The third semiconductor layer 24 is a transparent electrode layer. The material of the third semiconductor layer 24 includes an N-type semiconductor material such as N+A-Si, ITO, In2O3, and ZnO. When the material of the third semiconductor layer 24 is an N-type semiconductor material such as ZnO, ZnO can be directly grown in the third via 501, thereby eliminating the need for ion doping of the third semiconductor layer 24, further saving the number of masks.

[0064] Furthermore, the second stack 50 includes a first planar layer 51 and a second planar layer 53, which are stacked. The first planar layer 51 is disposed on the first stack 40 and the first source / drain layer SD1, and the first electrode 61 is disposed on the second planar layer 53. The display panel 100 also includes a second source / drain layer SD2 disposed between the first planar layer 51 and the second planar layer 53. A first auxiliary electrode AE1 is formed on the second source / drain layer SD2, and the first auxiliary electrode AE1 is connected between the first transistor T1 and the first electrode 61. The second source / drain layer SD2, the first source / drain layer SD1, and the first electrode 61 are made of different materials. For example, the first source / drain layer SD1 is a titanium-aluminum-titanium stack, the second source / drain layer SD2 is an electroplated copper layer, and the first electrode 61 is a molybdenum-aluminum-molybdenum stack. Since the first source / drain electrode layer SD1 is an electroplated copper layer and does not suffer from side etching, a wet etching process can be used to etch the first source / drain electrode layer SD1 in this embodiment. Furthermore, the wet etching process does not damage the organic planarization layer, eliminating the need for an inorganic insulating layer on the organic planarization layer. This further reduces the number of photomasks and reduces costs. For other details, please refer to the above embodiment and will not be repeated here.

[0065] In one embodiment, please refer to Figures 1 to 5. Figure 5 is another schematic cross-sectional structure diagram of the display panel 100 provided in the embodiment of the present application. Referring to Figure 5, different from the above embodiment, the display panel 100 also includes a reflective layer 90, and the reflective layer 90 is located in the third via hole 501, and a fourth opening is provided at a position corresponding to the second via hole 230, and the third semiconductor layer 24 covers the reflective layer 90 in the third via hole 501. Optionally, the material of the reflective layer 90 includes a metal material with reflective properties. In this embodiment, by providing the reflective layer 90 in the third via hole 501, the reflective layer 90 can reflect light onto the light sensor 20, thereby improving the light absorption efficiency of the light sensor 20, and thereby improving the sensitivity of the light sensor 20. For other descriptions, please refer to the above embodiment, which will not be repeated here.

[0066] In one embodiment, referring to Figures 1 to 7, Figure 6 is another schematic cross-sectional view of the display panel 100 provided in an embodiment of the present application, and Figure 7 is another schematic circuit diagram of the temperature sensor 30 provided in an embodiment of the present application. Referring to Figure 6, unlike the above embodiment, each sub-pixel SP further includes at least one second transistor T2 connected to the first transistor T1, wherein the first transistor T1 is a polysilicon transistor, and the second transistor T2 is an oxide transistor. Accordingly, the temperature sensor 30 includes a third transistor T3 and a fourth transistor T4 connected to the third transistor T3, wherein the third transistor T3 is disposed on the same layer as the first transistor T1, and the fourth transistor T4 is disposed on the same layer as the second transistor T2.

[0067] Specifically, the first transistor T1 includes a first active layer AS1, a first gate G11, a second gate G21, a first source S1, and a first drain D1. Correspondingly, the third transistor T3 includes a third active layer AS3, a third gate G12, a fourth gate G23, a third source S3, and a third drain D3. The second transistor T2 includes a fifth gate G22, a second active layer AS2, a sixth gate G31, a second source S2, and a second drain D2. Correspondingly, the fourth transistor T4 includes a seventh gate G24, a fourth active layer AS4, an eighth gate G32, a fourth source S4, and a fourth drain D4. The first gate G11 and the third gate G12 are formed by the first gate layer GL1; the second gate G21, the fourth gate G23, the fifth gate G22, and the seventh gate G24 are formed by the second gate layer GL2; and the sixth gate G31 and the eighth gate G32 are formed by the third gate layer GL3. The first active layer AS1 and the third active layer AS3 are both made of polycrystalline silicon, such as low-temperature polysilicon (LTPS). The second active layer AS2 and the fourth active layer AS4 are both made of metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO). By combining LTPS with IGZO to fabricate transistors, a low-temperature polycrystalline oxide (LTPO) architecture can be formed, enabling high- and low-frequency switching. This allows the temperature sensor 30 to include fewer transistors, reducing its footprint. For example, as shown in FIG7 , the temperature sensor 30 of this embodiment includes two transistors (T3 and FIG4 ). Compared to the temperature sensor 30 shown in FIG3 , which includes four transistors and one capacitor, the temperature sensor 30 of this embodiment has fewer transistors, thereby reducing its footprint.

[0068] Optionally, the second semiconductor layer 22 includes a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). By using IGZO to form the second semiconductor layer 22, the concentration of photogenerated carriers excited by IGZO is correspondingly increased, and the light sensitivity is enhanced, because IGZO itself has a higher light absorption coefficient than amorphous silicon.

[0069] In addition, different from the above embodiment, the first stack 40 includes a first gate insulating layer 41, a second gate insulating layer 42, a second interlayer insulating layer 44, a third gate insulating layer 45, and a first interlayer insulating layer 43. For other descriptions, please refer to the above embodiment and will not be repeated here.

[0070] Based on the same inventive concept, an embodiment of the present application also provides a display module. Please refer to Figures 1 to 9. Figure 8 is a schematic diagram of a planar structure of the display module provided in an embodiment of the present application, and Figure 9 is a schematic diagram of a partial cross-sectional structure of the display module provided in an embodiment of the present application. Referring to Figure 8, the display module 1000 includes a light-emitting device and a display panel 100 according to one of the above embodiments. The light-emitting device 200 is arranged on the display panel 100, and each light-emitting device 200 corresponds to a sub-pixel SP on the display panel 100, so that the light-emitting devices 200 are arranged in an array on the display panel 100. The display module also includes a chip-on-film (COF) and / or a flexible circuit board (FPC) and a controller MT. The chip-on-film (COF) and / or the flexible circuit board (FPC) are bound to the display panel 100, wherein a first driver chip IC1 is provided on the chip-on-film (COF), and a second driver chip IC2 is provided on the flexible circuit board (FPC).

[0071] Specifically, referring to FIG9 , the light-emitting device 200 is attached to the display panel 100. The light-emitting device 200 includes an insulated cathode 201 and an anode 202. The cathode 201 is electrically connected to the first electrode 61 on the display panel 100, and the anode 202 is electrically connected to the second electrode 62 of the display panel 100, thereby achieving electrical connection between the light-emitting device 200 and the display panel 100. The display panel 100 is configured to provide a driving signal to the light-emitting device 200 to cause the light-emitting device 200 to emit light. Optionally, the light-emitting device 200 includes a micro-light-emitting diode (Micro-LED) chip, a sub-millimeter light-emitting diode (Mini-LED) chip, or a light-emitting diode (LED) chip.

[0072] Correspondingly, the display module 1000 includes an LED display module, a Micro LED display module, or a Mini LED display module.

[0073] Exemplarily, the display module 1000 is applied to a display device, which may be a television, a mobile phone, a tablet computer, a computer monitor, a gaming device, a digital camera, a car navigation system, an electronic billboard, an ATM, a wearable device, or other electronic device with a display function, wherein the wearable device may be a display device such as a smart bracelet, smart glasses, a smart watch, or smart decoration.

[0074] According to the above embodiments, it can be seen that:

[0075] The present application provides a display panel and a display module, wherein the display panel includes a display area and a binding area located on one side of the display area, the binding area includes a terminal area and virtual terminal areas located on opposite sides of the terminal area; the display panel also includes a substrate and a plurality of sub-pixels and at least one light sensor arranged on the substrate, the plurality of sub-pixels are located within the display area, and each of the sub-pixels includes at least one first transistor; the light sensor is located within the virtual terminal area, and part of the film layer of the light sensor is arranged on the same layer as part of the film layer of the first transistor; the present application integrates the light sensor in the virtual terminal area of ​​the display panel, thereby allowing a smaller light sensor to be set without occupying additional space on the display panel, thereby improving the technical problem that the existing external light sensor is not conducive to improving the screen-to-body ratio of the display.

[0076] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0077] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel comprising a display area and a binding area located on one side of the display area, wherein the binding area comprises a terminal area and virtual terminal areas located on opposite sides of the terminal area; the display panel further comprising: substrate; A plurality of sub-pixels are arranged in an array on the substrate and located within the display area, each of the sub-pixels comprising at least one first transistor; as well as At least one light sensor is located within the virtual terminal area, and a portion of the film layer of the light sensor is provided on the same layer as a portion of the film layer of the first transistor.

2. The display panel according to claim 1, wherein The first transistor includes a first active layer disposed on the substrate, and the display panel further includes a first stacked layer and a first source and drain layer disposed on a side of the first active layer away from the substrate; The light sensor includes a first semiconductor layer, a second semiconductor layer, and a first protective layer that are stacked, the first semiconductor layer and the first active layer being arranged in the same layer, and a first via hole being provided in the first stack at a position corresponding to the first semiconductor layer; The second semiconductor layer is filled in the first via hole and contacts the first semiconductor layer, and the first protection layer covers a side of the second semiconductor layer away from the first semiconductor layer.

3. The display panel according to claim 2, wherein: The light sensor further includes a third semiconductor layer disposed on a side of the first protective layer away from the second semiconductor layer. The first protective layer is provided with a second via hole at a position corresponding to the second semiconductor layer. The third semiconductor layer is connected to the second semiconductor layer through the second via hole.

4. The display panel according to claim 3, wherein: The display panel also includes a second stack and a first electrode, the second stack is arranged on the side of the first source and drain layer away from the first stack, and the first electrode is arranged on the side of the second stack away from the first source and drain layer; the second stack is provided with a third via at a position corresponding to the first protective layer, and part of the third semiconductor layer is located in the third via.

5. The display panel according to claim 4, wherein: The display panel further includes a light shielding layer and a second protective layer provided on a side of the first electrode away from the second stack, the second protective layer being located on a side of the light shielding layer away from the second stack, the light shielding layer and the second protective layer being provided with a first opening at a position corresponding to the first electrode, and the light shielding layer being provided with a second opening at a position corresponding to the third via hole; The second protective layer is also located in the second opening and the third via hole, and a third opening is provided at a position corresponding to the second via hole. The third semiconductor layer covers the second protective layer in the second opening and the third via hole. The display panel according to claim 4 , wherein: The display panel further includes a reflective layer located in the third via hole and having a fourth opening at a position corresponding to the second via hole, and the third semiconductor layer covers the reflective layer in the third via hole.

7. The display panel according to claim 4, wherein: The second stack includes a first planar layer, a first passivation layer, a second planar layer, and a second passivation layer, the first planar layer being disposed on the first stack and the first source / drain layer, and the first electrode being disposed on the second passivation layer; The display panel further includes a second source-drain layer disposed between the first passivation layer and the second planar layer, wherein a first auxiliary electrode is formed on the second source-drain layer, and the first auxiliary electrode is connected between the first transistor and the first electrode; The first stack includes a first gate insulating layer, a second gate insulating layer and a first interlayer insulating layer that are stacked together, the first gate insulating layer is arranged on the first active layer and the first semiconductor layer, and the first source and drain layer is arranged on the first interlayer insulating layer; the display panel also includes a first gate layer and a second gate layer, the first gate layer is located between the first gate insulating layer and the second gate insulating layer, and the second gate is located between the second gate insulating layer and the first interlayer insulating layer.

8. The display panel according to claim 4, wherein: The second stack includes a first planar layer and a second planar layer stacked together, the first planar layer is disposed on the first stack and the first source / drain layer, and the first electrode is disposed on the second planar layer; The display panel further includes a second source-drain layer disposed between the first planar layer and the second planar layer, wherein the second source-drain layer is formed with a first auxiliary electrode, and the first auxiliary electrode is connected between the first transistor and the first electrode; The first stack includes a first gate insulating layer, a second gate insulating layer, and a first interlayer insulating layer, the first gate insulating layer being disposed on the first active layer and the first semiconductor layer, and the first source and drain layer being disposed on the first interlayer insulating layer; The display panel further includes a first gate layer and a second gate layer. The first gate layer is located between the first gate insulating layer and the second gate insulating layer. The second gate is located between the second gate insulating layer and the first interlayer insulating layer.

9. The display panel according to claim 2, wherein: The display panel further includes a plurality of temperature sensors located within the display area, wherein a portion of the temperature sensors is provided on the same layer as a portion of the first transistor, and an arrangement density of the temperature sensors close to the binding area is greater than an arrangement density of the temperature sensors far from the binding area; There is a gap between two adjacent sub-pixels, and the temperature sensor is disposed in at least a portion of the gap.

10. The display panel according to claim 9, wherein: Each of the sub-pixels further includes at least one second transistor connected to the first transistor, the first transistor is a polysilicon transistor, and the second transistor is an oxide transistor; a material of the second semiconductor layer includes a metal oxide semiconductor material.

11. The display panel according to claim 10, wherein: The temperature sensor includes a third transistor and a fourth transistor connected to the third transistor. The third transistor is provided in the same layer as the first transistor, and the fourth transistor is provided in the same layer as the second transistor.

12. A display module comprising a light-emitting device and a display panel, wherein the light-emitting device is disposed on the display panel, the display panel comprising a display area and a binding area located on one side of the display area, the binding area comprising a terminal area and virtual terminal areas located on opposite sides of the terminal area; the display panel further comprising: substrate; A plurality of sub-pixels are arranged in an array on the substrate and located within the display area, each of the sub-pixels comprising at least one first transistor; as well as At least one light sensor is located within the virtual terminal area, and a portion of the film layer of the light sensor is provided on the same layer as a portion of the film layer of the first transistor; Each of the light-emitting devices corresponds to one of the sub-pixels on the display panel.

13. The display module according to claim 12, wherein: The first transistor includes a first active layer disposed on the substrate, and the display panel further includes a first stacked layer and a first source and drain layer disposed on a side of the first active layer away from the substrate; The light sensor includes a first semiconductor layer, a second semiconductor layer, and a first protective layer that are stacked, the first semiconductor layer and the first active layer being arranged in the same layer, and a first via hole being provided in the first stack at a position corresponding to the first semiconductor layer; The second semiconductor layer is filled in the first via hole and contacts the first semiconductor layer, and the first protection layer covers a side of the second semiconductor layer away from the first semiconductor layer.

14. The display module according to claim 13, wherein: The light sensor further includes a third semiconductor layer disposed on a side of the first protective layer away from the second semiconductor layer. The first protective layer is provided with a second via hole at a position corresponding to the second semiconductor layer. The third semiconductor layer is connected to the second semiconductor layer through the second via hole.

15. The display module according to claim 14, wherein: The display panel also includes a second stack and a first electrode, the second stack is arranged on the side of the first source and drain layer away from the first stack, and the first electrode is arranged on the side of the second stack away from the first source and drain layer; the second stack is provided with a third via at a position corresponding to the first protective layer, and part of the third semiconductor layer is located in the third via.

16. The display module according to claim 15, wherein: The display panel further includes a light shielding layer and a second protective layer provided on a side of the first electrode away from the second stack, the second protective layer being located on a side of the light shielding layer away from the second stack, the light shielding layer and the second protective layer being provided with a first opening at a position corresponding to the first electrode, and the light shielding layer being provided with a second opening at a position corresponding to the third via hole; The second protective layer is also located in the second opening and the third via hole, and a third opening is provided at a position corresponding to the second via hole. The third semiconductor layer covers the second protective layer in the second opening and the third via hole.

17. The display module according to claim 15, wherein: The display panel further includes a reflective layer located in the third via hole and having a fourth opening at a position corresponding to the second via hole, and the third semiconductor layer covers the reflective layer in the third via hole.

18. The display module according to claim 15, wherein: The second stack includes a first planar layer, a first passivation layer, a second planar layer, and a second passivation layer, the first planar layer being disposed on the first stack and the first source / drain layer, and the first electrode being disposed on the second passivation layer; The display panel further includes a second source-drain layer disposed between the first passivation layer and the second planar layer, wherein a first auxiliary electrode is formed on the second source-drain layer, and the first auxiliary electrode is connected between the first transistor and the first electrode; The first stack includes a first gate insulating layer, a second gate insulating layer and a first interlayer insulating layer that are stacked together, the first gate insulating layer is arranged on the first active layer and the first semiconductor layer, and the first source and drain layer is arranged on the first interlayer insulating layer; the display panel also includes a first gate layer and a second gate layer, the first gate layer is located between the first gate insulating layer and the second gate insulating layer, and the second gate is located between the second gate insulating layer and the first interlayer insulating layer.

19. The display module according to claim 15, wherein: The second stack includes a first planar layer and a second planar layer stacked together, the first planar layer is disposed on the first stack and the first source / drain layer, and the first electrode is disposed on the second planar layer; The display panel further includes a second source-drain layer disposed between the first planar layer and the second planar layer, wherein the second source-drain layer is formed with a first auxiliary electrode, and the first auxiliary electrode is connected between the first transistor and the first electrode; The first stack includes a first gate insulating layer, a second gate insulating layer, and a first interlayer insulating layer, the first gate insulating layer being disposed on the first active layer and the first semiconductor layer, and the first source and drain layer being disposed on the first interlayer insulating layer; The display panel further includes a first gate layer and a second gate layer. The first gate layer is located between the first gate insulating layer and the second gate insulating layer. The second gate is located between the second gate insulating layer and the first interlayer insulating layer.

20. The display module according to claim 13, wherein: The display panel further includes a plurality of temperature sensors located within the display area, wherein a portion of the temperature sensors is provided on the same layer as a portion of the first transistor, and an arrangement density of the temperature sensors close to the binding area is greater than an arrangement density of the temperature sensors far from the binding area; There is a gap between two adjacent sub-pixels, and the temperature sensor is disposed in at least a portion of the gap.

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