Signal transmission structure, server, and signal transmission method

Abstract

Embodiments of the present application provide a signal transmission structure, a server, and a signal transmission method. The signal transmission structure comprises: a first component and a second component, wherein the first component comprises a group of first connectors, a processing component and a group of storage connectors, the second component comprises a group of second connectors, the first connectors and the second connectors are non-fixedly connected by means of cables, and the processing component is configured to determine, on the basis of preset correspondence between the second connectors and the storage connectors, the storage connector matched with a second target connector connected to a first target connector on the first component; and under the condition that a first storage connector matched with the second target connector exists on the first component, a first signal to be transmitted received by means of the first target connector is transmitted to the first storage connector, so that said first signal is transmitted, by means of the first storage connector, to a storage component connected to the first storage connector.

Description

Signal transmission structure, server and signal transmission method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 31, 2024, with application number 202410134843.4 and application name “Signal Transmission Structure, Server and Signal Transmission Method”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and specifically, to a signal transmission structure, a server, and a signal transmission method. Background Art

[0004] At present, due to the demand for high-density storage devices, the signal transmission structure needs to support multiple storage components at the front / middle / rear of the chassis, such as SSDs (Solid State Drives). The device system architecture design in related technologies usually connects the storage component on the first component of the device and the control component on the second component of the device through a cable, so that the control component can transmit signals with the storage component, for example, access data stored on the storage component, perform read or write operations, etc.

[0005] To ensure the correct connection between the control component and the storage component, it is usually necessary to add small labels to both ends of each cable to mark the interconnected connector position number. However, for high-density storage, the connectors on the control component and storage component ends of the device are densely packed, making it difficult to distinguish the different connector pins, and the probability of misplugging is very high.

[0006] It can be seen that the signal transmission structure in the related art has the problem of low accuracy of signal transmission due to low accuracy of cable connection.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a signal transmission structure, a server, and a signal transmission method to at least solve the problem of low signal transmission accuracy caused by low cable connection accuracy in the signal transmission structure in the related art.

[0009] According to one embodiment of the present application, a signal transmission structure is provided, comprising: a first component and a second component, the first component comprising a group of first connectors configured to connect to the second component and a group of storage connectors configured to connect to the storage component, the second component comprising a group of second connectors configured to connect to the first component, the first connector on the first component and the second connector on the second component being non-fixedly connected via a cable, wherein the first component further comprises: a processing component configured to determine, based on a preset correspondence between the second connector and the storage connector, a storage connector on the first component that matches the second target connector connected to the first target connector, wherein the first target connector is one connector in a group of first connectors, and the second target connector is one connector in a group of second connectors; in a case where there is a first storage connector on the first component that matches the second target connector, the first signal to be transmitted received through the first target connector is transmitted to the first storage connector, so as to transmit the first signal to be transmitted through the first storage connector to the storage component connected to the first storage connector.

[0010] According to another embodiment of the present application, a server is also provided, comprising any one of the above-mentioned signal transmission structures.

[0011] According to another embodiment of the present application, a signal transmission method is also provided, which is an electronic device that should be configured to include a first component and a second component, the first component including a group of first connectors configured to connect to the second component, a group of storage connectors configured to connect to the storage component, and a processing component, the second component including a group of second connectors configured to connect to the group of first components, and the first connectors on a group of first components and the second connectors on the second component are non-fixedly connected through cables; the method includes: based on a preset correspondence between the second connector and the storage connector, determining, by the processing component, a storage connector on the first component that matches the second target connector connected to the first target connector, wherein the first target connector is one connector in a group of first connectors, and the second target connector is one connector in a group of second connectors; in a case where there is a first storage connector on the first component that matches the second target connector, the processing component transmits a first signal to be transmitted received through the first target connector to the first storage connector, so as to transmit the first signal to be transmitted to the storage component connected to the first storage connector through the first storage connector.

[0012] According to another embodiment of the present application, a computer non-volatile readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0013] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0014] Through the present application, a new processing component is added to the first component, and the processing component determines the first storage connector corresponding to the second target connector that is non-fixedly connected to the current first target connector through a cable based on the preset correspondence between the second connector and the storage connector. Since the signal transmission from the second connector to the hard disk connector does not rely solely on the non-fixed connection relationship formed by the second connector on the second component and the first connector on the first component through the cable, a new processing component is added to the first component. When the processing component on the first component determines the second target connector connected to the first target connector on the first component, the first storage connector is determined based on the correspondence between the second connector and the storage connector, and the first signal to be transmitted received by the first target connector is transmitted to the first storage connector, so that the first signal to be transmitted is transmitted to the storage component connected to the first storage connector through the first storage connector, thereby realizing accurate signal transmission, solving the problem of low signal transmission accuracy in the signal transmission structure in the related art, and achieving the technical effect of improving the accuracy of signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic diagram of a signal transmission structure according to an embodiment of the present application.

[0016] FIG2 is a schematic diagram of a signal transmission structure according to the related art.

[0017] FIG3 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0018] FIG4 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0019] FIG5 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0020] FIG6 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0021] FIG7 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0022] FIG8 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0023] FIG9 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0024] FIG10 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0025] FIG11 is a schematic diagram of another signal transmission structure according to an embodiment of the present application.

[0026] FIG12 is a schematic diagram of a hardware environment of a server according to an embodiment of the present application.

[0027] FIG13 is a flow chart of a signal transmission method according to an embodiment of the present application.

[0028] FIG14 is a flow chart of another signal transmission method according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] It should be noted that the terms "target", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0031] In this embodiment, a signal transmission structure is provided. FIG1 is a schematic diagram of a signal transmission structure according to an embodiment of the present application. As shown in FIG1 , the signal transmission structure includes:

[0032] A first component and a second component, the first component includes a group of first connectors configured to connect to the second component and a group of storage connectors configured to connect to the storage component, the second component includes a group of second connectors configured to connect to the first component, the first connectors on the first component and the second connectors on the second component are non-fixedly connected via a cable, wherein:

[0033] The first component also includes:

[0034] A processing component is configured to determine a storage connector on the first component that matches the second target connector connected to the first target connector based on a preset correspondence between the second connector and the storage connector, wherein the first target connector is one connector in a group of first connectors and the second target connector is one connector in a group of second connectors; and when there is a first storage connector on the first component that matches the second target connector, the first signal to be transmitted received through the first target connector is transmitted to the first storage connector, so as to transmit the first signal to be transmitted through the first storage connector to the storage component connected to the first storage connector.

[0035] Optionally, the control component can be connected to a set of second connectors on the second component, wherein the control component can be configured to send a signal to be transmitted to the first component, the signal to be transmitted can include a first signal to be transmitted, the control component can be a CPU (Central Processing Unit), etc., and the control component can be located on the second component.

[0036] Currently, signal transmission structures in related technologies generally connect a first component and a second component via a cable. For example, a storage component on the first component and a control component on the second component are connected. For example, Patent 1, [CN114661546A] "Server Cable Detection System and Communication Method Thereof" as shown in FIG2, obtains whether the high-speed connector on the backplane is in a connected state and displays it by lighting an LED (Light-Emitting Diode), thereby obtaining information on whether the cable is incorrectly plugged in without repeated plugging and unplugging verification. The processor (usually referring to the CPU) establishes a communication link with the hard disk (storage component) through the connecting cable. During detection, the BMC (Baseboard Management Controller) controller modifies the hard disk status information of the CPLD (Complex Programmable Logic Device) to trigger the processor to send a lighting information to the corresponding hard disk. The correctness of the cable connection is determined based on the lighting status of the hard disk. When the connecting cable is correctly connected, the CPLD can light up the corresponding hard disk. When the connecting cable is not correctly connected, the corresponding hard disk is not lit.

[0037] In summary, when there are multiple storage components on the signal transmission structure, since the difference between the cables configured to connect a group of storage components on the first component and a group of control components on the second component is small, the probability of misinsertion is high when non-fixed connection is performed based on the cable. The signal transmission structure in the related art has the problem of low signal transmission accuracy due to the low accuracy of cable connection.

[0038] In order to at least partially solve the above technical problems, in this embodiment, on the basis of the non-fixed connection between the first component and the second component via a cable, a processing component is added to the first component. The processing component connected to the group of first connectors on the first component determines a second target connector in a group of second connectors that is connected to the first target connector in the group of first connectors via a cable. That is, the processing component on the first component determines the current second connector (second target connector) on the second component side that is connected to the current first connector (first target connector) on the first component side via a cable. Optionally, the processing component may store a preset correspondence between the second connector and the storage connector, or the processing component may obtain the preset correspondence between the second connector and the storage connector stored on the corresponding specified storage component. Alternatively, the processing component may obtain the preset correspondence between the second connector and the storage connector in other ways. This embodiment is not limited to this. The preset correspondence may be a correct connection relationship between the second connector and the storage connector. For example, in this embodiment, the preset correspondence between the second connector and the storage connector may correspond to a correct correspondence between the CPU position and the hard disk drive sequence.

[0039] Here, the cables can include high-speed signal cables, low-speed management cables, and power cables. Low-speed management cables and power cables can be shared across multiple cables, and the selection of connectors for the same type of cables can be varied, simplifying the connection relationship and preventing mis-insertion during assembly. High-speed connectors typically use standard specifications, such as x8 / x16, and have a consistent connector form factor. In at least some embodiments of this application, the cable connecting the first component and the second component is illustrated as a high-speed signal cable.

[0040] In the case where the processing component determines a second target connector that is non-fixedly connected to the first target connector via a cable, the processing component can determine a storage connector on the first component that matches the second target connector connected to the first target connector based on a preset correspondence between the second connector and the storage connector, the first target connector being one connector in a group of first connectors, and the second target connector being one connector in a group of second connectors. Optionally, the preset correspondence between the second connector and the storage connector can be a correspondence between identification information of a group of second connectors and a group of storage connectors. Based on the preset correspondence, the processing component can determine the identification information of the storage connector that matches the second target connector, wherein the identification information of the storage connector can be used to determine the corresponding storage connector. The identification information can be address information, serial number, etc., which is not limited in this embodiment.

[0041] In the case that there is a first storage connector on the first component that matches the second target connector, the first signal to be transmitted received by the first target connector is transmitted to the first storage connector, so that the first signal to be transmitted is transmitted to the storage component connected to the first storage connector through the first storage connector, thereby achieving the transmission of the signal received by the second target connector on the second component to the correct and corresponding storage component.

[0042] Through this embodiment, by adding a processing component connected to the first connector on the first component of the signal transmission structure, the processing component determines the first storage connector corresponding to the second target connector connected to the first target connector on the first component through a cable based on the preset correspondence between the second connector and the storage connector, thereby realizing signal transmission from the second target connector to the first target connector, then to the first storage connector, and then to the storage component, thereby ensuring the accuracy of signal transmission.

[0043] In an exemplary embodiment, the second component further includes a group of processors, wherein each processor in the group of processors corresponds to at least some of the second connectors in the group of second connectors, and the signals to be transmitted received by the first component through the group of first connectors are transmitted to the first component by the group of processors via the group of second connectors.

[0044] The signal to be transmitted can be transmitted from a group of processors on the second component to the first component via a group of second connectors. The signal to be transmitted can include a first signal to be transmitted. Optionally, the signal to be transmitted can include signals of types such as reading data, writing data, erasing data, and searching for data at a specific location.

[0045] For example, as shown in FIG3 , each processor in a group of processors may correspond to at least some of the second connectors in a group of second connectors. Optionally, the processor and the second connector may be fixedly connected via on-board PCB (Printed Circuit Board) wiring.

[0046] According to this embodiment, the processor on the second component transmits the signal to be transmitted to the first connector on the first component via the second connector, so that the signal to be transmitted sent by the processor can be transmitted to the first component.

[0047] In an exemplary embodiment, there are multiple first components, the second connector corresponding to each processor is connected to the first connector on at least one first component through a cable, and the first connector on each first component is connected to the second connector corresponding to at least one processor in a group of processors through a cable.

[0048] The number of first components that are non-fixedly connected to the second component through a cable can be one or more, the second connector corresponding to each processor is connected to the first connector on at least one first component through a cable, and the first connector on each first component is connected to the second connector corresponding to at least one processor in a group of processors through a cable.

[0049] For example, as shown in FIG4 , two first components and one second component may be non-fixedly connected via a cable. Optionally, the processor on the second component and the second connector may be fixedly connected via PCB routing, and the second connector and the first connector may be non-fixedly connected via a cable.

[0050] In an exemplary embodiment, the processing component is further configured to obtain a connector identifier of a second target connector transmitted by a second target connector and received by the first target connector, wherein the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector via a cable is the second target connector.

[0051] In order to improve the efficiency of information acquisition, in this embodiment, for the second component, the connector identifier of the second target connector can be transmitted to the first target connector through the second target connector. Here, the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector through a cable is the second target connector. Similar to the aforementioned embodiment, the connector identifier can be a number, letter, symbol or combination to identify the connector serial number, connector address information, etc., which is not limited in this embodiment.

[0052] For the first component, the first target connector connected to the second target connector through a cable can receive the connector identifier of the second target connector transmitted by the second target connector, and pass the connector identifier of the second target connector to the processing component. Optionally, the processing component can determine the corresponding second target connector by parsing the obtained connector identifier, and then determine the corresponding first storage connector.

[0053] For example, in this embodiment, each connector at the second component end is connected to the first component end through a cable, and the connector at the first component end can transmit signals to the processing component through fixed traces on the PCB board, so that the processing component can obtain the connector identifier of the second target connector transmitted by the second target connector at the second component end.

[0054] Through this embodiment, the processing component determines the second target connector connected to the first target connector on the first component through the connector identifier transmitted from the second component, which can improve the accuracy of determining the second target connector and ensure the reliability of acquired data.

[0055] In an exemplary embodiment, the processing component is further configured to use the connector identifier of the second target connector to poll the connector identifier of the second connector corresponding to the connector identifier of each storage connector on the first component until a storage connector whose connector identifier corresponds to the second connector is the connector identifier of the second target connector, wherein the preset correspondence is the correspondence between the connector identifier of the second connector and the connector identifier of the storage connector.

[0056] In order to improve the matching efficiency and accuracy between the second connector and the storage connector, in this embodiment, the correct correspondence between the connector identifier of the second connector and the connector identifier of the storage connector can be preset. When the processing component obtains the connector identifier of the second target connector, the processing component can, based on the preset correspondence, search and determine by polling whether there is a storage connector on the first component whose connector identifier of the second connector corresponding to the connector identifier of the storage connector is the connector identifier of the second target connector. Here, polling can refer to the operation of accessing or querying a group of data in sequence according to a certain order or rule. The form of the connector identifier of the storage connector and the connector identifier of the second connector can be similar to that in the aforementioned embodiment and will not be repeated here.

[0057] In an exemplary embodiment, a field replaceable component is mounted on each second connector in the set of second connectors, and a connector identification of each second connector is stored in the field replaceable component mounted on each second connector;

[0058] The second component is configured to transmit the connector identification of the second target connector stored in the field replaceable component mounted on the second target connector to the first target connector.

[0059] For the second component, each second connector in a group of second connectors on the second component is mounted with a field replaceable component, and the field replaceable component mounted on each second connector stores the connector identifier of each second connector. Through the second component, the connector identifier of the second target connector stored in the field replaceable component mounted on the second target connector can be transferred to the first target connector.

[0060] For the first component, the connector identifier of the second target connector can be received by the first target connector on the first component, which is connected to the second target connector via a cable, and passed to the first input pin of the logic device connected to the first target connector, so that the logic component can parse the connector identifier of the second target connector.

[0061] For example, in this embodiment, a FRU (Field Replace Unit) can be mounted on a group of second connectors (CON1AˉCON1N, ..., CONnAˉCONnN) on the second component, and the connector identifier of the corresponding second connector can be set and written in the FRU.

[0062] According to this embodiment, the field replaceable component mounted on the second connector stores the connector identifier of the corresponding second connector and transmits it to the logic device for parsing, thereby improving data reliability and ensuring accuracy of signal transmission.

[0063] In an exemplary embodiment, the processing component is a logic device including input pins and output pins, wherein each first connector on the first component is connected to an input pin of the logic device, and each storage connector on the first component is connected to an output pin of the logic device;

[0064] A logic device is configured to obtain a connector identifier of a second target connector transmitted by a first input pin, wherein the first input pin is an input pin on the logic device corresponding to the first target connector; and before transmitting a first signal to be transmitted to the first storage connector, control an output pin on the logic device corresponding to the first storage connector to be turned on.

[0065] For the first component, the processing component on the first component can be a logic device including input pins, each first connector on the first component can be connected to an input pin of the logic device, the number of input pins of the logic device can be greater than or equal to the number of first connectors, optionally, the input pins of the logic device and the first connector can be fixedly connected via PCB traces, when the first target connector on the first component receives the connector identifier of the second target connector transmitted by the second component, the logic device can obtain the connector identifier of the second target connector transmitted by the first input pin, and the first input pin is the input pin on the logic device corresponding to the first target connector.

[0066] For example, in this embodiment, the logic device may include a group of input pins fixedly connected to a group of first connectors (CON1A'ˉCON1N', ..., CONnA'ˉCONnN'), and the logic device can obtain the connector identifier of the second connector (CON1AˉCON1N, ..., CONnAˉCONnN) transmitted by the input pins 1A'Ad, ..., nN'Ad.

[0067] Corresponding to the input pins of the logic device, the logic device may further include output pins. Each storage connector on the first component is connected to an output pin of the logic device. The number of output pins may be equal to the number of storage connectors.

[0068] When the logic device determines the first storage connector corresponding to the second target connector, since the first storage connector is fixedly connected to an output pin of the logic device, before the first signal to be transmitted is transmitted to the first storage connector, the output pin corresponding to the first storage connector on the logic device can be controlled to be conductive, thereby achieving the internal signal of the logic device being conductive from the first input pin corresponding to the first target connector to the output pin corresponding to the first storage connector. Here, the first storage connector may include one or more storage connectors, which is not limited in this embodiment. Similar to the aforementioned embodiment, controlling the output pin corresponding to the first storage connector on the logic device to be conductive can be achieved by a logic switch within the logic device.

[0069] For example, in this embodiment, taking the case where the first storage connector corresponding to a second target connector includes two storage connectors and the logic device is an FPGA, the address signal stored in the FRU is transmitted to the FPGA through the first target connector at the first component end. After parsing, the address input to the 1A'Ad pin of the FPGA is the address of the second component end CON1A, and the address input to the 1B'Ad pin is the address of the second component end CON1B. Therefore, 1A' inside the FPGA is connected to SSD1A'1 / SSD1A'2, and 1B' is connected to SSD1B'1 / SSD1B'2.

[0070] In one exemplary embodiment, the logic device includes a logic switch;

[0071] The logic device is further configured to control the output pin corresponding to the first storage connector on the logic device to be turned on through a logic switch.

[0072] By configuring the logic switch inside the logic device, the connection status between the input pin and the output pin of the logic device can be controlled. For the first component, when the first storage connector corresponding to the second target connector is determined, the logic device can control the output pin corresponding to the first storage connector on the logic device through the logic switch to be turned on. Here, the storage connector and the output pin of the logic device can be fixedly connected through PCB routing. By controlling the logic switch inside the logic device, the first input pin fixedly connected to the first target connector and the output pin fixedly connected to the first storage connector on the logic device can be controlled to be turned on.

[0073] Through this embodiment, signal transmission from the control component to the storage component can be achieved by the second target connector and the first target connector connected by a cable, the first target connector and the first input pin of the logic device fixedly connected by PCB traces, and the output pin of the logic device and the first storage connector fixedly connected by PCB traces, thereby ensuring the accuracy of signal transmission.

[0074] In an exemplary embodiment, the processing component is a programmable controller, and the connector identification of each second connector on the second component is connector address information of each second connector.

[0075] The processing component can be a programmable controller. For example, in this embodiment, the programmable controller can be an FPGA (Field Programmable Gate Array). When the connector identifier of each second connector on the second component is the connector address information of each second connector, the FPGA can parse the address information composed of address bits.

[0076] Optionally, in this embodiment, the address bit can be set through 0 / 1 binary, the address reserved byte can be determined according to the number of second connectors extended on the second component end, and the address information of the received second target connector can be parsed through the FPGA. For example, when the address bit of the FRU mounted on the second connector on the second component end is set to five bits, it can support distinguishing 32 connector addresses.

[0077] In an exemplary embodiment, the signal transmission structure further includes: an integrated circuit bus and a high-speed peripheral component interconnect bus configured to connect the first component and the second component, wherein the connector identifier of the second target connector is transmitted via the integrated circuit bus, and the first signal to be transmitted is transmitted via the high-speed peripheral component interconnect bus.

[0078] For example, each second connector at the second component end can lead out an I2C (Inter-Integrated Circuit) bus configured to transmit the address information of the second connector, and a set of PCIe (Peripheral Component Interconnect Express) bus configured to transmit the first signal to be transmitted. Optionally, the first signal to be transmitted can be a high-speed signal from the second component end, and so on.

[0079] In an exemplary embodiment, the bandwidth of each first connector on the first component and the bandwidth of each second connector on the second component are the same and are both N times the bandwidth of each storage connector on the first component, where N is a positive integer greater than or equal to 2;

[0080] The processing component is also configured to transmit the first signal to be transmitted received through the first target connector to the corresponding storage connector in the storage connector group when there is a storage connector group that matches the second target connector on the first component, wherein the first storage connector includes N storage connectors in the storage connector group.

[0081] For example, in this embodiment, if the first component end and the second component end connectors both have an x8 bandwidth and the storage connector has an x4 bandwidth, then the first storage connector includes two storage connectors in the storage connector group, that is, N is 2, and one second connector corresponds to two storage connectors, forming a correct interconnection relationship from the second component end CONnN to the first component end CONnN' and then to the hard disk connector SSDnN1 / SSDnN2. Optionally, when the bandwidth of the first connector, the bandwidth of the second connector, and the bandwidth of the storage connector are all the same, N can be 1.

[0082] In an exemplary embodiment, the first component is a backplane, the second component is a motherboard, the first connector on the backplane is a motherboard connector configured to connect to the motherboard, the storage connector on the backplane is a hard disk connector configured to connect to a hard disk, and the second connector on the motherboard is a backplane connector configured to connect to the backplane;

[0083] For example, in this embodiment, a group of processors on the motherboard can be fixedly connected to a group of backplane connectors through PCB traces, a group of backplane connectors can be manually and non-fixedly connected to a group of motherboard connectors on the backplane through cables, a group of motherboard connectors can be fixedly connected to a group of input pins of the processing components through PCB traces, a group of output pins of the processing components can be fixedly connected to a group of hard disk connectors through PCB traces, and a group of hard disk connectors can be fixedly connected to a group of hard disks.

[0084] As an optional exemplary embodiment, in the embodiment of the present application, the first component is a backplane, the second component is a motherboard, the first connector on the backplane is a backplane-end high-speed connector, the storage connector on the backplane is a hard disk connector configured to connect to a hard disk, the second connector on the motherboard is a motherboard-end high-speed connector, and the processing component on the backplane is an FPGA. FIG5 shows a global topology diagram when the cables are correctly connected. As shown in FIG5, the motherboard-end processor 1 extends CON1AˉCON1N high-speed connectors, and the processor 2 extends CON2AˉCON2N high-speed connectors, and so on, which can cover the scenario of n processors. The motherboard-end CONnN and the backplane-end CONnN' constitute a correct inter-board interconnection relationship, and the boards are connected by cables. The backplane-side FPGA receives signals from the motherboard's high-speed connector and outputs them to the corresponding hard disk connectors through IO. Under the condition that the inter-board cables are correctly connected, if the high-speed connectors on the motherboard and backplane sides are both x8 bandwidth, and the hard disk connector is x4 bandwidth, then the input of CONnN' is connected to SSDnN1 and SSDnN2, thus forming a correct high-speed interconnection relationship from the motherboard-side CONnN to the backplane-side CONnN' to the hard disk connectors SSDnN1 / SSDnN2.

[0085] Optionally, the mainboard high-speed connector and FPGA internal judgment logic for mounting the FRU on the mainboard are shown in FIG6 .

[0086] Taking a group of PCIe signals extended by processor 1 as an example, the address bit of the FRU mounted on the high-speed connector on the motherboard is set to five bits (which can support the distinction of 32 connector addresses). Each high-speed connector on the motherboard leads out an I2C configured to transmit the FRU address and a group of PCIe. After the address signal stored in the FRU is transmitted to the FPGA through the backplane connector, after analysis, the address input by the 1A'Ad pin is the address of CON1A on the motherboard side, and the address input by the 1B'Ad pin is the address of CON1B on the motherboard side. Therefore, 1A' and SSD1A'1 / SSD1A'2 inside the FPGA are connected, and 1B' and SSD1B'1 / SSD1B'2 are connected. Finally, CON1A provides high-speed signals to SSD1A1 / SSD1A2, and CON1B provides high-speed signals to SSD1B1 / SSD1B2.

[0087] When an error occurs in the high-speed cable connection between boards, such as the scenario shown in FIG7 , the corresponding embodiment details will automatically correct the error through the technical solution shown in FIG8 .

[0088] Figure 7 shows a global topology diagram in a cable misconnection state (an example of a cable misconnection). As shown in Figure 7, when an inter-board cable misconnection occurs, the technical solution described in this application can still achieve automatic error correction, thereby matching the drive sequence set by the hard drive connector to the correct PCIe port on the motherboard. The specific implementation method is shown in Figure 8.

[0089] The address bits in the motherboard-side high-speed connector FRU are still set to 5 bytes. Taking the extended high-speed signals of CON1A and CON1B as an example, the correct cable connection should be motherboard CON1A connected to backplane CON1A' and motherboard CON1B connected to backplane CON1B'. Now, due to incorrect insertion, motherboard CON1A is connected to backplane CON1B' and motherboard CON1B' is connected to backplane CON1N'. The PCB traces on the backplane are fixed. At this time, the FPGA's input pins 1B'Ad and 1B' still receive signals from CON1B', and 1N'Ad and 1N' still receive signals from CON1N'. Address bit parsing determines that CON1B' is interconnected with CON1A, and CON1N' is interconnected with CON1B. Therefore, the FPGA internally conducts 1B' to SSD1A'1 / SSD1A'2, and 1N' to SSD1B'1 / SSD1B'2. Ultimately, the high-speed signals of the hard drive connectors SSD1A1 / SSD1A2 come from CON1A on the motherboard side, and the high-speed signals of SSD1B1 / SSD1B2 come from CON1B on the motherboard side. This ensures that even if the cables are incorrectly connected, the hard drive sequence is correct at the physical link and display levels.

[0090] Through this application, by setting up an FPGA chip on the backplane, based on the detection of whether the high-speed cable is inserted incorrectly, automatic error correction of the wrongly inserted high-speed cable is realized by relying on logical judgment, so that even if the cable is inserted incorrectly, the actual correspondence between the hard disk slot and the CPU Port (port, interface) is still correct, ensuring that the physical disk sequence of the hard disk is correct.

[0091] Through the high-speed connector with FRU (Field Replace Unit) on the motherboard side, the FRU can be configured to write the connector address. The FPGA (Field Programmable Gate Array) on the backplane side can read the address bit information transmitted by the high-speed connector, and control the logic switch to open and close by judging the configuration relationship between the address bit and the default value, so as to achieve accurate correspondence between the hard disk connector and the processor expansion PCIe Port.

[0092] In an exemplary embodiment, there are multiple first components, and different first components are connected via interconnecting connectors;

[0093] The processing component is further configured to transmit the connector identifier of the second target connector to other first components through the interconnection connector on the first component in the case that there is no storage connector matching the second target connector on the first component, so that the other first components can determine the storage connector matching the second target connector on the other first components, wherein the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector through a cable is the second target connector, and the other first components are first components other than the first component in a group of first components.

[0094] Taking into account that when there are multiple first components, the operator may mistakenly connect the second target connector on the second component to the wrong first component that does not have a corresponding first storage connector, in order to at least partially solve the above problem, for the first component to which the second target connector is connected via a cable, when there is no storage connector matching the second target connector on the first component, the connector identifier of the second target connector can be transmitted to other first components via the interconnecting connector on the first component, so that the other first components can determine whether there is a storage connector matching the second target connector on the other first components. Similar to the aforementioned embodiment, the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector via a cable is the second target connector.

[0095] Here, in the case where multiple first components are connected in series, the connector identifier of the second target connector can be passed to other first components one by one through the interconnection connector on the first component until the first component where the first storage connector corresponding to the second target connector is located is found or all other first components are polled. In the case where the first storage connector does not exist in all first components, the connection abnormality is indicated by an indication information. Here, the indication information can be issued by the processing component on the first component or by the control component, which is not limited in this embodiment.

[0096] It should be noted that signals can be transmitted between different first components by connecting the interconnecting connectors on each first component via cables, and the other first components are the first components in a group of first components except for the first component where the first target connector connected to the second target connector via a cable is located.

[0097] In an exemplary embodiment, the processing component is further configured to transmit the connector identification of the second target connector to at least one interconnect connector on the first component via a board trace when no storage connector matching the second target connector exists on the first component;

[0098] The at least one interconnecting connector is configured to transmit the connector identification of the second target connector to the other first component through a cable between the first component where the second target connector is located and the other first component.

[0099] Here, the number of interconnecting connectors on the first component can be equal to the first connector, so that when there is no storage connector corresponding to the second target connector on the current first component, the connector identifier of the second target connector received by the first target connector is passed to other first components through the interconnecting connector corresponding to the first target connector.

[0100] For example, in this embodiment, taking the backplane 1 as the first component to which the second target connector is connected via a cable, and the hard disk connector as the storage connector, the processing component FPGA1 on the backplane 1 obtains an address from the second target connector CON2A via the input pin 1B'Ad. After internal polling fails to match the hard disk connector on the backplane 1, the signal is sent to the interconnect connector CON1B'' via the output pin 1B'Ad through the on-board routing, and then the signal is transmitted to the backplane 2 via the inter-backplane cable.

[0101] In an exemplary embodiment, the processing component is further configured to receive matching indication information sent by a target component in other first components through a target interconnect connector in at least one interconnect connector, wherein the matching indication information is used to indicate the presence of a second storage connector on the target component that matches the second target connector; and transmit the second signal to be transmitted received through the first target connector to the target component through the target interconnect connector, so as to transmit the second signal to be transmitted through the second storage connector to the storage component connected to the second storage connector.

[0102] For a processing component on a first component where a first target connector connected to a second target connector via a cable is located, if it is determined that no storage connector matching the second target connector exists on the current first component, transmitting the connector identifier of the second target connector to another first component via an interconnect connector on the first component;

[0103] For other first components that receive the connector identification of the second target connector through the interconnected connector thereon, the first component on which there is a storage connector matching the second target connector is the target component, that is, the target component is the first component among the other first components on which there is a storage connector matching the second target connector, the processing component on the target component can determine whether there is a storage connector matching the second target connector on the target component based on the connector identification of the second target connector received by the interconnected connector on the target component, and the processing component on the target component can send matching indication information to the processing component of the first component where the first target connector connected to the second target connector through a cable is located through the interconnected connector thereon, and the matching indication information is used to indicate that there is a second storage connector matching the second target connector on the target component; thereby, the second signal to be transmitted received through the first target connector is transmitted to the target component through the target interconnected connector, so as to transmit the second signal to be transmitted to the storage component connected to the second storage connector through the second storage connector.

[0104] Through this embodiment, through the matching indication information transmitted by the target component where the second storage connector that matches the second target connector is located, the first component where the first target connector that is connected to the second target connector through a cable is located can transmit the received signal sent by the second component end to the storage component connected to the second storage connector on the target component, thereby realizing accurate transmission of the signal.

[0105] In an exemplary embodiment, the processing component is further configured to save the correspondence between the connector identifier of the second target connector and the connector identifier of the target interconnect connector.

[0106] For the processing component on the first component where the first target connector connected to the second target connector via a cable is located, the correspondence between the connector identifier of the second target connector and the connector identifier of the target interconnect connector can be saved for subsequent signal transmission. Here, the form of the connector identifier can be similar to that in the aforementioned embodiment and will not be repeated here.

[0107] Through this embodiment, when the processing component of the current first component receives a signal transmitted by the second target connector, it can determine the target interconnect connector that matches the second target connector based on the correspondence between the stored connector identifier of the second target connector and the connector identifier of the target interconnect connector, and then transmit the connector identifier of the second target connector to other first components through the target interconnect connector, thereby improving signal transmission efficiency.

[0108] In an exemplary embodiment, the processing component is further configured to, when no storage connector matching the second target connector exists on the first component, determine an abnormal connector on the first component, wherein the abnormal connector is a first connector of the first component in which the storage connector corresponding to the second target connector is connected does not belong to the first connector of the first component.

[0109] An abnormal connection prompt message is issued, wherein the abnormal connection prompt message is used to provide a connection abnormality prompt for an abnormal connector.

[0110] As another solution for correcting a cable connection error between a first component and a second component, in this embodiment, if a storage connector matching the second target connector does not exist on the first component where the first target connector is connected to the second target connector via a cable, the first target connector can be identified as an abnormal connector, and a processing component on the first component can issue an abnormal connection prompt message to notify an operator of the cable connection error. Based on the abnormal connection prompt message, the operator can manually reconnect the cable. The form of the abnormal connection prompt message is not limited in this embodiment.

[0111] As an optional exemplary embodiment, in the embodiment of the present application, the first component is a backplane, the second component is a motherboard, the first connector on the backplane is a backplane-end high-speed connector, the storage connector on the backplane is a hard disk connector configured to connect to a hard disk, the second connector on the motherboard is a motherboard-end high-speed connector, and the processing component on the backplane is an FPGA. For illustration, if a motherboard needs to be interconnected with multiple backplanes, taking a motherboard connected to two backplanes as an example, an FPGA needs to be set on each backplane. The correct cable interconnection relationship between boards can be shown in Figure 9. If the internal cables of the same backplane are cross-connected, the technical solution described in the aforementioned embodiment can be adopted to achieve automatic error correction of the interconnection relationship, which will not be repeated here.

[0112] If cross-connection of cables between different backplanes occurs, as shown in FIG10 , it is necessary to add high-speed connectors (interconnect connectors) equal to the first connector CONnN′ to each board based on the above embodiment, and connect two different backplanes through cables.

[0113] As shown in Figure 10, if CON1B, which should be connected to backplane 1, is mistakenly connected to CON2A' of backplane 2, and CON2A, which should be connected to backplane 2, is mistakenly connected to CON1B' of backplane 1, it is necessary to build an interconnection channel for the two backplanes, that is, backplane 1 is provided with interconnection connectors CON1A", CON1B", ..., CON1N", and backplane 2 is provided with interconnection connectors CON2A", CON2B", ..., CON2N", as shown in Figure 11.

[0114] As shown in Figure 11, the FRU addresses of CON1B and CON2A are set respectively. The setting steps are similar to those in the aforementioned embodiment and are not described in detail here. FPGA1 and FPGA2 respectively parse the addresses of the high-speed connectors on the mainboard side connected to backplane 1 and backplane 2 through cables. The address obtained by FPGA1 through 1B'Ad comes from CON2A. After the internal polling fails to match the hard disk connector on backplane 1, the signal is given to CON1B" through the on-board routing through the output IO pins 1B" and 1B"Ad, and then the signal is transmitted to backplane 2 through the cable between the backplanes. FPGA2 on backplane 2 parses the signal from CON2B" and finds that it comes from CON2A. It executes the connection between SSD2A'1 / SSD2A'2, and the hard disk connector SSD2A1 / SSD2A2 can obtain the correct high-speed signal CON2A on the mainboard side. Similarly, the address obtained by FPGA2 through 2A'Ad comes from CON1B. There is no matching output port within the range of backplane 2, so the obtained signal is output through 2A" and 2A"Ad to the interconnection connector CON2A" on backplane 2, and then transmitted to the interconnection connector CON1A" on backplane 1 through the backplane cable. FPGA1 on backplane 1 parses its high-speed connector address and finds out that it comes from CON1B. After connecting to SSD1B'1 / SSD1B'2, the hard disk connector SSD1B1 / SSD1B2 can obtain the correct high-speed signal from the motherboard end.

[0115] Through this embodiment, when a mainboard is interconnected with multiple backplanes, if a high-speed connector connection between the backplanes is incorrect, automatic correction of the physical connection of the high-speed signal can still be achieved.

[0116] In this embodiment, a server is further provided, which includes the signal transmission result of any of the above embodiments, and the details that have been explained will not be repeated.

[0117] Figure 12 is a block diagram of the hardware structure of a server in an embodiment of the present application. As shown in Figure 12, the server may include one or more (only one is shown in Figure 12) processors (the processor may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a storage component configured to store data, wherein the above-mentioned server device may also include a group of first connectors, a group of second connectors, and a group of storage connectors (only one is shown in Figure 12). It will be understood by those skilled in the art that the structure shown in Figure 12 is only for illustration and does not limit the structure of the above-mentioned server device. For example, the server device may also include more or fewer components than shown in Figure 12, or have a configuration different from that shown in Figure 12.

[0118] In this embodiment, a signal transmission method is provided. FIG13 is a flow chart of a signal transmission method according to an embodiment of the present application. As shown in FIG13 , the flow chart includes the following steps:

[0119] Step S1302, based on a preset correspondence between the second connector and the storage connector, determine, through the processing component, a storage connector on the first component that matches the second target connector connected to the first target connector, wherein the first target connector is a connector in a group of first connectors, and the second target connector is a connector in a group of second connectors.

[0120] The signal transmission method in this embodiment can be applied to a scenario in which signal transmission is performed between a first component and a second component connected by a cable. For example, the electronic device should be configured to include a first component and a second component, the first component includes a group of first connectors configured to connect to the second component, a group of storage connectors configured to connect to the storage component, and a processing component, the second component includes a group of second connectors configured to connect to a group of first components, and the first connectors on a group of first components are non-fixedly connected to the second connectors on the second component via a cable. In at least some embodiments of the present application, the electronic device is described as a server as an example.

[0121] Currently, due to the demand for high-density storage devices, an electronic device (e.g., a server) needs to support multiple storage components, such as SSDs (Solid State Drives), at the front / middle / rear of the chassis. The device system architecture design in related technologies usually connects the storage component on the first component of the device and the control component on the second component of the device through a cable, so that the control component can transmit signals with the storage component, for example, to access data stored on the storage component, perform read or write operations, etc.

[0122] To ensure the correct connection between the control component and the storage component, it is usually necessary to add small labels to both ends of each cable to mark the interconnected connector position number. However, for high-density storage, the connectors on the control component and storage component ends of the device are densely packed, making it difficult to distinguish the different connector pins, and the probability of misplugging is very high.

[0123] In order to at least partially solve the above technical problems, in this embodiment, by setting a processing component on the first component, not only can it be detected whether the cable is plugged in incorrectly, but also automatic error correction of the wrongly plugged cable can be achieved by relying on logical judgment, so that in the case of incorrectly plugged cables, the correspondence between the actual storage connector and the control component connector is still correct.

[0124] In this embodiment, since the processing component on the first component is fixedly connected to a group of first connectors, when a group of first connectors on the first component is connected to a group of second connectors on the second component through a cable, when the processing component receives a first signal to be transmitted from the second component via a first target connector in a group of first connectors, the second target connector connected to the first target connector in a group of second connectors can be determined. Optionally, the first signal to be transmitted emitted by the second component may include identification information of the second target connector.

[0125] For the processing component on the first component, when determining the second target connector connected to the first target connector via a cable, the storage connector on the first component that matches the second target connector can be determined based on the preset correspondence between the second connector and the storage connector. Here, the preset correspondence can be stored on the processing component or on the execution storage component corresponding to the processing component, and this is not limited in this embodiment.

[0126] Step S1304, when there is a first storage connector on the first component that matches the second target connector, the first signal to be transmitted received through the first target connector is transmitted to the first storage connector through the processing component, so as to transmit the first signal to be transmitted to the storage component connected to the first storage connector through the first storage connector.

[0127] In this embodiment, the processing component on the first component can be connected to the storage connector on the first component, and the connection method may include but is not limited to fixed connection through PCB routing. Based on this, when the processing component determines the storage connector on the first component that matches the second target connector based on a preset correspondence, and there is a first storage connector on the first component that matches the second target connector, the first signal to be transmitted received through the first target connector can be transmitted to the first storage connector through the processing component, so as to transmit the first signal to be transmitted through the first storage connector to the storage component connected to the first storage connector.

[0128] It should be noted that, in this embodiment, steps S1302 to S1304 can be executed by the processing components on the aforementioned signal transmission structure, and have been described, so they will not be repeated here.

[0129] Through the above steps, the processing component determines the storage connector on the first component that matches the second target connector connected to the first target connector based on the preset correspondence between the second connector and the storage connector, wherein the first target connector is one connector in a group of first connectors, and the second target connector is one connector in a group of second connectors; when there is a first storage connector that matches the second target connector on the first component, the processing component transmits the first signal to be transmitted received through the first target connector to the first storage connector, so as to transmit the first signal to be transmitted through the first storage connector to the storage component connected to the first storage connector, thereby solving the problem of low signal transmission accuracy due to low cable connection accuracy in the signal transmission method in the related art and improving the accuracy of signal transmission.

[0130] In an exemplary embodiment, before determining, by the processing component, a storage connector on the first component that matches the second target connector connected to the first target connector based on a preset correspondence between the second connector and the storage connector, the method further includes:

[0131] The processing component obtains a connector identifier of the second target connector received by the first target connector and transmitted by the second target connector, wherein the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector through a cable is the second target connector.

[0132] In order to improve the efficiency and accuracy of the processing component in determining the second target connector, in this embodiment, for the second component, the connector identifier of the second target connector can be transmitted to the first component through the second target connector. For the first component, the connector identifier of the second target connector is received by the first target connector and transmitted to the processing component. The processing component obtains the connector identifier of the second target connector received by the first target connector and transmitted by the second target connector. Similar to the aforementioned embodiment, the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector through a cable is the second target connector, and the connector identifier of the second target connector can be transmitted through the integrated circuit bus.

[0133] In one exemplary embodiment, the first component includes a logic device including input pins and output pins, wherein each first connector on the first component is connected to an input pin of the logic device, and each storage connector on the first component is connected to an output pin of the logic device;

[0134] Acquiring, by a processing component, a connector identifier of a second target connector transmitted by a second target connector and received by the first target connector, comprising: acquiring, by a logic device, the connector identifier of the second target connector transmitted by a first input pin, wherein the first input pin is an input pin on the logic device corresponding to the first target connector;

[0135] Before transmitting the first signal to be transmitted received through the first target connector to the first storage connector through the processing component, the method further includes: controlling an output pin corresponding to the first storage connector on the logic device to be turned on through the logic device.

[0136] In this embodiment, the processing component on the first component can be a logic device including a group of input pins and a group of output pins. Each first connector on the first component is connected to an input pin of the logic device, and each storage connector on the first component is connected to an output pin of the logic device. The connection method between the first connector and the input pin of the logic device and the storage connector and the output pin of the logic device can include but is not limited to fixed connection through PCB routing.

[0137] The first component may receive the connector identification of the second target connector on the second component transmitted via the second target connector through the first input pin of the logic device connected to the first target connector.

[0138] Accordingly, in the case of a first storage connector that matches the second target connector based on a preset correspondence between the logic device, before the logic device transmits the first signal to be transmitted received by the first target connector connected to the second connector via a cable to the first storage connector, the output pin corresponding to the first storage connector on the logic device is controlled to be turned on through the logic switch inside the logic device.

[0139] Here, the first connector connected to the input pin of the logic device and the storage connector connected to the output pin of the logic device may be one-to-one or one-to-many, which may be consistent with the multiple relationship between the bandwidth of the first connector and the storage connector.

[0140] For example, in this embodiment, if a group of first connectors CONnN' at the first component end and a group of second connectors CONnN at the second component end both have a bandwidth of x8, and the storage connector has a bandwidth of x4, then the input of the first connector CONnN' is connected to the storage connectors SSDnN1 and SSDnN2, and the output pins SSDnN'1 / SSDnN'2 corresponding to SSDnN1 and SSDnN2 on the logic device can be controlled to be turned on through the logic switch inside the logic device.

[0141] Through this embodiment, by adding a logic device including input pins and output pins to the first component, the input pin of the logic device can receive the connector identifier of the second target connector, the logic device can parse the received connector identifier, and control the output pin corresponding to the first storage connector that matches the second target connector to be turned on through the logic switch inside the logic device, thereby realizing accurate signal transmission.

[0142] In an exemplary embodiment, there are multiple first components, and different first components are connected via interconnecting connectors;

[0143] After determining, by the processing component, a storage connector on the first component that matches the second target connector based on a preset correspondence between the second connector and the storage connector, the method further includes:

[0144] In the case that there is no storage connector matching the second target connector on the first component, the connector identifier of the second target connector is transmitted to other first components through the interconnection connector on the first component by the processing component, so that the other first components can determine the storage connector matching the second target connector on the other first components, wherein the other first components are the first components in a group of second components other than the first component.

[0145] The signal processing method in this embodiment is explained below in conjunction with optional examples. Taking the application of this embodiment to a server as an example, this optional example provides a server high-speed cable connection automatic error correction method for realizing automatic correction of cable mis-insertion within the same backplane or between different backplanes, thereby ensuring the correct physical connection between the hard disk on the backplane and the PCIe high-speed connector on the motherboard end without opening the cover or powering off, and realizing the nearby connection of the high-speed cable between the motherboard and the backplane without errors, thereby realizing the simplicity of the cables between the boards, reducing the wind resistance near the hard disk inside the chassis, and improving the heat dissipation effect; in addition, the high-speed interconnection relationship between the motherboard and the backplane can be based solely on the convenience of winding, which can shorten the length of the high-speed cable inside the chassis, thereby reducing the cost of cable use.

[0146] In this embodiment, the first component is a server backplane, the first connector is a backplane end connector, the replaceable unit is a FRU, the second component is a server motherboard, the second connector is a motherboard end connector, and the processing component is an FPGA.

[0147] At present, due to the demand for high-density storage servers, a server needs to support multiple hard disks in the front / middle / rear of the chassis, such as SSDs (Solid State Drives). The server system architecture design in the related art usually connects the motherboard and the backplane through cables, for example, connecting the CPU on the motherboard and the hard disk on the backplane, wherein the cables include high-speed signal cables, low-speed management cables, and power cables. The low-speed management cables and power cables can be shared by multiple disks in design, and the selection of connectors for the same type of cables varies greatly, which makes the connection relationship simpler and less likely to cause mis-insertion during assembly. High-speed connectors usually adopt standard specifications, such as x8 / x16, and the connector shape is consistent. In order to make the hard disk sequence correct, small labels need to be added to both ends of each high-speed cable to mark the interconnection connector position number. However, for high-density storage, the high-speed connectors on the board are densely packed, and it is very difficult to distinguish the pin positions of different connectors, and the probability of mis-insertion is very high. It can be seen that the signal transmission structure in the related art has the problem of low signal transmission accuracy due to the low accuracy of cable connection.

[0148] Furthermore, the CPU position and hard drive order also rely on high-speed interconnects, placing higher demands on the accuracy of high-speed cable interconnects within the server chassis. Consequently, if the CPU position and the required hard drive order are inconsistent, cable routing inside the chassis becomes complex. This increases cable length and internal routing complexity, making it prone to misplugging. This significantly increases cable production costs and increases wind resistance near the hard drives, thereby reducing the product's internal cooling effectiveness.

[0149] The CPU processor on the motherboard side and its corresponding extended high-speed connector are fixedly connected through wiring on the PCB (Printed Circuit Board). The high-speed connector on the motherboard side is mounted on the FRU, and the address information of the high-speed connector is set and written in the FRU. The address bit here is set through 0 / 1 binary, and the address reserved bytes can be determined according to the number of high-speed connectors extended on the motherboard side.

[0150] Each high-speed connector on the motherboard is connected to the backplane via a cable. Address information stored by the motherboard FRU is transmitted via I2C. The high-speed connector on the backplane transmits high-speed signals and address signals to the FPGA input pins via fixed traces on the PCB.

[0151] The FPGA parses the received high-speed connector address information and controls the corresponding output pins to conduct through internal logic switches. The FPGA output pins on the backplane side are fixedly connected to the hard disk connector through on-board routing, so that the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) order of the motherboard processor expansion can be consistent with the hard disk connector disk sequence.

[0152] Optionally, in conjunction with FIG14 , the signal transmission method in the embodiment of the present application may include the following steps:

[0153] Step 1: Determine the interconnection relationship between the mainboard processor and the extended high-speed connector, and set the address information of each connector;

[0154] Step 2: Connect each high-speed connector on the motherboard to the high-speed connector on the backplane through a cable.

[0155] Step 3: The high-speed connector on the backplane side that receives the motherboard signal is connected to the backplane side FPGA through the PCB traces on the board, and the motherboard side address information is transmitted synchronously;

[0156] Step 4: The FPGA parses the high-speed connector address on the mainboard and selects the IO (input / output) pin that matches the connector address to conduct the high-speed signal.

[0157] Step 5: The FPGA output IO pins are fixedly connected to the hard disk connector through the PCB traces on the board, transmitting high-speed signals to the hard disk connector.

[0158] Through this application, a high-speed connector with address information can be set, on which FRU is mounted, and the address bit can be flexibly set according to the number of high-speed connectors to be distinguished; the programmable controller (such as FPGA) parses the address bit information and logically disconnects the output IO, thereby controlling the correctness of the interconnection relationship; for multi-backplane scenarios, by setting up the connection between the connector and the programmable controller on each backplane, it is ensured that the cable connection errors between the boards can still be automatically corrected.

[0159] It should be noted that the present application can be applied to a wide range of components or machines that require cable connections. If there is a condition where a processing component (e.g., a programmable controller) is embedded on the board, the technical solutions mentioned in the embodiments of the present application can be used. For the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are optional embodiments for implementing the solutions of the present application, and the actions and modules involved are not necessarily required by the present application.

[0160] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM (Read-Only Memory, Read-Only Memory) / RAM (Random Access Memory, Random Access Memory), a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0161] An embodiment of the present application further provides a computer non-volatile readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0162] In an exemplary embodiment, the above-mentioned computer non-volatile readable storage medium may include but is not limited to: a USB flash drive, a ROM (Read-Only Memory), a RAM (Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0163] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0164] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0165] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0166] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0167] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A signal transmission structure, characterized in that: include: A first component and a second component, wherein the first component includes a group of first connectors configured to connect to the second component and a group of storage connectors configured to connect to the storage component, and the second component includes a group of second connectors configured to connect to the first component, and the first connectors on the first component and the second connectors on the second component are non-fixedly connected via a cable, wherein The first component further includes: A processing component is configured to determine a storage connector on the first component that matches the second target connector connected to the first target connector based on a preset correspondence between the second connector and the storage connector, wherein the first target connector is one of the connectors in the group of first connectors and the second target connector is one of the connectors in the group of second connectors; in a case where there is a first storage connector on the first component that matches the second target connector, the first signal to be transmitted received through the first target connector is transmitted to the first storage connector, so as to transmit the first signal to be transmitted to the storage component connected to the first storage connector through the first storage connector.

2. The signal transmission structure according to claim 1, characterized in that: The second component also includes a group of processors, wherein each processor in the group of processors corresponds to at least some of the second connectors in the group of second connectors, and the signals to be transmitted received by the first component through the group of first connectors are transmitted to the first component by the group of processors via the group of second connectors.

3. The signal transmission structure according to claim 2, characterized in that: There are multiple first components, and the second connector corresponding to each processor is connected to the first connector on at least one of the first components through a cable, and the first connector on each first component is connected to the second connector corresponding to at least one processor in the group of processors through a cable.

4. The signal transmission structure according to claim 1, wherein: The processing component is further configured to obtain a connector identifier of the second target connector received by the first target connector and transmitted by the second target connector, wherein the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector via a cable is the second target connector.

5. The signal transmission structure according to claim 4, characterized in that: The processing component is further configured to use the connector identifier of the second target connector to poll the connector identifier of the second connector corresponding to the connector identifier of each storage connector on the first component until a storage connector whose connector identifier corresponds to the second connector is the connector identifier of the second target connector, wherein the preset correspondence is a correspondence between the connector identifier of the second connector and the connector identifier of the storage connector.

6. The signal transmission structure according to claim 4, characterized in that: A field replaceable component is mounted on each second connector in the set of second connectors, and a connector identifier of each second connector is stored in the field replaceable component mounted on each second connector; The second component is configured to transmit the connector identification of the second target connector stored in the field replaceable component mounted on the second target connector to the first target connector.

7. The signal transmission structure according to claim 4, characterized in that: The processing component is a logic device comprising input pins and output pins, wherein each first connector on the first component is connected to an input pin of the logic device, and each storage connector on the first component is connected to an output pin of the logic device; The logic device is configured to obtain a connector identifier of the second target connector transmitted by a first input pin, wherein the first input pin is an input pin on the logic device corresponding to the first target connector; and before transmitting the first signal to be transmitted to the first storage connector, control the output pin on the logic device corresponding to the first storage connector to be turned on.

8. The signal transmission structure according to claim 7, characterized in that: The logic device includes a logic switch; The logic device is further configured to control the output pin corresponding to the first storage connector on the logic device to be turned on through the logic switch.

9. The signal transmission structure according to claim 4, characterized in that: The processing component is a programmable controller, and the connector identifier of each second connector on the second component is the connector address information of each second connector.

10. The signal transmission structure according to claim 4, characterized in that: The signal transmission structure further includes: an integrated circuit bus and a high-speed peripheral component interconnect bus configured to connect the first component and the second component, wherein the connector identifier of the second target connector is transmitted via the integrated circuit bus, and the first signal to be transmitted is transmitted via the high-speed peripheral component interconnect bus.

11. The signal transmission structure according to claim 1, wherein: The bandwidth of each first connector on the first component and the bandwidth of each second connector on the second component are the same, and both are N times the bandwidth of each storage connector on the first component, where N is a positive integer greater than or equal to 2; The processing component is also configured to transmit the first signal to be transmitted received through the first target connector to the corresponding storage connector in the storage connector group when there is a storage connector group matching the second target connector on the first component, wherein the first storage connector includes N storage connectors in the storage connector group.

12. The signal transmission structure according to claim 1, wherein: There are multiple first components, and different first components are connected via interconnecting connectors; The processing component is further configured to, when there is no storage connector matching the second target connector on the first component, pass the connector identifier of the second target connector to other first components through the interconnection connector on the first component, so that the other first components can determine the storage connector matching the second target connector on the other first components, wherein the connector identifier of the second target connector is used to indicate that the second connector connected to the first target connector via a cable is the second target connector, and the other first components are the first components in a group of first components other than the first component where the first component is located.

13. The signal transmission structure according to claim 12, wherein: The processing component is further configured to transmit the connector identifier of the second target connector to at least one interconnect connector on the first component via an on-board trace when no storage connector matching the second target connector exists on the first component; The at least one interconnect connector is configured to transmit the connector identification of the second target connector to the other first component through the cable between the first component where the second target connector is located and the other first component.

14. The signal transmission structure according to claim 13, characterized in that: The processing component is further configured to receive matching indication information sent by a target component in another of the first components through a target interconnect connector in the at least one interconnect connector, wherein the matching indication information is used to indicate that there is a second storage connector on the target component that matches the second target connector; and to transmit a second signal to be transmitted received through the first target connector to the target component through the target interconnect connector, so as to transmit the second signal to be transmitted through the second storage connector to the storage component connected to the second storage connector.

15. The signal transmission structure according to claim 14, characterized in that: The processing component is further configured to save the correspondence between the connector identifier of the second target connector and the connector identifier of the target interconnect connector.

16. The signal transmission structure according to claim 12, wherein: The processing component is further configured to, if no storage connector matching the second target connector exists on the first component, determine an abnormal connector on the first component, wherein the abnormal connector is a first connector of the first component in which the storage connector corresponding to the second target connector is connected does not belong to the first connector of the first component; An abnormal connection prompt message is issued, wherein the abnormal connection prompt message is used to provide a connection abnormality prompt to the abnormal connector.

17. The signal transmission structure according to any one of claims 1 to 16, characterized in that: The first component is a backplane, the second component is a motherboard, the first connector on the backplane is a motherboard connector configured to connect to the motherboard, the storage connector on the backplane is a hard disk connector configured to connect to the hard disk, and the second connector on the motherboard is a backplane connector configured to connect to the backplane.

18. A server, characterized in that: The signal transmission structure comprises the signal transmission structure according to any one of claims 1 to 17.

19. A signal transmission method, characterized in that: An electronic device that is configured to include a first component and a second component, wherein the first component includes a set of first connectors configured to connect to the second component, a set of storage connectors configured to connect to a storage component, and a processing component, and the second component includes a set of second connectors configured to connect to the set of first components, and the first connectors on the set of first components are non-fixedly connected to the second connectors on the second component via a cable; The method comprises: determining, by the processing component, a storage connector on the first component that matches a second target connector connected to the first target connector based on a preset correspondence between the second connector and the storage connector, wherein the first target connector is one of the group of first connectors and the second target connector is one of the group of second connectors; In the event that there is a first storage connector on the first component that matches the second target connector, the first signal to be transmitted received through the first target connector is transmitted to the first storage connector through the processing component, so as to transmit the first signal to be transmitted through the first storage connector to the storage component connected to the first storage connector.

20. The method according to claim 19, characterized in that Before determining, by the processing component, a storage connector on the first component that matches the second target connector connected to the first target connector based on a preset correspondence between the second connector and the storage connector, the method further includes: The processing component obtains a connector identifier of the second target connector transmitted by the second target connector and received by the first target connector, wherein the connector identifier of the second target connector is used to indicate that a second connector connected to the first target connector through a cable is the second target connector.

21. The method according to claim 20, characterized in that The first component includes a logic device including input pins and output pins, wherein each first connector on the first component is connected to an input pin of the logic device, and each storage connector on the first component is connected to an output pin of the logic device; The acquiring, by the processing component, the connector identifier of the second target connector received by the first target connector and transmitted by the second target connector, comprises: acquiring, by the logic device, the connector identifier of the second target connector transmitted by a first input pin, wherein the first input pin is an input pin on the logic device corresponding to the first target connector; Before transmitting the first signal to be transmitted received through the first target connector to the first storage connector through the processing component, the method further includes: controlling, through the logic device, an output pin on the logic device corresponding to the first storage connector to be turned on.

22. The method according to any one of claims 19 to 21, characterized in that There are multiple first components, and different first components are connected via interconnecting connectors; After determining, by the processing component, a storage connector on the first component that matches the second target connector based on a preset correspondence between the second connector and the storage connector, the method further includes: In the case that there is no storage connector matching the second target connector on the first component, the connector identifier of the second target connector is transmitted to other first components by the processing component through the interconnection connector on the first component, so that the other first components can determine the storage connector matching the second target connector on the other first components, wherein the other first components are the first components in a group of second components other than the first component.

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