Chip and manufacturing method therefor, and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a chip and a manufacturing method therefor, and an electronic device, which are used for improving the performance of components while meeting the requirement for miniaturized sizes of the components of the electronic device. The chip comprises a plurality of array structures, wherein first isolation barriers in the array structures are located between first transistor columns and second transistor columns. The first transistor columns and the second transistor columns each comprise a plurality of vertical channels, gate dielectric layers and first signal lines. The plurality of vertical channels are arranged at intervals on side walls of the first isolation barriers. The gate dielectric layers and the first signal lines encase the vertical channels on three sides, and the gate dielectric layers and the first signal lines continuously cover the plurality of vertical channels and some of the first isolation barriers between the plurality of vertical channels. The gate dielectric layers and the first signal lines and the vertical channels encased thereby constitute a vertical transistor. The vertical transistor is provided with a first signal line as a gate electrode only on a single side, so as to improve the miniaturization of a device.

Description

Chip, manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 2, 2024, with application number 202410157375.2 and invention name “A chip, its manufacturing method, and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a chip, a manufacturing method thereof, and an electronic device. Background Art

[0003] With the continuous advancement of semiconductor technology, components in electronic devices, such as memory chips, need to be continuously miniaturized to meet user demands for high-performance electronic devices, such as large-capacity and high-bandwidth storage, within the limited layout space of electronic devices. However, the performance and storage density of memory chips are gradually becoming important factors limiting the performance of electronic devices. For example, as storage density continues to increase, the miniaturization of storage cells within memory chips will affect the performance of components within the memory chips, such as transistors, thereby reducing product reliability.

[0004] Summary of the Invention

[0005] The present application provides a chip and a manufacturing method thereof, and an electronic device, which are used to improve the performance of components while meeting the miniaturization requirements of components of electronic devices.

[0006] To achieve the above objectives, this application adopts the following technical solutions:

[0007] In one aspect of the present application, a chip is provided, comprising a substrate and multiple array structures. The multiple array structures are disposed on the substrate and spaced apart along a first direction. The array structures include a first isolation barrier, a first transistor column, and a second transistor column. The first isolation barrier is located between the first transistor column and the second transistor column. Each of the first and second transistor columns includes multiple vertical channels, a gate dielectric layer, and a first signal line. The multiple vertical channels are spaced apart along a second direction on the sidewalls of the first isolation barrier. The vertical channels are disposed perpendicular to the substrate, with the first and second directions intersecting and parallel to the substrate. The gate dielectric layer is located on the side of the vertical channels facing away from the isolation barrier. The gate dielectric layer wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels. The first signal line is located on the side of the gate dielectric layer facing away from the first isolation barrier. The first signal line wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels.

[0008] As can be seen from the above, on the one hand, the first isolation barrier is located between the first transistor column and the second transistor column, and in either of the first transistor column and the second transistor column, the first signal line is arranged on the side of the gate dielectric layer or the vertical channel facing away from the first isolation barrier. Therefore, the vertical channel and the portion of the first signal line that wraps around the vertical channel can constitute a vertical transistor, and the portion of the first signal line that wraps around the vertical channel can serve as the gate of the vertical transistor. Because the side of the vertical channel of the vertical transistor facing the first isolation barrier is located on the sidewall of the first isolation barrier, no gate is provided on the side of the vertical channel facing the first isolation barrier. In this way, along the first direction, the vertical transistor is only provided with a gate on one side, thereby making the chip scalable in the first direction. On the other hand, the vertical channel of the vertical transistor is located on the sidewall of the first isolation barrier, and the first isolation barrier can support the vertical channel, thereby reducing the processing difficulty of reducing the thickness of the vertical channel along the first direction and improving scalability.

[0009] On the other hand, the first signal line wraps around the vertical channel on three sides to provide three-dimensional coverage of the first signal line on three sides, so that the electric field lines of the vertical transistor are more concentrated, which is beneficial to improving the gate control ability and on-state current of the vertical transistor, and achieving the purpose of improving the performance of the vertical transistor, thereby being able to improve the performance of the components while meeting the miniaturization requirements of the components of the electronic device. In addition, the gate dielectric layer and the first signal line can continuously cover the multiple vertical channels and part of the first isolation barrier between the multiple vertical channels. Therefore, along the direction in which the multiple vertical channels are arranged (i.e., the second direction), the gate dielectric layer and the first signal line are both continuous structures. In this way, during the manufacturing process, the multiple vertical channels arranged at intervals can be first formed on both sides of the first isolation barrier, and then the gate dielectric layer and the first signal line can be formed in sequence on the side of any row of multiple vertical channels away from the first isolation barrier.

[0010] In an optional embodiment, the vertical channel includes a first portion and a second portion. The first portion is arranged in a direction perpendicular to the substrate. The second portion is connected to an end of the first portion facing the substrate, and the second portion is arranged along the first direction. The chip also includes a second signal line, which is arranged between the array structure and the substrate, the second signal line extending along the first direction, and the second signal line contacts the second portion. In this way, since the second portion is electrically connected to the second signal line and the second portion is arranged along the first direction, the second portion can increase the contact area between the entire vertical channel and the second signal line, thereby reducing the contact resistance.

[0011] In one optional embodiment, the second portions of two adjacent vertical channels in different array structures are connected, so that the two connected vertical channels form a U-shaped structure. A portion of the U-shaped semiconductor structure is arranged along the first direction and is electrically connected to the second signal line, thereby increasing the contact area between the entire vertical channel and the second signal line and reducing contact resistance.

[0012] In one optional embodiment, the chip includes multiple second signal lines. The chip also includes a third isolation barrier wall, which is disposed between two adjacent second signal lines to isolate the adjacent second signal lines. Furthermore, the third isolation barrier wall is made of a different material than the first isolation barrier wall. This ensures that the structure of the first isolation barrier wall is not affected during wet etching of the third isolation barrier wall.

[0013] In an optional embodiment, two adjacent first signal lines of different array structures are connected to form a conductive integral structure, which is filled between two adjacent rows of vertical channels. The conductive integral structure and the two oppositely positioned vertical channels surrounded on three sides by the conductive integral structure can form a vertical transistor with a dual channel. Compared to a single-channel vertical transistor, the on-state current of this dual-channel vertical transistor can be doubled.

[0014] In an optional embodiment, the chip further includes a second isolation barrier. The second isolation barrier is disposed between two adjacent array structures and is located on the side of the conductive integral structure facing away from the substrate. The second isolation barrier is used to isolate portions of the vertical channels in the two adjacent array structures that are not covered by the conductive integral structure.

[0015] In an optional embodiment, the chip also includes a second isolation barrier. The second isolation barrier is arranged between two adjacent array structures. Two adjacent first signal lines of different array structures are isolated on both sides of the second isolation barrier, and two adjacent vertical channels of different array structures are isolated on both sides of the second isolation barrier. The second isolation barrier can isolate two adjacent first signal lines in different array structures. In addition, the second isolation barrier can also isolate two adjacent vertical channels in different array structures. Among them, the side surface of the first signal line facing away from the first isolation barrier is flush with the side surface of the second part facing away from the first isolation barrier, and the side surface of the gate dielectric layer facing away from the first isolation barrier. In this way, the above-mentioned L-shaped vertical channel, gate dielectric layer and first signal line can be formed simultaneously through this photolithography process.

[0016] In one alternative embodiment, the first signal line covers the surface of the first portion facing away from the first isolation barrier, as well as the surfaces of the first and second portions perpendicular to the first isolation barrier and the substrate. In this case, the portion of the first signal line covering the second portion resembles a horseshoe shape, thereby increasing the coverage area of ​​the first signal line and reducing the resistance of the first signal line.

[0017] In an optional embodiment, the chip further includes a second isolation barrier wall, which is disposed between two adjacent array structures, and two adjacent first signal lines of different array structures are isolated and disposed on both sides of the second isolation barrier wall. The technical effect of the second isolation barrier wall is the same as described above and will not be repeated here. The first signal line covers a portion of the first isolation barrier wall, and has a first groove on the side facing away from the first isolation barrier wall, and a portion of the second isolation barrier wall is located in the first groove. The top-view structure of the second isolation barrier wall located between two adjacent array structures can be similar to the shape of a "N" character.

[0018] In an optional embodiment, the first transistor column and the second transistor column are symmetrically arranged with respect to the first isolation barrier. This allows the chip structure to have a certain regularity. When manufacturing the chip using a patterning process, preparing a patterned structure with the regularity can simplify the manufacturing process.

[0019] In an optional embodiment, the first transistor column and the second transistor column each further include a first electrode and a second electrode. The first electrode is arranged on the side of the vertical channel facing the substrate. The second electrode is arranged on the side of the vertical channel facing away from the substrate. In this case, a voltage can be applied to the first electrode (e.g., source) and the second electrode (e.g., drain) so that a conducting current flows through the vertical channel. At this time, the vertical transistors in the above-mentioned transistor column can be in an on state. Alternatively, when no conducting current flows through the vertical channel, the vertical transistor can be in an off state.

[0020] In an optional embodiment, the chip further includes a capacitor array disposed on a side of the array structure facing away from the substrate. The capacitor array is electrically connected to at least one of the first transistor column or the second transistor column to form a memory array. The chip having this memory array may be a memory chip.

[0021] In an optional implementation, the chip further includes a controller, which is electrically connected to the storage array. The controller is used to control the reading and writing of the storage array to achieve access to the storage array.

[0022] Another aspect of the present application provides a chip comprising a substrate and multiple array structures. The multiple array structures are disposed on the substrate and spaced apart along a first direction. The array structures include a first isolation barrier, a first transistor column, and a second transistor column. The first isolation barrier is located between the first and second transistor columns. Each of the first and second transistor columns includes multiple vertical channels, a gate dielectric layer, and a first signal line. The multiple vertical channels are spaced apart along a second direction on the sidewalls of the first isolation barrier. The vertical channels are disposed perpendicular to the substrate, with the first and second directions intersecting and parallel to the substrate. The gate dielectric layer is located on the side of the vertical channels facing away from the isolation barrier. The gate dielectric layer wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels. The first signal line is located on the side of the gate dielectric layer facing away from the first isolation barrier. The first signal line wraps around the vertical channels on three sides and continuously covers the multiple vertical channels and the portion of the first isolation barrier between the multiple vertical channels. The first signal line can be used as the gate of multiple transistors in the first transistor column or the second transistor column. The chip has the same technical effects as the chip provided in the above embodiment, and will not be described in detail here.

[0023] Another aspect of the present application provides an electronic device comprising a circuit board and any of the chips described above. The circuit board is electrically connected to the chip. The electronic device has the same technical effects as the chip provided in the previous embodiment and will not be described in detail here.

[0024] Another aspect of the present application provides a chip fabrication method, comprising: forming a plurality of first isolation barriers arranged at intervals along a first direction on a substrate. Next, forming transistor columns on both sidewalls of the first isolation barriers. Forming transistor columns on both sidewalls of the first isolation barriers includes: forming a plurality of vertical channels arranged at intervals along a second direction on the sidewalls, wherein the vertical channels are perpendicular to the substrate. The first direction intersects with the second direction and are both parallel to the substrate. Next, forming a gate dielectric layer on a side of the plurality of vertical channels facing away from the isolation barriers. The gate dielectric layer wraps around the vertical channels on three sides and continuously covers the plurality of vertical channels, as well as portions of the first isolation barriers between the plurality of vertical channels. Next, forming a first signal line on a side of the gate dielectric layer facing away from the first isolation barriers. The first signal line wraps around the vertical channels on three sides and continuously covers the plurality of vertical channels, as well as portions of the first isolation barriers between the plurality of vertical channels. In this way, the first signal line formed on the gate dielectric layer can conform to the gate dielectric layer.

[0025] In an optional embodiment, forming a plurality of first isolation walls spaced apart along a first direction on a substrate includes: forming a semiconductor material layer on the substrate. Next, forming a plurality of second grooves extending along the first direction on the semiconductor material layer, and forming third isolation walls within the second grooves, wherein the third isolation walls are made of a different material than the first isolation walls. Next, forming a first mask structure on the semiconductor material layer. Next, removing the semiconductor material layer and the third isolation walls exposed by the first mask structure to form a plurality of third grooves spaced apart along the first direction. Next, forming the first isolation walls within the third grooves. The first isolation walls formed by the photolithography and deposition processes have a high degree of precision in terms of size, position, and spacing between the plurality of first isolation walls.

[0026] In an optional embodiment, after forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewalls includes: removing the first mask structure, forming a second mask structure on the sidewalls of the first isolation barrier, and removing the semiconductor material layer and the third isolation barrier exposed by the second mask structure to form the vertical channels. The vertical channels can form vertical transistors together with the first signal line covering the vertical channels.

[0027] In an optional embodiment, after forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewalls includes: removing the first mask structure, forming a second mask structure on the sidewalls of the first isolation barrier, and removing a portion of the semiconductor material layer and the third isolation barrier exposed by the second mask structure to form the plurality of U-shaped vertical channels. The technical effect of the U-shaped vertical channels is the same as described above and will not be further elaborated here.

[0028] In an optional embodiment, after forming the first mask structure, a plurality of vertical channels spaced apart along the second direction are formed on the sidewalls, and the gate dielectric layer and the first signal line are formed, including: removing the first mask structure, and forming a second mask structure on the sidewalls of the first isolation barrier wall, removing a portion of the semiconductor material layer and the third isolation barrier wall exposed by the second mask structure to form a plurality of U-shaped semiconductor structures. Next, a gate dielectric material layer and a second metal material layer are sequentially formed in the U-shaped semiconductor structure, the gate dielectric material layer and the second metal material layer both wrap the plurality of U-shaped semiconductor structures on three sides, and the gate dielectric material layer and the second metal material layer both continuously cover the U-shaped semiconductor structure, and a portion of the first isolation barrier wall between the plurality of U-shaped semiconductor structures. Next, a portion of the bottom of the U-shaped semiconductor structure is removed, and a portion of the gate dielectric material layer and the second metal material layer covering the bottom of the U-shaped semiconductor structure is removed to form an L-shaped vertical channel, a gate dielectric layer, and a first signal line. The technical effect of the L-shaped vertical channel is the same as described above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0030] FIG2 is a schematic diagram of a chip structure used in an electronic device according to an embodiment of the present application;

[0031] FIG3 is a top view taken along the direction A in FIG2 ;

[0032] FIG4 is another top view taken along the direction A in FIG2 ;

[0033] FIG5 is a schematic diagram of the structure of two symmetrically arranged vertical transistors in FIG2;

[0034] FIG6 is a cross-sectional view taken along the dotted line O1-O2 in FIG5;

[0035] FIG7 is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0036] FIG8 is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0037] FIG9 is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0038] FIG10 is a cross-sectional view taken along the dotted line O3-O4 in FIG7;

[0039] FIG11 is a schematic structural diagram of the storage array shown in FIG9 ;

[0040] FIG12 is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0041] FIG13 is a flow chart of a chip manufacturing method provided in an embodiment of the present application;

[0042] FIG14 is a schematic diagram of a portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0043] FIG15 is a schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0044] FIG16A is a schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0045] FIG16B is a top view taken along the direction B1 in FIG16A ;

[0046] FIG17A is a schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0047] FIG17B is a top view taken along the direction B2 in FIG17A;

[0048] FIG18A is a schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0049] FIG18B is a top view taken along the direction B3 in FIG18A;

[0050] FIG19A is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0051] FIG19B is a top view taken along the direction B4 in FIG19A;

[0052] FIG20A is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0053] FIG20B is a top view taken along the direction B5 in FIG20A ;

[0054] FIG21A is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0055] FIG21B is a top view taken along the direction B6 in FIG21A;

[0056] FIG22A is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0057] FIG22B is a top view taken along the direction B7 in FIG22A ;

[0058] FIG23 is a schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0059] FIG24A is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0060] FIG24B is a top view taken along the direction B8 in FIG24A;

[0061] FIG25A is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0062] FIG25B is a top view taken along the direction B9 in FIG25A;

[0063] FIG26A is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0064] FIG26B is a cross-sectional view taken along the dotted line O5-O6 in FIG26A;

[0065] FIG27 is a schematic diagram of another part of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0066] FIG28A is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0067] FIG28B is a top view taken along the direction C1 in FIG28A;

[0068] FIG29A is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0069] FIG29B is a cross-sectional view taken along the dotted line O7-O8 in FIG29A;

[0070] FIG29C is a top view taken along the direction C2 in FIG29A ;

[0071] FIG30A is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0072] FIG30B is a side view taken along the direction C3 in FIG30A;

[0073] FIG30C is a top view taken along the direction C4 in FIG30A ;

[0074] FIG30D is a cross-sectional view taken along the dotted line P1-P2 in FIG30A;

[0075] FIG31 is a schematic diagram of a structure of a vertical channel in a chip provided in an embodiment of the present application;

[0076] FIG32 is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0077] FIG33 is a schematic diagram of a partial structure of a chip structure applied to an electronic device according to an embodiment of the present application;

[0078] FIG34A is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0079] FIG34B is a side view taken along the direction D2 in FIG34A;

[0080] FIG34C is a cross-sectional view taken along the dotted line P3-P4 in FIG34A;

[0081] FIG35 is a schematic diagram of another portion of the structure of the chip manufacturing process provided in an embodiment of the present application;

[0082] FIG36 is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0083] FIG37A is a schematic diagram of another chip structure used in an electronic device according to an embodiment of the present application;

[0084] FIG37B is a cross-sectional view taken along the dotted line P5-P6 in FIG37A;

[0085] FIG. 37C is a side view taken along the direction C3 in FIG. 37A .

[0086] Figures: 01-electronic device; 101-bus; 102-SoC; 103-second RAM; 104-communication chip; 105-power management chip; 112-AP; 122-GPU; 132-first RAM; 20-chip; 21-array structure; 211-first isolation barrier; 221-first transistor column; 222-second transistor column; 200-substrate; 2101-vertical channel; 2102-gate dielectric layer; 2103-first signal line; T1-first vertical transistor; T2-second vertical transistor; 504-fourth groove; a1-first surface; a2-second surface; a3-third surface; a4-fourth surface; 30-storage array; 31-controller; 300-storage unit; 311-decoder; 312-driver; 313-timing Controller; 314-cache; 315-input and output drive; 41-bottom electrode; 42-dielectric layer; 43-top electrode; 2104-second signal line; 51-first metal material layer; 52-semiconductor material layer; 213-third isolation barrier; 53-first mask structure; 503-third groove; 54-second mask structure; 55-second metal material; 212-second isolation barrier; 501-first groove; 60-metal contact electrode; 400-conductive integrated structure; 21011-first part; 21012-second part; 520-U-shaped semiconductor structure; 56-third mask structure. DETAILED DESCRIPTION

[0087] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0088] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0089] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integrated connection; or, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0090] In addition, unless otherwise clearly specified and limited, the term "electrical connection" should be understood in a broad sense. For example, "electrical connection" can be a direct electrical connection, for example, physical contact and electrical conduction between two components. It can also be understood as the electrical connection between different components in the circuit structure through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals to transmit electrical signals; or, "electrical connection" can be an indirect electrical connection between two components through an intermediate medium; or, "electrical connection" can be an electrical connection between two components in an air / non-contact manner, for example, two components are electrically connected by capacitive coupling to transmit electrical signals.

[0091] In the embodiments of the present application, the descriptions "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range, and the error range may be a range in which the deviation angle relative to absolute vertical and absolute parallel is less than or equal to 5°, 8° or 10°, respectively, and no specific limitation is made here.

[0092] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0093] In the drawings of the embodiments of the present application, components are represented by guide lines with arrows; parts are represented by guide lines only; openings, holes and the like are represented by guide lines with wavy lines at the ends.

[0094] An embodiment of the present application provides an electronic device. The electronic device can be applied to various communication systems or communication protocols, such as: Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology, and other future communication technologies.

[0095] The electronic device in the embodiments of the present application may be a mobile phone, a tablet computer (pad), a laptop computer, a smart home, a smart wearable device (e.g., a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, etc. The electronic device may also be a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, an in-vehicle device, an electronic device in a 5G network, or an electronic device in a future-evolved public land mobile network (PLMN), etc., and the embodiments of the present application are not limited thereto.

[0096] For example, as shown in FIG1 , the electronic device 01 may include a circuit board (e.g., the PCB) 100, a bus 101 disposed on and electrically connected to the PCB 100, and a processor connected to the bus 101, such as a system on chip (SoC) 102 or a central processing unit (CPU), or a microcontroller unit (MCU). The SoC 102 may be used to process data, such as application data, image data, and temporary data.

[0097] In one embodiment, the SoC 102 may include an application processor (AP) 112 for processing application programs, a graphics processing unit (GPU) 122 for processing image data, and a first RAM 132 for caching high-speed data. The first RAM 132 may be a static random access memory (SRAM) or an embedded flash memory (EFlash). The above-mentioned SoC or CPU may be referred to as a logic chip. For example, the first RAM 132 may be integrated with the AP 112 and the GPU 122 into a single chip, or the first RAM 132 may be separately provided in a single memory chip.

[0098] In addition, as shown in Figure 1, the electronic device 01 may further include a memory chip connected to the SoC 102 via the bus 101, such as a second RAM 103. The second RAM 103 may be a dynamic random access memory (DRAM). The second RAM 103 may be used to store volatile data, such as temporary data generated by the SoC 102. The storage capacity of the second RAM 103 may generally be greater than that of the first RAM 132, but the reading speed is generally slower than that of the first RAM 132.

[0099] Furthermore, the electronic device 01 may further include a communication chip 104 and a power management chip 105 connected to the SoC 102 via the bus 101. The communication chip 104 may be used for protocol stack processing, or for amplifying and filtering analog RF signals, or for performing the aforementioned functions simultaneously. The power management chip 105 may be used to power other chips. In one embodiment, the SoC 102 and the second RAM 103 may be packaged in a single package structure, such as a 2.5D (dimension) or 3D package, to achieve faster inter-chip data transmission rates.

[0100] The above examples illustrate the chips provided in the embodiments of the present application using logic chips, memory chips, or communication chips, and do not constitute a limitation on the chip type. Other types of chips are not described in detail here. In addition, the chip 20 provided in the embodiments of the present application, as shown in Figure 2, may include a substrate 200 and a plurality of array structures 21. Figure 2 is an example of three array structures 21, and the present application does not limit the number of array structures 21. The above-mentioned multiple array structures 21 can be provided on the substrate 200, and the multiple array structures 21 are arranged at intervals along the first direction X.

[0101] The "substrate" mentioned above refers to a structure on which other film layers can be fabricated. The substrate can be patterned or unpatterned, and the film layers fabricated on the substrate can also be patterned or unpatterned. Furthermore, the substrate can include semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can include non-conductive materials such as glass, resin, or sapphire, which is not limited in this application.

[0102] To illustrate the structure of the chip 20, an XYZ coordinate system is established in the accompanying drawings, wherein the first direction X is the arrangement direction of the plurality of array structures 21, and the second direction Y is arranged to intersect (e.g., can be arranged perpendicular to) the first direction X. Both the first direction X and the second direction Y are parallel to the supporting surface of the substrate 200 (the surface for supporting the array structure 21), so the plane formed by the first direction X and the second direction Y can be parallel to the supporting surface of the substrate 200. In addition, the third direction Z is a direction perpendicular to the substrate 200.

[0103] Based on this, as shown in FIG2 , each array structure 21 may include a first isolation barrier 211, a first transistor column 221, and a second transistor column 222. The first isolation barrier 211 is located between the first transistor column 221 and the second transistor column 222. Each of the first transistor column 221 and the second transistor column 222 may include a plurality of vertical channels 2101, a gate dielectric layer 2102, and a first signal line 2103. The first isolation barrier 211 may also be referred to as a shallow trench isolation (STI) structure.

[0104] The plurality of vertical channels 2101 can be arranged at intervals along the second direction Y on the sidewalls of the first isolation barrier 211. Furthermore, the vertical channels 2101 are disposed perpendicularly to the substrate 200. In this case, the vertical channels 2101 can extend in a third direction Z perpendicular to the supporting surface of the substrate 200. The vertical channels 2101 can comprise semiconductor material. The gate dielectric layer 2102 can also be referred to as a gate oxide (Gate-OX) dielectric layer.

[0105] For example, the length of the vertical channel 2101 along the third direction Z can be 30 to 500 nm, the width along the second direction Y can be 10 to 100 nm, and the thickness along the first direction X can be 5 to 50 nm. In this case, the vertical channel 2101 can be a nanowire (NW). In addition, the materials constituting the vertical channel 2101 can include, but are not limited to: single crystal silicon, single crystal germanium, polycrystalline silicon, polycrystalline germanium, oxide semiconductors, such as indium gallium zinc oxide (IGZO), tungsten indium oxide (IWO), etc., organic semiconductors (such as pentacene, P3HT, etc.), two-dimensional material semiconductors, such as molybdenum disulfide (MoS2), tungsten selenide (WSe2), etc., one-dimensional semiconductors, such as carbon nanotubes (CNTs), etc.

[0106] In addition, the gate dielectric layer 2102 may wrap the vertical channel 2101 on three sides, and the gate dielectric layer 2102 continuously covers the plurality of vertical channels 2101 and a portion of the first isolation barrier 211 between the plurality of vertical channels 2101. For example, the gate dielectric layer 2102 may include a dielectric material, such as silicon oxide (e.g., SiO2), silicon nitride (SiN x ), silicon oxynitride, or a high-k dielectric material, such as hafnium dioxide (HfO2) or zirconium dioxide (ZrO2). Furthermore, a first signal line 2103 is located on the side of the gate dielectric layer 2102 facing away from the first isolation barrier 211. The first signal line 2103 can wrap around three sides of the vertical channel 2101 and continuously cover multiple vertical channels 2101, as well as portions of the first isolation barrier 211 between the multiple vertical channels 2101. The first signal line 2103 can be made of metal.

[0107] The following example illustrates how the gate dielectric layer 2102 and the first signal line 2103 wrap around the vertical channel 2101 on three sides. For example, as shown in FIG3 (a top view taken along the direction A in FIG2 ), the cross-section of the vertical channel 2101 (parallel to the XY plane) can be rectangular. In this case, the gate dielectric layer 2102 and the first signal line 2103 wrap around the vertical channel 2101 on three sides, which means that along the second direction Y, the gate dielectric layer 2102 and the first signal line 2103 can wrap around the first surface a1, the second surface a2, and the third surface a3 of the vertical channel 2101, which are connected in sequence. The first surface a1 and the third surface a3 are arranged opposite to each other and are both arranged perpendicular to the first isolation barrier 211. The second surface a2 is arranged opposite to the fourth surface a4 of the vertical channel 2101 that contacts the first isolation barrier 211, and the second surface a2 can be parallel to the sidewalls of the first isolation barrier 211.

[0108] The above description uses the example of a rectangular or semicircular cross-section of the vertical channel 2101. For further example, the cross-section of the vertical channel 2101 may also be triangular, trapezoidal, or a polygon with four or more sides, and this application will not elaborate on each of these. As long as the gate dielectric layer 2102 and the first signal line 2103 can wrap around multiple sequentially connected surfaces of the vertical channel 2101 along the second direction Y, the gate dielectric layer 2102 and the first signal line 2103 are protected by the vertical channel 2101 being wrapped around three sides.

[0109] Alternatively, as another example, as shown in FIG4 (a top view taken along the direction A in FIG2 ), the cross-section of the vertical channel 2101 may be semicircular (or semi-elliptical). In this case, the gate dielectric layer 2102 and the first signal line 2103 wrapping around the vertical channel 2101 on three sides means that, along the second direction Y, the gate dielectric layer 2102 and the first signal line 2103 may wrap around the curved surface of the vertical channel 2101.

[0110] In addition, the gate dielectric layer 2102 and the first signal line 2103 continuously cover multiple vertical channels 2101, and the portion of the first isolation barrier 211 between the multiple vertical channels 2101 means that along the Y direction in Figure 2, the gate dielectric layer 2102 and the first signal line 2103 are continuous film layers, that is, the gate dielectric layer 2102 and the first signal line 2103 cover the portion of the vertical channel 2101, and the gate dielectric layer 2102 and the first signal line 2103 cover the portion of the first isolation barrier 211 between two adjacent vertical channels 2101 are connected.

[0111] Based on this, continuing with FIG. 2 , in the first transistor column 221, a vertical channel 2101, a portion of the gate dielectric layer 2102 surrounding the vertical channel 2101 on three sides, and a first signal line 2103 can constitute a first vertical transistor T1. Therefore, the first transistor column 221 can include a plurality of first vertical transistors T1 located on one side of the first isolation barrier 211 and spaced apart along the second direction Y. Similarly, in the second transistor column 222 in FIG. 2 , a vertical channel 2101, a portion of the gate dielectric layer 2102 surrounding the vertical channel 2101 on three sides, and a first signal line 2103 can constitute a second vertical transistor T2. Therefore, the second transistor column 222 can include a plurality of second vertical transistors T2 located on the other side of the first isolation barrier 211 and spaced apart along the second direction Y. The first vertical transistor T1 and the second vertical transistor T2 are respectively disposed on either side of the first isolation barrier 211. The first vertical transistor T1 and the second vertical transistor T2 can be field effect transistors (FETs). In addition, it can be seen from the above that the vertical channel 2101 is a nanowire, so the first vertical transistor T1 and the second vertical transistor T2 can also be called vertical nanowire transistors (VNWFETs).

[0112] In other embodiments of the present application, as shown in FIG2 , a chip 20 is provided. As described above, the chip 20 may include a substrate 200 and a plurality of array structures 21 disposed on the substrate 200. Each array structure 21 includes: a first isolation barrier 211, a first transistor column 221, and a second transistor column 222. The first transistor column 221 and the second transistor column 222 may each include a plurality of vertical channels 2101, a gate dielectric layer 2102, and a first signal line 2103. The configuration of the vertical channels 2101, the gate dielectric layer 2102, and the first signal line 2103 is the same as described above and will not be repeated here.

[0113] As can be seen from the above, the first signal line 2103 can wrap around the vertical channel 2101 on three sides, and the first signal line 2103 continuously covers multiple vertical channels 2101, as well as portions of the first isolation barrier 211 between the multiple vertical channels 2101. In the first transistor column 221, a vertical channel 2101, a portion of the gate dielectric layer 2102 wrapping around the vertical channel 2101 on three sides, and the first signal line 2103 can form a first vertical transistor T1. In the second transistor column 222, a vertical channel 2101, a portion of the gate dielectric layer 2102 wrapping around the vertical channel 2101 on three sides, and the first signal line 2103 can form a second vertical transistor T2.

[0114] Based on this, the first signal line 2103 can serve as the gates of multiple transistors in the first transistor column 221 or the second transistor column 222. For example, the first signal line 2103 in the first transistor column 221 can serve as the gates of multiple first vertical transistors T1 in the first transistor column 221. Similarly, the first signal line 2103 in the second transistor column 222 can serve as the gates of multiple second vertical transistors T2 in the second transistor column 222. Specifically, the portion of the first signal line 2103 that surrounds a vertical channel 2101 on three sides serves as the gate of a first vertical transistor T1 or a second vertical transistor T2 having the vertical channel 2101.

[0115] In this case, the vertical channels 2101 of the first vertical transistor T1 and the second vertical transistor T2 are both surrounded on three sides by the first signal line 2103 serving as the gate. Therefore, in the first vertical transistor T1 and the second vertical transistor T2, the first signal line 2103 serving as the gate can be called a tri-gate structure, and the vertical channel 2101 can also be called a gate all around (GAA).

[0116] In some embodiments of the present application, the first transistor column 221 and the second transistor column 222 may be symmetrically arranged with respect to the first isolation barrier 211. In this case, a first vertical transistor T1 in the first transistor column 221 and a second vertical transistor T2 in the second transistor column 222 may be symmetrically arranged with respect to the first isolation barrier 211. This allows the structure of the chip 20 to have a certain regularity. When fabricating the chip 20 using a patterning process, fabricating a patterned structure having this regularity can simplify the manufacturing process.

[0117] In the embodiments of the present application, the patterning process may include a photolithography process, or a photolithography process and an etching step, and may also include other processes such as printing and inkjet printing for forming a predetermined pattern. The photolithography process refers to a process that uses photoresist, a mask, an exposure machine, and the like to form a pattern, including film formation, exposure, and development processes. The corresponding patterning process can be selected based on the structure formed in the present application.

[0118] In addition, as shown in Figure 5, part of the first signal line 2103 in the first vertical transistor T1 (as shown in Figure 2) can serve as the gate (gate, G) of the first vertical transistor T1, and part of the first signal line 2103 in the second vertical transistor T1 (as shown in Figure 2) can serve as the gate G of the second vertical transistor T2. In addition, any one of the above-mentioned first vertical transistor T1 and second vertical transistor T2 may further include a first electrode, such as a source (source, S), and a second electrode, such as a drain (drain, D), as shown in Figure 6 (a cross-sectional view taken along the dotted line O1-O2 in Figure 5). For the sake of convenience, the following examples are all taken as examples in which the first electrode in the transistor is the source S and the second electrode is the drain D. In other embodiments of the present application, the first electrode may be the drain D and the second electrode may be the source S.

[0119] Based on this, as shown in Figure 6, the first electrode (for example, the source S) can be arranged on the side of the vertical channel 2101 facing the substrate 200, and the second electrode (for example, the drain D) can be on the side of the vertical channel 2101 away from the substrate 200. In this case, a voltage can be applied to the first electrode (for example, the source S) and the second electrode (for example, the drain D) so that a conduction current (or an on-state current) flows through the vertical channel 2101. At this time, the first vertical transistor T1 and the second vertical transistor T2 can be in a conducting state (or an on-state, referred to as an on-state). Alternatively, when no conduction current flows through the vertical channel 2101, the first vertical transistor T1 and the second vertical transistor T2 can be in a cut-off state.

[0120] For example, in the first vertical transistor T1 or the second vertical transistor T2, the first electrode (e.g., source S), the second electrode (e.g., drain D), and the vertical channel 2101 can be connected to form an integrated structure. During the manufacturing process, a columnar intrinsic semiconductor structure can be formed on the sidewalls of the first isolation barrier 211, and ion doping is performed on both ends of the semiconductor structure facing toward and away from the substrate 200 to form the first electrode (e.g., source S) and the second electrode (e.g., drain D). In addition, the undoped portion between the first electrode (e.g., source S) and the second electrode (e.g., drain D) can form the vertical channel 2101.

[0121] In summary, in the chip 20 shown in FIG. 2 provided by an embodiment of the present application, on the one hand, the first isolation barrier 211 is located between the first transistor column 221 and the second transistor column 222, and in any of the first transistor column 221 and the second transistor column 222, the first signal line 2103 is arranged on the side of the gate dielectric layer 2102 or the vertical channel 2101 facing away from the first isolation barrier 211. Therefore, the vertical channel 2101 and the portion of the first signal line 2103 that wraps around the vertical channel 2101 can constitute a vertical transistor (for example, the first vertical transistor T1 or the second vertical transistor T2 shown in FIG. 5 ). The portion of the first signal line 2103 that wraps around the vertical channel 2101 can serve as the gate of the vertical transistor. Because the side of the vertical channel 2101 of the vertical transistor facing the first isolation barrier 211 is located on the sidewall of the first isolation barrier 211, no gate is provided on the side of the vertical channel 2101 facing the first isolation barrier 211. In this way, along the first direction X, the vertical transistor is provided with a gate only on one side, so that the chip 20 has miniaturization in the first direction X.

[0122] On the other hand, as shown in FIG2 , the vertical channel 2101 of the vertical transistor can be located on the sidewall of the first isolation barrier 211. The first isolation barrier 211 can support the vertical channel 2101, thereby reducing the processing difficulty of reducing the thickness of the vertical channel 2101 along the first direction X, thereby improving the scalability of the vertical transistor. For example, the size of the vertical transistor can be miniaturized to 45nm or below 40nm, so that the size of the chip 20 having the vertical transistor can be effectively reduced to 6F. 2 ~4F 2 Among them, the minimum processing size of semiconductor is F.

[0123] On the other hand, as shown in Figure 2, the first signal line 2103 wraps the vertical channel on three sides to provide three-dimensional coverage of the first signal line 2103 on three sides, so that the electric field lines of the vertical transistor are more concentrated, which is beneficial to improving the gate control capability and on-state current of the vertical transistor, thereby achieving the purpose of improving the performance of the vertical transistor, thereby improving the performance of the vertical transistor and the chip 20 while meeting the miniaturization requirements of components of electronic equipment.

[0124] For example, the on-state current of the first vertical transistor T1 or the second vertical transistor T2 may be 100nA to 1000μA. The off-state leakage current of the first vertical transistor T1 or the second vertical transistor T2 may be 0.1fA to 100pA. The gate turn-on voltage of the first vertical transistor T1 or the second vertical transistor T2 may be 1V to 5V. The gate threshold voltage of the first vertical transistor T1 or the second vertical transistor T2 may be -0.5V to 0.7V.

[0125] Furthermore, the gate dielectric layer 2102 and the first signal line 2103 can both continuously cover the plurality of vertical channels 2101 and portions of the first isolation barrier 211 between the plurality of vertical channels 2101. Therefore, along the direction in which the plurality of vertical channels 2101 are arranged (i.e., the second direction Y), the gate dielectric layer 2102 and the first signal line 2103 are both continuous structures. This allows, during the manufacturing process, the plurality of vertical channels 2101, arranged in intervals, to be formed on both sides of the first isolation barrier. Subsequently, the gate dielectric layer 2102 and the first signal line 2103 can be sequentially formed on the side of any row of the plurality of vertical channels 2101 facing away from the first isolation barrier 211, thereby simplifying the manufacturing process.

[0126] In an embodiment of the present application, the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 can be prepared using a front-end of line (FEOL) process or a back-end of line (BEOL) process, which is not limited in this application. For example, when the first vertical transistor T1 or the second vertical transistor T2 is prepared using a front-end process, the substrate 200 of the chip 20 can be a silicon substrate or a sapphire substrate of a wafer. In addition, when the first vertical transistor T1 or the second vertical transistor T2 is prepared using a back-end process, the substrate 200 can be made on a wafer.

[0127] As can be seen from the above, the chip 20 in FIG2 can be the aforementioned logic chip. In this case, the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 can be manufactured using the aforementioned front-end process. Alternatively, when the chip 20 in FIG2 is the aforementioned memory chip, the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 can be manufactured using either the front-end process or the back-end process.

[0128] Based on this, when the first vertical transistor T1 or the second vertical transistor T2 in the chip 20 is manufactured using a back-end process, the semiconductor material used for the vertical channel 2101 of the vertical transistor is polycrystalline silicon (poly-silicon, Poly-Si), which has a reduced mobility compared to the vertical transistor manufactured using single crystal silicon in the front-end process. However, as can be seen from the above, the vertical transistor in the chip 20 shown in Figure 2 has a high gate control capability and on-state current. Therefore, even if the vertical transistor is manufactured using a back-end process, a high-performance chip 20 can still be obtained.

[0129] The following is an example of the structure of the memory chip, taking the above-mentioned chip 20 as an example of a memory chip. In this case, the memory chip in the above-mentioned electronic device 01 provided in an embodiment of the present application can be a memory chip, such as the first RAM 132 or the second RAM 103 in Figure 1. This application does not limit the application scenario of the above-mentioned memory chip. In some embodiments of the present application, as shown in Figure 7, the above-mentioned chip 20 may further include a capacitor array 22, which may be arranged on the side of the array structure 21 away from the substrate 200, and the capacitor array 22 is electrically connected to at least one of the first transistor column 221 or the second transistor column 222 to form a memory array 30. The above-mentioned capacitor array 22 may include a plurality of storage capacitors C arranged in an array.

[0130] 8 , when the chip 20 is a memory chip, the chip 20 may further include a controller 31 electrically connected to the plurality of memory arrays 30. The controller 31 may be used to control read and write operations of the memory arrays 30 to enable access to the memory arrays 30.

[0131] For example, in the chip 20 described above, the memory array 30 and the controller 31 can be two independent chips. The memory array 30 and the controller 31 can be separately disposed on a carrier board (e.g., a packaged transistor chain or an adapter board), and the memory array 30 and the controller 31 are electrically connected to the carrier board. In this way, the memory array 30 and the controller 31 can achieve signal transmission through metal traces within the carrier board. Based on this, the chip 20 having the memory array 30 described above can be called a stand-alone memory chip.

[0132] Alternatively, as another example, in the above-mentioned chip 20, the storage array 30 and the controller 31 can be two independent chips, and the storage array 30 and the controller 31 are stacked on the above-mentioned carrier board. The storage array 30 and the controller 31 can be electrically connected through silicon vias (TSV) or redistribution layers (RDL), so that the storage array 30 and the controller 31 can transmit signals with the carrier board. Similarly, the chip 20 having the above-mentioned storage array 30 is the above-mentioned independent storage chip. Alternatively, as another example, in the above-mentioned chip 20, the storage array 30 and the controller 31 can be integrated into the same chip, and the integrated chip can be electrically connected to the above-mentioned carrier board. Based on this, the chip 20 having the above-mentioned storage array 30 can be called an embedded storage chip.

[0133] On this basis, as shown in FIG9 , the memory array 30 may include a plurality of memory cells 300 , wherein each memory cell 300 may be used to store 1 bit or multiple bits of data. For example, when the memory array 30 is mainly composed of the capacitor array 22 and the array structure 21 (including the first transistor column 221 and the second transistor column 222 ) shown in FIG7 , the memory cell 300 shown in FIG9 may include a first vertical transistor T1 and a storage capacitor C electrically connected to the first vertical transistor T1 as shown in FIG10 . Alternatively, the memory cell 300 may include a second vertical transistor T2 and a storage capacitor C electrically connected to the second vertical transistor T2 as shown in FIG10 .

[0134] For example, the storage capacitor C shown in Figure 7 or Figure 10 is a columnar capacitor, and the columnar capacitor can be a cube as shown in Figure 7. Or the columnar capacitor can be a cylinder. The present application does not limit the shape of the columnar capacitor. In addition, as shown in Figure 10, the columnar storage capacitor C can include a bottom electrode (BE) 41, a top electrode (TE) 43 and a dielectric layer 42. At least a portion of the top electrode 43 is disposed in the bottom electrode 41. At least a portion of the dielectric layer 42 is disposed in the bottom electrode 41, and the dielectric layer 42 is located between the bottom electrode 41 and the top electrode 43. In some embodiments of the present application, the material of the bottom electrode 41 or the top electrode 43 can include at least one of tungsten (W), titanium nitride (TiN), and molybdenum (Mo).

[0135] In some embodiments of the present application, the dielectric layer 42 may be a ferroelectric thin film layer, or a ferroelectric insulator layer. In this case, the storage capacitor C may be a ferroelectric capacitor (FeCAP), and the chip 20 having the ferroelectric capacitor may be a ferroelectric random access memory (FeRAM or FRAM).

[0136] Alternatively, in other embodiments of the present application, the dielectric layer 42 may be a resistive switching layer. In this case, the storage capacitor C may be a resistive switching capacitor, and the chip 20 having the resistive switching capacitor may be a resistive random access memory (RRAM). Alternatively, in other embodiments of the present application, the dielectric layer 42 may be a phase change material layer. In this case, the chip 20 may be a phase change memory (PCM).

[0137] In the memory cell 300, the bottom electrode (i.e., bottom electrode 41) of the storage capacitor C can be electrically connected to the second electrode of the first vertical transistor T1 or the second vertical transistor T2, such as the drain D. The top electrodes 43 of different memory cells 300 can be electrically connected through a signal line SL. The memory cell 300 shown in Figure 10 is illustrated by taking the 1T1C (one transistor and one capacitor) shown in Figure 11, i.e., one transistor T (e.g., the first vertical transistor T1 or the second vertical transistor T2) and one storage capacitor C as an example. The embodiment of the present application does not limit the number of transistors and storage capacitors C in the memory cell 300. For example, the above-mentioned memory cell 300 can also be a 2T1C (two transistors and one capacitor) or a 2T0C (two transistors and zero capacitor) structure.

[0138] Continuing with FIG11 , it can be seen from the above that the control terminal (e.g., gate) of transistor T can be electrically connected to the first signal line 2103 shown in FIG2 , which can serve as a word line (WL). The first electrode (e.g., source S) of transistor T can be electrically connected to a second signal line, such as a bit line (BL), and the top electrode 43 of storage capacitor C (as shown in FIG10 ) is electrically connected to the signal line SL. One or more of the above WL, BL, and SL are used to select the memory cell 300 to be read or written in the memory array 30 by receiving the control level output by the control circuit, so as to change the polarization direction of the storage capacitor C in the memory cell 300, thereby realizing the data read and write operation.

[0139] In some other embodiments of the present application, the storage capacitor C in the storage unit 300 can be replaced with a magnetic tunnel junction (MTJ), and the chip 20 having the MTJ can be a magnetoresistive random access memory (MRAM). Alternatively, in some other embodiments of the present application, the storage capacitor C in the storage unit 300 can be replaced with.

[0140] In addition, the controller 31 shown in FIG8 may include one or more of the circuit structures shown in FIG9 , including the decoder 311, driver 312, timing controller 313, buffer 314, or input / output driver 315. The decoder 311 is used to decode the address of the storage unit 300. The decoder 311 decodes the received address to determine the storage unit 300 to be accessed. The driver 312 controls the level of the signal line based on the decoding result generated by the decoder 311, thereby enabling access to the specified storage unit 300. The buffer 314 caches read data, for example, using a first-in, first-out (FIFO) cache. The timing controller 313 controls the timing of the buffer 314 and the timing of the driver 312 driving the signal lines in the storage unit 300. The input / output driver 315 drives transmission signals, such as received data signals and transmitted data signals, to enable long-distance transmission of the data signals. The memory array 30 , decoder 311 , driver 312 , timing controller 313 , buffer 314 and input / output driver 315 may be integrated into one chip or integrated into multiple chips.

[0141] In the case where the chip 20 is a memory chip, the first electrode (e.g., source S) of the first vertical transistor T1 or the second vertical transistor T2 shown in FIG10 may be electrically connected to the second signal line, e.g., BL, shown in FIG11 . Based on this, in some embodiments of the present application, when the chip 20 is manufactured using a front-end process, the first vertical transistor T1 or the second vertical transistor T2 may be formed on the substrate 200 first, and then the second signal line, e.g., BL, may be formed.

[0142] Alternatively, in other embodiments of the present application, when the chip 20 is manufactured using a back-end process, as shown in FIG12 , a second signal line 2104, such as BL, may be first fabricated on the substrate 200, and then the first vertical transistor T1 or the second vertical transistor T2 may be fabricated. The following describes an example of a method for fabricating the chip 20 shown in FIG12 . The aforementioned fabrication method may include steps S101 to S104 as shown in FIG13 .

[0143] S101 , forming a plurality of first isolation barriers arranged at intervals along a first direction on a substrate.

[0144] For example, as shown in FIG14 , a first metal material layer 51 and a semiconductor material layer 52 are first formed sequentially on a substrate 200. Next, an etching process can be used on the semiconductor material layer 52 to remove portions of the first metal material layer 51 and the semiconductor material layer 52 shown in FIG14 , thereby forming a plurality of second grooves 502 extending along the first direction X as shown in FIG15 . The bottoms of the second grooves 502 can expose the upper surface of the substrate 200. At this point, the portion of the metal material layer between two adjacent second grooves 502 can serve as a second signal line 2104 (e.g., BL in FIG11 ).

[0145] Then, a dielectric material can be deposited into the second recess 502 to form the third isolation barrier 213 as shown in FIG16A . The third isolation barrier 213 can be positioned between two adjacent second signal lines 2104, thereby isolating the adjacent second signal lines 2104. Furthermore, the third isolation barrier 213 can be made of a different material than the first isolation barrier 211 shown in FIG12 . For example, the first isolation barrier 211 can be made of silicon nitride, while the third isolation barrier 213 can be made of silicon oxide. Alternatively, the first isolation barrier 211 can be made of silicon oxide, while the third isolation barrier 213 can be made of silicon nitride. This ensures that the structure of the first isolation barrier 211 is not affected during the subsequent wet etching of the third isolation barrier 213. Consequently, as shown in FIG16B (a top view taken along direction B1 in FIG16A ), the semiconductor material layer 52 is separated into a plurality of strip-shaped structures by the plurality of third isolation barriers 213 extending along the first direction X.

[0146] Next, as shown in FIG17A , a first mask structure 53 is formed on the semiconductor material layer 52. As shown in FIG17B (a top view taken along direction B2 in FIG17A ), the hollowed-out portion of the first mask structure 53 exposes a portion of the semiconductor material layer 52 and a portion of the third isolation barrier 213. Then, a photolithography process is performed on the film layer below the first mask structure 53 using the first mask structure 53 as a mask to remove the semiconductor material layer 52 and the third isolation barrier 213 exposed by the first mask structure 53. This forms a plurality of third grooves 503 spaced apart along the first direction X, as shown in FIG18A . As shown in FIG18B (a top view taken along direction B3 in FIG18A ), the bottoms of the third grooves 503 expose portions of the second signal lines 2104 and the third isolation barrier 213 disposed between adjacent second signal lines 2104.

[0147] Next, a dielectric material can be deposited into the third recess 503 shown in FIG18A to form the first isolation walls 211 shown in FIG19A. As shown in FIG19B (a top view taken along direction B4 in FIG19A), the first isolation walls 211 are located in the hollowed-out portion of the first mask structure 53, so that the plurality of first isolation walls 211 are arranged at intervals along the first direction X and extend along the second direction Y.

[0148] S102 , forming transistor columns on both sidewalls of the first isolation barrier.

[0149] For example, the first mask structure 53 shown in FIG19A can be removed first, so that a portion of the first isolation barrier 211 shown in FIG20A is located within the semiconductor material layer 52 and the third isolation barrier 213, while another portion of the first isolation barrier 211 extends out of the semiconductor material layer 52 and the third isolation barrier 213. Based on this, as shown in FIG20B (a top view taken along direction B5 in FIG20A ), a portion of the semiconductor material layer 52 and a portion of the third isolation barrier 213 can be exposed between two adjacent first isolation barrier 211.

[0150] Next, as shown in FIG21A , a second mask structure 54 is formed on the sidewalls of the first isolation walls 211. As can be seen above, using the first mask structure 53 shown in FIG19A as a mask, the first isolation walls 211 shown in FIG21A are formed through photolithography and deposition processes. The dimensions, positions, and spacing between the first isolation walls 211 are highly accurate. Consequently, the second mask structure 54 formed on the sidewalls of the first isolation walls 211 can be self-aligned with the first isolation walls 211, thereby achieving a second mask structure 54 with high precision in dimensions, positions, and spacing.

[0151] Furthermore, as shown in FIG21B (a top view taken along direction B6 in FIG21A ), the hollowed-out portion of the second mask structure 54 can expose a portion of the semiconductor material layer 52 and a portion of the third isolation barrier 213. Subsequently, a photolithography process is performed on the film layer below the second mask structure 54 using the second mask structure 54 as a mask to remove the semiconductor material layer 52 and the third isolation barrier 213 exposed by the second mask structure 54. The remaining portion of the semiconductor material layer 52 can form a vertical channel 2101 as shown in FIG22A . The vertical channel 2101 is perpendicular to the substrate 200. Based on this, as shown in FIG22B (a top view taken along direction B7 in FIG22A ), a portion of the second signal line 2104 and the third isolation barrier 213 can be exposed between two adjacent second mask structures 54.

[0152] As can be seen from the above, the second mask structure 54 formed on the sidewall of the first isolation barrier 211 can be self-aligned with the first isolation barrier 211, thereby obtaining a second mask structure 54 with high precision in size, position, and spacing. In this case, by using the second mask structure 54 with high precision in size, position, and spacing as a mask, the size, position, and spacing of the formed vertical channels 2101 can also be highly precise.

[0153] Next, a chemical mechanical polishing (CMP) process can be used to remove the second mask structure 54 on top of the vertical trench 2101 and the portion of the first isolation barrier 211 protruding from the vertical trench 2101, so that the upper surface of the first isolation barrier 211 is flush with the upper surface of the vertical trench 2101, as shown in FIG23 . Next, as can be seen above, the first isolation barrier 211 and the third isolation barrier 213 are made of different materials. Therefore, a wet etching process can be used to remove the third isolation barrier 213 between two adjacent vertical trenches 2101, so that a gap is formed between the two adjacent vertical trenches 2101, as shown in FIG24A . Furthermore, in the aforementioned wet etching process, the third isolation barrier 213 can be retained between two adjacent second signal lines 2104 by controlling relevant wet etching process parameters, such as etching time.

[0154] Based on this, as shown in FIG24B (a top view taken along direction B8 in FIG24A ), a plurality of vertical channels 2101 spaced apart and arranged in a row along the second direction Y can be formed on two opposing sidewalls of the first isolation barrier 211. Furthermore, the vertical projection of a vertical channel 2101 on the substrate 200 in FIG24A can overlap with the vertical projection of a second signal line 2104 on the substrate 200.

[0155] On this basis, as shown in FIG25A , a gate dielectric layer 2102 is formed on the side of the multiple vertical channels 2101 facing away from the isolation barrier 211. As shown in FIG25B (a top view taken along direction B9 in FIG25A ), the gate dielectric layer 2102 wraps around the vertical channels 2101 on three sides and continuously covers the multiple vertical channels 2101 as well as portions of the first isolation barrier 211 between the multiple vertical channels 2101.

[0156] Next, as shown in FIG26A , a second metal material layer 55 is formed on a side of the gate dielectric layer 2102 facing away from the first isolation barrier 211. In some embodiments of the present application, as shown in FIG26B (a cross-sectional view taken along the dotted line O5-O6 in FIG26A ), the second metal material layer 55 may cover the gate dielectric layer 2102 with a uniform thickness at all locations.

[0157] Based on this, it can be seen from the above that the gate dielectric layer 2102 shown in FIG26A wraps around the vertical channels 2101 on three sides, and the gate dielectric layer 2102 continuously covers the multiple vertical channels 2101, as well as portions of the first isolation walls 211 between the multiple vertical channels 2101. Therefore, the second metal material layer 55 formed on the gate dielectric layer 2102 can be conformal to the gate dielectric layer 2102, that is, the second metal material layer 55 can have the same or approximately the same shape as the gate dielectric layer 2102. In this way, the second metal material layer 55 can also wrap around the vertical channels 2101 on three sides, and the gate dielectric layer 2102 continuously covers the multiple vertical channels 2101, as well as portions of the first isolation walls 211 between the multiple vertical channels 2101.

[0158] Next, as shown in FIG27 , the bottom of the portion of the second metal material layer 55 between two adjacent first isolation walls 211 is cut open to form a fourth recess 504. As shown in FIG3 (a top view taken along direction A in FIG27 ), the bottom of the fourth recess 504 may expose a portion of the gate dielectric layer 2102. In this case, the remaining portion of the second metal material layer 55 in FIG27 may form the first signal line 2103 in FIG3 . Because the second metal material layer 55 conforms to the gate dielectric layer 2102, the first signal line 2103 also conforms to the gate dielectric layer 2102, such that the first signal line 2103 wraps around the vertical channel 2101 on three sides and continuously covers multiple vertical channels 2101, as well as portions of the first isolation walls 211 between the multiple vertical channels 2101.

[0159] In this case, as shown in FIG28A , a vertical channel 2101 located on one side of the first isolation barrier 211, a portion of the gate dielectric layer 2102 surrounding the vertical channel 2101 on three sides, and a first signal line 2103 can constitute a first vertical transistor T1. The plurality of first vertical transistors T1 are arranged at intervals along the second direction Y to form a first transistor column 221. Furthermore, a vertical channel 2101 located on the other side of the first isolation barrier 211, a portion of the gate dielectric layer 2102 surrounding the vertical channel 2101 on three sides, and a first signal line 2103 can constitute a second transistor column 222. The plurality of second vertical transistors T2 are arranged at intervals along the second direction Y to form a second transistor column 222. The first transistor column 221 and the second transistor column 222 are respectively disposed on either side of the first isolation barrier 211.

[0160] As can be seen from the above, the size, position and spacing of the vertical channel 2101 can also have a high precision. Therefore, the size of the above-mentioned transistor column having the vertical channel 2101, such as the first transistor column 221 and the second transistor column 222, can also have a high precision, which can be beneficial to improving the miniaturization of the transistor column and the chip 20 having the transistor column.

[0161] S103: forming a second retaining wall between the array structures.

[0162] For example, as shown in FIG28A , a second isolation barrier 212 is formed on a substrate 200 having a plurality of array structures 21. A portion of the isolation barrier 212 covers the surface of the array structure 21 facing away from the substrate 200, and a portion is located between two adjacent array structures 21. Two adjacent first signal lines 2103 belonging to different array structures 21 are isolated and arranged on both sides of the second isolation barrier 212. Two adjacent vertical channels 2101 in different array structures 21 are isolated on both sides of the second isolation barrier 212. The second isolation barrier 212 can isolate two adjacent first signal lines 2103 in different array structures 21. In addition, the second isolation barrier 212 can also isolate two adjacent vertical channels 2101 in different array structures 21.

[0163] As can be seen from the above description, the first signal line 2103 continuously covers portions of the first isolation barrier 211 between the plurality of vertical channels 2101. Therefore, as shown in FIG28B (a top view taken along direction C1 in FIG28A ), the first signal line 2103 covers portions of the first isolation barrier 211, and a first groove 501 is formed on the side facing away from the first isolation barrier 211. A portion of the second isolation barrier 212 located between two adjacent array structures 21 is located within the first groove 501. In this case, the top view of the second isolation barrier 212 located between two adjacent array structures 21 in FIG28B can resemble a "N" shape.

[0164] S104 , forming metal contact electrodes on the array structure.

[0165] For example, as shown in FIG29A , first, the first signal line 2103 is etched to reduce its height along the third direction Z. Then, a plurality of metal contact electrodes 60 are formed on the plurality of array structures 21. Each metal contact electrode 60 can be electrically connected to a vertical transistor, such as the first vertical transistor T1 or the second vertical transistor T2. Furthermore, a second isolation barrier 212 is provided between the metal contact electrode 60 and the first signal line 2103.

[0166] For example, as shown in FIG29B (a cross-sectional view taken along the dashed line O7-O8 in FIG29A ), the second electrode of the first vertical transistor T1 or the second vertical transistor T2, such as the drain D (as shown in FIG10 ), is electrically connected to the metal contact electrode 60. In this case, as shown in FIG29C (a top view taken along the direction C2 in FIG29A ), a plurality of metal contact electrodes 60 can be arranged on the sidewalls of the first isolation barrier 211, spaced apart along the second direction Y.

[0167] As can be seen from the above, as shown in FIG26B , the second metal material layer 55 can cover the gate dielectric layer 2102 with uniform thickness throughout. Next, as shown in FIG27 , the bottom of the second metal material layer 55 between two adjacent first isolation walls 211 is cut off to form the first signal line 2103 shown in FIG29B . Therefore, two adjacent first signal lines 2103 belonging to different array structures 21 are separated by the second isolation wall 212 located between the two first signal lines 2103.

[0168] In other embodiments of the present application, two adjacent first signal lines 2103 (as shown in FIG. 29B ) belonging to different array structures 21 are connected to form a conductive integral structure 400 as shown in FIG. 30A , and the conductive integral structure 400 is filled between two adjacent rows of vertical channels 2101. In this case, as shown in FIG. 30B (a side view taken along direction C3 in FIG. 30A ), multiple vertical channels 2101 located in the same row along the second direction Y are covered by the conductive integral structure 400. Furthermore, as shown in FIG. 30A , a second isolation barrier 212 of the chip 20 can be disposed between two adjacent array structures 21, and the second isolation barrier 212 can be located on the side of the conductive integral structure 400 facing away from the substrate 200. The second isolation barrier 212 is used to isolate the portions of the vertical channels 2101 in the two adjacent array structures 21 that are not covered by the conductive integral structure 400.

[0169] In this case, as shown in FIG30C (a top view taken along the direction C4 in FIG30A ), the conductive integral structure 400 and the two oppositely disposed vertical channels 2101 surrounded on three sides by the conductive integral structure 400 can form a vertical transistor T with two channels. Compared to a vertical transistor with a single channel, the on-state current of the vertical transistor T with two channels can be doubled.

[0170] In order to manufacture the above-mentioned conductive integrated structure 400, as shown in Figure 30D (a cross-sectional view obtained by cutting along the dotted line P1-P2 in Figure 30A), after forming the gate dielectric layer 2102, the above-mentioned second metal material layer (the material for forming the conductive integrated structure 400) is formed on the gate dielectric layer 2102. The second metal material layer does not need to cover the gate dielectric layer 2102 with the same thickness, but is filled between two adjacent first isolation walls 211, and covers the surface of the gate dielectric layer 2102 facing away from the first isolation wall 211 and the substrate 200.

[0171] Next, the second metal material layer is etched back to form the conductive integral structure 400, so that the height of the conductive integral structure 400 along the third direction Z is less than the height of the second electrode of the vertical transistor, such as the drain D. In this way, after the metal contact electrode 60 is formed, the metal contact electrode 60 contacts the second electrode of the vertical transistor, such as the drain D, and the metal contact electrode 60 and the conductive integral structure 400 are separated by the second isolation barrier 212.

[0172] As can be seen from the above, in FIG22A , the second mask structure 54 is used as a mask pair to remove the semiconductor material layer 52 and third isolation barrier ribs 213 exposed by the second mask structure 54. The remaining portion of the semiconductor material layer 52 blocked by the second mask structure 54 can form a vertical channel 2101. Therefore, along the first direction X, the thickness of the second mask structure 54 is the same as the thickness of the vertical channel 2101. The vertical channel 2101 is a cubic structure perpendicular to the substrate 200. The following examples illustrate vertical channels 2101 of other shapes and methods for fabricating the same.

[0173] In other embodiments of the present application, as shown in FIG31 , the vertical channel 2101 may include a first portion 21011 and a second portion 21012. The first portion 21011 is arranged in a direction perpendicular to the substrate 200, and the second portion 21012 is connected to an end of the first portion 21011 facing the substrate 200. The second portion 21012 is arranged along the first direction X and contacts the second signal line 2104, so that the second portion 21012 can be electrically connected to the second signal line 2104. In this way, since the second portion 21012 is electrically connected to the second signal line 2104 and the second portion 21012 is arranged along the first direction X, the second portion 21012 can increase the contact area between the entire vertical channel 2101 and the second signal line 2104, thereby reducing the contact resistance.

[0174] In this case, as shown in FIG31 , the first portion 21011 and the second portion 21012 of the vertical channel 2101 can form an L-shaped structure. In some embodiments of the present application, as shown in FIG32 , the gate dielectric layer 2102 surrounding the L-shaped vertical channel 2101 on three sides can expose an end of the second portion 21012 facing away from the first isolation barrier 211. Furthermore, as shown in FIG33 , the first signal line 2103 covers the surface of the first portion 21011 facing away from the first isolation barrier 211. The first signal line 2103 also covers the surfaces of the first portion 21011 and the second portion 21012 that are perpendicular to the first isolation barrier 211 and the substrate 200. Therefore, as shown in FIG34A , the portion of the first signal line 2103 covering the second portion 21012 as viewed from the direction D1 resembles a horseshoe shape, thereby increasing the coverage area of ​​the first signal line 2103 and reducing the resistance of the first signal line 2103.

[0175] On this basis, as shown in FIG34B (a top view taken along direction D2 in FIG34A ), a gap exists between two first signal lines 2103 between adjacent first isolation walls 211, thereby enabling the multiple array structures 21 in FIG34A to be spaced apart along the first direction X. Furthermore, the surface of the first signal line 2103 facing away from the first isolation wall 211 is planar. Specifically, as shown in FIG34C (a cross-sectional view taken along dashed line P3-P4 in FIG34A ), the surface of the first signal line 2103 facing away from the first isolation wall 211 is flush with the surface of the second portion 21012 of the vertical channel 2101 facing away from the first isolation wall 211, as well as the surface of the gate dielectric layer 2102 facing away from the first isolation wall 211.

[0176] Based on this, after forming the first mask structure 53 (as shown in Figure 19A), forming a plurality of vertical channels 2101 spaced apart along the second direction Y on the side wall of the first isolation barrier 211 shown in Figure 34C, and forming a gate dielectric layer 2102 and a first signal line 2103 may include: first, removing the first mask structure 53 (as shown in Figure 19A), and forming a second mask structure 54 on the side wall of the first isolation barrier 211 as shown in Figure 21A, removing a portion of the semiconductor material layer 52 and the third isolation barrier 213 exposed by the second mask structure 54 to form a plurality of U-shaped semiconductor structures.

[0177] Removing the portion of the semiconductor material layer 52 exposed by the second mask structure 54 means that the entire semiconductor material layer 52 exposed by the second mask structure 54 need not be etched. A portion of the semiconductor material layer 52 at the bottom remains, so that the unetched semiconductor material layer 52 forms the U-shaped semiconductor structure 520 shown in FIG. 35 . A portion of the U-shaped semiconductor structure 520 is arranged along the first direction X and is electrically connected to the second signal line 2104. This increases the contact area between the entire vertical channel 2101 and the second signal line 2104, thereby reducing contact resistance.

[0178] Next, as shown in Figure 35, a gate dielectric layer 2102 and a second metal material layer 55 are sequentially formed in the U-shaped semiconductor structure 520. As described above, the gate dielectric layer 2102 and the second metal material layer 55 both wrap the multiple U-shaped semiconductor structures 520 on three sides, and the gate dielectric layer 2102 and the second metal material layer 55 both continuously cover the U-shaped semiconductor structure 520, as well as part of the first isolation barrier 211 between the multiple U-shaped semiconductor structures.

[0179] Next, as shown in FIG35 , a third mask structure 56 is formed on the side of the U-shaped semiconductor structure 520 facing away from the substrate 200. Using the third mask structure 56 as a mask, a portion of the bottom of the U-shaped semiconductor structure 520 exposed by the third mask structure 56 is removed. The gate dielectric layer 2102 and a portion of the second metal material layer 55 covering the bottom of the U-shaped semiconductor structure 520 are also removed to form the L-shaped vertical channel 2101, gate dielectric layer 2102, and first signal line 2103 shown in FIG34C . In this way, using the third mask structure 56 as a mask, the L-shaped vertical channel 2101, gate dielectric layer 2102, and first signal line 2103 can be simultaneously formed through a photolithography process.

[0180] On this basis, a second isolation barrier 212 is formed as shown in FIG34C . Two adjacent first signal lines 2103 belonging to different array structures 21 (as shown in FIG34A ) are isolated and arranged on both sides of the second isolation barrier 212. Two vertical channels 2101 belonging to different array structures 21 are isolated on both sides of the second isolation barrier 212.

[0181] In other embodiments of the present application, as shown in FIG36 , when the vertical channel 2101 is L-shaped and the second portion of the vertical channel 2101 extending along the first direction X is covered by the gate dielectric layer 2102 on a side facing away from the first isolation barrier 211, two adjacent first signal lines 2103 (as shown in FIG34C ) belonging to different array structures 21 are connected to form a conductive integrated structure 400 as shown in FIG36 . The conductive integrated structure 400 is filled between two adjacent rows of L-shaped vertical channels 2101. The technical effects of the conductive integrated structure 400 are the same as those described above and will not be repeated here.

[0182] In some other embodiments of the present application, as shown in FIG37A , the vertical channel 2101 has a U-shaped structure. As shown in FIG37B (a cross-sectional view taken along the dashed line P5-P6 in FIG37A ), the second portions 21012 of two adjacent vertical channels 2101 are connected, so that the two connected vertical channels 2101 form a U-shaped structure.

[0183] Based on this, after forming the first mask structure 53 (as shown in Figure 19A), as shown in Figure 37A, a plurality of vertical channels 2101 arranged at intervals along the second direction Y are formed on the side wall of the first isolation barrier 211, including: removing the first mask structure 53 (as shown in Figure 19A), and forming a second mask structure 54 on the side wall of the first isolation barrier 211 as shown in Figure 21A, removing a portion of the semiconductor material layer 52 and the third isolation barrier 213 exposed by the second mask structure 54 to form a plurality of U-shaped vertical channels 2101.

[0184] On this basis, two adjacent first signal lines 2103 in FIG. 37B , belonging to different array structures 21 (as shown in FIG. 37A ), are connected to a conductive integrated structural member 400, which is filled between two adjacent rows of L-shaped vertical channels 2101. The technical effects of the conductive integrated structural member 400 are the same as those described above and will not be repeated here.

[0185] Furthermore, as shown in FIG37C (a side view taken along direction D3 in FIG37A ), the first signal line 2103 covers the surface of the first portion 21011 (shown in FIG37B ) facing away from the first isolation barrier 211. The first signal line 2103 also covers the surfaces of the first portion 21011 and the second portion 21012 that are perpendicular to the first isolation barrier 211 and the substrate 200. Therefore, the portion of the first signal line 2103 covering the second portion 21012 resembles a horseshoe shape. The technical effects of this horseshoe-shaped first signal line 2103 are the same as those described above and will not be further elaborated here.

Claims

1. A chip, characterized in that: include: substrate; A plurality of array structures are provided on the substrate, and the plurality of array structures are arranged at intervals along a first direction; Each of the array structures comprises: First isolation retaining wall; a first transistor column; A second transistor column, wherein the first isolation barrier is located between the first transistor column and the second transistor column; wherein the first transistor column and the second transistor column both include: A plurality of vertical channels are arranged on the sidewalls of the first isolation barrier at intervals along a second direction, and the vertical channels are vertically disposed on the substrate; the first direction intersects with the second direction and are both parallel to the substrate; a gate dielectric layer, wherein the gate dielectric layer wraps the vertical channels on three sides and continuously covers the plurality of vertical channels and a portion of the first isolation barrier wall between the plurality of vertical channels; A first signal line is located on a side of the gate dielectric layer away from the first isolation barrier wall. The first signal line wraps around the vertical channel on three sides and continuously covers the multiple vertical channels and a portion of the first isolation barrier wall between the multiple vertical channels.

2. The chip according to claim 1, characterized in that The vertical channel includes: The first part is arranged in a direction perpendicular to the substrate; a second portion connected to an end of the first portion facing the substrate, the second portion being arranged along the first direction; The chip further includes: A second signal line is provided between the array structure and the substrate, and extends along the first direction; the second signal line contacts the second portion.

3. The chip according to claim 2, characterized in that In different array structures, the second portions of two adjacent vertical channels are connected so that the two connected vertical channels form a U-shaped structure.

4. The chip according to claim 2 or 3, characterized in that: The chip includes a plurality of second signal lines; The chip further includes a third isolation barrier wall, which is disposed between two adjacent second signal lines. The third isolation barrier wall is made of a different material from the first isolation barrier wall.

5. The chip according to any one of claims 1 to 4, characterized in that: In different array structures, two adjacent first signal lines are connected to form a conductive integrated structure, and the conductive integrated structure is filled between two adjacent rows of vertical channels.

6. The chip according to claim 5, characterized in that The chip further includes: A second isolation barrier is provided between two adjacent array structures and is located on a side of the conductive integrated structure facing away from the substrate.

7. The chip according to claim 2, characterized in that The chip further includes: A second isolation barrier is provided between two adjacent array structures; two adjacent first signal lines of different array structures are isolated on both sides of the second isolation barrier; and two adjacent vertical channels of different array structures are isolated on both sides of the second isolation barrier; A surface of the first signal line facing away from the first isolation barrier wall is flush with a surface of the second portion facing away from the first isolation barrier wall and a surface of the gate dielectric layer facing away from the first isolation barrier wall.

8. The chip according to claim 7, characterized in that The first signal line covers a surface of the first portion facing away from the first isolation barrier wall, and surfaces of the first portion and the second portion that are perpendicular to the first isolation barrier wall and the substrate.

9. The chip according to claim 1, characterized in that The chip further includes: A second isolation barrier is provided between two adjacent array structures; two adjacent first signal lines of different array structures are isolated and provided on both sides of the second isolation barrier; The first signal line covers a portion of the first isolation barrier wall and has a first groove on a side away from the first isolation barrier wall; a portion of the second isolation barrier wall is located in the first groove.

10. The chip according to any one of claims 1 to 9, characterized in that: The first transistor column and the second transistor column are symmetrically arranged with respect to the first isolation barrier.

11. The chip according to any one of claims 1 to 9, characterized in that: The first transistor column and the second transistor column each further include: A first electrode is provided on a side of the vertical channel facing the substrate; The second electrode is arranged on a side of the vertical channel away from the substrate.

12. The chip according to any one of claims 1 to 11, characterized in that: The chip further includes: A capacitor array is provided on a side of the array structure facing away from the substrate. The capacitor array is electrically connected to at least one of the first transistor column or the second transistor column to form a storage array.

13. The chip according to claim 12, characterized in that The chip further includes: A controller is electrically connected to the storage array and is used to control the reading and writing of the storage array.

14. An electronic device, characterized in that: include: circuit boards; The chip according to any one of claims 1 to 13, wherein the circuit board is electrically connected to the chip.

15. A method for manufacturing a chip, characterized in that: include: forming a plurality of first isolation barriers arranged at intervals along a first direction on the substrate; Transistor columns are formed on both sidewalls of the first isolation barrier, including: forming a plurality of vertical channels spaced apart along a second direction on the sidewall, wherein the vertical channels are perpendicular to the substrate; The first direction intersects with the second direction, and both are parallel to the substrate; A gate dielectric layer is formed on a side of the plurality of vertical channels away from the isolation barrier wall; the gate dielectric layer wraps around the vertical channels on three sides, and the gate dielectric layer continuously covers the plurality of vertical channels and a portion of the first isolation barrier wall between the plurality of vertical channels; A first signal line is formed on a side of the gate dielectric layer away from the first isolation barrier wall; the first signal line wraps around the vertical channel on three sides, and the first signal line continuously covers the multiple vertical channels and a portion of the first isolation barrier wall between the multiple vertical channels.

16. The method for manufacturing a chip according to claim 15, wherein: The forming of a plurality of first isolation barriers spaced apart along a first direction on the substrate comprises: forming a semiconductor material layer on a substrate; forming a plurality of second grooves extending along the first direction on the semiconductor material layer, and forming third isolation walls in the second grooves, wherein the third isolation walls are made of a different material from the first isolation walls; forming a first mask structure on the semiconductor material layer; removing the semiconductor material layer and the third isolation barrier wall exposed by the first mask structure to form a plurality of third grooves spaced apart along the first direction; The first isolation retaining wall is formed in the third groove.

17. The chip manufacturing method according to claim 16, characterized in that: After forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewall includes: The first mask structure is removed, and a second mask structure is formed on the sidewalls of the first isolation barrier wall. The semiconductor material layer and the third isolation barrier wall exposed by the second mask structure are removed to form the vertical channel.

18. The method for manufacturing a chip according to claim 16, wherein: After forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewall includes: The first mask structure is removed, and a second mask structure is formed on the sidewall of the first isolation barrier wall. A portion of the semiconductor material layer and the third isolation barrier wall exposed by the second mask structure are removed to form a plurality of U-shaped vertical channels.

19. The method for manufacturing a chip according to claim 16, wherein: After forming the first mask structure, forming a plurality of vertical channels spaced apart along the second direction on the sidewall, and forming the gate dielectric layer and the first signal line includes: removing the first mask structure, forming a second mask structure on the sidewalls of the first isolation barrier, and removing a portion of the semiconductor material layer and the third isolation barrier exposed by the second mask structure to form a plurality of U-shaped semiconductor structures; forming a gate dielectric material layer and a second metal material layer in sequence within the U-shaped semiconductor structure, wherein the gate dielectric material layer and the second metal material layer each wrap around the plurality of U-shaped semiconductor structures on three sides, and the gate dielectric material layer and the second metal material layer each continuously cover the U-shaped semiconductor structure and portions of the first isolation barrier between the plurality of U-shaped semiconductor structures; A portion of the bottom of the U-shaped semiconductor structure is removed, and a portion of the gate dielectric material layer and the second metal material layer covering the bottom of the U-shaped semiconductor structure are removed to form the L-shaped vertical channel, the gate dielectric layer and the first signal line.

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