Clock signal processing system, method, and apparatus, and server

Abstract

The present application relates to the field of computer technology, and discloses a clock signal processing system, method, and apparatus, and a server. The system comprises an overclocking module, a non-overclocking module and a signal processor; the overclocking module is configured to generate an overclocked clock signal and send the overclocked clock signal to the signal processor; the non-overclocking module is configured to generate a non-overclocked clock signal and send the non-overclocked clock signal to the signal processor; and the signal processor is configured to select the overclocked clock signal or the non-overclocked clock signal as a target clock signal on the basis of current service information of a server, and send the target clock signal to a clock signal receiving end by means of an output end. According to the system provided by the solution, both the overclocking module and the non-overclocking module are provided in the system, and switching and output of overclocked clock signals and non-overclocked clock signals are realized by means of the signal processor on the basis of current service information of the server, so that the system is compatible with both overclocking and non-overclocking working modes, thereby meeting the needs of users.

Description

Clock signal processing system, method, device and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 30, 2024, with application number 202410130675.1, and entitled “A clock signal processing system, method, device and server”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a clock signal processing system, method, device and server. Background Art

[0004] At present, with the generation of massive data, servers have been applied to various fields. As the upper-level business development of big data, cloud computing and artificial intelligence becomes more and more complex, in order to improve the performance and energy efficiency of a single CPU (Central Processing Unit) of a server when dealing with complex applications, two technologies, overclocking and turbo frequency, have been developed.

[0005] In related technologies, overclocking and non-overclocking are usually implemented based on two sets of hardware architectures. Users can choose to deploy overclocking architecture or non-overclocking architecture on the server according to actual needs.

[0006] However, as user needs continue to change, some users require a server system that is compatible with both overclocking and non-overclocking. However, traditional hardware architecture cannot achieve compatibility between overclocking and non-overclocking.

[0007] Summary of the Invention

[0008] The present application provides a clock signal processing system, method, device and server to solve the defects of related technologies such as the inability to achieve a system compatible with overclocking and non-overclocking.

[0009] A first aspect of the present application provides a clock signal processing system, comprising: an overclocking module, a non-overclocking module, and a signal processor, wherein the output ends of the overclocking module and the non-overclocking module are both connected to the input end of the signal processor;

[0010] The overclocking module is configured to generate an overclocked clock signal and send the overclocked clock signal to the signal processor;

[0011] The non-overclocking module is configured to generate a non-overclocking clock signal and send the non-overclocking clock signal to the signal processor;

[0012] The signal processor is configured to select the overclocked clock signal or the non-overclocked clock signal as the target clock signal according to current service information of the server, and send the target clock signal to the clock signal receiving end through the output end.

[0013] In an optional embodiment, the signal processor includes an overclocking register;

[0014] The overclocking register is configured to record the clock signal requirement represented by the current service information of the server, so that the signal processor selects the overclocked clock signal or the non-overclocked clock signal as the target clock signal according to the clock signal requirement.

[0015] In an optional embodiment, the signal processor includes a demand detection process and a signal processing process, which are parallel processes. The demand detection process is used to obtain the current business information of the server in real time and determine the corresponding clock signal requirements; the signal processing process is used to monitor the overclocking register in real time to select the overclocked clock signal or the non-overclocked clock signal as the target clock signal based on the clock signal requirements currently recorded in the overclocking register.

[0016] In an optional implementation, the signal processor is configured to:

[0017] Obtaining current service information of the server;

[0018] Determining a clock signal requirement of the server according to the current service information;

[0019] The clock signal requirement is written into the overclocking register.

[0020] In an optional embodiment, a business information communication link is provided between the signal processor and the central processing unit CPU of the server;

[0021] The signal processor obtains the current service information sent by the CPU through the service information communication link.

[0022] In an optional embodiment, the service information communication link between the signal processor and the CPU of the server is constructed through an integrated south bridge;

[0023] A direct media interface DMI link is provided between the integrated south bridge and the CPU;

[0024] An enhanced serial peripheral interface (ESPI) link is provided between the integrated south bridge and the signal processor;

[0025] The service information communication link includes the DMI link and the peripheral component interconnect express channel ESPI link.

[0026] In an optional embodiment, the clock signal receiving end includes at least a CPU and a PCIe device of a server;

[0027] The output end of the signal processor is connected to the input end of the CPU and the input end of the PCIe device;

[0028] The signal processor is configured to fan out the target clock signal to an input terminal of the CPU and an input terminal of a PCIe device.

[0029] In an optional implementation, the PCIe device includes at least a graphics processing unit (GPU), a network card, and a solid-state drive.

[0030] In an optional embodiment, the overclocking module includes: an overclocking clock generator;

[0031] The overclocking clock generator is configured to obtain an initial clock signal, perform frequency multiplication processing on the initial clock signal to obtain a target clock signal, perform overclocking processing on the target clock signal to obtain an overclocked clock signal, and output the overclocked clock signal to send the overclocked clock signal to the signal processor.

[0032] In an optional embodiment, the overclocking module includes: a firmware memory, the firmware memory being connected to the overclocking clock generator via an I2C bus;

[0033] The firmware memory is configured to store the overclocking firmware of the overclocking clock generator;

[0034] The overclocking clock generator is configured to access the firmware memory to load the overclocking firmware after obtaining the target clock signal, and configure the overclocking clock generator to an overclocking mode based on the overclocking firmware, so that the overclocking clock generator overclocks the target clock signal in the overclocking mode to obtain an overclocked clock signal.

[0035] In an optional embodiment, the overclocking clock generator includes: an overclocking phase-locked loop controller;

[0036] The overclocking phase-locked loop controller is configured to perform frequency multiplication processing on the initial clock signal obtained by the overclocking clock generator to obtain a target clock signal.

[0037] In an optional embodiment, the non-overclocking module includes: a non-overclocking clock generator;

[0038] The non-overclocked clock generator is configured to obtain an initial clock signal, perform frequency multiplication on the initial clock signal to obtain a target clock signal, use the target clock signal as a non-overclocked clock signal, and output the non-overclocked clock signal to send the non-overclocked clock signal to the signal processor.

[0039] In an optional embodiment, the non-overclocked clock generator includes: a non-overclocked phase-locked loop controller;

[0040] The non-overclocked phase-locked loop controller is configured to perform frequency multiplication processing on the initial clock signal obtained by the non-overclocked clock generator to obtain a target clock signal.

[0041] In an optional embodiment, the system further comprises: an oscillator, wherein an output end of the oscillator is connected to an input end of the overclocking clock generator and an input end of the non-overclocking clock generator;

[0042] The oscillator is configured to generate the initial clock signal, so as to send the initial clock signal to the overclocking clock generator and the non-overclocking clock generator.

[0043] In an optional implementation, the signal processor includes an FPGA chip.

[0044] A second aspect of the present application provides a clock signal processing method, comprising:

[0045] Get the current business information of the server;

[0046] receiving an overclocked clock signal or a non-overclocked clock signal according to the current service information;

[0047] Using the overclocked clock signal or the non-overclocked clock signal as a target clock signal;

[0048] The target clock signal is sent to a clock signal receiving end.

[0049] In an optional implementation, the receiving the overclocked clock signal or the non-overclocked clock signal according to the current service information includes:

[0050] Determining a clock signal requirement of the server according to the current service information;

[0051] According to the clock signal requirement, a target uplink data link is selected to receive an overclocked clock signal or a non-overclocked clock signal based on the target uplink data link.

[0052] A third aspect of the present application provides a clock signal processing device, comprising:

[0053] The acquisition module is configured to obtain the current business information of the server;

[0054] a signal receiving module configured to receive an overclocked clock signal or a non-overclocked clock signal according to the current service information;

[0055] A selection module is configured to use the overclocked clock signal or the non-overclocked clock signal as a target clock signal;

[0056] The processing module is configured to send the target clock signal to a clock signal receiving end.

[0057] The fourth aspect of the present application provides a server, comprising: a clock signal processing system as described in the first aspect and various possible designs of the first aspect.

[0058] A fifth aspect of the present application provides an electronic device, comprising: at least one processor and a memory;

[0059] The memory stores computer-executable instructions;

[0060] The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the clock signal processing method described in the first aspect and various possible designs of the first aspect.

[0061] The sixth aspect of the present application provides a computer non-volatile readable storage medium, which stores computer execution instructions. When the processor executes the computer execution instructions, it implements the clock signal processing method described in the first aspect and various possible designs of the first aspect.

[0062] The technical solution of this application has the following advantages:

[0063] The present application provides a clock signal processing system, method, device and server, the system includes: an overclocking module, a non-overclocking module and a signal processor, the output ends of the overclocking module and the non-overclocking module are both connected to the input end of the signal processor; the overclocking module is configured to generate an overclocked clock signal and send the overclocked clock signal to the signal processor; the non-overclocking module is configured to generate a non-overclocked clock signal and send the non-overclocked clock signal to the signal processor; the signal processor is configured to select an overclocked clock signal or a non-overclocked clock signal as the target clock signal according to the current business information of the server, and send the target clock signal to the clock signal receiving end through the output end. The system provided by the above scheme realizes the switching and output of the overclocked clock signal and the non-overclocked clock signal based on the current business information of the server by setting the overclocking module and the non-overclocking module in the system at the same time, so that the system is compatible with both overclocking and non-overclocking working modes, thereby meeting the needs of users. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0065] FIG1 is a schematic diagram of the structure of a clock signal processing system provided in an embodiment of the present application;

[0066] FIG2 is a schematic diagram of the workflow of a signal processor provided in an embodiment of the present application;

[0067] FIG3 is a schematic diagram of the overall structure of a clock signal processing system provided in an embodiment of the present application;

[0068] FIG4 is a flow chart of a clock signal processing method according to an embodiment of the present application;

[0069] FIG5 is a schematic structural diagram of a clock signal processing device provided in an embodiment of the present application;

[0070] FIG6 is a schematic diagram of the structure of a server provided in an embodiment of the present application;

[0071] FIG7 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0072] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0073] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0074] In addition, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the following embodiments, "plurality" means more than two, unless otherwise explicitly defined.

[0075] In recent years, with the expansion of the application market and the generation of massive amounts of data, the complexity of big data, cloud computing, and artificial intelligence has increased. To improve the performance and energy efficiency of single CPUs when handling these complex applications, overclocking and turbo boosting technologies have been developed. These technologies automatically increase the operating frequency to boost speed, making it easier to handle demanding multitasking. When switching between tasks, if only the memory and hard drive are performing the primary work, the processor immediately switches to a power-saving mode. This ensures efficient energy use and significantly improves program speed. By intelligently increasing processor speed, performance is maximized based on application needs, increasing the operating frequency by up to 20% for optimal performance for high-load tasks. This maximizes performance to meet the needs of high-load applications. By allocating multiple threads to handle AI, physics simulation, and rendering, users can experience a smoother and more realistic video experience.

[0076] Due to different user needs, some users will use the turbo function to improve the upper-level application experience, while some users will use the overclocking function to improve the user experience. Since overclocking is achieved by increasing the CPU's external core clock frequency through external hardware settings, overclocking and non-overclocking are achieved through two sets of hardware systems in traditional designs. However, some customers need to use one system to be compatible with overclocking and non-overclocking, because some businesses need to use the overclocking function to run, and some businesses only need to use the non-overclocking function to run based on CPU performance and energy efficiency. Therefore, the switching of different businesses on the same server system requires the underlying 100Mhz clock signal to switch between overclocking and non-overclocking. Therefore, customers need to use a set of hardware systems at the bottom of the entire system to meet the overclocking and non-overclocking requirements of different application layer businesses in the same system. However, traditional hardware architecture cannot achieve compatibility between overclocking and non-overclocking.

[0077] In response to the above problems, an embodiment of the present application provides a clock signal processing system, method, device and server, the system includes: an overclocking module, a non-overclocking module and a signal processor, the output ends of the overclocking module and the non-overclocking module are both connected to the input end of the signal processor; the overclocking module is configured to generate an overclocked clock signal and send the overclocked clock signal to the signal processor; the non-overclocking module is configured to generate a non-overclocked clock signal and send the non-overclocked clock signal to the signal processor; the signal processor is configured to select an overclocked clock signal or a non-overclocked clock signal as the target clock signal according to the current business information of the server, and send the target clock signal to the clock signal receiving end through the output end. The system provided by the above scheme realizes the switching and output of the overclocked clock signal and the non-overclocked clock signal by simultaneously setting the overclocking module and the non-overclocking module in the system based on the signal processor according to the current business information of the server, so that the system is compatible with both overclocking and non-overclocking working modes, thereby meeting the needs of users.

[0078] The following optional embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The following describes the embodiments of the present application in conjunction with the accompanying drawings.

[0079] An embodiment of the present application provides a clock signal processing system configured to achieve compatibility between overclocking and non-overclocking.

[0080] As shown in Figure 1, it is a structural diagram of the clock signal processing system provided in an embodiment of the present application. The system includes: an overclocking module, a non-overclocking module and a signal processor. The output ends of the overclocking module and the non-overclocking module are both connected to the input end of the signal processor.

[0081] Among them, the overclocking module is configured to generate an overclocked clock signal and send the overclocked clock signal to the signal processor; the non-overclocking module is configured to generate a non-overclocked clock signal and send the non-overclocked clock signal to the signal processor; the signal processor is configured to select the overclocked clock signal or the non-overclocked clock signal as the target clock signal according to the current business information of the server, and send the target clock signal to the clock signal receiving end through the output end.

[0082] It should be noted that the current service information can at least indicate whether the server CPU is in a non-overclocking mode or an overclocking mode.

[0083] In some embodiments, the signal processor may actually first obtain the current service information of the server, and then select an uplink based on the current service information, such as selecting to connect to an overclocking module to receive an overclocked clock signal; or selecting to connect to a non-overclocking module to receive a non-overclocked clock signal.

[0084] In some embodiments, the signal processor includes an overclocking register; the overclocking register is set to record the clock signal requirements represented by the current business information of the server, so that the signal processor can select the overclocked clock signal or the non-overclocked clock signal as the target clock signal according to the clock signal requirements.

[0085] In some embodiments, the signal processor includes a demand detection process and a signal processing process, which are parallel processes. The demand detection process is used to obtain current service information of the server in real time, determine the corresponding clock signal requirements, and then write the obtained clock signal requirements into the overclocking register. The signal processing process is used to monitor the overclocking register in real time and, based on the clock signal requirements currently recorded in the overclocking register, use the overclocked clock signal or the non-overclocked clock signal as the target clock signal.

[0086] In some embodiments, the signal processor is configured to obtain current service information of the server; determine the clock signal requirement of the server based on the current service information; and write the clock signal requirement into the overclocking register.

[0087] The current service information at least includes the name of the service currently running on the CPU and the corresponding service attribute information.

[0088] In some embodiments, based on a preset overclocking service item table and current service information, it can be determined whether the service currently being run by the CPU needs to be run in overclocking mode. If it is determined that it needs to be run in overclocking mode, the clock signal requirement of the server is determined to be an overclocked clock signal, and the clock signal requirement is then written into an overclocking register. For example, when the clock signal requirement is an overclocked clock signal, "1" is written into the overclocking register, and when the clock signal requirement is a non-overclocked clock signal, "0" is written into the overclocking register. The default value of the overclocking register is "0", which instructs the signal processor to select the non-overclocked clock signal.

[0089] For example, as shown in FIG2 , which is a schematic diagram of the workflow of the signal processor provided in an embodiment of the present application, after the signal processor system is powered on, the code is first loaded from the internal configuration flash memory module (CompactFlash Module, CFM module) so that the signal processor can run the above-mentioned clock signal processing logic by running the loaded code. The signal processor reads the value of the overclock register (overclock) from the internal register for judgment. If overclock == 0, the non-overclocked clock signal output by the non-overclocked clock generator is selected and given to the clock signal receiving end; if overclock == 1, the overclocked clock signal output by the overclocked clock generator is selected and given to the clock signal receiving end.

[0090] In some embodiments, a service information communication link is provided between the signal processor and the CPU of the server; the signal processor obtains the current service information sent by the CPU through the service information communication link.

[0091] In some embodiments, the optional type of the service information communication link may be determined according to the CPU model, so that the CPU can send current service information to the signal processor through the service information communication link.

[0092] In some embodiments, the business information communication link between the signal processor and the CPU of the server is constructed through an integrated south bridge; a DMI (Direct Media Interface) link is provided between the integrated south bridge and the CPU; an ESPI (Enhanced Serial Peripheral Interface) link is provided between the integrated south bridge and the signal processor; the business information communication link includes a DMI link and an ESPI link.

[0093] The signal processor includes an FPGA (Field-Programmable Gate Array) chip.

[0094] In some embodiments, the integrated south bridge is referred to as PCH (Platform Controller Hub). If the CPU of this application does not have the PCH function, a business information communication link between the FPGA chip and the server's CPU can be constructed by adding an integrated south bridge.

[0095] It should be noted that to improve CPU operational stability, current service information can be set as the highest priority information. For example, if the CPU is currently operating in overclocked mode and the CPU is running services that only require non-overclocked clock signals, the CPU can interrupt the service information communication link to transmit the current service information to the PCH. The PCH then transmits the information to the FPGA chip via the ESPI link, causing the FPGA chip to switch to outputting non-overclocked clock signals.

[0096] In some embodiments, as shown in FIG3 , which is a schematic diagram of the overall structure of the clock signal processing system provided in an embodiment of the present application, the CPU and PCH are interconnected through a DMI link, and the PCH and FGPA chip are interconnected through an ESPI link.

[0097] In some embodiments, the clock signal receiving end includes at least a CPU and a PCIe (Peripheral Component Interconnect Express) device of the server; the output end of the signal processor is connected to the input end of the CPU and the input end of the PCIe device; the signal processor is configured to fan out the target clock signal to the input end of the CPU and the input end of the PCIe device.

[0098] Among them, PCIe devices include at least a GPU (Graphics Processing Unit), a network card and a solid-state drive, and the server's CPU and PCIe devices are connected via a PCIe link.

[0099] In some embodiments, a clock signal transmission link is provided between the output end of the signal processor and the input end of the CPU, and a clock signal transmission link is also provided between the output end of the signal processor and the input end of the PCIe device. The signal processor fans out the target clock signal to the input end of the CPU and the input end of the PCIe device through the clock signal transmission link.

[0100] It should be noted that the clock signal processing system provided in the embodiments of the present application can meet the switching requirements of different services on the same server system, requiring the underlying 100Mhz clock signal to switch between overclocking and non-overclocking. Therefore, users need to use a set of hardware systems at the bottom layer of the entire system to meet the overclocking and non-overclocking requirements of different application layer services in the same system. The system provided in the embodiments of the present application is low-cost to implement, requiring only hardware and FPGA FW (Field-Programmable Gate Array Firmware) to cooperate in implementation. The hardware architecture is simple, maintenance and repair costs are low, and reliability is high. At the same time, the architecture is highly versatile and can be applied to server systems on platforms such as X86, ARM, and MIPS.

[0101] Based on the above embodiment, as an implementable manner, in one embodiment, the overclocking module includes: an overclocking clock generator.

[0102] Among them, the overclocking clock generator is configured to obtain an initial clock signal, multiply the initial clock signal to obtain a target clock signal, overclock the target clock signal to obtain an overclocked clock signal, and output the overclocked clock signal to send the overclocked clock signal to the signal processor.

[0103] In some embodiments, as shown in Figure 3, the overclocking clock generator first receives an initial clock signal of 25Mhz, multiplies the initial clock signal of 25Mhz into a target clock signal of 100Mhz by multiplying the initial clock signal, then overclocks the target clock signal to obtain an overclocked clock signal of 100Mhz, and finally sends the overclocked clock signal of 100Mhz to the signal processor.

[0104] In some embodiments, the overclocking module includes a firmware memory connected to the overclocking clock generator via an I2C bus. As shown in FIG3 , the firmware memory may be an EEPROM.

[0105] Among them, the firmware memory is configured to store overclocking firmware of the overclocking clock generator; the overclocking clock generator is configured to access the firmware memory to load the overclocking firmware after obtaining the target clock signal, and configure the overclocking clock generator to an overclocking mode based on the overclocking firmware, so that the overclocking clock generator overclocks the target clock signal in the overclocking mode to obtain an overclocked clock signal.

[0106] In some embodiments, the overclocking clock generator loads overclocking firmware from a firmware memory into the overclocking clock generator chip, and modifies the overclocking clock generator related registers based on the overclocking firmware to configure the overclocking clock generator to an overclocking mode, so that the overclocking clock generator can overclock the target clock signal to obtain an overclocked clock signal.

[0107] In some embodiments, the overclocking clock generator includes an overclocking phase-locked loop controller.

[0108] The overclocking phase-locked loop controller is configured to perform frequency multiplication processing on the initial clock signal obtained by the overclocking clock generator to obtain a target clock signal.

[0109] In some embodiments, the overclocking phase-locked loop controller is referred to as PLL, and the overclocking clock generator is based on the overclocking phase-locked loop controller to multiply the initial clock signal of 25 MHz into a target clock signal of 100 MHz.

[0110] Based on the above embodiment, as an implementable manner, in one embodiment, the non-overclocking module includes: a non-overclocking clock generator.

[0111] Among them, the non-overclocked clock generator is configured to obtain an initial clock signal, multiply the initial clock signal to obtain a target clock signal, use the target clock signal as a non-overclocked clock signal, output a non-overclocked clock signal, and send the non-overclocked clock signal to the signal processor.

[0112] In some embodiments, as shown in Figure 3, the non-overclocked clock generator first receives an initial clock signal of 25Mhz, multiplies the initial clock signal of 25Mhz into a target clock signal of 100Mhz by multiplying the initial clock signal, and finally sends the target clock signal of 100Mhz as a non-overclocked clock signal to the signal processor.

[0113] Accordingly, the non-overclocked clock generator includes: a non-overclocked phase-locked loop controller;

[0114] The non-overclocked phase-locked loop controller is configured to perform frequency multiplication processing on the initial clock signal obtained by the non-overclocked clock generator to obtain a target clock signal.

[0115] In some embodiments, the overclocked phase-locked loop controller is referred to as PLL, and the non-overclocked clock generator is based on the non-overclocked phase-locked loop controller to multiply the 25 MHz initial clock signal into a 100 MHz target clock signal.

[0116] In some embodiments, as shown in FIG3 , the system further includes: an oscillator, wherein an output end of the oscillator is connected to an input end of the overclocking clock generator and an input end of the non-overclocking clock generator.

[0117] The oscillator is configured to generate an initial clock signal, so as to send the initial clock signal to the overclocking clock generator and the non-overclocking clock generator.

[0118] The oscillator may be a 25 MHz crystal (quartz crystal oscillator), which is configured to provide a 25 MHz single-ended clock signal (initial clock signal) for the overclocked clock generator and the non-overclocked clock generator.

[0119] The clock signal processing system provided by the embodiment of the present application includes: an overclocking module, a non-overclocking module and a signal processor, the output ends of the overclocking module and the non-overclocking module are both connected to the input end of the signal processor; the overclocking module is configured to generate an overclocked clock signal and send the overclocked clock signal to the signal processor; the non-overclocking module is configured to generate a non-overclocked clock signal and send the non-overclocked clock signal to the signal processor; the signal processor is configured to select an overclocked clock signal or a non-overclocked clock signal as the target clock signal according to the current business information of the server, and send the target clock signal to the clock signal receiving end through the output end. The system provided by the above scheme realizes the switching and output of the overclocked clock signal and the non-overclocked clock signal based on the current business information of the server by simultaneously setting the overclocking module and the non-overclocking module in the system, so that the system is compatible with both overclocking and non-overclocking working modes, thereby meeting the needs of users. In addition, the bottom layer can implement different mode switching of the 100Mhz clock signal for different upper-layer services, thereby reducing the power consumption of the entire system while satisfying the customer experience of application-layer services, which can greatly reduce the customer's hardware costs. The system is low-cost to implement and only requires hardware and FPGA FW collaboration. It has a simple hardware architecture, low maintenance and repair costs, high reliability, and strong versatility.

[0120] The embodiment of the present application provides a clock signal processing method for providing a clock signal receiving end with a clock signal that conforms to the current service scenario of a server. The execution subject of the embodiment of the present application is an electronic device, such as an FPGA chip or other electronic device that can be used to implement clock signal processing.

[0121] FIG4 is a flow chart of a clock signal processing method according to an embodiment of the present application, which includes:

[0122] Step 401: Obtain the current service information of the server;

[0123] Step 402: receiving an overclocked clock signal or a non-overclocked clock signal according to current service information;

[0124] Step 403: Using the overclocked clock signal or the non-overclocked clock signal as the target clock signal;

[0125] Step 404: Send the target clock signal to the clock signal receiving end.

[0126] In some embodiments, the clock signal requirement of the server can be determined based on current business information; based on the clock signal requirement, the target uplink data link is selected to receive an overclocked clock signal or a non-overclocked clock signal based on the target uplink data link.

[0127] Among them, the target uplink data link refers to the data link connecting the overclocked clock signal sending end or the non-overclocked clock signal sending end. The FPGA chip selects the target clock signal by selecting the target uplink data link.

[0128] Regarding the clock signal processing method in this embodiment, the optional implementation methods of each step have been described in detail in the embodiment of the system and will not be elaborated here.

[0129] The clock signal processing method provided in the embodiment of the present application is used as the execution method of the clock signal processing system provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0130] An embodiment of the present application provides a clock signal processing device, which is configured to execute the clock signal processing method provided in the above embodiment.

[0131] As shown in FIG5 , which is a schematic diagram of the structure of a clock signal processing device provided in an embodiment of the present application, the clock signal processing device 50 comprises: an acquisition module 501 , a signal receiving module 502 , a selection module 503 and a processing module 504 .

[0132] Among them, the acquisition module is configured to obtain the current business information of the server; the signal receiving module is configured to receive an overclocked clock signal or a non-overclocked clock signal based on the current business information; the selection module is configured to use the overclocked clock signal or the non-overclocked clock signal as the target clock signal; the processing module is configured to send the target clock signal to the clock signal receiving end.

[0133] Regarding the clock signal processing device in this embodiment, the optional manners in which each module performs operations have been described in detail in the embodiment of the method and will not be elaborated on here.

[0134] The clock signal processing device provided in the embodiment of the present application is configured to execute the clock signal processing method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0135] An embodiment of the present application provides a server configured to deploy the clock signal processing system provided in the above embodiment.

[0136] As shown in FIG6 , it is a schematic diagram of the structure of a server provided in an embodiment of the present application, and the server includes the clock signal processing system provided in the above embodiment.

[0137] The clock signal processing system is configured to enable the server to achieve compatibility between overclocking and non-overclocking.

[0138] The server provided in the embodiment of the present application is configured to deploy the clock signal processing system provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0139] An embodiment of the present application provides an electronic device configured to execute the clock signal processing method provided in the above embodiment.

[0140] As shown in FIG7 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the electronic device 70 includes at least one processor 71 and a memory 72 .

[0141] The memory stores computer-executable instructions; and at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the clock signal processing method provided in the above embodiment.

[0142] The electronic device provided in the embodiment of the present application is configured to execute the clock signal processing method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0143] An embodiment of the present application provides a computer non-volatile readable storage medium, in which computer execution instructions are stored. When a processor executes the computer execution instructions, the clock signal processing method provided in any of the above embodiments is implemented.

[0144] The non-volatile readable storage medium containing computer-executable instructions provided in the embodiment of the present application can be configured to store computer-executable instructions of the clock signal processing method provided in the aforementioned embodiment. The implementation method and principle are the same and will not be repeated here.

[0145] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0146] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0147] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0148] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer non-volatile readable storage medium. The above-mentioned software functional unit is stored in a non-volatile readable storage medium, including a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute some steps of the methods of each embodiment of the present application. The aforementioned non-volatile readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc., various non-volatile readable storage media that can store program code.

[0149] Those skilled in the art will clearly understand that for the sake of convenience and brevity, the division of the above-mentioned functional modules is only used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The working process of the device described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A clock signal processing system, characterized in that: include: An overclocking module, a non-overclocking module and a signal processor, wherein the output ends of the overclocking module and the non-overclocking module are both connected to the input end of the signal processor; The overclocking module is configured to generate an overclocked clock signal and send the overclocked clock signal to the signal processor; The non-overclocking module is configured to generate a non-overclocking clock signal and send the non-overclocking clock signal to the signal processor; The signal processor is configured to select the overclocked clock signal or the non-overclocked clock signal as the target clock signal according to current service information of the server, and send the target clock signal to the clock signal receiving end through the output end.

2. The system according to claim 1, wherein: The signal processor includes: an overclocking register; The overclocking register is configured to record the clock signal requirement represented by the current service information of the server, so that the signal processor selects the overclocked clock signal or the non-overclocked clock signal as the target clock signal according to the clock signal requirement.

3. The system according to claim 2, characterized in that The signal processor includes a demand detection process and a signal processing process. The demand detection process and the signal processing process are parallel processes. The demand detection process is used to obtain the current business information of the server in real time and determine the corresponding clock signal requirements; the signal processing process is used to monitor the overclocking register in real time to select the overclocked clock signal or the non-overclocked clock signal as the target clock signal according to the clock signal requirements currently recorded in the overclocking register.

4. The system according to claim 2, wherein: The signal processor is configured to: Obtaining current service information of the server; Determining a clock signal requirement of the server according to the current service information; The clock signal requirement is written into the overclocking register.

5. The system according to claim 1, wherein: A service information communication link is provided between the signal processor and the central processing unit (CPU) of the server; The signal processor obtains the current service information sent by the CPU through the service information communication link.

6. The system according to claim 5, characterized in that The service information communication link between the signal processor and the CPU of the server is constructed through an integrated south bridge; A direct media interface DMI link is provided between the integrated south bridge and the CPU; An enhanced serial peripheral interface (ESPI) link is provided between the integrated south bridge and the signal processor; The service information communication link includes the DMI link and the ESPI link.

7. The system according to claim 1, wherein: The clock signal receiving end includes at least a CPU and a PCIe device of the server; The output end of the signal processor is connected to the input end of the CPU and the input end of a peripheral component interconnect express channel PCIe device; The signal processor is configured to fan out the target clock signal to an input terminal of the CPU and an input terminal of a PCIe device.

8. The system according to claim 7, characterized in that The PCIe device includes at least a graphics processing unit (GPU), a network card, and a solid-state hard disk.

9. The system according to claim 1, wherein: The overclocking module includes: an overclocking clock generator; The overclocking clock generator is configured to obtain an initial clock signal, perform frequency multiplication processing on the initial clock signal to obtain a target clock signal, perform overclocking processing on the target clock signal to obtain an overclocked clock signal, and output the overclocked clock signal to send the overclocked clock signal to the signal processor.

10. The system according to claim 9, characterized in that The overclocking module includes: a firmware memory, wherein the firmware memory is connected to the overclocking clock generator via an I2C bus; The firmware memory is configured to store the overclocking firmware of the overclocking clock generator; The overclocking clock generator is configured to access the firmware memory to load the overclocking firmware after obtaining the target clock signal, and configure the overclocking clock generator to an overclocking mode based on the overclocking firmware, so that the overclocking clock generator overclocks the target clock signal in the overclocking mode to obtain an overclocked clock signal.

11. The system according to claim 9, wherein: The overclocking clock generator includes: an overclocking phase-locked loop controller; The overclocking phase-locked loop controller is configured to perform frequency multiplication processing on the initial clock signal obtained by the overclocking clock generator to obtain a target clock signal.

12. The system according to claim 1, wherein: The non-overclocking module includes: a non-overclocking clock generator; The non-overclocked clock generator is configured to obtain an initial clock signal, perform frequency multiplication on the initial clock signal to obtain a target clock signal, use the target clock signal as a non-overclocked clock signal, and output the non-overclocked clock signal to send the non-overclocked clock signal to the signal processor.

13. The system according to claim 12, wherein: The non-overclocked clock generator includes: a non-overclocked phase-locked loop controller; The non-overclocked phase-locked loop controller is configured to perform frequency multiplication processing on the initial clock signal obtained by the non-overclocked clock generator to obtain a target clock signal.

14. The system according to claim 9 or 12, characterized in that The system further comprises: an oscillator, wherein an output end of the oscillator is connected to an input end of the overclocking clock generator and an input end of the non-overclocking clock generator; The oscillator is configured to generate the initial clock signal, so as to send the initial clock signal to the overclocking clock generator and the non-overclocking clock generator.

15. The system according to claim 1, wherein: The signal processor includes an FPGA chip.

16. A clock signal processing method, characterized in that: include: Get the current business information of the server; receiving an overclocked clock signal or a non-overclocked clock signal according to the current service information; Using the overclocked clock signal or the non-overclocked clock signal as a target clock signal; The target clock signal is sent to a clock signal receiving end.

17. The method according to claim 16, characterized in that The receiving the overclocked clock signal or the non-overclocked clock signal according to the current service information includes: Determining a clock signal requirement of the server according to the current service information; According to the clock signal requirement, a target uplink data link is selected to receive an overclocked clock signal or a non-overclocked clock signal based on the target uplink data link.

18. A clock signal processing device, characterized in that: include: The acquisition module is configured to obtain the current business information of the server; a signal receiving module configured to receive an overclocked clock signal or a non-overclocked clock signal according to the current service information; A selection module is configured to use the overclocked clock signal or the non-overclocked clock signal as a target clock signal; The processing module is configured to send the target clock signal to a clock signal receiving end.

19. A server, characterized in that: The method comprises the clock signal processing system according to any one of claims 1 to 15.

20. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the method according to claim 16 or 17.

21. A computer-readable non-volatile storage medium, characterized in that: The computer non-volatile readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the method according to claim 16 or 17 is implemented.

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