Time synchronization method, electronic device, and storage medium

Abstract

The present application relates to the technical field of wireless transmission. Disclosed are a time synchronization method, an electronic device, and a storage medium. The time synchronization method is applied to a slave device based on Bluetooth low energy (BLE) connectivity, and comprises: establishing a time synchronization channel with a master device; at a first moment, receiving and parsing a broadcast packet sent by the master device to acquire a system clock inserted into the broadcast packet by the master device for time synchronization; at a second moment, updating a system clock of the slave device on the basis of the system clock acquired by parsing; and sending a synchronization completion message to the master device. It can be seen from the description above that time synchronization between a master device and a slave device is realized on the basis of BLE, thereby reducing communication power consumption and costs on the basis of the advantages of BLE.

Description

Time synchronization method, electronic device and storage medium

[0001] This application is based on the Chinese patent application with application number "202410154837.5" and application date of February 4, 2024, and claims the priority of the above-mentioned Chinese patent application. The entire content of the above-mentioned Chinese patent application is hereby incorporated into this application by introduction. Technical Field

[0002] The present disclosure relates to the field of wireless transmission technology, and in particular to a time synchronization method, electronic equipment, and storage medium. Background Art

[0003] Bluetooth Low Energy (also known as Bluetooth LE, BLE, and formerly Bluetooth Smart), also known as Bluetooth Low Energy, is a personal area network technology designed and marketed by the Bluetooth Special Interest Group (SIG). It is intended for emerging applications in healthcare, fitness, beacons, security, home entertainment, and other fields. Compared to Classic Bluetooth, Bluetooth Low Energy aims to significantly reduce power consumption and cost while maintaining the same communication range.

[0004] Time synchronization is the process of maintaining a unified time scale for a distributed system by manipulating local clocks. In a centralized system, all processes or modules obtain their time from a single global clock, ensuring a clear order of events between any two events. However, in a distributed system, due to physical dispersion, a unified global clock cannot be provided for independent modules. Instead, each process or module maintains its own local clock. Due to inconsistencies in the timing rates and operating environments of these local clocks, even if all local clocks are aligned at a given moment, they can become inconsistent over time. Time synchronization is necessary to restore these local clocks to the same value.

[0005] How to use BLE to achieve time synchronization between devices is a technical problem that needs to be solved urgently. Summary of the Invention

[0006] The present disclosure provides a time synchronization method, an electronic device, and a storage medium, which implement clock synchronization between devices based on BLE to reduce communication power consumption and cost.

[0007] An embodiment of the present disclosure provides a time synchronization method, which is applied to a slave device interconnected based on low-power Bluetooth, including: establishing a time synchronization channel between the slave device and the master device; receiving and parsing a broadcast packet sent by the master device at a first moment to obtain a system clock inserted by the master device in the broadcast packet for time synchronization; updating its own system clock based on the system clock obtained by parsing at a second moment; and sending a synchronization completion message to the master device.

[0008] In a specific implementation scheme, the method for establishing a time synchronization channel with a master device includes: establishing a GATT connection with the master device; initiating a time synchronization request to the master device, and waiting for a response from the master device to establish the time synchronization channel.

[0009] In a specific possible implementation scheme, the synchronization completion message is sent at a third time, and the third time is obtained after a fixed delay from the first time.

[0010] In a specific embodiment, the difference between the first moment and the second moment is obtained based on a chip type of the slave device.

[0011] In a specific feasible implementation plan, before updating the own system clock based on the system clock obtained by analysis at the second moment, it also includes: obtaining a synchronization deviation clock based on the system clock obtained by analysis and the own clock; obtaining a crystal oscillator deviation value based on the synchronization deviation clock and the time synchronization interval between this time synchronization and the last time synchronization; after updating the own system clock, adjusting the system clock based on the crystal oscillator deviation value.

[0012] In a specific possible implementation scheme, before adjusting the system clock based on the crystal oscillator deviation value, the method further includes: smoothing the crystal oscillator deviation value.

[0013] Another embodiment of the present disclosure provides a time synchronization method, which is applied to a master device based on low-power Bluetooth interconnection, including: establishing a time synchronization channel between the master device and the slave device; inserting the system clock into the broadcast packet to be sent at a first initial moment; sending the broadcast packet to the slave device at a second initial moment; and waiting to receive a synchronization completion message sent by the slave device.

[0014] In a specific possible implementation scheme, the difference between the first initial time and the second initial time is obtained based on the chip type of the master device.

[0015] Another embodiment of the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the time synchronization method provided in the above embodiment.

[0016] Yet another embodiment of the present disclosure provides a storage medium storing a computer program, including: when the computer program is executed by a processor, implementing the time synchronization method provided in the above embodiment.

[0017] In the implementation of the present disclosure, time synchronization between a master device and a slave device is implemented based on BLE, thereby combining the advantages of BLE and reducing communication power consumption and costs. In addition, in some embodiments, the crystal oscillator of the slave device is adjusted to reduce the time synchronization frequency of the slave device, thereby further reducing communication power consumption and costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] FIG1 is a timing diagram of a single time synchronization method provided by an embodiment of the present disclosure;

[0020] FIG2 is a timing diagram of a multiple time synchronization method provided by an embodiment of the present disclosure;

[0021] FIG3 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. Modes for Carrying Out the Invention

[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0023] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0024] An embodiment of the present disclosure provides a time synchronization method, which is applied to slave devices interconnected based on low-power Bluetooth, and implements clock synchronization between devices based on BLE to reduce communication power consumption and cost.

[0025] Refer to FIG1 , which is a timing diagram of a single time synchronization method provided by an embodiment of the present disclosure. The time synchronization method is applied between at least two devices to make the clocks of the synchronized devices consistent.

[0026] Specifically, the time synchronization method is used to adjust the time of the synchronized device to be the same as the time of the synchronizer device.

[0027] It should be noted that in the subsequent description of this embodiment, the synchronizer is regarded as the master device 101, and the synchronized device is regarded as the slave device 102; in a single time synchronization process, the master device 101 can synchronize time with a single slave device 102, or can synchronize time with multiple slave devices 102 separately, and the interaction relationship between each slave device 102 and the master device 101 is shown in Figure 1.

[0028] For the slave device 102, during the time synchronization process, it is first necessary to establish a time synchronization channel with the master device 101, and the time synchronization channel is established based on BLE.

[0029] Specifically, slave device 102 requests a GATT connection from master device 101 to establish a GATT connection. GATT, short for Generic Atribute Profile, defines how two BLE devices communicate using services and characteristics. GATT uses the ATT (Atribute Profile) protocol, which stores service and characteristic data in a lookup table indexed by a 16-bit ID. Once a connection is established between two BLE devices, GATT becomes effective. It's important to note that GATT connections are exclusive. A slave device 102 can only be connected to one master device 101 at a time. Once a slave device 102 is connected, master device 101 immediately stops advertising, making it invisible to other slave devices. When slave device 102 disconnects, master device 101 resumes advertising. For bidirectional communication between master device 101 and slave device 102, establishing a GATT connection is the only way.

[0030] After establishing the GATT connection, the slave device 102 initiates a time synchronization request to the master device 101 and waits for a response from the master device 101 to establish a time synchronization channel. The time synchronization process between the master device 101 and the slave device 102 is completed based on the established time synchronization channel.

[0031] Specifically, at a first time T2, slave device 102 receives and parses the broadcast packet sent by master device 101 to obtain the system clock inserted by master device 101 for time synchronization. The system clock at this time is the first initial time T0 when the master device generated the broadcast packet. At a second time T3, slave device 102 updates its own system clock based on the parsed system clock and sends a synchronization completion message to master device 101.

[0032] The time difference between first time T2 and second time T3 is a third interval Δt3. This third interval Δt3 is the data processing time required for slave device 102 to parse the advertising packet and obtain the system time of master device 101. Different chips have different data processing efficiencies. That is, the difference between first time T2 and second time T3 is determined based on the chip type of slave device 102. Specifically, in some embodiments, the third interval Δt3 is measured and obtained by the BLE chip manufacturer. For the same chip model, the third interval Δt3 is the same.

[0033] At the second time T3, slave device 102 updates its own system clock based on the parsed system clock, changing its own system clock to T0 + Δt1 + Δt2 + Δt3, thereby achieving time synchronization between master device 101 and slave device 102. The time difference between the first initial time T0 and the second initial time T1 is the first interval Δt1. This first interval Δt1 represents the data processing time required for master device 101 to insert the system clock into the broadcast packet to be transmitted. Different chips have different data processing efficiencies, so the difference between the first initial time T0 and the second initial time T1 is determined based on the chip type of master device 101. Specifically, in some embodiments, the first interval Δt1 is measured and obtained by the BLE chip manufacturer. For the same chip model, the first interval Δt1 is the same. The second interval Δt2 represents the data transmission time of the broadcast packet and can be calculated based on the BLE protocol. In some embodiments, Δt2 = (1 + 4 + 2 + adv_len + 3) * 8us, where adv_len represents the data length of the broadcast packet.

[0034] In some embodiments, the slave device 102 sends a synchronization completion message at a third moment, and the third moment is obtained after the first moment has passed a fixed delay Δt4. In one example, the third moment is the first moment T2 + 150us, i.e., the fixed delay Δt4 = 150us; in other examples, the fixed delay Δt4 can be configured to be 130us, 170us, or 200us. Specifically, the fixed delay Δt4 can be configured to be any time after the slave device 102 completes time synchronization, i.e., the third moment can be configured to be any time node after the slave device 102 completes time synchronization.

[0035] Since time synchronization is relatively resource-intensive and the master device 101 and the slave device 102 that have already been synchronized cannot be synchronized frequently, ensuring the consistency of the system clock of the slave device 102 with the system clock of the master device 101 after synchronization can reduce the synchronization frequency of the master device 101 and the slave device 102, thereby further reducing communication power consumption and cost.

[0036] Specifically, the system time of the device is controlled by the crystal oscillator of the chip. The crystal oscillator deviation between the master device 101 and the slave device 102 accumulates over a long period of time and is reflected in the system time, resulting in a difference in the system time of the master device 101 and the slave device 102 after synchronization.

[0037] In some embodiments, referring to Figure 2, Figure 2 is a timing diagram of multiple time synchronization methods provided in an embodiment of the present disclosure. The time synchronization method includes: before updating its own system clock based on the system clock obtained by analysis at the second moment, it also includes: obtaining a synchronization deviation clock based on the system clock obtained by analysis and its own clock.

[0038] Specifically, as previously discussed, the principle of clock synchronization between master device 101 and slave device 102 is to synchronize the system clock of master device 101 with that of slave device 102. After the first clock synchronization, system clock A0 of master device 101 is synchronized with that of slave device 102, with slave device system clock B0 now equal to A0. The purpose of the second clock synchronization is to synchronize system clock A1 of master device 101 with that of slave device 102, with slave device 102 system clock B1 now equal to A1. Assuming that, before synchronization, A1 = A0 + Δta and B1 = B0 + Δtb during the second clock synchronization, the deviation between the system clocks of master device 101 and slave device 102 is Δtb - Δta. The synchronization deviation between master device 101 and slave device 102 is therefore Δtb - Δta.

[0039] It should be noted that if Δtb=Δta, there is no deviation in the system clocks between the master device 101 and the slave device 102, and there is no need to perform time synchronization.

[0040] As mentioned above, A1 = A0 + Δta, and B1 = B0 + Δtb. Therefore, during the current clock transmission process, the slave device can obtain Δta using the system clock in the broadcast packet of this clock synchronization and the system clock in the broadcast packet of the previous clock synchronization. It can also obtain Δtb based on the system clock after the last clock synchronization and the current system clock, thereby obtaining the synchronization deviation clock.

[0041] After obtaining the system deviation clock, slave device 102 calculates the crystal oscillator deviation value based on the synchronization deviation clock and the time synchronization interval between the current time synchronization and the previous time synchronization, where the time synchronization interval between the current time synchronization and the previous time synchronization is Δta. Therefore, the crystal oscillator deviation value = (Δtb - Δta) / Δta, which is used to measure the relative crystal oscillator deviation between master device 101 and slave device 102.

[0042] After updating the system clock, the slave device 102 adjusts the system clock based on the crystal oscillator deviation. Specifically, assuming that the time after the last time synchronization is T10, the relative crystal oscillator deviation is calculated to be slop. After ΔT time, the obtained time = T10-(ΔT*slop), so that the system clock changes of the master device 101 and the slave device 102 are relatively consistent, thereby reducing the frequency of time synchronization between the master device 101 and the slave device 102.

[0043] As shown in Figure 2, for synchronizations other than the first synchronization, such as the second and third synchronizations, a crystal oscillator offset value is obtained during each synchronization process to adjust the system clock. In some embodiments, before adjusting the system clock based on the crystal oscillator offset value, the crystal oscillator offset value is smoothed, i.e., the value is averaged based on the previous crystal oscillator offset value and the currently obtained crystal oscillator offset value. In one example, assume that after the second synchronization process, the crystal oscillator offset value is P2, and slave device 102 adjusts the system clock based on the crystal oscillator offset value P2. During the third synchronization process, the crystal oscillator offset value obtained is ΔP3. At this time, slave device 102 adjusts the system clock based on the crystal oscillator offset value P3 = (P2 + ΔP3) / 2. During the fourth synchronization process, the crystal oscillator offset value obtained is ΔP4. At this time, slave device 102 adjusts the system clock based on the crystal oscillator offset value P4 = (P3 + ΔP4) / 2.

[0044] It should be noted that in actual applications, the crystal oscillator deviation value is very small. Therefore, it can be expanded during the crystal oscillator deviation acquisition process and then reduced during system clock adjustment. For example, when acquiring the crystal oscillator deviation value, the crystal oscillator deviation value = (Δtb - Δta) / Δta * 0Xfffff. When adjusting the system clock based on the crystal oscillator deviation value, assuming the time after the last time synchronization is T10, the calculated relative crystal oscillator deviation is slop. After ΔT, the acquired time is T10 - (ΔT * slop / 0Xfffff).

[0045] By smoothing the crystal oscillator deviation value, the difference between the adjusted crystal oscillator of the slave device 102 and the crystal oscillator of the master device 101 is gradually reduced, thereby further reducing communication power consumption and cost.

[0046] In summary, the time synchronization method provided in this embodiment implements time synchronization between master device 101 and slave device 102 based on BLE, thereby combining the advantages of BLE to reduce communication power consumption and costs. Furthermore, in some embodiments, the crystal oscillator of slave device 102 is adjusted to reduce the time synchronization frequency of slave device 102, thereby further reducing communication power consumption and costs.

[0047] It should be noted that the features disclosed in the time synchronization method provided in the above embodiments can be arbitrarily combined without conflict to obtain a new time synchronization method embodiment.

[0048] Another embodiment of the present disclosure provides a time synchronization method, which is applied to a master device interconnected based on low-power Bluetooth, and implements clock synchronization between devices based on BLE to reduce communication power consumption and cost.

[0049] Continuing to refer to FIG1 , the master device 101 first needs to establish a time synchronization channel with the slave device 102 , and the time synchronization channel is established based on BLE.

[0050] Specifically, the master device 101 receives and responds to the GATT connection request of the slave device 102 to establish a GATT connection with the slave device 102; after the GATT connection is established, the master device 101 receives and responds to the time synchronization request initiated by the slave device 102 to establish a time synchronization channel. The time synchronization process between the master device 101 and the slave device 102 is completed based on the established time synchronization channel.

[0051] Specifically, the master device 101 inserts the current system clock into the broadcast packet to be sent at the first initial time T0, and sends the broadcast packet to the slave device 102 at the second initial time T1, and then waits to receive a synchronization completion message from the slave device 102.

[0052] The time difference between the first initial time T0 and the second initial time T1 is the first interval time Δt1. This first interval time Δt1 represents the data processing time required for master device 101 to insert the system clock into the advertising packet to be transmitted. Different chips have different data processing efficiencies, meaning the difference between the first initial time T0 and the second initial time T1 is determined based on the chip type of master device 101. Specifically, in some embodiments, the first interval time Δt1 is measured and obtained by the BLE chip manufacturer. For the same chip type, the first interval time Δt1 is the same. While master device 101 is waiting for slave device 102 to send a synchronization completion message, slave device 102 receives and parses the advertising packet sent by master device 101 at first time T2 to obtain the system clock inserted by master device 101 for time synchronization. This system clock at this time is the first initial time T0 when the master device generated the advertising packet. At second time T3, slave device 102 updates its own system clock based on the parsed system clock and sends a synchronization completion message to master device 101.

[0053] The time difference between first time T2 and second time T3 is a third interval Δt3. This third interval Δt3 is the data processing time required for slave device 102 to parse the advertising packet and obtain the system time of master device 101. Different chips have different data processing efficiencies. That is, the difference between first time T2 and second time T3 is determined based on the chip type of slave device 102. Specifically, in some embodiments, the third interval Δt3 is measured and obtained by the BLE chip manufacturer. For the same chip model, the third interval Δt3 is the same.

[0054] At the second time T3, slave device 102 updates its own system clock based on the parsed system clock, changing its own system clock to T0 + Δt1 + Δt2 + Δt3, thereby achieving time synchronization between master device 101 and slave device 102. The time difference between the first initial time T0 and the second initial time T1 is the first interval Δt1. This first interval Δt1 represents the data processing time required for master device 101 to insert the system clock into the broadcast packet to be transmitted. Different chips have different data processing efficiencies, so the difference between the first initial time T0 and the second initial time T1 is determined based on the chip type of master device 101. Specifically, in some embodiments, the first interval Δt1 is measured and obtained by the BLE chip manufacturer. For the same chip model, the first interval Δt1 is the same. The second interval Δt2 represents the data transmission time of the broadcast packet and can be calculated based on the BLE protocol. In some embodiments, Δt2 = (1 + 4 + 2 + adv_len + 3) * 8us, where adv_len represents the data length of the broadcast packet.

[0055] In summary, the time synchronization method provided in this embodiment implements time synchronization between the master device 101 and the slave device 102 based on BLE, thereby combining the advantages of BLE and reducing communication power consumption and cost.

[0056] This embodiment can be implemented in conjunction with the time synchronization method provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment and will not be repeated here to reduce repetition.

[0057] Another embodiment of the present disclosure provides an electronic device, as shown in Figure 3, which is a structural diagram of the electronic device provided by the embodiment of the present disclosure. The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the above-mentioned time synchronization method embodiment.

[0058] Memory 201 and processor 202 are connected using a bus. The bus may include any number of interconnected buses and bridges, connecting various circuits of one or more processors and memories. The bus may also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and are not further described herein.

[0059] The bus interface provides an interface between the bus and the transceiver. A transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a means for communicating with various other devices over a transmission medium. Data processed by processor 202 is transmitted over the wireless medium via an antenna. Furthermore, the antenna receives data and transmits it to processor 202.

[0060] The processor 202 is responsible for managing the bus and general processing, and may also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. The memory 201 may be used to store data used by the processor 202 when performing operations.

[0061] Another embodiment of the present disclosure provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-mentioned time synchronization method embodiment.

[0062] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program. The program is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps in the methods described in the various embodiments of this application. The aforementioned storage medium includes: a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0063] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A time synchronization method, applied to a slave device interconnected based on low-power Bluetooth, comprising: Establish a time synchronization channel with the master device; receiving and parsing a broadcast packet sent by the master device at a first moment to obtain a system clock inserted by the master device for time synchronization in the broadcast packet; updating its own system clock based on the system clock obtained through analysis at a second moment; Send a synchronization completion message to the master device.

2. The time synchronization method according to claim 1, wherein: The method for establishing a time synchronization channel with a master device includes: Establishing a GATT connection with the master device; A time synchronization request is initiated to the master device, and a response from the master device is waited for to establish the time synchronization channel.

3. The time synchronization method according to claim 1, wherein: A synchronization completion message is sent at a third time, and the third time is obtained after a fixed delay from the first time.

4. The time synchronization method according to claim 1, wherein: The difference between the first moment and the second moment is obtained based on a chip type of the slave device.

5. The time synchronization method according to claim 1, wherein: include: Before updating the own system clock based on the system clock obtained through analysis at the second moment, the method further includes: obtaining a synchronization deviation clock based on the system clock obtained through analysis and the own clock; Obtain the crystal oscillator deviation value based on the synchronization deviation clock and the time synchronization interval between the current time synchronization and the last time synchronization; After updating its own system clock, the system clock is adjusted based on the crystal oscillator deviation value. The time synchronization method according to claim 5 , wherein: Before adjusting the system clock based on the crystal oscillator deviation value, the method further includes: smoothing the crystal oscillator deviation value.

7. A time synchronization method, applied to a master device interconnected by low-power Bluetooth, comprising: Establish a time synchronization channel with the slave device; At a first initial moment, inserting a system clock into a broadcast packet to be sent; sending the broadcast packet to the slave device at a second initial moment; Waiting to receive a synchronization completion message from the slave device.

8. The time synchronization method according to claim 7, wherein: The difference between the first initial time and the second initial time is obtained based on a chip type of the master device.

9. An electronic device comprising: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the time synchronization method according to any one of claims 1 to 6 or 7 to 8.

10. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the time synchronization method according to any one of claims 1 to 6 or 7 to 8 is implemented.

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