Control circuit

Abstract

Disclosed in embodiments of the present application is a control circuit. The control circuit comprises a period control module, an on-time control module and a driving module. The period control module is used for outputting a first control signal. The driving module is used for controlling, when the first control signal suddenly changes from a low level to a high level, a first switching transistor in a buck power factor correction (PFC) circuit to be turned on. The on-time control module is used for outputting a second control signal. When a first product of a first average current value and the current on time of the first switching transistor reaches a second preset threshold value, the second control signal suddenly changes from a low level to a high level, and the first average current value is the average current value of a first current signal in a switching period of the first switching transistor. The driving module is used for controlling, when the second control signal suddenly changes from the low level to the high level, the first switching transistor to be turned off. The embodiments of the present application can save the control costs of buck PFC circuits.

Description

A control circuit Technical Field

[0001] The present application relates to driving technology, applied in the field of electricity, and in particular to a control circuit. Background Art

[0002] With the rapid development of fast charging technology, the power supply of consumer electronic devices such as mobile phones, tablets, computers, notebooks, and televisions is constantly increasing. Therefore, it is necessary to equip their power adapters with power factor correction (PFC) circuits to meet the requirements of GB17625.1 and IEC61000-3-2 for input current harmonics. For adapter power supplies, when the power is above 100W, an active PFC circuit is usually required. The active PFC circuit controls the DC / DC converter circuit composed of power electronic switching devices so that the average input current value of the PFC circuit follows the input voltage value, thereby achieving power factor correction. In order to be suitable for high-power scenarios, the operating mode of the conversion circuit in the active PFC circuit is usually continuous current mode (CCM). In CCM mode, the control principle of the traditional PFC circuit is to sample the input voltage and multiply it with the output voltage value of the voltage outer loop circuit as the reference value for controlling the current inner loop circuit, thereby controlling the average input current to follow the sinusoidal input voltage to achieve power factor correction. The above control method is complex and costly.

[0003] For active PFC circuits (i.e., Boost PFC) whose DC / DC conversion circuit is a boost circuit, the existing technology uses a peak current single-cycle control method. This method can achieve the effect of average current following the input voltage without sampling the input voltage, simplifying the PFC circuit control in CCM mode. However, in scenarios where voltage reduction is required, a step-down PFC circuit (such as Buck PFC) is usually used. Due to the different circuit structures of the step-down PFC circuit and the Boost PFC circuit, the input current of the step-down PFC circuit is discontinuous and the peak input current and average input current of the step-down PFC circuit do not have a linear relationship. Therefore, the above-mentioned peak current single-cycle control method is no longer applicable. Therefore, how to reduce the control cost of the step-down PFC circuit is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] An embodiment of the present application discloses a control circuit for reducing the control cost of a buck-type PFC circuit.

[0005] In a first aspect, an embodiment of the present application provides a control circuit, which includes a period control module 11, a conduction time control module 12, and a drive module 13, wherein: the period control module 11 is used to output a first control signal V_ON, and the period of the first control signal V_ON is a first preset threshold; the drive module 13 is used to control the first switch Q1 in the buck power factor correction PFC circuit 2 to be turned on when the first control signal V_ON suddenly changes from a low level to a high level, and the working mode of the buck PFC circuit 2 is a continuous current mode CCM, and the input current of the buck PFC circuit 2 is The current value is equal to the current value of the first current signal I_Q1 flowing through the first switch tube Q1; the on-time control module 12 is used to output the second control signal V_OFF. When the first product of the first average current value and the current on-time of the first switch tube Q1 reaches a second preset threshold, the second control signal V_OFF suddenly changes from a low level to a high level. The first average current value is the average current value of the first current signal I_Q1 within one switching cycle of the first switch tube Q1; the driving module 13 is used to control the first switch tube Q1 to be turned off when the second control signal V_OFF suddenly changes from a low level to a high level.

[0006] The control circuit can control the maximum value of the first product (i.e., equivalent to the product of the average input current of the buck PFC circuit 2 and the total on-time of the first switch Q1) to be constant (i.e., equal to the second preset threshold value) within a single switching cycle of the first switch Q1 in the buck PFC circuit 2, thereby controlling the average input current of the buck PFC circuit 2 to follow the input voltage value. This allows the buck PFC circuit 2 to be controlled to achieve power factor correction without sampling the input voltage, thereby reducing the control cost of the buck PFC circuit 2.

[0007] In combination with the first aspect, in a possible implementation, the on-time control module 12 includes a current sampling module 121 and an operation module 122, wherein: the current sampling module 121 is used to convert the first current signal I_Q1 into a first voltage signal V_CS, and the current value of the first current signal I_Q1 is proportional to the voltage value of the first voltage signal V_CS; the operation module 122 is used to operate on the first voltage signal V_CS when the first switch tube Q1 is turned on to generate a second voltage signal V_INT2, and the voltage value of the second voltage signal V_INT2 is proportional to the first product; the operation module 122 is also used to output a second control signal V_OFF, and when the voltage value of the second voltage signal V_INT2 reaches a third preset threshold, the second control signal V_OFF suddenly changes from a low level to a high level.

[0008] The control circuit can sample the first current signal I_Q1 flowing through the first switch Q1 and calculate the first voltage signal V_CS obtained after the sampling when the first switch Q1 is turned on, so that the voltage value of the second voltage signal V_INT2 calculated during the on-time of the first switch Q1 is proportional to the first product, and the maximum voltage value of the second voltage signal V_INT2 is constant (i.e., equal to the third preset threshold value), thereby indirectly maintaining the maximum value of the first product within a single switching cycle of the first switch Q1 at a constant value, thereby controlling the average input current value of the Buck PFC circuit 21 to follow the input voltage value.

[0009] In combination with the first aspect, or any of the above-mentioned possible implementations of the first aspect, in another possible implementation, the operation module 122 includes a voltage amplifier circuit GAIN, a voltage sampling and holding circuit S / H, an addition and subtraction operation circuit SUM, and an integration circuit 1221; the positive input terminal of the addition and subtraction operation circuit SUM is connected to the output terminal of the voltage amplifier circuit GAIN, the negative input terminal of the addition and subtraction operation circuit SUM is connected to the output terminal of the voltage sampling and holding circuit S / H, and the output terminal of the addition and subtraction operation circuit SUM is connected to the input terminal of the integration circuit 1221, wherein: the voltage amplifier circuit GAIN is used to amplify the first voltage signal V_CS to output a third voltage signal V_GAIN, and the third voltage signal V_GAIN The voltage value of AIN is proportional to the voltage value of the first voltage signal V_CS; the voltage sampling and holding circuit S / H is used to output a fourth voltage signal V_SH, and the voltage value of the fourth voltage signal V_SH is equal to the initial voltage value of the first voltage signal V_CS when the first switch tube Q1 starts to turn on; the addition and subtraction circuit SUM is used to output a fifth voltage signal V_SUM, and the voltage value of the fifth voltage signal V_SUM is equal to the difference between the voltage value of the third voltage signal V_GAIN and the voltage value of the fourth voltage signal V_SH; the integration circuit 1221 is used to perform a secondary integration of the fifth voltage signal V_SUM with respect to time when the first switch tube Q1 is turned on, so as to generate a second voltage signal V_INT2.

[0010] In combination with the first aspect, or any of the foregoing possible implementations of the first aspect, in yet another possible implementation, the operation module 122 further includes a comparator CMP and a voltage loop module 1222, wherein the positive input terminal of the comparator CMP is connected to the output terminal of the integration circuit 1221, and the negative input terminal of the comparator CMP is connected to the output terminal of the voltage loop module 1222, wherein: the voltage loop module 1222 is configured to output a sixth voltage signal V_C based on a voltage difference between a reference voltage signal and an output voltage signal V_OUT of the buck PFC circuit 2, wherein the voltage value of the sixth voltage signal V_C is equal to a third preset threshold value; and the comparator CMP is configured to compare the sixth voltage signal V_C with the second voltage signal V_INT2 and output the second control signal V_OFF.

[0011] In combination with the first aspect, or any of the above-mentioned possible implementations of the first aspect, in another possible implementation, the first input terminal of the integration circuit 1221 is connected to the output terminal of the addition and subtraction circuit SUM, the first output terminal of the driving module 13 is connected to the gate of the first switch tube Q1, the second output terminal of the driving module 13 is connected to the second input terminal of the integration circuit 1221, the first input terminal of the driving module 13 is connected to the output terminal of the period control module 11, and the second input terminal of the driving module 13 is connected to the output terminal of the comparator CMP, wherein: the driving module 13 is further used to control the integration circuit 1221 to output the second voltage signal V_INT2 when the first control signal V_ON suddenly changes from a low level to a high level; the driving module 13 is also used to control the voltage value of the second voltage signal V_INT2 to be zero when the second control signal V_OFF suddenly changes from a low level to a high level.

[0012] In combination with the first aspect, or any of the foregoing possible implementations of the first aspect, in another possible implementation, the integration circuit 1221 includes a first integration circuit 1221 and a second integration circuit 1221, wherein the first input terminal of the integration circuit 1221 is connected to the first input terminal of the first integration circuit 1221, the output terminal of the first integration circuit 1221 is connected to the first input terminal of the second integration circuit 1221, the output terminal of the second integration circuit 1221 is connected to the output terminal of the integration circuit 1221, and the second input terminal of the integration circuit 1221 is connected to the second input terminal of the first integration circuit 1221 and the second input terminal of the second integration circuit 1221, wherein: the driving module 13 is configured to drive the first input terminal of the integration circuit 1221 through the first input terminal of the driving module 13. The second output terminal outputs the third control signal V_RST. When the first control signal V_ON suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a high level to a low level. When the second control signal V_OFF suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a low level to a high level. The first integration circuit 1221 is used to perform a first-level integration of the fifth voltage signal V_SUM with respect to time to generate a seventh voltage signal when the third control signal V_RST is at a low level. The second integration circuit 1221 is used to perform a first-level integration of the seventh voltage signal with respect to time to generate a second voltage signal V_INT2 when the third control signal V_RST is at a low level.

[0013] In combination with the first aspect, or any one of the above-mentioned possible implementations of the first aspect, in another possible implementation, the driving module 13 includes a trigger SR and a driving circuit DRV, a first input end of the driving module 13 is connected to the set end of the trigger SR, a second input end of the driving module 13 is connected to the reset end of the trigger SR, a first output end of the trigger SR is connected to the input end of the driving circuit DRV, an output end of the driving circuit DRV is connected to a first output end of the driving module 13, and a second output end of the trigger SR is connected to a second output end of the driving module 13.

[0014] In combination with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation, the voltage value V of the second voltage signal V_INT2 is cs_int2 Satisfies the following formula: V cs_s =V cs_g -V cs0 =3V cs -V cs0

[0015] Among them, β0 is the preset secondary integral coefficient, V cs_s is the voltage value of the fifth voltage signal V_SUM, V cs_g is the voltage value of the third voltage signal V_GAIN, V cs0is the voltage value of the fourth voltage signal V_SH, V cs is the voltage value of the first voltage signal V_CS.

[0016] In combination with the first aspect, or any one of the foregoing possible implementations of the first aspect, in another possible implementation, the buck PFC circuit 2 includes a buck PFC circuit 21 , a forward topology PFC circuit 71 , or a push-pull topology PFC circuit 72 .

[0017] In a second aspect, an embodiment of the present application provides a control device, which includes the control circuit described in the first aspect or any possible implementation manner of the first aspect.

[0018] In a third aspect, an embodiment of the present application provides a PFC device, which includes the control circuit and the buck PFC circuit described in the first aspect or any possible implementation manner of the first aspect.

[0019] The beneficial effects of the related devices provided in the second and third aspects of this application can refer to the beneficial effects of the technical solution of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following is a brief introduction to the drawings required for describing the embodiments of this application.

[0021] FIG1 is a schematic structural diagram of a control circuit provided in an embodiment of the present application;

[0022] FIG2 is a schematic structural diagram of another control circuit provided in an embodiment of the present application;

[0023] FIG3 is a schematic structural diagram of a voltage loop module provided in an embodiment of the present application;

[0024] FIG4 is a schematic structural diagram of a driving module provided in an embodiment of the present application;

[0025] FIG5 is a signal waveform diagram provided by an embodiment of the present application;

[0026] FIG6 is another signal waveform diagram provided in an embodiment of the present application;

[0027] FIG7 a is a schematic structural diagram of a Buck PFC circuit provided in an embodiment of the present application;

[0028] FIG7 b is a schematic structural diagram of a forward topology PFC circuit provided in an embodiment of the present application;

[0029] FIG7 c is a schematic structural diagram of a push-pull topology PFC circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] Please refer to Figure 1, which is a schematic diagram of the structure of a control circuit provided by an embodiment of the present application. The control circuit 1 includes a cycle control module 11, an on-time control module 12, and a driver module 13. The output terminal a of the cycle control module 11 is connected to the first input terminal b1 of the driver module, and the output terminal c of the on-time control module 12 is connected to the second input terminal b2 of the driver module. The control circuit 1 can control the average input current value I of the buck-type PFC circuit 2. avg Follow the input voltage value V in changes, thereby achieving power factor correction.

[0032] The buck PFC circuit 2 includes a first switch tube Q1. The input current value I in is equal to the current value I1 of the first current signal I_Q1 flowing through the first switch tube Q1, and the operating mode of the buck PFC circuit 2 is the continuous current mode CCM. It can be understood that the first switch tube Q1 can be regarded as the main switch tube in the buck PFC circuit 2. The embodiment of the present application does not strictly limit the specific circuit structure of the buck PFC circuit 2. For example, the buck PFC circuit 2 can be a buck PFC circuit, a forward topology PFC circuit, or a push-pull topology PFC circuit. In addition, in actual applications, the DC power at the input end of the buck PFC circuit 2 is usually obtained by AC / DC conversion of the AC power of the AC power supply. For example, as shown in Figure 1, the input end of the buck PFC circuit 2 is connected to the AC / DC conversion circuit 3, and the AC / DC conversion circuit 3 includes an AC power supply S, an electromagnetic interference (EMI) filter circuit 31, and a rectifier bridge DBI. The output of the AC power supply S is connected to the rectifier bridge DBI via an EMI filter circuit 31. The output of the rectifier bridge DBI is connected to the input of the buck-type PFC circuit 2. The EMI filter circuit 31 is used to filter out circuit interference. The rectifier bridge DBI is used to convert the sinusoidal AC voltage signal V_AC output by the AC power supply S into a steamed-bun DC voltage signal (i.e., the input voltage signal V_IN of the buck-type PFC circuit 2) for output.

[0033] From the output side, the input voltage value V in , average input current value I avg And the equivalent impedance R e Satisfy formula (1-1): v in =I avg *R e (1-1)

[0034] According to the second-volt balance principle, in the continuous current mode CCM, the output voltage value V of the buck PFC circuit 2 is out and input voltage V in The ratio of the duty cycle D of the first switch tube Q1 on Assuming the proportional coefficient is k1, the output voltage value V out 、Input voltage value V in and duty cycle D on Satisfy formula (1-2):

[0035] Formula (1-3) is obtained from formula (1-1) and formula (1-2):

[0036] Among them, T on The first switch tube Q1 in a single switching cycle T s The total on-time (hereinafter referred to as the total on-time T on ).

[0037] In the control circuit 1, the period control module 11 is configured to output a first control signal V_ON, whose period is a first preset threshold. The driver module 13 is configured to control the first switch Q1 in the buck PFC circuit 2 to conduct when the first control signal suddenly changes from a low level to a high level. It is understood that the first control signal V_ON is a continuous and periodic voltage signal composed of a combination of high and low levels. Alternatively, the first control signal V_ON may be a pulse signal with a fixed frequency.

[0038] The on-time control module 12 is used to output a second control signal V_OFF. When the first average current value is equal to the current on-time t of the first switch tube Q1, on When the first product of reaches the second preset threshold, the second control signal V_OFF suddenly changes from a low level to a high level, and the first average current value is the first current signal I_Q1 in a single switching cycle T of the first switch tube Q1. s The driving module 13 is used to control the first switch tube to turn off when the second control signal suddenly changes from a low level to a high level. It can be understood that the total on-time T of the first switch tube Q1 is on The switching period T of the first switch Q1 is the time when the first product reaches the second preset threshold. s is a constant value, which is equal to the period of the first control signal V_ON, that is, equal to the first preset threshold. Then, in a single switching period T of the first switch tube Q1 s The maximum value of the first product is equal to the first average current value and the total conduction time T on The product of is always equal to the second preset threshold. And because the input current value Iin is equal to the current value I1 of the first current signal I_Q1 flowing through the first switch tube Q1, and the first average current value is equal to the average input current value I avg The maximum value of the first product is equal to the average input current value I of the buck PFC circuit 2. avg The total on-time T of the first switch tube Q1 on The product of .

[0039] From formula (1-3), we can see that the left side of formula (1-3) is the maximum value of the first product, and the right side of the formula is the second preset threshold. s The output voltage V when the step-down PFC circuit 2 is stable is a constant value. out It can be regarded as a constant value. Therefore, the control circuit 1 can realize the equivalent impedance R of the buck PFC circuit 2. e is a constant value, then, from formula (1-1), it can be seen that the average input current value I of the buck PFC circuit 2 is avg Follow the input voltage value V in change.

[0040] It can be seen that the control circuit 1 in the embodiment of the present application can control the average input current value I of the buck PFC circuit 2 within a single switching cycle of the first switch tube Q1 in the buck PFC circuit 2. avg The total on-time T of the first switch tube Q1 on The product of is a constant value (ie, equal to the second preset threshold value) to control the average input current value I of the buck PFC circuit 2. avg Follow the input voltage value V in The buck PFC circuit 2 is controlled to achieve power factor correction without sampling the input voltage, thereby saving the control cost of the buck PFC circuit.

[0041] The working principle of the control circuit 1 shown in FIG1 is further explained below in conjunction with FIG2 to FIG7c.

[0042] In an optional embodiment, the step-down PFC circuit 2 shown in FIG1 is a Buck PFC circuit, the first control signal V_ON is a pulse signal with a fixed frequency, and the on-time control module 12 includes a current sampling module and a calculation module. Please refer to FIG2 , which is a schematic diagram of the structure of another control circuit provided in an embodiment of the present application.

[0043] As shown in Figure 2, the Buck PFC circuit 21 includes a first capacitor C1, a second capacitor C2, a first diode D1, a first switch Q1, and a first inductor L1. The positive input terminal i1 of the Buck PFC circuit 21 is connected to one end of the first capacitor C1, the cathode of the first diode D1, one end of the second capacitor C2, and the positive output terminal o1 of the Buck PFC circuit 21. The anode of the first diode D1 is connected to one end of the first inductor L1 and the drain of the first switch Q1. The other end of the second capacitor C2 is connected to the other end of the first inductor L1 and the negative output terminal o2 of the Buck PFC circuit 21. The negative input terminal i2 of the Buck PFC circuit 21 is connected to the other end of the first capacitor C1, the source of the first switch Q1, and the reference ground.

[0044] The first input terminal e1 of the on-time control module 12 in the control circuit 1 is connected to the source of the first switching transistor Q1. The second input terminal e2 of the on-time control module 12 is connected to the output terminal of the Buck PFC circuit 21. The first output terminal d1 of the driver module 13 is connected to the gate of the first switching transistor Q1. The second output terminal d2 of the driver module 13 is connected to the third input terminal e3 of the on-time control module 12. The output terminal a of the cycle control module 11 is connected to the first input terminal b1 of the driver module and the fourth input terminal e4 of the on-time control module 12. The output terminal c of the on-time control module 12 is connected to the second input terminal b2 of the driver module.

[0045] The on-time control module 12 includes a current sampling module 121 and a calculation module 122. An input terminal f of the current sampling module 121 is connected to a first input terminal e1 of the on-time control module 12; an output terminal g of the current sampling module 121 is connected to a first input terminal h1 of the calculation module 122; a second input terminal h2 of the calculation module 122 is connected to a second input terminal e2 of the on-time control module 12; a third input terminal h3 of the calculation module 122 is connected to a third input terminal e3 of the on-time control module 12; a fourth input terminal h4 of the calculation module 122 is connected to a fourth input terminal e4 of the on-time control module 12; and an output terminal j of the calculation module 122 is connected to an output terminal c of the on-time control module 12.

[0046] The current sampling module 121 is used to convert the first current signal I_Q1 into a first voltage signal V_CS. The current value I1 of the first current signal I_Q1 and the voltage value V of the first voltage signal V_CS are proportional to each other. csThe period control module 11 is configured to output a first control signal V_ON to the driver module 13. The first control signal V_ON is a pulse signal with a fixed frequency, and the period of the pulse signal is a first preset threshold. The driver module 13 is configured to output a fourth control signal V_GATE to the first switch tube Q1. When the first control signal V_ON suddenly changes from a low level to a high level, the fourth control signal V_GATE suddenly changes from a low level to a high level, thereby controlling the first switch tube Q1 to turn on. Optionally, since the current signal flowing through the first inductor L1 when the first switch tube Q1 is turned on is equivalent to the first current signal I_Q1 flowing through the first switch tube Q1, the input terminal f of the current sampling module 121 can also be connected to one end of the first inductor L1 in the Buck PFC circuit 21 to sample the first current signal I_Q1.

[0047] The calculation module 122 in the conduction time control module 12 is used to calculate the first voltage signal V_CS when the first switch tube Q1 is turned on to generate a second voltage signal V_INT2. The voltage value V cs_int2 and the first product (which is equivalent to the average input current value Iavg of the Buck PFC circuit 21 and the current on-time t of the first switch tube Q1 on The operation module 122 is also used to output a second control signal V_OFF to the driving module 13. When the voltage value V cs_int2 When the third preset threshold is reached, the second control signal V_OFF changes from low level to high level. When the second control signal V_OFF changes from low level to high level, the fourth control signal V_GATE output by the driving module 13 changes from high level to low level, thereby controlling the first switch Q1 to turn off.

[0048] It can be understood that the control circuit 1 shown in FIG2 can sample the first current signal I_Q1 flowing through the first switch tube Q1 and calculate the first voltage signal V_CS obtained after sampling when the first switch tube Q1 is turned on, so that the voltage value V of the second voltage signal V_INT2 calculated during the conduction period of the first switch tube Q1 is cs_int2 is proportional to the first product, and makes the voltage value V of the second voltage signal V_INT2 cs_int2 is a constant value (i.e., equal to the third preset threshold), thereby indirectly making the maximum value of the first product within a single switching cycle of the first switch tube Q1 (i.e., the average input current value I of the buck PFC circuit 2) avg The total on-time T of the first switch tube Q1 on The product of ) is a constant value, thereby controlling the average input current value I of the Buck PFC circuit 21 avg Follow the input voltage value Vin change.

[0049] Exemplarily, as shown in FIG2 , the operation module 122 in the on-time control module 12 includes a voltage amplifier circuit GAIN, a voltage sample and hold circuit S / H, an addition and subtraction operation circuit SUM, an integration circuit 1221 , a comparator CMP and a voltage loop module 1222 .

[0050] Among them, the first input terminal h1 of the operation module 122 is connected to the input terminal of the voltage amplifier circuit GAIN and the first input terminal k1 of the voltage sampling and holding circuit S / H, the second input terminal k2 of the circuit S / H is connected to the fourth input terminal h4 of the operation module 122, the output terminal of the voltage amplifier circuit GAIN is connected to the positive input terminal of the addition and subtraction operation circuit SUM, the output terminal of the voltage sampling and holding circuit S / H is connected to the negative input terminal of the addition and subtraction operation circuit, the output terminal of the addition and subtraction operation circuit SUM is connected to the first input terminal m1 of the integration circuit 1221, the second output terminal m2 of the integration circuit 1221 is connected to the third input terminal h3 of the operation module 122, the output terminal of the integration circuit 1221 is connected to the positive input terminal of the comparator CMP, the negative input terminal of the comparator CMP is connected to the output terminal p of the voltage loop module 1222, the input terminal n of the voltage loop module 1222 is connected to the second input terminal h2 of the operation module 122, and the output terminal of the comparator CMP is connected to the output terminal j of the operation module 122.

[0051] The voltage amplifier circuit GAIN is used to amplify the first voltage signal V_CS output by the current sampling module 121 to output a third voltage signal V_GAIN. The voltage value of the third voltage signal V_GAIN is V cs_g and the voltage value V of the first voltage signal V_CS cs is proportional to. The voltage sampling and holding circuit S / H is used to start sampling the current voltage value of the first voltage signal V_CS when the first control signal V_ON suddenly changes from a low level to a high level (that is, at the moment when the first switch tube Q1 is turned on), and when the voltage sampling and holding circuit S / H suddenly changes from a high level to a low level, it maintains the sampled current voltage value and outputs the fourth voltage signal V_SH. It can be understood that it takes a certain amount of time for the voltage sampling and holding circuit S / H to perform voltage sampling, and the sampling time is equal to the time when the first control signal V_ON is at a high level. As mentioned above, the first control signal V_ON is a pulse signal with a fixed frequency. In actual applications, the time that the first control signal V_ON is at a high level (that is, the pulse width) can be set according to the time required for sampling and holding, without affecting its control effect on the switching period of the first switch tube Q1, and this time is usually short. In other words, the voltage value V of the fourth voltage signal V_SH is cs_h It can be regarded as equal to the initial voltage value V of the first voltage signal V_CS when the first switch tube Q1 starts to turn on.cs0 The addition and subtraction circuit SUM is used to output a fifth voltage signal V_SUM. The voltage value V of the fifth voltage signal V_SUM is cs_s is equal to the voltage value V of the third voltage signal V_GAIN cs_g and the voltage value V of the fourth voltage signal V_SH cs_h (ie the initial voltage value V of the first voltage signal V_CS cs0 ) between .

[0052] The driving module 13 is further configured to output a third control signal V_RST to the integration circuit 1221 via the second output terminal d2. When the first control signal V_ON suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a high level to a low level. When the second control signal V_OFF suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a low level to a high level. The integration circuit 1221 is configured to, when the third control signal V_RST suddenly changes from a high level to a low level, begin performing a two-stage integration of the fifth voltage signal V_SUM with respect to time to generate a second voltage signal V_INT2. Furthermore, when the third control signal V_RST suddenly changes from a low level to a high level, control the voltage of the second voltage signal V_INT2 to zero (i.e., the integration circuit 1221 is reset, and the voltage at the positive input terminal of the comparator CMP is zero) until the next time the third control signal V_RST suddenly changes from a high level to a low level, at which time the fifth voltage signal V_SUM is again subjected to a two-stage integration with respect to time to generate the second voltage signal V_INT2. That is, the integration circuit 1221 can perform a secondary integration of the fifth voltage signal V_SUM with respect to time when the first switch Q1 is turned on to generate the second voltage signal V_INT2. The voltage loop module 1222 is used to output the sixth voltage signal V_C according to the voltage difference between the reference voltage signal and the output voltage signal VOUT of the Buck PFC circuit 21. The voltage value V c It is understandable that the output voltage Vout of the Buck PFC circuit 21 when it is working stably can be regarded as a constant value, so the voltage value V of the sixth voltage signal V_C is c Can be considered as a constant value.

[0053] The comparator CMP is used to compare the sixth voltage signal V_C with the second voltage signal V_INT2 and output the second control signal V_OFF. It can be understood that after the first switch Q1 is turned on, the second voltage signal V_INT2 gradually increases. When the voltage value of the second voltage signal V_INT2 reaches V cs_int2 Equal to the voltage value V of the sixth voltage signal V_C cWhen the second control signal V_OFF changes from low level to high level, the first switch tube Q1 is turned off, and the integration circuit 1221 stops the integration operation. The voltage value V of the second voltage signal V_INT2 is cs_int2 Therefore, in a single switching cycle of the first switch Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2 The maximum value of is a constant value, which is equal to the voltage value V of the sixth voltage signal V_C. c .

[0054] Furthermore, during the conduction period of the first switch tube Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2 Proportional to the first product. For example, the amplification factor of the voltage amplifier circuit GAIN is 3, and the secondary integration coefficient of the integration circuit 1221 is β0, then the voltage value V of the second voltage signal V_INT2 is cs_int2 Formulas (1-4) and (1-5) can be satisfied: V cs_s =V cs_g -V cs0 =3V cs -V cs0 (1-5)

[0055] Among them, formula (1-4) is the integration formula when the integration circuit 1221 is working, T s is a single switching cycle of the first switch tube Q1, V cs_s is the voltage value of the fifth voltage signal V_SUM, V cs_g is the voltage value of the third voltage signal V_GAIN, V cs0 is the initial voltage value of the first voltage signal V_CS, V cs is the voltage value of the first voltage signal V_CS.

[0056] Based on the working principle of the Buck PFC circuit 21, in a single switching cycle of the first switch tube Q1, the voltage value V of the first voltage signal V_CS is cs Satisfy formula (1-6):

[0057] Wherein, k2 is the rising slope of the first voltage signal V_CS.

[0058] According to formulas (1-4) to (1-6), during the conduction period of the first switch tube Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2 Satisfy formula (1-7):

[0059] From formula (1-6), it can be seen that in a single switching cycle of the first switch tube Q1, the average voltage value V of the first voltage signal V_CS is cs_avg Satisfy formula (1-8):

[0060] Since the current value I1 of the first current signal I_Q1 (which is equivalent to the input current value I in ) and the voltage value V of the first voltage signal V_CS cs The average input current value I of the Buck PFC circuit 21 is proportional to avg and the average voltage value V of the first voltage signal V_CS cs_avg Proportional, assuming the sampling ratio is k3, then the average input current value I avg And the average voltage value V cs_avg Satisfy formula (1-9): V cs_avg =k3*I avg (1-9)

[0061] Therefore, combining formula (1-7) to formula (1-9), the first product (ie, the average input current value Iavg of the Buck PFC circuit 21 and the current on-time t of the first switch tube Q1) is on The product of ) satisfies formula (1-10):

[0062] It can be seen that when the amplification factor of the voltage amplifier circuit GAIN is 3, the secondary integration coefficient of the integration circuit 1221 is β0, and the integration formula of the integration circuit 1221 during operation satisfies formula (1-4), during the conduction period of the first switch tube Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2 Proportional to the first product.

[0063] Furthermore, it can be seen from formula (1-7) that during the conduction period of the first switch tube Q1, the maximum voltage value V of the second voltage signal V_INT2 is cs_int2(max) Satisfy formula (1-11):

[0064] From formula (1-10), it can be seen that the maximum value of the first product (i.e. the average input current value I of the Buck PFC circuit 21) avg The total on-time T of the first switch tube Q1 on The product of ) satisfies formula (1-12):

[0065] Optionally, due to the switching period T of the first switch tube Q1 s It can be regarded as a constant value, and the secondary integral coefficient β0 of the integration circuit 1221 can be

[0066] It can be seen that the control circuit 1 shown in FIG2 can control the maximum value of the first product to be a constant value within a single switching cycle of the first switch tube Q1. Based on formula (1-3), it can be seen that when the maximum value of the first product is a constant value, the average input current value I of the Buck PFC circuit 21 avg Follow the input voltage value V in change.

[0067] The specific circuit structures of the integration circuit 1221 , the voltage loop module 1222 and the driving module 13 in FIG. 2 are exemplarily described below.

[0068] Optionally, as shown in FIG2 , the integration circuit 1221 may include a first integration circuit INT1 and a second integration circuit INT2. A first input terminal m1 of the integration circuit 1221 is connected to a first input terminal of the first integration circuit INT1, an output terminal of the first integration circuit INT1 is connected to a first input terminal of the second integration circuit INT2, a first input terminal m2 of the integration circuit 1221 is connected to a second input terminal of the first integration circuit INT1 and a second input terminal of the second integration circuit INT2, and an output terminal of the second integration circuit INT2 is connected to an output terminal of the integration circuit 1221.

[0069] Specifically, the first integration circuit INT1 is configured to perform a first-order integration of the fifth voltage signal V_SUM with respect to time to generate a seventh voltage signal V_INT1 when the third control signal V_RST is at a low level. The second integration circuit INT2 is configured to perform a first-order integration of the seventh voltage signal V_INT1 with respect to time to generate a second voltage signal V_INT2 when the third control signal V_RST is at a low level.

[0070] The voltage value V of the seventh voltage signal V_INT1 cs_int1 Formula (1-13) can be satisfied:

[0071] Then, the voltage value V of the second voltage signal V_INT2 cs_int2 Formula (1-14) can be satisfied:

[0072] Among them, formula (1-13) and formula (1-14) are the integration formulas when the first integration circuit INT1 and the second integration circuit INT2 are working, β1 is the first-level integration coefficient of the first integration circuit INT1, and β2 is the first-level integration coefficient of the first integration circuit INT2.

[0073] It can be seen from formula (1-14) that when the product of the first-order integration coefficient β1 of the first integration circuit INT1 and the first-order integration coefficient β2 of the second integration circuit INT2 is β0, formula (1-14) is the same as formula (1-4). It should be noted that the present application does not strictly limit the values ​​of β1 and β2. For example, β1 and β2 can both be equal to

[0074] In addition, in actual applications, when the third control signal V_RST suddenly changes from a high level to a low level, the first integration circuit INT1 and the second integration circuit INT2 usually do not integrate the voltage signal immediately, but wait for a period of time before integrating the voltage signal. In other words, the first integration circuit INT1 and the second integration circuit INT2 are provided with a buffer time T banking , to filter out the current ringing and noise when the first switch tube Q1 is turned on. Buffer time T banking The setting can be realized by the internal circuits of the first integration circuit INT1 and the second integration circuit INT2, or by the first control signal V_ON. Taking the first integration circuit INT1 as an example, the first integration circuit INT1 includes a third input terminal, and the third input terminal of the first integration circuit INT1 is connected to the fourth input terminal h4 of the operation module 122 (that is, the first integration circuit INT1 can receive the first control signal V_ON). The first integration circuit INT1 will start the integration operation only when the third control signal V_RST is low and the first control signal V_ON suddenly changes from a high level to a low level. In other words, the buffer time T banking It can be equal to the time that the first control signal V_ON is at a high level.

[0075] Optionally, refer to FIG3 , which is a schematic diagram of the structure of a voltage loop module provided in an embodiment of the present application. As shown in FIG3 , the input terminal n of the voltage loop module 1222 includes a first sub-input terminal n 11 and the second sub-input terminal n 12 The voltage loop module 1222 includes a voltage detection module VSENCE and a loop compensation module LOOP. The positive output terminal o1 of the Buck PFC circuit 21 is connected to the first sub-input terminal n of the voltage loop module 1222. 11 The negative output terminal o2 of the Buck PFC circuit 21 is connected to the second sub-input terminal n of the voltage loop module 1222. 12 , the first sub-input terminal n of the voltage loop module 1222 11 Connect the first input terminal of the voltage detection module VSENCE and the second sub-input terminal n of the voltage loop module 1222 12The second input terminal of the voltage detection module VSENCE is connected, the output terminal of the voltage detection module VSENCE is connected to the first input terminal of the loop compensation module LOOP, and the output terminal of the loop compensation module LOOP is connected to the output terminal p of the voltage loop module 1222.

[0076] Specifically, the voltage detection module VSENCE is used to output the eighth voltage signal V_FB, and the voltage value of the eighth voltage signal V_FB is equal to the output voltage value V of the Buck PFC circuit 21. out The loop compensation module LOOP is configured to output a sixth voltage signal V_C according to a voltage difference between the reference voltage signal V_REF and the eighth voltage signal V_FB. In practical applications, the loop compensation module LOOP may include a PI compensation circuit or a type II compensation circuit.

[0077] Optionally, please refer to FIG4 , which is a schematic diagram of the structure of a driving module provided by an embodiment of the present application. As shown in FIG4 , the driving module 13 includes a trigger SR and a driving circuit DRV. The first input terminal b1 of the driving module 13 is connected to the set terminal S of the trigger SR, the second input terminal b2 of the driving module 13 is connected to the reset terminal R of the trigger SR, the first output terminal Q of the trigger SR is connected to the input terminal of the driving circuit DRV, the output terminal of the driving circuit DRV is connected to the first output terminal d1 of the driving module 13, and the second output terminal d2 of the trigger SR is connected to the reset terminal R of the trigger SR. Connected to the second output terminal d2 of the driving module 13.

[0078] Specifically, the drive circuit DRV is used to amplify the fifth control signal V_SR outputted from the first output terminal of the flip-flop SR to generate a fourth control signal V_GATE. The fourth control signal V_GATE has the same change trend as the fifth control signal V_SR.

[0079] It can be understood that when the first control signal V_ON received by the reset terminal R of the flip-flop SR suddenly changes from a low level to a high level, and the second control signal V_OFF received by the set terminal S of the flip-flop SR is at a low level, the fourth control signal V_GATE suddenly changes from a low level to a high level and remains at a high level until the second control signal V_OFF next suddenly changes from a low level to a high level, and the first switch Q1 is turned on. At the same time, the third control signal V_RST output by the second output terminal of the flip-flop SR suddenly changes from a high level to a low level and remains at a low level until the second control signal V_OFF suddenly changes from a low level to a high level, and the integrator circuit 1221 can be in an operating state when the first switch Q1 is turned on.

[0080] After the first switch Q1 is turned on, the voltage value V of the second voltage signal V_INT2 generated by the integration circuit 1221 is cs_int2gradually increases and reaches the voltage value V of the sixth voltage signal V_C c When the second control signal V_OFF received by the reset terminal R of the flip-flop SR suddenly changes from a low level to a high level, the fourth control signal V_GATE suddenly changes from a high level to a low level and remains at a low level until the first control signal V_ON next suddenly changes from a low level to a high level, and the first switch Q1 switches to the off state. At the same time, the third control signal V_RST output by the second output terminal of the flip-flop SR suddenly changes from a low level to a high level and remains at a high level until the first control signal V_ON next suddenly changes from a low level to a high level, and the integrator circuit 1221 can be in a reset state when the first switch Q1 is turned off.

[0081] It can be seen that the control circuit 1 shown in FIG2 controls the average input current value I of the Buck PFC circuit 21. avg Follow the input voltage value V in When the control circuit 1 changes, it involves the synergy between multiple signals. In order to better understand the working principle of the control circuit 1, the following is further explained based on the waveform diagram of the signal. Please refer to Figure 5, which is a signal waveform diagram provided in an embodiment of the present application.

[0082] Waveforms 501 to 510 are waveforms of the first control signal V_ON, the first current signal I_Q1 (equivalent to the input current signal I_IN of the Buck PFC circuit 21), the first voltage signal V_CS, the third voltage signal V_GAIN, the fifth voltage signal V_SUM, the third control signal V_RST, the seventh voltage signal V_INT1, the second voltage signal V_INT2, the second control signal V_OFF, and the fourth control signal V_GATE. Based on the waveform 501 of the first current signal I_Q1, it can be understood that in a single switching cycle T of the first switch tube Q1, s The input current of the internal Buck PFC circuit 21 is discontinuous and the peak input current and the average input current thereof do not have a linear relationship.

[0083] In conjunction with Figures 2 to 5 , it can be understood that when the first control signal V_ON output by the cycle control module 11 in the control circuit 1 suddenly changes from a low level to a high level, the fourth control signal V_GATE output by the drive circuit DRV in the drive module 13 suddenly changes from a low level to a high level and remains at a high level. The first switch tube Q1 in the Buck PFC circuit 21 begins to conduct (i.e., current flows through the first switch tube Q1), and the voltage sampling and holding circuit S / H begins to collect the initial voltage value V of the first voltage signal V_CS. cs0, and outputs a fourth voltage signal V_SH when the first control signal V_ON suddenly changes from a high level to a low level (the voltage value of the fourth voltage signal V_SH is the initial voltage value V cs0 At the same time, the third control signal V_RST output by the trigger SR in the driving module 13 suddenly changes from a high level to a low level and remains at a low level. The first integration circuit INT1 and the second integration circuit INT1 in the integration circuit 1221 start to perform a first-level integration operation respectively. Specifically, during the conduction time T on In the example, the voltage value of the first voltage signal V_CS output by the current sampling module 121 increases with the current value of the first current signal I_Q1. The voltage amplifier circuit GAIN in the on-time control module 12 amplifies the first voltage signal V_CS and outputs a third voltage signal V_GAIN. The addition and subtraction circuit SUM amplifies the voltage value V of the third voltage signal V_GAIN. cs_g and the initial voltage value V of the first voltage signal V_CS cs0 The first integration circuit INT1 performs a first-level integration operation on the fifth voltage signal V_SUM and outputs a seventh voltage signal V_INT1. The second integration circuit INT2 performs a first-level integration operation on the seventh voltage signal V_INT1 and outputs a second voltage signal V_INT2. The voltage value of the second voltage signal V_INT2 is V cs_int2 It is showing a gradual upward trend.

[0084] When the voltage value of the second voltage signal V_INT2 is V cs_int2 The voltage value V of the sixth voltage signal V_C output by the voltage loop module 1222 is reached c , the second control signal V_OFF output by the comparator CMP suddenly changes from a low level to a high level, the trigger SR is reset and the fourth control signal V_GATE output by the drive circuit DRV suddenly changes from a high level to a low level, and remains at a low level. The first switch tube Q1 in the Buck PFC circuit 21 begins to turn off (i.e., no current flows through the first switch tube Q1), and the voltage sampling and holding circuit S / H still outputs the fourth voltage signal until the first control signal V_ON output by the control module 11 in the next cycle suddenly changes from a low level to a high level. It will then restart the collection of the initial voltage value of the first voltage signal V_CS. At the same time, the third control signal V_RST output by the trigger SR in the drive module 13 suddenly changes from a low level to a high level, and remains at a high level. The first integration circuit INT1 and the second integration circuit INT1 in the integration circuit 1221 stop performing the first-level integration operation (i.e., are reset). Specifically, during the turn-off time T of the first switch tube Q1 offDuring the period, the seventh voltage signal V_INT1 and the second voltage signal V_INT2 are both zero. The first switch Q1 will not be turned on again until the first control signal V_ON output by the control module 11 changes from a low level to a high level in the next cycle.

[0085] Combined with the working principle of the control circuit 1 described in detail above, it can be seen that the control circuit 1 shown in FIG2 can control the average input current value I of the Buck PFC circuit 21 in a single cycle of the first switch Q1. avg Follow the input voltage value V in Therefore, from the perspective of the AC power supply S, in a single power frequency cycle of the AC power supply S, the average input current value I of the Buck PFC circuit 21 is avg Follow the input voltage value V in For easier understanding, please refer to FIG6 , which is another signal waveform diagram provided by an embodiment of the present application.

[0086] Waveforms 601 to 604 are respectively the sinusoidal AC voltage signal V_AC output by the AC power source S, the AC current signal I_AC output by the AC power source S, the input voltage signal V_IN of the Buck PFC circuit 21 , and the input current signal I_IN of the Buck PFC circuit 21 .

[0087] As shown in FIG6 , since the Buck PFC circuit 21 is a step-down circuit, in a single power frequency cycle T of the AC power source S ac In the circuit, only the voltage value V of the input voltage signal V_IN of the Buck PFC circuit 21 is in Greater than the output voltage V of the Buck PFC circuit 21 out , the current value of the AC current signal I_AC and the current value of the input current signal I_IN are not zero.

[0088] Moreover, since the control circuit 1 shown in FIG2 has a single switching cycle T of the first switch tube Q1 in the Buck PFC circuit 21, s The current signal flowing through the first switch tube Q1 is sampled in real time, so that in a single switching cycle T s Tracking the control target. Therefore, the control circuit 1 shown in FIG2 has a fast response speed and can achieve rapid convergence to circuit disturbances, thereby reducing current oscillations generated in the Buck PFC circuit 21 during the control process. As can be seen from markers 611 and 612 in FIG6 , the Buck PFC circuit 21 essentially does not generate current oscillations.

[0089] It should be noted that the Buck PFC circuit 21 shown in FIG2 is a low-end drive Buck PFC circuit (i.e., the source voltage of the main switch in the Buck PFC circuit is zero). The embodiment of the present application does not strictly limit the circuit structure of the Buck PFC circuit 21. The structure of the Buck PFC circuit 21 shown in FIG2 is only an example.

[0090] Optionally, the Buck PFC circuit 21 shown in FIG2 can also be a high-end drive Buck PFC circuit (i.e., the source voltage of the main switch in the Buck PFC circuit is non-zero). Please refer to FIG7a, which is a schematic diagram of the structure of a Buck PFC circuit provided in an embodiment of the present application. Compared to the Buck PFC circuit 21 shown in FIG2, the Buck PFC circuit 21 shown in FIG7a has the same electrical components, but the connection method between the electrical components is different. Specifically, the positive input terminal i1 of the Buck PFC circuit 21 is connected to one end of the first capacitor C1 and the drain of the first switch tube Q1, the source of the first switch tube Q1 is connected to the cathode of the first diode D1 and one end of the first inductor L1, the other end of the first inductor L1 is connected to one end of the second capacitor C2 and the positive output terminal o1 of the Buck PFC circuit 21, and the negative input terminal i2 of the Buck PFC circuit 21, the other end of the first capacitor C1, the positive electrode of the first diode D1, the other end of the second capacitor C2, and the negative output terminal o2 of the Buck PFC circuit 21 are all connected to the reference ground.

[0091] It is understood that for the Buck PFC circuit 21 shown in FIG2 and the Buck PFC circuit 21 shown in FIG7a , the proportional coefficient k1 in formula (1-2) is both 1. Therefore, referring to the operating principle of the control circuit 1 shown in FIG2 described in detail above, it can be seen that when the Buck PFC circuit 21 shown in FIG2 is replaced by the Buck PFC circuit 21 shown in FIG7a , the control circuit 1 can still control the average input current value of the Buck PFC circuit 21 shown in FIG7a to follow the input voltage value, thereby achieving power factor correction.

[0092] Optionally, the Buck PFC circuit 21 shown in FIG2 may also be a forward topology PFC circuit. For example, see FIG7b, which is a schematic structural diagram of a forward topology PFC circuit provided in an embodiment of the present application. As shown in FIG7b, the forward topology PFC circuit 71 includes a third capacitor C3, a fourth capacitor C4, a second switch tube Q2, a second diode D2, a third diode D3, a second inductor L2, and a first primary winding N p1 、First secondary winding N s1 , first iron core F1.

[0093] Specifically, the positive input terminal i3 of the forward topology PFC circuit 71 is connected to one end of the third capacitor C3 and the first primary winding N p1 One end of the first main winding N p1 The other end of the first primary winding N is connected to the drain of the second switch tube Q2, and the negative input terminal i4 of the forward topology PFC circuit 71, the other end of the third capacitor C3 and the source of the second switch tube Q2 are all connected to the reference ground. p1 and the first secondary winding N s1 Wound on the first core F1, the first secondary winding N s1 One end of the first inductor L2 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the cathode of the third diode D3 and one end of the second inductor L2, the other end of the second inductor L2 is connected to one end of the fourth capacitor C4 and the positive output end o3 of the forward topology PFC circuit 71, and the negative output end o4 of the forward topology PFC circuit 71 is connected to the first secondary winding N s1 the other end of the third diode D3, the anode of the third diode D3 and the other end of the fourth capacitor C4.

[0094] It can be understood that the second switch Q2 in the forward topology PFC circuit 71 shown in FIG7b can be regarded as equivalent to the first switch Q1 in the Buck PFC circuit 21 shown in FIG2. For the Buck PFC circuit 21 shown in FIG2, the proportionality coefficient k1 in formula (1-2) is 1. For the forward topology PFC circuit 71 shown in FIG7b, the proportionality coefficient k1 in formula (1-2) is the first secondary winding N s1 The number of turns of the first main winding N p1 The ratio of the number of turns, i.e., the proportional coefficient k1, remains constant. Therefore, referring to the operating principle of the control circuit 1 shown in FIG2 , as detailed above, it can be seen that when the Buck PFC circuit 21 shown in FIG2 is replaced by the forward topology PFC circuit 71 shown in FIG7b , the control circuit 1 can still control the average input current of the forward topology PFC circuit 71 to follow the input voltage, thereby achieving power factor correction.

[0095] Optionally, the Buck PFC circuit 21 shown in FIG2 may also be a push-pull topology PFC circuit. For example, see FIG7c, which is a schematic structural diagram of a push-pull topology PFC circuit provided in an embodiment of the present application. As shown in FIG7c, the push-pull topology PFC circuit 72 includes a fourth capacitor C4, a fifth capacitor C5, a third switch tube Q3, a fourth switch tube Q4, a fourth diode D4, a fifth diode D5, a third inductor L3, and a second primary winding N p2 , the third main winding N p3 , the second secondary winding N s2 and the third secondary winding N s3 .

[0096] Specifically, the positive input terminal i5 of the push-pull topology PFC circuit 72 is connected to one end of the fourth capacitor C4 and the third primary winding N p3 One end of the second main winding N p2 and the third main winding N p3 After being connected in series, the main side series winding is formed, and the second main side winding N p2 One end of the third primary winding N is connected to the drain of the third switch tube Q3. p3 The other end of is connected to the drain of the fourth switch tube Q4, the negative input terminal i6 of the push-pull topology PFC circuit 72, the other end of the fourth capacitor C4, the source of the third switch tube Q3, and the source of the fourth switch tube Q4 are all connected to the reference ground. s2 and the third secondary winding N s3 After being connected in series, the secondary series winding is formed. The primary series winding and the secondary series winding are wound on the second core F2. The second secondary winding N s2 One end of the diode is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to one end of the third inductor L3 and the cathode of the fifth diode D5, and the anode of the fifth diode D5 is connected to the third secondary winding N s3 The other end of the third inductor L3 is connected to one end of the fifth capacitor C5 and the positive output terminal o5 of the push-pull topology PFC circuit 72, and the other end of the fifth capacitor C5 is connected to the third secondary winding N s3 and the negative output terminal o6 of the push-pull topology PFC circuit 72.

[0097] It can be understood that the third switch tube Q3 and the fourth switch tube Q4 in the push-pull topology PFC circuit 72 shown in FIG. 7 c are switched alternately to output a voltage.

[0098] For the Buck PFC circuit 21 shown in FIG2 , the proportionality coefficient k1 in formula (1-2) is 1. For the push-pull topology PFC circuit 72 shown in FIG7 b , the proportionality coefficient k1 in formula (1-2) is twice the ratio of the number of turns of the primary series winding to the number of turns of the secondary series winding, i.e., the proportionality coefficient k1 remains constant. Therefore, referring to the operating principle of the control circuit 1 shown in FIG2 described in detail above, it can be seen that when the Buck PFC circuit 21 shown in FIG2 is replaced by the push-pull topology PFC circuit 72 shown in FIG7 c , the control circuit 1 can control the third switch Q3 in the same manner as it controls the first switch Q1 in the Buck PFC circuit 21 shown in FIG2 , thereby controlling the average input current of the push-pull topology PFC circuit 72 to follow the input voltage, thereby achieving power factor correction.

[0099] In summary, the control circuit in the embodiments of the present application can sample the current signal flowing through the main switch in a buck-type PFC circuit in real time during a single switching cycle of the main switch, thereby controlling the average input current value of the buck-type PFC circuit to follow the input voltage value. This not only allows the buck-type PFC circuit to be controlled to achieve power factor correction without sampling the input voltage, thus reducing the control cost of the buck-type PFC circuit, but also achieves rapid convergence in response to circuit disturbances, reduces current oscillations generated in the buck-type PFC circuit during the control process, and enhances the stability of the buck-type PFC circuit. Furthermore, the control circuit in the embodiments of the present application can be applied to a variety of buck-type PFC circuits, thus providing a wide range of applications and high flexibility.

[0100] In the embodiments of this application, the term "multiple" refers to two or more. Furthermore, unless otherwise specified, the term "first" in the embodiments of this application is used solely for name identification and is not intended to define the order, timing, priority, or importance of multiple objects, such as a first control signal or a first switching transistor. This rule also applies to "second," "third," and "fourth," etc.

[0101] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A control circuit, characterized in that: The control circuit comprises a period control module (11), a conduction time control module (12) and a driving module (13), wherein: The period control module (11) is used to output a first control signal (V_ON), the period of the first control signal (V_ON) being a first preset threshold; The driving module (13) is used to control the first switch tube (Q1) in the buck-type power factor correction (PFC) circuit (2) to be turned on when the first control signal (V_ON) suddenly changes from a low level to a high level, the working mode of the buck-type PFC circuit (2) is a continuous current mode (CCM), and the input current value of the buck-type PFC circuit (2) is equal to the current value of the first current signal (I_Q1) flowing through the first switch tube (Q1); The on-time control module (12) is used to output a second control signal (V_OFF), and when a first product of a first average current value and a current on-time of the first switch tube (Q1) reaches a second preset threshold, the second control signal (V_OFF) suddenly changes from a low level to a high level, and the first average current value is an average current value of the first current signal (I_Q1) within one switching cycle of the first switch tube (Q1); The driving module (13) is used to control the first switch tube (Q1) to be turned off when the second control signal (V_OFF) suddenly changes from a low level to a high level.

2. The control circuit according to claim 1, wherein: The on-time control module (12) comprises a current sampling module (121) and a calculation module (122), wherein: The current sampling module (121) is used to convert the first current signal (I_Q1) into a first voltage signal (V_CS), and the current value of the first current signal (I_Q1) is proportional to the voltage value of the first voltage signal (V_CS); The operation module (122) is used to operate the first voltage signal (V_CS) when the first switch tube (Q1) is turned on to generate a second voltage signal (V_INT2), wherein the voltage value of the second voltage signal (V_INT2) is proportional to the first product; The operation module (122) is further configured to output the second control signal (V_OFF), and when the voltage value of the second voltage signal (V_INT2) reaches a third preset threshold, the second control signal (V_OFF) suddenly changes from a low level to a high level.

3. The control circuit according to claim 2, characterized in that: The operation module (122) comprises a voltage amplifier circuit (GAIN), a voltage sampling and holding circuit (S / H), an addition and subtraction operation circuit (SUM) and an integration circuit (1221); the positive input terminal of the addition and subtraction operation circuit (SUM) is connected to the output terminal of the voltage amplifier circuit (GAIN), the negative input terminal of the addition and subtraction operation circuit (SUM) is connected to the output terminal of the voltage sampling and holding circuit (S / H), and the output terminal of the addition and subtraction operation circuit (SUM) is connected to the input terminal of the integration circuit (1221), wherein: The voltage amplifier circuit (GAIN) is used to amplify the first voltage signal (V_CS) to output a third voltage signal (V_GAIN), and the voltage value of the third voltage signal (V_GAIN) is proportional to the voltage value of the first voltage signal (V_CS); The voltage sampling and holding circuit (S / H) is used to output a fourth voltage signal (V_SH), wherein the voltage value of the fourth voltage signal (V_SH) is equal to the initial voltage value of the first voltage signal (V_CS) when the first switch tube (Q1) starts to conduct; The addition and subtraction circuit (SUM) is used to output a fifth voltage signal (V_SUM), wherein a voltage value of the fifth voltage signal (V_SUM) is equal to a difference between a voltage value of the third voltage signal (V_GAIN) and a voltage value of the fourth voltage signal (V_SH); The integration circuit (1221) is used for performing a secondary integration of the fifth voltage signal (V_SUM) with respect to time when the first switch tube (Q1) is turned on, to generate the second voltage signal (V_INT2).

4. The control circuit according to claim 3, characterized in that: The operation module (122) further comprises a comparator (CMP) and a voltage loop module (1222), wherein the positive input terminal of the comparator (CMP) is connected to the output terminal of the integration circuit (1221), and the negative input terminal of the comparator (CMP) is connected to the output terminal of the voltage loop module (1222), wherein: The voltage loop module (1222) is used to output a sixth voltage signal (V_C) according to a voltage difference between a reference voltage signal and an output voltage signal (V_OUT) of the buck-type PFC circuit (2), wherein the voltage value of the sixth voltage signal (V_C) is equal to the third preset threshold value; The comparator (CMP) is used to compare the sixth voltage signal (V_C) with the second voltage signal (V_INT2) and output the second control signal (V_OFF).

5. The control circuit according to claim 4, characterized in that: The first input end of the integration circuit (1221) is connected to the output end of the addition and subtraction circuit (SUM), the first output end of the driving module (13) is connected to the gate of the first switch tube (Q1), the second output end of the driving module (13) is connected to the second input end of the integration circuit (1221), the first input end of the driving module (13) is connected to the output end of the period control module (11), and the second input end of the driving module (13) is connected to the output end of the comparator (CMP), wherein: The driving module (13) is further configured to control the integration circuit (1221) to output the second voltage signal (V_INT2) when the first control signal (V_ON) suddenly changes from a low level to a high level; The driving module (13) is further used for controlling the voltage value of the second voltage signal (V_INT2) to be zero when the second control signal (V_OFF) suddenly changes from a low level to a high level.

6. The control circuit according to claim 5, characterized in that: The integration circuit (1221) comprises a first integration circuit (INT1) and a second integration circuit (INT2), wherein a first input terminal of the integration circuit (1221) is connected to a first input terminal of the first integration circuit (INT1), an output terminal of the first integration circuit (INT1) is connected to a first input terminal of the second integration circuit (INT2), an output terminal of the second integration circuit (INT2) is connected to an output terminal of the integration circuit (1221), and a second input terminal of the integration circuit (1221) is connected to a second input terminal of the first integration circuit (INT1) and a second input terminal of the second integration circuit (INT2), wherein: The driving module (13) is used to output a third control signal (V_RST) through a second output terminal of the driving module (13); when the first control signal (V_ON) suddenly changes from a low level to a high level, the third control signal (V_RST) suddenly changes from a high level to a low level; and when the second control signal (V_OFF) suddenly changes from a low level to a high level, the third control signal (V_RST) suddenly changes from a low level to a high level; The first integration circuit (INT1) is configured to perform a first-order integration of the fifth voltage signal (V_SUM) with respect to time to generate a seventh voltage signal when the third control signal (V_RST) is at a low level; The second integration circuit (INT2) is configured to perform a first-order integration of the seventh voltage signal with respect to time to generate the second voltage signal (V_INT2) when the third control signal (V_RST) is at a low level.

7. The control circuit according to claim 6, characterized in that: The driving module (13) comprises a trigger (SR) and a driving circuit (DRV), wherein a first input end of the driving module (13) is connected to a set end of the trigger (SR), a second input end of the driving module (13) is connected to a reset end of the trigger (SR), a first output end of the trigger (SR) is connected to an input end of the driving circuit (DRV), an output end of the driving circuit (DRV) is connected to a first output end of the driving module (13), and a second output end of the trigger (SR) is connected to a second output end of the driving module (13).

8. The control circuit according to any one of claims 3 to 7, characterized in that: The voltage value V of the second voltage signal (V_INT2) cs_int2 Satisfies the following formula: V cs_int2 =β0*∫0 t (∫0 t V cs_s dt)dt V cs_s =V cs_g -V cs0 =3V cs -V cs0 Wherein, the β0 is the preset secondary integral coefficient V cs_s is the voltage value of the fifth voltage signal (V_SUM), the V cs_g is the voltage value of the third voltage signal (V_GAIN), the V cs0 is the voltage value of the fourth voltage signal (V_SH), the V cs is the voltage value of the first voltage signal (V_CS).

9. The control circuit according to claim 8, characterized in that: The step-down PFC circuit (2) comprises a step-down Buck PFC circuit (21), a forward topology PFC circuit (71), or a push-pull topology PFC circuit (72).

10. A control circuit, characterized in that: include: The period control module (11) is used to output a first control signal (V_ON), The on-time control module (12) is used to output a second control signal (V_OFF); The driving module (13) is used to control the switching cycle of the first switch tube (Q1) of the buck PFC circuit (2) according to the first control signal (V_ON), and to control the on-time of the first switch tube (Q1) in the current switching cycle according to the second control signal (V_OFF), so that the first product is maintained at a constant value, wherein: The working mode of the buck-type PFC circuit (2) is a continuous current mode (CCM); the input current value of the buck-type PFC circuit (2) is equal to the current value of the first current signal (I_Q1) flowing through the first switch tube (Q1); the first product is the product of the first average current value and the conduction time of the first switch tube (Q1) in the current switching cycle; the first average current value is the average current value of the first current signal (I_Q1) within one switching cycle of the first switch tube (Q1).

11. The control circuit according to claim 10, characterized in that: The on-time control module (12) comprises a current sampling module (121) and a calculation module (122), wherein: The current sampling module (121) is used to convert the first current signal (I_Q1) into a first voltage signal (V_CS), and the current value of the first current signal (I_Q1) is proportional to the voltage value of the first voltage signal (V_CS); The operation module (122) is used to operate the first voltage signal (V_CS) when the first switch tube (Q1) is turned on to generate a second voltage signal (V_INT2), wherein the voltage value of the second voltage signal (V_INT2) is proportional to the first product; The operation module (122) is further configured to output a corresponding second control signal (V_OFF) when the voltage value of the second voltage signal (V_INT2) reaches a third preset threshold value, so as to enable the driving module (13) to control the first switch tube (Q1) to turn off.

12. The control circuit according to claim 11, characterized in that: The operation module (122) includes: a voltage sampling and holding circuit (S / H), an addition and subtraction operation circuit (SUM) and an integration circuit (1221); The positive input terminal of the addition and subtraction operation circuit (SUM) receives the third voltage signal (V_GAIN), the negative input terminal of the addition and subtraction operation circuit (SUM) is connected to the output terminal of the voltage sampling and holding circuit (S / H), and the output terminal of the addition and subtraction operation circuit (SUM) is connected to the input terminal of the integration circuit (1221); The voltage sampling and holding circuit (S / H) is used to output a fourth voltage signal (V_SH), wherein the voltage value of the fourth voltage signal (V_SH) is equal to the initial voltage value of the first voltage signal (V_CS) when the first switch tube (Q1) starts to conduct; the addition and subtraction circuit (SUM) is configured to output a fifth voltage signal (V_SUM), wherein a voltage value of the fifth voltage signal (V_SUM) is equal to a difference between a voltage value of the third voltage signal (V_GAIN) and a voltage value of the fourth voltage signal (V_SH); and the voltage value of the third voltage signal (V_GAIN) is proportional to the voltage value of the first voltage signal (V_CS); The integration circuit (1221) is used for performing a secondary integration of the fifth voltage signal (V_SUM) with respect to time when the first switch tube (Q1) is turned on, to generate the second voltage signal (V_INT2).

13. The control circuit according to claim 12, characterized in that: The first output end of the driving module (13) is connected to the gate of the first switching tube (Q1), the first input end of the integration circuit (1221) is connected to the output end of the addition and subtraction operation circuit (SUM), and the second output end of the driving module (13) is connected to the second input end of the integration circuit (1221); The driving module (13) is further configured to control the integration circuit (1221) to output the second voltage signal (V_INT2) when controlling the first switch tube (Q1) to be turned on; The driving module (13) is further configured to control the voltage value of the second voltage signal (V_INT2) to be zero when the first switch tube (Q1) is controlled to be turned off.

14. The control circuit according to claim 13, wherein: The first input end of the driving module (13) is connected to the output end of the period control module (11), and the second input end of the driving module (13) is connected to the conduction time control module (12), wherein: The driving module (13) is used to control the first switch tube (Q1) to be turned on when the first control signal (V_ON) suddenly changes from a low level to a high level; When the first product reaches a second preset threshold, the second control signal (V_OFF) suddenly changes from a low level to a high level, and the driving module (13) is used to control the first switch tube (Q1) to turn off when the second control signal (V_OFF) suddenly changes from a low level to a high level.

15. The control circuit according to claim 14, characterized in that: The driving module (13) is used to output a third control signal (V_RST) through a second output terminal of the driving module (13); when the first control signal (V_ON) suddenly changes from a low level to a high level, the third control signal (V_RST) suddenly changes from a high level to a low level; and when the second control signal (V_OFF) suddenly changes from a low level to a high level, the third control signal (V_RST) suddenly changes from a low level to a high level; The integration circuit (1221) is used for performing a secondary integration of the fifth voltage signal (V_SUM) with respect to time when the third control signal (V_RST) is at a low level, to generate the second voltage signal (V_INT2).

16. The control circuit according to claim 15, characterized in that: The integration circuit (1221) is provided with a buffer time (T banking ); The integration circuit (1221) is further configured to wait for the buffer time (T banking ), the fifth voltage signal (V_SUM) is subjected to a secondary integration with respect to time to generate the second voltage signal (V_INT2).

17. The control circuit according to claim 15, characterized in that: The integration circuit (1221) includes a first integration circuit (INT1) and a second integration circuit (INT2); The output end of the addition and subtraction operation circuit (SUM) is connected to the first input end of the first integration circuit (INT1), the output end of the first integration circuit (INT1) is connected to the first input end of the second integration circuit (INT2), the output end of the second integration circuit (INT2) is connected to the output end of the integration circuit (1221), and the second input end of the integration circuit (1221) is connected to the second input end of the first integration circuit (INT1) and the second input end of the second integration circuit (INT2), wherein: The first integration circuit (INT1) is configured to perform a first-order integration of the fifth voltage signal (V_SUM) with respect to time to generate a seventh voltage signal when the third control signal (V_RST) is at a low level; The second integration circuit (INT2) is configured to perform a first-order integration of the seventh voltage signal with respect to time to generate the second voltage signal (V_INT2) when the third control signal (V_RST) is at a low level.

18. The control circuit according to claim 17, characterized in that: The first integration circuit (INT1) comprises a third input terminal, and the third input terminal of the first integration circuit (INT1) is used to receive the first control signal (V_ON); Among them, the first integration circuit (INT1) is also used to perform a first-level integration of the fifth voltage signal (V_SUM) with respect to time to generate a seventh voltage signal only when the third control signal (V_RST) is at a low level and the first control signal (V_ON) suddenly changes from a high level to a low level.

19. The control circuit according to claim 14, wherein: The driving module (13) comprises a trigger (SR) and a driving circuit (DRV), wherein a first input end of the driving module (13) is connected to a set end of the trigger (SR), a second input end of the driving module (13) is connected to a reset end of the trigger (SR), a first output end of the trigger (SR) is connected to an input end of the driving circuit (DRV), an output end of the driving circuit (DRV) is connected to a first output end of the driving module (13), and a second output end of the trigger (SR) is connected to a second output end of the driving module (13).

20. The control circuit according to claim 12, wherein: The operation module (122) further includes: a voltage amplifier circuit (GAIN), the input end of the voltage amplifier circuit (GAIN) being connected to the output end of the current sampling module (121); the output end of the voltage amplifier circuit (GAIN) being connected to the positive input end of the addition and subtraction operation circuit (SUM), wherein: The voltage amplifying circuit (GAIN) is used to amplify the first voltage signal (V_CS) to output the third voltage signal (V_GAIN).

21. The control circuit according to claim 11, wherein: The operation module (122) further comprises a comparator (CMP) and a voltage loop module (1222), wherein the positive input terminal of the comparator (CMP) is connected to the output terminal of the operation module (122), and the negative input terminal of the comparator (CMP) is connected to the output terminal of the voltage loop module (1222), wherein: The voltage loop module (1222) is used to output a sixth voltage signal (V_C) according to a voltage difference between a reference voltage signal and an output voltage signal (V_OUT) of the buck-type PFC circuit (2), wherein the voltage value of the sixth voltage signal (V_C) is equal to the third preset threshold value; The comparator (CMP) is used to compare the sixth voltage signal (V_C) with the second voltage signal (V_INT2) and output the second control signal (V_OFF).

22. The control circuit according to claim 21, characterized in that: The step-down PFC circuit (2) is a Buck PFC circuit (21); The input terminal (n) of the voltage loop module (1222) includes a first sub-input terminal (n11) and a second sub-input terminal (n12); The voltage loop module (1222) includes: a voltage detection module (VSENCE) and a loop compensation module (LOOP); The positive output terminal (o1) of the Buck PFC circuit (21) is connected to the first sub-input terminal (n11) of the voltage loop module (1222), the negative output terminal (o2) of the Buck PFC circuit (21) is connected to the second sub-input terminal (n12) of the voltage loop module (1222), the first sub-input terminal (n11) of the voltage loop module (1222) is connected to the first input terminal of the voltage detection module (VSENCE), the second sub-input terminal (n12) of the voltage loop module (1222) is connected to the second input terminal of the voltage detection module (VSENCE), the output terminal of the voltage detection module (VSENCE) is connected to the first input terminal of the loop compensation module (LOOP), and the output terminal of the loop compensation module (LOOP) is connected to the output terminal (p) of the voltage loop module (1222), wherein: The voltage detection module (VSENCE) is used to output an eighth voltage signal (V_FB), the voltage value of the eighth voltage signal (V_FB) being equal to the output voltage value (Vout) of the Buck PFC circuit (21), and the loop compensation module (LOOP) is used to output the sixth voltage signal (V_C) according to the voltage difference between the reference voltage signal (V_REF) and the eighth voltage signal (V_FB).

23. The control circuit according to claim 22, characterized in that: The loop compensation module (LOOP) includes a PI compensation circuit or a type II compensation circuit.

24. The control circuit according to any one of claims 12 to 20, characterized in that: The voltage value V of the second voltage signal (V_INT2) cs_int2 Satisfies the following formula: V cs_int2 =β0*∫0 t (∫0 t V cs_s dt)dt V cs_s =V cs_g -V cs0 Wherein, β0 is the preset secondary integral coefficient, and V cs_s is the voltage value of the fifth voltage signal (V_SUM), the V cs_g is the voltage value of the third voltage signal (V_GAIN), the V cs0 is the voltage value of the fourth voltage signal (V_SH).

25. A PFC circuit comprising: Buck PFC circuit (2) and A control circuit (1) as claimed in any one of claims 1 to 24.

26. The PFC circuit according to claim 25, characterized in that The step-down PFC circuit (2) includes a Buck PFC circuit (21), a forward topology PFC circuit (71), or a push-pull topology PFC circuit (72).

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