Display panel and display apparatus

Abstract

A display panel, comprising: a substrate; a plurality of sub-pixels and a plurality of data lines, which are located in a display area; and a plurality of data fan-out lines and a plurality of control signal lines, which are located in a first frame area. The plurality of data fan-out lines comprise a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise a first group of control signal lines and a second group of control signal lines, wherein the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate. At least one organic insulating layer is provided between each data fan-out line and a control signal line, the orthographic projection of which on the substrate overlaps with the data fan-out line.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed on January 30, 2024, with application number 202410129884.4 and invention name “Display Panel and Display Device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, display devices using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present application provide a display panel and a display device.

[0006] On the one hand, this embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate comprises: a display area, and a first frame area located on one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of data fan-out lines and a plurality of control signal lines are located in the first frame area. The plurality of data fan-out lines are configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines comprise: a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise: a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate. At least one organic insulating layer is provided between the data fan-out lines and the control signal lines whose orthographic projections overlap with the substrate.

[0007] In some exemplary embodiments, the control signal line includes: a first control line segment, the first control line segment having an orthographic projection on the substrate overlapping with the orthographic projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate, the first control line segment being located on a side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control line segment intersecting with an extension direction of the multiple data fan-out lines.

[0008] In some exemplary embodiments, the display panel includes at least a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, arranged in a direction perpendicular to the display panel and away from the substrate; at least a first planarization layer is disposed between the first source / drain metal layer and the second source / drain metal layer. The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and a first control line segment of the plurality of control signal lines is located in the second source / drain metal layer.

[0009] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes at least: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer, arranged in a direction away from the substrate; at least a first planarization layer is disposed between the first source / drain metal layer and the second source / drain metal layer, and at least a second planarization layer is disposed between the second source / drain metal layer and the third source / drain metal layer. The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and a first control line segment of the plurality of control signal lines is located in the third source / drain metal layer.

[0010] In some exemplary embodiments, the plurality of data fan-out lines include: a plurality of first data fan-out lines located in the first gate metal layer and a plurality of second data fan-out lines located in the second gate metal layer. The plurality of first data fan-out lines and the plurality of second data fan-out lines are arranged one by one, and their orthographic projections on the substrate do not overlap.

[0011] In some exemplary embodiments, the control signal line further includes: a second control line segment and a third control line segment, the second control line segment being connected to one end of the first control line segment, the third control line segment being connected to the other end of the first control line segment, the orthographic projections of the second control line segment and the third control line segment on the substrate not overlapping with the orthographic projections of the multiple data fan-out lines on the substrate; the second control line segment and the third control line segment are of the same layer structure, and are located on the side of the first control line segment close to the substrate.

[0012] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate, and a ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.1.

[0013] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes a first sub-line segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes a second sub-line segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

[0014] In some exemplary embodiments, a ratio of the line width of the second sub-line segment to the line width of the first sub-line segment is greater than 1 and less than 2.

[0015] In some exemplary embodiments, each data fan-out line within the first group of data fan-out lines further includes: a third sub-segment connected to one end of the first sub-segment, and a fourth sub-segment connected to the other end of the first sub-segment; the orthographic projections of the third and fourth sub-segments on the substrate do not overlap with the orthographic projections of the first group of control signal lines on the substrate; the first, third, and fourth sub-segments of each data fan-out line within the first group of data fan-out lines are interconnected as an integrated structure. Each data fan-out line within the second group of data fan-out lines further includes: a fifth sub-segment connected to one end of the second sub-segment, and a sixth sub-segment connected to the other end of the second sub-segment; the orthographic projections of the fifth and sixth sub-segments on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate. The second, fifth, and sixth sub-segments of each data fan-out line within the second group of data fan-out lines are interconnected as an integrated structure. The first sub-line segment, the third sub-line segment, the fourth sub-line segment, the fifth sub-line segment, and the sixth sub-line segment have the same line width.

[0016] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes a first sub-segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes a second sub-segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-segment on the substrate is a straight line, and the orthographic projection of the second sub-segment on the substrate is a serpentine line.

[0017] In some exemplary embodiments, each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-segment connected to one end of the second sub-segment, and a sixth sub-segment connected to the other end of the second sub-segment; the orthographic projections of the fifth and sixth sub-segments on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate. The second, fifth, and sixth sub-segments of each data fan-out line in the second group of data fan-out lines are interconnected and integrally formed; and the orthographic projections of the fifth or sixth sub-segment of at least one data fan-out line in the second group of data fan-out lines on the substrate are serpentine.

[0018] In some exemplary embodiments, each control signal line within the first group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate; each control signal line within the second group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate; the line width of the first control line segment of at least one control signal line within the second group of control signal lines is greater than the line width of the first control line segment of the control signal lines within the first group of control signal lines.

[0019] In some exemplary embodiments, the substrate further comprises: a second border region and a third border region located on both sides of the display region along the first direction, the second border region and the third border region both being connected to the first border region. The display panel further comprises: a first group of gate drive circuits located in the second border region and a second group of gate drive circuits located in the third border region, the number of gate drive circuits included in the first group of gate drive circuits being greater than the number of gate drive circuits included in the second gate drive circuit. The first group of control signal lines comprises: a plurality of first drive control lines, the plurality of first drive control lines being configured to provide drive control signals to the first group of gate drive circuits. The second group of control signal lines comprises: a plurality of second drive control lines, the plurality of second drive control lines being configured to provide drive control signals to the second group of gate drive circuits.

[0020] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a pixel circuit. The first set of gate driver circuits includes a light-emitting driver circuit, a first reset driver circuit, and a second reset driver circuit; the light-emitting driver circuit is configured to provide a light-emitting control signal to the pixel circuit, the first reset driver circuit is configured to provide a first reset control signal to the pixel circuit, and the second reset driver circuit is configured to provide a second reset control signal to the pixel circuit. The second set of gate driver circuits includes a first scan driver circuit and a second scan driver circuit; the first scan driver circuit is configured to provide a first scan signal to the pixel circuit, and the second scan driver circuit is configured to provide a second scan signal to the pixel circuit.

[0021] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0022] On the other hand, this embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate comprises: a display area, and a first frame area located on one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. A plurality of data fan-out lines and a plurality of control signal lines are located in the first frame area, and the plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines comprise: a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate. Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate. The ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.1.

[0023] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes a first sub-line segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes a second sub-line segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

[0024] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes a first sub-segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes a second sub-segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-segment on the substrate is a straight line, and the orthographic projection of the second sub-segment on the substrate is a serpentine line.

[0025] In some exemplary embodiments, each control signal line in the first group of control signal lines includes a first control line segment that overlaps with an orthographic projection of the first group of data fan-out lines on the substrate. Each control signal line in the second group of control signal lines includes a first control line segment that overlaps with an orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control line segment of at least one control signal line in the second group of control signal lines is greater than the line width of the first control line segment of the control signal lines in the first group of control signal lines.

[0026] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0027] Summary of the Figures

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0029] FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0030] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0031] FIG3 is a timing diagram of the operation of the pixel circuit provided in FIG2 ;

[0032] FIG4 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0033] FIG5 is a schematic diagram illustrating the configuration of a gate drive circuit according to at least one embodiment of the present disclosure;

[0034] FIG6 is a partial plan view of a first frame region according to at least one embodiment of the present disclosure;

[0035] FIG7 is a partial enlarged schematic diagram of area S1 in FIG6 ;

[0036] FIG8A is an example diagram of a partial cross-section along the Q1-Q1' direction in FIG7;

[0037] FIG8B is an example diagram of a partial cross-section along the Q2-Q2' direction in FIG7;

[0038] FIG9 is another partial cross-sectional schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0039] FIG10A is another partial cross-sectional view along the Q1-Q1' direction in FIG7;

[0040] FIG10B is another partial cross-sectional view along the Q2-Q2' direction in FIG7;

[0041] FIG11 is another partial schematic plan view of the first border area according to at least one embodiment of the present disclosure;

[0042] FIG12A is a partial enlarged schematic diagram of area S2 in FIG11 ;

[0043] FIG12B is a partial schematic diagram of the first set of data fan-out lines in FIG12A;

[0044] FIG13A is a partial enlarged schematic diagram of area S3 in FIG11 ;

[0045] FIG13B is a partial schematic diagram of the second set of data fan-out lines in FIG13A;

[0046] FIG14A is another partially enlarged schematic diagram of the area S3 in FIG11 ;

[0047] FIG14B is a partial schematic diagram of the second set of data fan-out lines in FIG14A;

[0048] FIG15 is another partially enlarged schematic diagram of the area S3 in FIG11 ;

[0049] FIG16A is another partially enlarged schematic diagram of the area S2 in FIG11 ;

[0050] FIG16B is a partial schematic diagram of the first set of data fan-out lines in FIG16A;

[0051] FIG17A is another partially enlarged schematic diagram of the area S3 in FIG11 ;

[0052] FIG17B is a partial schematic diagram of the second set of data fan-out lines in FIG17A;

[0053] FIG. 18 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0054] Details

[0055] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0056] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0057] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0058] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0059] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0060] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0061] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0062] In this specification, "connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0063] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0064] The terms “approximately” and “substantially” in the present disclosure do not strictly define the limits and allow for errors within the range of process and measurement errors.

[0065] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0066] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0067] With the advancement of display technology, user requirements for display quality are gradually increasing. In the lower bezel area of ​​a display panel, the capacitance generated by overlapping traces can affect the load differences of the signals transmitted by the traces (for example, the load differences of the data signal), resulting in poor display performance. For example, in wearable products such as watches, the overlap of the data fan-out lines transmitting data signals with the traces transmitting AC signals can cause signal load differences, resulting in poor display performance such as light and dark stripes or a split screen.

[0068] This embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate comprises: a display area and a first frame area located to one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first frame area. The plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines comprise: a first group of data fan-out lines and a second group of data fan-out lines. The plurality of control signal lines comprise: a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate. At least one organic insulating layer is disposed between the data fan-out line and the control signal line whose orthographic projection overlaps with the substrate.

[0069] In the display panel provided by this embodiment, in the first frame area, at least one organic insulating layer is arranged between the data fan-out line and the overlapping control signal line, which can increase the distance between the data fan-out line and the overlapping control signal line, thereby reducing the parasitic capacitance between the data fan-out line and the overlapping control signal line, and can improve display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line transmitting the AC signal.

[0070] In some exemplary embodiments, the control signal line may include: a first control line segment, wherein the orthographic projection of the first control line segment on the substrate overlaps with the orthographic projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate; the first control line segment may be located on a side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control line segment may intersect the extension direction of the multiple data fan-out lines. In some examples, in a direction perpendicular to the display panel, the display panel may include at least: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer arranged in a direction away from the substrate; at least a first planar layer is disposed between the first source / drain metal layer and the second source / drain metal layer. The multiple data fan-out lines may be located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segment of the multiple control signal lines may be located in the second source / drain metal layer. In other examples, in a direction perpendicular to the display panel, the display panel may include at least: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in a direction away from the substrate; at least a first flat layer may be arranged between the first source-drain metal layer and the second source-drain metal layer, and at least a second flat layer may be arranged between the second source-drain metal layer and the third source-drain metal layer. A plurality of data fan-out lines may be located in at least one of the first gate metal layer and the second gate metal layer, and a first control line segment of a plurality of control signal lines may be located in the third source-drain metal layer. In this example, by setting the film layer where the first control line segment of the control signal line is located (for example, the first control line segment is located in the second source-drain metal layer or the third source-drain metal layer), the distance between the data fan-out line and the first control line segment of the overlapping control signal line is increased, thereby reducing the parasitic capacitance between the data fan-out line and the overlapping control signal line, thereby effectively improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line.

[0071] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate. The ratio of the first overlapping area to the second overlapping area can range from 0.9 to 1.1, such as 1.0. For example, the first overlapping area and the second overlapping area can be approximately the same. This example adjusts the parasitic capacitance between the data fan-out line and the overlapping control signal lines by adjusting the overlapping area between each data fan-out line and the plurality of control signal lines, so that the parasitic capacitance between the two groups of data fan-out lines and the control signal lines is approximately the same, thereby optimizing display defects such as low grayscale dark stripes caused by uneven overlap between the data fan-out lines and the control signal lines transmitting AC signals.

[0072] In some exemplary embodiments, each data fan-out line within the first group of data fan-out lines may include a first sub-segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate; and each data fan-out line within the second group of data fan-out lines may include a second sub-segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-segment may be smaller than the line width of the second sub-segment. For example, the ratio of the line width of the second sub-segment to the line width of the first sub-segment may be greater than 1 and less than 2. In this example, by increasing the line width of the second sub-segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines and the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines can be roughly the same, and the parasitic capacitance between the second group of data fan-out lines and the overlapping routing lines is increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping routing lines is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0073] In some exemplary embodiments, each data fan-out line within the first group of data fan-out lines may include a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; and each data fan-out line within the second group of data fan-out lines may include a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-segment on the substrate may be a straight line, and the orthographic projection of the second sub-segment on the substrate may be a serpentine line. A serpentine line is a type of meandering curve. For example, one end of the line extends a certain distance in one direction, then bends and twists and extends a certain distance in the opposite direction, then bends and twists again and extends in the same direction, and repeats this process several times to form a serpentine line. In this example, by designing a serpentine line for some segments of the second group of data fan-out lines, the overlap area between the second group of data fan-out lines and the second group of control signal lines can be increased, thereby reducing the difference in parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines.

[0074] In some exemplary embodiments, each control signal line within the first group of control signal lines may include a first control line segment that overlaps with an orthographic projection of the first group of data fan-out lines on the substrate; and each control signal line within the second group of control signal lines may include a first control line segment that overlaps with an orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control line segment of at least one control signal line within the second group of control signal lines may be greater than the line width of the first control line segment of the control signal lines within the first group of control signal lines. In this example, by increasing the line width of the first control line segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines is approximately the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap between the data fan-out lines and the control signal lines.

[0075] The solution of this embodiment is illustrated below through some examples.

[0076] Figure 1 is a schematic diagram of a display panel of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display panel may include: a display area AA, a peripheral border area B2 surrounding the display area AA, and a first border area B1 located on one side of the display area AA. The first border area B1 may be located on the side of the peripheral border area B2 away from the display area AA along the second direction Y. The first border area B1 may be connected to the peripheral border area B2. For example, the first border area B1 may be the lower border of the display panel. The peripheral border area B2 may include: a second border area B21 and a third border area B22 located on both sides of the display area AA along the first direction X. The second border area B21 may be connected to the first border area B1, and the third border area B22 may be connected to the first border area B1. For example, the second border area B21 may be the left border of the display panel, and the third border area B22 may be the right border of the display panel.

[0077] In some examples, as shown in FIG1 , the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic image or a still image. The display area AA may be referred to as an active area. In some examples, the display area AA may be circular or elliptical. However, this embodiment is not limited thereto. For example, the display area may be other shapes such as a rectangle. In some examples, the display panel may be a flexible panel, and thus the display panel may be deformable, such as being curled, bent, folded, or rolled up.

[0078] In some examples, as shown in FIG1 , the display area AA may include: a display structure layer provided on a substrate, or may include a display structure layer and a touch structure layer provided in sequence on a substrate. For example, the display panel may integrate a touch structure to form a structure in which the touch structure is on a thin film package (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0079] In some examples, the display structure layer may include a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions. One sub-pixel PX may be arranged in one sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate drive signals to the plurality of sub-pixels PX. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0080] In some examples, as shown in FIG1 , the first direction X may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y may be an extending direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0081] In some examples, a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0082] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0083] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.

[0084] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0085] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data write transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0086] In some examples, the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0087] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display panel to form a low-temperature polycrystalline oxide (LTPS+Oxide) display panel can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0088] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0089] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0090] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0091] FIG3 is an operating timing diagram of the pixel circuit shown in FIG2. The operating process of the pixel circuit shown in FIG2 will be described below with reference to FIG3. In the pixel circuit, the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0092] In some examples, as shown in FIG. 2 and FIG. 3 , during a frame display period, the operation process of the pixel circuit may include at least: a first stage S11 , a second stage S12 , a third stage S13 , and a fourth stage S14 .

[0093] The first stage S11 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0094] The second stage S12 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The first transistor T1 and the second transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0095] The third stage S13 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0096] In the fourth stage S14, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0097] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2=K×[VDD-Vdata] 2 ;

[0098] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0099] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0100] FIG4 is a partial cross-sectional schematic diagram of a display region according to at least one embodiment of the present disclosure. FIG4 illustrates the structure of a sub-pixel in the display region as an example. In this example, the pixel circuit shown in FIG2 includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0101] In some examples, as shown in FIG4 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include at least a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 10. The display structure layer may include at least the circuit structure layer 12 and the light-emitting structure layer 13. The circuit structure layer 12 may include at least pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least light-emitting elements for multiple sub-pixels.

[0102] In some examples, FIG4 illustrates each sub-pixel as including a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second-type transistor 22 may be an oxide thin-film transistor.

[0103] In some examples, the circuit structure layer 12 in the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, disposed on a substrate 10. A first gate insulating (GI) layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third gate insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth gate insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; an interlayer insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a passivation (PVX) layer 106 and a first planarization (PLN) layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; the first planarization layer 107 may be located on a side of the passivation layer 106 away from the substrate 10; and a second planarization layer 108 may be disposed on a side of the second source / drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the third gate insulating layer 103, the fourth gate insulating layer 104, the interlayer insulating layer 105 and the passivation layer 106 can be inorganic insulating layers, and the first flat layer 107 and the second flat layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be further provided on the side of the first semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also increase the adhesion of the film layer in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can be further provided on the side of the buffer layer close to the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the first flat layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0104] In some examples, as shown in FIG4 , the first semiconductor layer in the display area may include at least a first active layer 210 of the first-type transistor 21. The first active layer 210 of the first-type transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate 213 of the first-type transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first-type transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate 224 of the second-type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap. The second semiconductor layer may include at least a second active layer 220 of the second-type transistor 22. The third gate metal layer may include at least a second gate 223 of the second-type transistor 22. The orthographic projection of the second gate 223 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second-type transistor 22, and the second gate 223 may be the top gate of the second-type transistor 22.

[0105] In some examples, as shown in FIG4 , the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first-type transistor 21, and a second source 221 and a second drain 222 of the second-type transistor 22. The interlayer insulating layer 105 may have a plurality of pixel vias (e.g., a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The interlayer insulating layer 105, the fourth gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The interlayer insulating layer 105, the third gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The interlayer insulating layer 105, fourth gate insulating layer 104, and third gate insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source 211 of the first-type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second-type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second-type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first transfer electrode 241. The first transfer electrode 241 can be electrically connected to the first drain 212 of the first-type transistor 21 of the pixel circuit through a fifth pixel via defined through the passivation layer 106 and the first planarization layer 107. In this example, the first switching electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0106] In some examples, the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer, the data lines of the display area may be located in the second source / drain metal layer, and the high-potential power lines of the display area may be located in the second source / drain metal layer. This embodiment is not limited to this.

[0107] In some examples, as shown in FIG4 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the second planar layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 108. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0108] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0109] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0110] In some examples, as shown in FIG4 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer containing a desiccant or a polymer that can block moisture, or a polymer resin to planarize the surface of the display panel and relieve stress on the first and third encapsulation layers 141 and 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic.

[0111] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0112] In some examples, as shown in FIG4 , in a direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a protective layer 154, arranged in sequence. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an interconnected integral structure. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias provided in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an interconnected integral structure; the second touch conductive layer may include a plurality of first connecting portions, wherein the first connecting portions may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In some examples, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0113] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the embodiments of the present disclosure.

[0114] In some examples, the first and second touch electrodes may be transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0115] FIG5 is a schematic diagram of the gate drive circuit configuration of at least one embodiment of the present disclosure. In some examples, as shown in FIG5 , multiple gate drive circuits may be provided in the peripheral border area, and the multiple gate drive circuits may include: a first scan drive circuit 31, a second scan drive circuit 32, a light-emitting drive circuit 33, a first reset drive circuit 34, and a second reset drive circuit 35. The first scan drive circuit 31 may be configured to provide a first scan signal to multiple rows of pixel circuits in the display area AA. The second scan drive circuit 32 may be configured to provide a second scan signal to multiple rows of pixel circuits in the display area AA. The light-emitting drive circuit 33 may be configured to provide a light-emitting control signal to multiple rows of pixel circuits in the display area AA. The first reset drive circuit 34 may be configured to provide a first reset control signal to multiple rows of pixel circuits in the display area AA.

[0116] The second reset driving circuit 35 may be configured to provide a second reset control signal to the plurality of rows of pixel circuits in the display area AA.

[0117] In some examples, the display area AA includes M rows of pixel circuits, where M is a positive integer. The multiple rows of pixel circuits in the display area can be labeled sequentially from row 1 to row M along a direction approaching the first border area B1. The multiple gate drive circuits can include: a first group of gate drive circuits located in the second border area, and a second group of gate drive circuits located in the third border area. The first group of gate drive circuits can include the following three gate drive circuits: a light-emitting drive circuit 33, a first reset drive circuit 34, and a second reset drive circuit 35. For example, within the second border area, the second reset drive circuit 35, the light-emitting drive circuit 33, and the first reset drive circuit 34 can be arranged sequentially in a first direction X approaching the display area AA. The second group of gate drive circuits can include the following two gate drive circuits: a first scan drive circuit 31 and a second scan drive circuit 32. For example, within the third border area, the first scan drive circuit 31 and the second scan drive circuit 32 can be arranged sequentially in the first direction X away from the display area AA. In other examples, three gate drive circuits can be provided in the peripheral border area, one gate drive circuit can be provided in the second border area, and two gate drive circuits can be provided in the third border area. This embodiment is not limited to this.

[0118] In some examples, the first scan driving circuit 31 may include a plurality of cascaded first scan driving units (e.g., GP(1) to GP(M)). Each level of the first scan driving unit may be configured to provide a first scan signal to a row of pixel circuits in the display area AA. For example, the first-level first scan driving unit GP(1) may be configured to provide a first scan signal to the first row of pixel circuits in the display area AA; the M-th level first scan driving unit GP(M) may be configured to provide a first scan signal to the M-th row of pixel circuits in the display area AA.

[0119] In some examples, the second scan driving circuit 32 may include a plurality of cascaded second scan driving units (e.g., GN(1) to GN(M / 2)). Each level of the second scan driving unit may be configured to provide a second scan signal to two adjacent rows of pixel circuits in the display area AA. For example, the first level second scan driving unit GN(1) may be configured to provide a second scan signal to the 1st and 2nd rows of pixel circuits in the display area AA; the M / 2th level second scan driving unit GP(M / 2) may be configured to provide a second scan signal to the M-1th and Mth rows of pixel circuits in the display area AA.

[0120] In some examples, the light-emitting driving circuit 33 may include a plurality of cascaded light-emitting driving units (e.g., EM(1) to EM(M / 2)). Each level of light-emitting driving units may be configured to provide light-emitting control signals to two adjacent rows of pixel circuits in the display area AA. For example, the first-level light-emitting driving unit EM(1) may be configured to provide light-emitting control signals to the 1st and 2nd rows of pixel circuits in the display area AA; the M / 2-level light-emitting driving unit EM(M / 2) may be configured to provide light-emitting control signals to the M-1st and Mth rows of pixel circuits in the display area AA.

[0121] In some examples, the first reset driving circuit 34 may include a plurality of cascaded first reset driving units (e.g., RP(1) to RP(M / 2)). Each level of the first reset driving unit may be configured to provide a first reset control signal to two adjacent rows of pixel circuits in the display area AA. For example, the first reset driving unit RP(1) of the first level may be configured to provide a first reset control signal to the 1st and 2nd rows of pixel circuits in the display area AA; the M / 2th level of the first reset driving unit RP(M / 2) may be configured to provide a first reset control signal to the M-1th and Mth rows of pixel circuits in the display area AA.

[0122] In some examples, the second reset driving circuit 35 may include a plurality of cascaded second reset driving units (e.g., RH(1) to RH(M / 2)). Each stage of the second reset driving unit may be configured to provide a second reset control signal to two adjacent rows of pixel circuits in the display area AA. For example, the first stage of the second reset driving unit RH(1) may be configured to provide a second reset control signal to the 1st and 2nd rows of pixel circuits in the display area AA; the M / 2th stage of the second reset driving unit RH(M / 2) may be configured to provide a second reset control signal to the M-1th and Mth rows of pixel circuits in the display area AA.

[0123] In some examples, as shown in Figure 1, the first border area B1 may include: a bending area B12, a fan-out area B13, a first signal access area B14, and a second signal access area B15, which are arranged in sequence along a direction away from the display area AA. The bending area B12 can be connected to the peripheral border area B2 and the fan-out area B13, and is located on the side of the peripheral border area B2 away from the display area AA. The fan-out area B13 can be located on the side of the bending area B12 away from the display area AA. The first signal access area B14 can be located on the side of the fan-out area B13 away from the display area AA. The second signal access area B15 can be located on the side of the first signal access area B14 away from the display area AA.

[0124] In some examples, the peripheral frame area B2 may be provided with a first peripheral power line, a second peripheral power line, and a plurality of gate drive circuits. The first peripheral power line may be connected to a first power line electrically connected to the pixel circuits of the plurality of sub-pixels PX of the display area AA, and configured to transmit a first voltage signal. The second peripheral power line may extend from the left side along the edge of the display panel to the second frame area, and from the right side along the edge of the display panel to the third frame area. The second peripheral power line may be connected to the second power line, and configured to transmit a second voltage signal to the plurality of sub-pixels of the display area AA. The plurality of gate drive circuits may be arranged in the second frame area B21 and the third frame area B22.

[0125] In some examples, the peripheral border region B2 between the display area AA and the first border region B1 may be provided with multiple multiplexing circuits. For example, one multiplexing circuit may be connected to a multiplexed data line and multiple data lines, and configured to provide a data signal transmitted by one multiplexed data line to multiple data lines.

[0126] In some examples, the peripheral border area B2 may also be provided with a plurality of peripheral control lines. The plurality of peripheral control lines may include: a first group of peripheral control lines and a second group of peripheral control lines. For example, the first group of peripheral control lines may include: a plurality of peripheral drive control lines that provide drive control signals (such as start signals, clock signals, power signals, etc.) to the first group of gate drive circuits in the second border area B21; the second group of peripheral control lines may include: a plurality of peripheral drive control lines that provide drive control signals to the second group of gate drive circuits in the third border area B22. In other examples, each group of peripheral control lines may include: a plurality of peripheral drive control lines and a plurality of peripheral multiplexing control lines, and the plurality of peripheral multiplexing control lines may be connected to a plurality of multiplexing circuits and configured to provide a multiplexing control signal to the multiplexing circuit so that the multiplexing circuit provides the data signal transmitted by the multiplexed data line to the plurality of data lines under the control of the multiplexing control signal.

[0127] In some examples, the peripheral frame area B2 may further be provided with a plurality of peripheral touch lines, which may be located in the touch structure layer and connected to the first touch electrode or the second touch electrode of the display area AA.

[0128] In some examples, the bending region B12 can be configured to bend the fan-out region B13, the first signal access region B14, and the second signal access region B15 toward the back of the display area AA. The bending region B12 can be provided with multiple curved connecting lines to connect the lines transmitting the same signal within the peripheral border region B2 and the fan-out region B13. The multiple curved connecting lines in the bending region B12 can be in the same layer structure, for example, they can all be located in the second source and drain metal layer.

[0129] Figure 6 is a partial plan view of the first border area of ​​at least one embodiment of the present disclosure. Figure 6 illustrates the partial structure of the bend area B12, the fan-out area B13, the first signal access area B14, and the second signal access area B15. Figure 6 provides an overall schematic diagram of the data bend connection lines, touch bend connection lines, control bend connection lines, control connection lines, and data fan-out lines in the first border area. The control signal lines are illustrated using only a few lines as an example. This example does not limit the number of various lines in the first border area.

[0130] In some examples, as shown in FIG6 , the plurality of bending connection lines in the bending region B12 may include: first power bending connection lines 53a, 53b, 53c, and 53d, second power bending connection lines 54a and 54b, a first group of data bending connection lines 51a, a second group of data bending connection lines 51b, a group of control bending connection lines 52, a first group of touch bending connection lines 55a, and a second group of touch bending connection lines 55b. The second power bending connection line 54a, the first group of data bending connection lines 51a, the first power bending connection line 53a, the first group of touch bending connection lines 55a, the first power bending connection line 53b, the group of control bending connection lines 52, the first power bending connection line 53c, the second group of touch bending connection lines 55b, the first power bending connection line 53d, the first group of data bending connection lines 51b, and the second power bending connection line 54b may be arranged sequentially along the first direction X.

[0131] In some examples, as shown in Figure 6, the fan-out area B13 can be provided with at least a first power lead 43, a second power lead 44a and 44b, multiple data fan-out lines (for example, including a first group of data fan-out lines 41a and a second group of data fan-out lines 41b), multiple control connection lines (for example, including a first group of control connection lines 56a and a second group of control connection lines 56b), multiple control signal lines (for example, including a first group of control signal lines 42a and a second group of control signal lines 42b), and multiple touch lead lines (for example, including a first group of touch lead lines 45a and a second group of touch lead lines 45b).

[0132] In some examples, as shown in FIG6 , the first power lead 43 can be connected to the first peripheral power line of the peripheral border area via the first power connection lines 53a, 53b, 53c, and 53d of the bend region B12. The first power lead 43 can be located, for example, in the first source / drain metal layer, or in the second source / drain metal layer, or can adopt a dual-layer routing structure arranged in the first source / drain metal layer and the second source / drain metal layer. The first power lead 43 can include at least: a first main portion extending along the first direction X, four connecting portions extending along the second direction Y toward the side of the bend region B12, a first power extension portion extending along a third direction F3, and a second power extension portion extending along a fourth direction F4. The third direction F3 can intersect both the first direction X and the second direction Y, the fourth direction F4 can intersect both the first direction X and the second direction Y, and the third direction F3 can intersect the fourth direction F4. The four connecting portions of the first power lead 43 can be electrically connected to the four first power connection lines 53a, 53b, 53c, and 53d of the bend region B12 in a one-to-one correspondence. The first power extension portion can extend from the left side around the first signal access area B14 to connect with the contact pad in the second signal access area B15, and the second power extension portion can extend from the right side around the first signal access area B14 to connect with the contact pad in the second signal access area B15.

[0133] In some examples, as shown in FIG6 , the second power lead 44a can be connected to the second peripheral power line of the peripheral frame area through the second power connection line 54a of the bending area B12, and the second power lead 44b can be connected to the second peripheral power line of the peripheral frame area through the second power connection line 54b of the bending area B12. The second power lead 44a can be located on the side opposite to the first power lead 43 along the first direction X, and the second power lead 44b can be located on the side of the first power lead 43 along the first direction X. The second power leads 44a and 44b can both be located in the first source and drain metal layer, or can both be located in the second source and drain metal layer, or can adopt a double-layer routing structure arranged in the first source and drain metal layer and the second source and drain metal layer. The second power lead 44a can bypass the first signal access area B14 from the left to extend to connect to the contact pad in the second signal access area B15. The second power lead 44b can bypass the first signal access area B14 from the right to extend to connect to the contact pad in the second signal access area B15.

[0134] In some examples, as shown in FIG6 , the plurality of data fan-out lines in the fan-out area B13 may extend substantially along the second direction Y toward the first signal access area B14. The plurality of data fan-out lines may include a first group of data fan-out lines 41 a and a second group of data fan-out lines 41 b. The first group of data fan-out lines 41 a may be located between the second power lead line 44 a and the first group of control connection lines 56 a, and the second group of data fan-out lines 41 b may be located between the second power lead line 44 b and the second group of control connection lines 56 b. Multiple data fan-out lines in the first group of data fan-out lines 41a can be connected to multiple multiplexed data lines in the peripheral frame area through multiple data bend connection lines in the first group of data bend connection lines 51a in the bend area B12, so as to provide data signals to the multiple data lines through multiple multiplexing circuits; multiple data fan-out lines in the second group of data fan-out lines 41b can be connected to multiple multiplexed data lines in the peripheral frame area through multiple data bend connection lines in the second group of data bend connection lines 51b in the bend area B12, so as to provide data signals to the multiple data lines through multiple multiplexing circuits. For example, the first group of data fan-out lines 41a can be configured to provide data signals to sub-pixels in the left half area of ​​the display area, and the second group of data fan-out lines 41b can be configured to provide data signals to sub-pixels in the right half area of ​​the display area. The number of data fan-out lines in the first group of data fan-out lines 41a can be the same as the number of data fan-out lines in the second group of data fan-out lines 41b. For example, the plurality of data fan-out lines may be located in the first gate metal layer, or may be located in the second gate metal layer, or may be alternately arranged in the first gate metal layer and the second gate metal layer.

[0135] In some examples, as shown in FIG6 , the plurality of control connection lines may include: a first group of control connection lines 56 a and a second group of control connection lines 56 b. The first group of control connection lines 56 a and the second group of control connection lines 56 b may be located between the first group of data fan-out lines 41 a and the second group of data fan-out lines 41 b. The plurality of control connection lines may be connected to the plurality of peripheral control lines in the peripheral border area through a group of control bending connection lines 52 in the bending area B12. The first group of control connection lines 56 a and the second group of control connection lines 56 b may be arranged in a shape of an inverted Y. For example, the plurality of control connection lines may be located in the first gate metal layer, or in the second gate metal layer, or may adopt a double-layer routing structure arranged in the first gate metal layer and the second gate metal layer.

[0136] In some examples, as shown in FIG6 , the multiple control signal lines in the fan-out region B13 may include: a first group of control signal lines 42a and a second group of control signal lines 42b. The first group of control signal lines 42a may be connected to the first group of control connection lines 56a, and the second group of control signal lines 42b may be connected to the second group of control connection lines 56b. The orthographic projection of the first group of control signal lines 42a on the substrate overlaps with the orthographic projection of the first group of data fan-out lines 41a on the substrate, and the orthographic projection of the second group of control signal lines 42b on the substrate overlaps with the orthographic projection of the second group of data fan-out lines 41b on the substrate. The first group of control signal lines 42a and the second group of control signal lines 42b may be located on the side of the first main body of the first power lead 43 away from the bending region B12.

[0137] In some examples, each group of control signal lines may include at least a plurality of drive control lines, and the drive control lines may be configured to provide drive control signals to the gate drive circuit. The plurality of drive control lines included in the first group of control signal lines may be configured to provide drive control signals to the first group of gate drive circuits located in the second border area, and the plurality of drive control lines included in the second group of control signal lines may be configured to provide drive control signals to the second group of gate drive circuits located in the third border area. In other examples, each group of control signal lines may include at least: a plurality of drive control lines and a plurality of multiplexing control lines, and the plurality of multiplexing control lines may be configured to provide multiplexing control signals to a plurality of multiplexing circuits in the peripheral border area.

[0138] In some examples, the first group of control signal lines 42a can bypass the first signal access area B14 from the left to extend to connect with the contact pads within the second signal access area B15; the second group of control signal lines 42b can bypass the first signal access area B14 from the right to extend to connect with the contact pads within the second signal access area B15.

[0139] In some examples, the fan-out area B13 may also be provided with a first electrostatic discharge circuit 46 and a second electrostatic discharge circuit 47. The first group of control signal lines 42a may be connected to the first electrostatic discharge circuit 46, and the second group of control signal lines 42b may be connected to the second electrostatic discharge circuit 47. The first electrostatic discharge circuit 46 may be configured to provide an electrostatic discharge path for the first group of control signal lines 42a, and the second electrostatic discharge circuit 47 may be configured to provide an electrostatic discharge path for the second group of control signal lines 42b. The first electrostatic discharge circuit 46 may be located between the first group of data fan-out lines 41a and the first group of touch lead lines 45a, and the second electrostatic discharge circuit 47 may be located between the second group of data fan-out lines 41b and the second group of touch lead lines 45b.

[0140] In some examples, as shown in FIG6 , the plurality of touch lead lines in the fan-out area B12 may extend approximately along the second direction Y toward the first signal access area B14. The plurality of touch lead lines may include a first group of touch lead lines 45a and a second group of touch lead lines 45b. The first group of touch lead lines 45a may be connected to the peripheral touch lines in the peripheral frame area through the first group of touch bending connection lines 55a in the bending area B12, and the second group of touch lead lines 45b may be connected to the peripheral touch lines in the peripheral frame area through the second group of touch bending connection lines 55b in the bending area B12. The arrangement shape of the first group of touch lead lines 45a and the second group of touch lead lines 45b may be approximately Y-shaped. For example, the plurality of touch lead lines may be located in the first touch conductive layer or the second touch conductive layer of the touch structure layer. The orthographic projection of the first group of touch lead lines 45a on the substrate may overlap with the orthographic projection of the first group of control connection lines 56a on the substrate, and the orthographic projection of the second group of touch lead lines 45b on the substrate may overlap with the orthographic projection of the second group of control connection lines 56b on the substrate. The first group of touch lead lines 45a and the second group of touch lead lines 45b may be located between the first group of control signal lines 42a and the second group of control signal lines 42b.

[0141] In some examples, as shown in FIG6 , the first signal access area B14 can be configured to house a driver chip (IC). For example, the driver chip housed in the first signal access area B14 can be a display driver chip or a touch and display driver integrated circuit (TDDI). The first signal access area B14 can also be referred to as a driver chip placement area. The driver chip can be configured to generate data signals required to drive the sub-pixels and provide the data signals to the data lines of the display area.

[0142] In some examples, the first signal access area B14 may be provided with a plurality of first contact pads, which may include: a first group of first contact pads 61 and a second group of first contact pads 62. The second group of first contact pads 62 may be located on a side of the first group of first contact pads 61 away from the bending area B12. The plurality of first contact pads within the first group of first contact pads 61 may be arranged in at least one row along the first direction X. A plurality of data fan-out lines may be connected to the plurality of first contact pads within the first group of first contact pads 61 within the first signal access area B14 to receive data signals from a driver chip; a plurality of touch lead-out lines may be connected to the plurality of first contact pads within the first group of first contact pads 61 within the first signal access area B14 to receive touch signals from the driver chip. The plurality of first contact pads within the second group of first contact pads 62 may be arranged in a row along the first direction X.

[0143] In some examples, the second signal access area B15 may be provided with a plurality of second contact pads 63. The plurality of second contact pads 63 may be configured to bind a flexible printed circuit (FPC) so that a plurality of signal lines (for example, including a plurality of control signal lines, a first power lead line and a second power lead line, etc.) are connected to an external control device through the plurality of second contact pads 63. The second signal access area B15 may also be referred to as a circuit binding area. The second group of first contact pads 62 within the first signal access area B14 may be electrically connected to the plurality of second contact pads 63 within the second signal access area B15 through a plurality of pin connection lines 64.

[0144] In some examples, since the number of gate drive circuits set in the peripheral border area is odd (for example, five), the number of gate drive circuits set in the second border area and the third border area cannot be evenly distributed (for example, three gate drive circuits are set in the second border area, and two gate drive circuits are set in the third border area), which will cause uneven overlap of the routing of the two groups of data fan-out lines and the two groups of control signal lines in the first border area. For example, the number of control signal lines in the first group of control signal lines that overlap with the first group of data fan-out lines is greater than the number of control signal lines in the second group of control signal lines that overlap with the second group of data fan-out lines, thereby causing inconsistent parasitic capacitances between multiple data fan-out lines and the overlapping routings, which can easily cause poor display such as low grayscale dark stripes. This example reduces the parasitic capacitance between the data fan-out lines and the overlapping control signal lines by increasing the distance between the data fan-out lines and the overlapping control signal lines, thereby improving poor display such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0145] Figure 7 is a partially enlarged schematic diagram of region S1 in Figure 6. Figure 8A is an example of a partial cross-section taken along the Q1-Q1' direction in Figure 7. Figure 8B is an example of a partial cross-section taken along the Q2-Q2' direction in Figure 7. The following describes the positional relationship between the first set of data fan-out lines 41a and the first set of control signal lines 42a as an example.

[0146] In some examples, as shown in FIG7 , the first group of data fan-out lines 41a may include: a plurality of first data fan-out lines 411a located in the first gate metal layer and a plurality of second data fan-out lines 412a located in the second gate metal layer. The plurality of first data fan-out lines 411a and the plurality of second data fan-out lines 412a may be spaced apart from each other, and the orthographic projections of the first data fan-out lines 411a and the second data fan-out lines 412a on the substrate do not overlap. In other words, the spacing between the orthographic projections of the first data fan-out lines 411a and the adjacent second data fan-out lines 412a on the substrate may be greater than zero.

[0147] In some examples, as shown in Figures 6 and 7, each control signal line within the first group of control signal lines 42a may include a first control line segment 421a, a second control line segment 422a, and a third control line segment 423a. One end of the first control line segment 421a is connected to one end of the second control line segment 422a, and the other end of the first control line segment 421a is connected to one end of the third control line segment 423a. The other end of the third control line segment 423a may be connected to the control connection line 56. The other end of the second control line segment 422a may extend to connect to a contact pad of the second signal access area. The orthographic projection of the first control line segment 421a on the substrate overlaps with the orthographic projection of the first group of data fan-out lines 41a on the substrate, while the orthographic projections of the second control line segment 422a and the third control line segment 423a on the substrate do not overlap with the orthographic projections of the first group of data fan-out lines 41a on the substrate.

[0148] In some examples, the second control line segment 422a and the third control line segment 423a can be in the same layer structure, for example, they can be located in the first source-drain metal layer. The first control line segment 421a and the second control line segment 422a and the third control line segment 423a can be in different layers. For example, the first control line segment 421a can be located on the side of the second control line segment 422a and the third control line segment 423a away from the substrate. For example, the first control line segment 421a can be located in the second source-drain metal layer. However, this embodiment is not limited to this. In other examples, the first control line segment, the second control line segment, and the third control line segment of the control signal line can be an integrated structure connected to each other, for example, they can be located in the second source-drain metal layer.

[0149] In some examples, as shown in Figures 8A and 8B, the first data fan-out line 411a is located in the first gate metal layer, the second data fan-out line 412a is located in the second gate metal layer, and the first control line segment 421a of the control signal line within the first group of control signal lines 42a is located in the second source-drain metal layer. At least one organic insulating layer (including the first planarizing layer 107) and multiple inorganic insulating layers (for example, including at least the passivation layer 106, the interlayer insulating layer 105, and the second gate insulating layer 102) are disposed between the first control line segment 421a of the control signal line and the overlapping first data fan-out line 411a. At least one organic insulating layer (including the first planarizing layer 107) and multiple inorganic insulating layers (for example, including at least the passivation layer 106 and the interlayer insulating layer 105) are disposed between the first control line segment 421a of the control signal line and the overlapping second data fan-out line 412a.

[0150] In some examples, as shown in FIG6 , each control signal line within the second group of control signal lines 42 b may include a first control line segment 421 b, a second control line segment 422 b, and a third control line segment 423 b. The orthographic projection of the first control line segment 421 b on the substrate overlaps with the orthographic projection of the second group of data fan-out lines 41 b on the substrate, while the orthographic projections of the second control line segment 422 b and the third control line segment 423 b on the substrate do not overlap with the orthographic projections of the second group of data fan-out lines 41 b on the substrate. The film layer configuration of the second group of data fan-out lines 41 b is the same as that of the first group of data fan-out lines 41 a, and the film layer configuration of the second group of control signal lines 42 b is the same as that of the second group of control signal lines 42 a, and therefore will not be further described herein.

[0151] In this example, an organic insulating layer is provided between the data fan-out line and the first control line segment of the overlapping control signal line, so that the data fan-out line and the first control line segment of the control signal line are spaced farther apart, thereby reducing the parasitic capacitance between the data fan-out line and the control signal line, and improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line.

[0152] Figure 9 is another partial cross-sectional view of a display panel according to at least one embodiment of the present disclosure. Figure 10A is another partial cross-sectional view taken along the Q1-Q1' direction in Figure 7. Figure 10B is another partial cross-sectional view taken along the Q2-Q2' direction in Figure 7.

[0153] In some examples, as shown in FIG9 , in a direction perpendicular to the display panel, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer, disposed on a substrate 10. A passivation layer 106 and a first planarization layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; a second planarization layer 108 may be disposed between the second source / drain metal layer and the third source / drain metal layer; and a third planarization layer 109 may be disposed on the side of the third source / drain metal layer facing away from the substrate 10. The first planarization layer 107, the second planarization layer 108, and the third planarization layer 109 may be organic insulating layers. The third source / drain metal layer may include at least a second transfer electrode 242. The second transfer electrode 242 may be connected to a first transfer electrode 241 located in the second source / drain metal layer via a via provided in the second planarization layer 108. In this example, the second transfer electrode 242 and the first transfer electrode 241 enable electrical connection between the pixel circuit and the light-emitting element. The remaining film layer structures of the display panel of this example can be referred to the description of the embodiment shown in FIG4 , and therefore will not be described again here.

[0154] In some examples, as shown in Figures 10A and 10B, the first data fan-out line 411a is located in the first gate metal layer, the second data fan-out line 412a is located in the second gate metal layer, and the first control line segment 421a of the control signal line within the first group of control signal lines 42a can be located in the third source-drain metal layer. At least two organic insulating layers (including a first planar layer 107 and a second planar layer 108) and multiple inorganic insulating layers (for example, including at least a passivation layer 106, an interlayer insulating layer 105, and a second gate insulating layer 102) are provided between the first control line segment 421a of the control signal line and the overlapping first data fan-out line 411a. At least two organic insulating layers (including a first planar layer 107 and a second planar layer 108) and multiple inorganic insulating layers (for example, including at least a passivation layer 106 and an interlayer insulating layer 105) are provided between the first control line segment 421a of the control signal line and the overlapping second data fan-out line 412a. The remaining description of the first border area of ​​this example can be referred to the description of the previous embodiment, and is not repeated here.

[0155] In this example, two organic insulating layers are set between the data fan-out line and the first control line segment of the overlapping control signal line, so that the data fan-out line and the first control line segment of the control signal line can be further apart, and the parasitic capacitance between the data fan-out line and the control signal line can be better isolated, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line.

[0156] This example increases the distance between the data fan-out line and the first control line segment of the overlapping control signal line by adjusting the film layer where the first control line segment of the control signal line is located (for example, the first control line segment is located in the second source-drain metal layer or the third source-drain metal layer), and reduces the parasitic capacitance between the data fan-out line and the overlapping control signal line, thereby effectively improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out line and the control signal line.

[0157] Figure 11 is another partial plan view of the first border area of ​​at least one embodiment of the present disclosure. Figure 11 illustrates the partial structure of the bending area B12, the fan-out area B13, the first signal access area B14, and the second signal access area B15. Figure 11 provides an overall schematic diagram of the data bending connection lines, touch bending connection lines, control bending connection lines, control connection lines, and data fan-out lines in the first border area. The control signal lines are illustrated using only a few lines as an example. This example does not limit the number of various lines in the first border area.

[0158] In some examples, as shown in FIG11 , the number of control signal lines within the first group of control signal lines 42 a is greater than the number of control signal lines within the second group of control signal lines 42 b. Each control signal line within the first group of control signal lines 42 a may be an integral structure located in the same film layer, and each control signal line within the second group of control signal lines 42 b may be an integral structure located in the same film layer. For example, multiple control signal lines may be located in the first source / drain metal layer. However, this embodiment is not limited to this. In other examples, multiple control signal lines may be located in the second source / drain metal layer or the third source / drain metal layer.

[0159] Figure 12A is a partially enlarged schematic diagram of area S2 in Figure 11. Figure 12B is a partially enlarged schematic diagram of the first group of data fan-out lines in Figure 12A. In some examples, as shown in Figures 12A and 12B, the first group of data fan-out lines 41a may include: a plurality of first data fan-out lines 411a located in the first gate metal layer and a plurality of second data fan-out lines 412a located in the second gate metal layer. The plurality of first data fan-out lines 411a and the plurality of second data fan-out lines 412a may be arranged one by one, and the orthographic projections of the first data fan-out lines 411a and the second data fan-out lines 412a on the substrate do not overlap. In other words, the spacing between the orthographic projections of the first data fan-out lines 411a and the adjacent second data fan-out lines 412a on the substrate may be greater than zero.

[0160] In some examples, as shown in Figures 12A and 12B, each data fan-out line within the first group of data fan-out lines 41a may include a first sub-segment 41-1, a third sub-segment 41-3, and a fourth sub-segment 41-4. One end of the first sub-segment 41-1 is connected to one end of the third sub-segment 41-3, and the other end of the first sub-segment 41-1 is connected to one end of the fourth sub-segment 41-4. The other end of the third sub-segment 41-3 may extend toward the bending region, and the other end of the fourth sub-segment 41-4 may extend toward the first signal access region. The orthographic projection of the first sub-segment 41-1 on the substrate overlaps with the orthographic projection of the first group of control signal lines 42a on the substrate, while the orthographic projections of the third sub-segment 41-3 and the fourth sub-segment 41-4 on the substrate may not overlap with the orthographic projections of the first group of control signal lines 42a on the substrate. The first sub-segment 41-1, third sub-segment 41-3, and fourth sub-segment 41-4 of the data fan-out lines within the first group of data fan-out lines 41a can be interconnected and integrated. The orthographic projection of the data fan-out lines within the first group of data fan-out lines 41a onto the substrate can be a straight line, and the orthographic projection of the first sub-segment 41-1 onto the substrate can be roughly a long strip. The line width of the first sub-segment 41-1 of the data fan-out line can be a first line width W1, and the line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4 can be the same as the line width of the first sub-segment 41-1.

[0161] In some examples, as shown in Figures 12A and 12B, each control signal line within the first group of control signal lines 42a may include a first control line segment 421a, wherein an orthographic projection of the first control line segment 421a on the substrate overlaps an orthographic projection of a first sub-segment 41-1 of a data fan-out line within the first group of data fan-out lines 41a on the substrate. For example, the first control line segment 421a of each control signal line may have a third line width K1.

[0162] In some examples, each data fan-out line in the first group of data fan-out lines 41a can have a first overlapping area with the orthographic projection of the first group of control signal lines 42a on the substrate. The first overlapping area can be the sum of the overlapping areas of a data fan-out line in the first group of data fan-out lines 41a and all control signal lines in the first group of control signal lines 42a. The first overlapping areas corresponding to multiple data fan-out lines in the first group of data fan-out lines 41a can be substantially the same.

[0163] Figure 13A is a partially enlarged schematic diagram of area S3 in Figure 11. Figure 13B is a partially enlarged schematic diagram of the second group of data fan-out lines in Figure 13A. In some examples, as shown in Figures 13A and 13B, the second group of data fan-out lines 41b may include: a plurality of first data fan-out lines 411b located in the first gate metal layer and a plurality of second data fan-out lines 412b located in the second gate metal layer. The plurality of first data fan-out lines 411b and the plurality of second data fan-out lines 412b may be arranged one by one, and the orthographic projections of the first data fan-out lines 411b and the second data fan-out lines 412b on the substrate do not overlap. In other words, the spacing between the orthographic projections of the first data fan-out lines 411b and the adjacent second data fan-out lines 412b on the substrate may be greater than zero.

[0164] In some examples, as shown in Figures 13A and 13B, each data fan-out line within the second group of data fan-out lines 41b may include a second sub-segment 41-2, a fifth sub-segment 41-5, and a sixth sub-segment 41-6. One end of the second sub-segment 41-2 is connected to one end of the fifth sub-segment 41-5, and the other end of the second sub-segment 41-2 is connected to one end of the sixth sub-segment 41-6. The other end of the fifth sub-segment 41-5 may extend toward the bending region, and the other end of the sixth sub-segment 41-6 may extend toward the first signal access region. The orthographic projection of the second sub-segment 41-2 on the substrate overlaps with the orthographic projection of the second group of control signal lines 42b on the substrate, while the orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 on the substrate may not overlap with the orthographic projections of the second group of control signal lines 42b on the substrate. The second sub-segment 41 - 2 , the fifth sub-segment 41 - 5 and the sixth sub-segment 41 - 6 of the data fan-out lines in the second group of data fan-out lines 41 b may be an integrated structure connected to each other.

[0165] In some examples, as shown in Figures 13A and 13B, each control signal line within the second group of control signal lines 42b may include a first control line segment 421b, whose orthographic projection on the substrate overlaps with the orthographic projection on the substrate of the second sub-segment 41-2 of the data fan-out line within the second group of data fan-out lines 41b. For example, the first control line segment 421b of each control signal line may have a fourth line width K2. For example, the fourth line width K2 may be substantially the same as the third line width K1.

[0166] In some examples, each data fan-out line in the second group of data fan-out lines 41b may have a second overlapping area with an orthographic projection of the second group of control signal lines 42b on the substrate. The second overlapping area may be the sum of overlapping areas of a data fan-out line in the second group of data fan-out lines 41b and all control signal lines in the second group of control signal lines 42b. The second overlapping areas corresponding to multiple data fan-out lines in the second group of data fan-out lines 41b may be substantially the same.

[0167] In some examples, the orthographic projection of the second sub-segment 41-2 of the data fan-out lines within the second group of data fan-out lines 41b onto the substrate can be a serpentine routing. Because the number of control signal lines within the second group of control signal lines is less than the number of control signal lines within the first group of control signal lines, the number of control signal lines overlapped by each data fan-out line within the second group of data fan-out lines 41b is less than the number of control signal lines overlapped by each data fan-out line within the first group of data fan-out lines 41a. In this example, by configuring the second sub-segment 41-2 of the data fan-out lines within the second group of data fan-out lines 41b as a serpentine routing, the second overlapping area corresponding to the data fan-out lines within the second group of data fan-out lines can be increased, such that the second overlapping area can be substantially the same as the first overlapping area corresponding to the data fan-out lines within the first group of data fan-out lines, thereby reducing the difference in parasitic capacitance between the two groups of data fan-out lines and the overlapping routing lines. In some examples, the ratio of the first overlapping area to the second overlapping area can range from 0.9 to 1.1, for example, can be approximately 1.0.

[0168] In some examples, the orthographic projection of the fifth sub-segment 41-5 or the sixth sub-segment 41-6 of at least one data fan-out line in the second group of data fan-out lines 41b onto the substrate may be a serpentine line. For example, the orthographic projection of the fifth sub-segment 41-5 or the sixth sub-segment 41-6 of multiple data fan-out lines in the second group of data fan-out lines 41b near the touch lead lines onto the substrate may be a serpentine line. In some examples, due to the different numbers of pixel circuits electrically connected to each of the multiple data lines in the display area, the loads on the multiple data lines are different. For example, the display area is circular or elliptical, and the display area can be divided into a central area and left and right areas along the first direction X. The number of pixel circuits connected to the data lines in the central area is greater than the number of pixel circuits connected to the data lines in the left or right areas. As a result, the load on the data lines in the central area is different from the load on the data lines in the left and right areas. To ensure the display effect of the display area, load compensation is required for the data lines to ensure that the loads on the multiple data lines in the display area are approximately the same. In this example, the load compensation for the data lines in the display area is adjusted by setting the orthographic projection of the fifth sub-segment 41 - 5 or the sixth sub-segment 41 - 6 of at least one data fan-out line on the substrate to be a serpentine line.

[0169] In some examples, the line widths of the fifth and sixth sub-segments 41-5 and 41-6 in the second group of data fan-out lines 41b, which adopt a straight line design, may be substantially the same as the first line width of the first sub-segment 41-1 in the first group of data fan-out lines 41a.

[0170] This example utilizes a serpentine routing design for some segments of the second set of data fan-out lines. This not only increases the overlapping area between the second set of data fan-out lines and the second set of control signal lines, thereby reducing the parasitic capacitance difference between the two sets of data fan-out lines and the overlapping control signal lines, but also performs load compensation on the data lines in the display area to ensure that the loads of multiple data lines in the display area are roughly the same.

[0171] Figure 14A is another partially enlarged schematic diagram of area S3 in Figure 11. Figure 14B is a partially enlarged schematic diagram of the second group of data fan-out lines in Figure 14A. In some examples, as shown in Figures 14A and 14B, each data fan-out line within the second group of data fan-out lines 41b may include: a second sub-segment 41-2, a fifth sub-segment 41-5, and a sixth sub-segment 41-6. One end of the second sub-segment 41-2 is connected to one end of the fifth sub-segment 41-5, and the other end of the second sub-segment 41-2 is connected to one end of the sixth sub-segment 41-6. The other end of the fifth sub-segment 41-5 may extend toward the bending region, and the other end of the sixth sub-segment 41-6 may extend toward the first signal access region. The orthographic projection of the second sub-segment 41-2 on the substrate overlaps with the orthographic projection of the second group of control signal lines 42b on the substrate. The orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 on the substrate may not overlap with the orthographic projections of the second group of control signal lines 42b on the substrate. The second sub-segment 41-2, the fifth sub-segment 41-5, and the sixth sub-segment 41-6 of the data fan-out lines within the second group of data fan-out lines 41b may be interconnected and integrally formed.

[0172] In some examples, as shown in Figures 14A and 14B, the orthographic projection of the second sub-segment 41-2 of the data fan-out lines of the second group of data fan-out lines 41b on the substrate can be a straight line. The second sub-segment 41-2 can have a second line width W2. The second line width W2 can be the maximum line width of the second sub-segment 41-2. The second line width W2 of the second sub-segment 41-2 can be greater than the first line width W1 of the first sub-segment 41-1 of the data fan-out lines of the first group of data fan-out lines 41a.

[0173] In some examples, the orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 of the data fan-out lines of the second group of data fan-out lines 41b on the substrate can both be straight lines. The line widths of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 can be substantially the same, for example, the same as the first line width W1. For example, the ratio of the second line width W2 to the first line width W1 can be greater than 1 and less than 2, for example, approximately 1.7. In some examples, the first line width W1 can be approximately 5.1 microns (μm), and the second line width W2 can be approximately 8.7 μm.

[0174] In this example, by increasing the line width of the second sub-segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines and the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines can be roughly the same, and the parasitic capacitance between the second group of data fan-out lines and the overlapping routing lines is increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping routing lines is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0175] Figure 15 is another partially enlarged schematic diagram of area S3 in Figure 11. In some examples, as shown in Figure 15, the line shape and line width of the data fan-out lines in the second group of data fan-out lines 41b can be the same as the line shape and line width of the data fan-out lines in the first group of data fan-out lines 41a. The fourth line width K2 of the first control line segment 421b of at least one control signal line in the second group of control signal lines can be greater than the third line width K1 of the first control line segment 421a of the control signal line in the first group of control signal lines. For example, the fourth line width K2 of the first control line segment 421b of each control signal line in the second group of control signal lines can be the same and greater than the third line width K1.

[0176] In this example, by increasing the line width of the first control line segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be roughly the same as the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines, thereby increasing the parasitic capacitance between the second group of data fan-out lines and the overlapping control signal lines, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0177] In some examples, in the embodiments shown in Figures 13A to 15, in order to ensure that the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be approximately the same as the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines, the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines can be increased by increasing the overlapping area between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines.

[0178] In other examples, the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be reduced by reducing the overlapping area between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines, thereby ensuring that the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be approximately the same as the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines.

[0179] Figure 16A is another partially enlarged schematic diagram of region S2 in Figure 11. Figure 16B is a partially enlarged schematic diagram of the first set of data fan-out lines in Figure 16A. Figure 17A is another partially enlarged schematic diagram of region S3 in Figure 11. Figure 17B is a partially enlarged schematic diagram of the second set of data fan-out lines in Figure 17A.

[0180] In some examples, as shown in Figures 16A and 16B, each data fan-out line within the first group of data fan-out lines 41a may include a third sub-segment 41-3, a first sub-segment 41-1, and a fourth sub-segment 41-4, which are connected in sequence. The orthographic projection of the first sub-segment 41-1 on the substrate may overlap with the orthographic projection of the first group of control signal lines 42a on the substrate. The orthographic projection of the data fan-out lines within the first group of data fan-out lines 41a on the substrate may be a straight line. The minimum line width of the first sub-segment 41-1 may be smaller than the line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4. The line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4 may be substantially the same.

[0181] In some examples, as shown in Figures 17A and 17B, each data fan-out line within the second group of data fan-out lines 41b may include a fifth sub-segment 41-5, a second sub-segment 41-2, and a sixth sub-segment 41-6, which are connected in sequence. The orthographic projection of the second sub-segment 41-2 on the substrate may overlap with the orthographic projection of the second group of control signal lines 42b on the substrate. The orthographic projection of the data fan-out lines within the second group of data fan-out lines 41b on the substrate may be a straight line. The line widths of the second sub-segment 41-2, the fifth sub-segment 41-5, and the sixth sub-segment 41-6 may be substantially the same. The line width of the second sub-segment 41-2 may be greater than the line width of the first sub-segment 41-1.

[0182] In this example, by reducing the line width of the first sub-segment of the first group of data fan-out lines, the overlapping area between the first group of data fan-out lines and the first group of control signal lines can be reduced, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be roughly the same, thereby reducing the parasitic capacitance between the first group of data fan-out lines and the overlapping wiring, and making the parasitic capacitance between the two groups of data fan-out lines and the overlapping wiring roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0183] In other examples, by reducing the line width of the first control line segment of the first group of control signal lines, the overlapping area between the first group of data fan-out lines and the first group of control signal lines can be reduced, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be approximately the same, thereby reducing the parasitic capacitance between the first group of data fan-out lines and the overlapping control signal lines, and making the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines approximately the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0184] In other examples, the line width of the first sub-segment of the first group of data fan-out lines can be reduced, and the line width of the second sub-segment of the second group of data fan-out lines can be increased, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be substantially the same. Alternatively, in other examples, the line width of the first control line segment of the first group of control signal lines can be reduced, and the line width of the first control line segment of the second group of control signal lines can be increased, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be substantially the same. Alternatively, in other examples, the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be made approximately the same by reducing the line width of the first sub-line segment of the first group of data fan-out lines and increasing the line width of the second sub-line segment of the second group of data fan-out lines, and reducing the line width of the first control line segment of the first group of control signal lines and increasing the line width of the first control line segment of the second group of control signal lines.

[0185] In the embodiments shown in Figures 11 to 17B, the parasitic capacitance between the data fan-out lines and the overlapping control signal lines is adjusted by adjusting the overlapping area between the data fan-out lines and the overlapping control signal lines, so that the parasitic capacitance between the first group of data fan-out lines and the second group of data fan-out lines and the overlapping control signal lines is roughly the same, thereby effectively improving display defects such as low grayscale dark stripes caused by uneven overlapping of the data fan-out lines and the control signal lines.

[0186] In other examples, the parasitic capacitance between the data fan-out lines and the overlapping control signal lines can be adjusted by adjusting the film layer where the first control line segment of the control signal lines is located and adjusting the overlapping area between the data fan-out lines and the overlapping control signal lines, so that the parasitic capacitance between the first group of data fan-out lines and the second group of data fan-out lines and the overlapping control signal lines is approximately the same, thereby effectively improving display defects such as low grayscale dark stripes caused by uneven overlap between the data fan-out lines and the control signal lines. For example, the first control line segment of the multiple control signal lines can be located in the second source-drain metal layer or the third source-drain metal layer; the line width of the second sub-line segment of the second group of data fan-out lines can be greater than the line width of the first sub-line segment of the first group of data fan-out lines; or the line width of the first control line segment of the second group of control signal lines can be greater than the line width of the first control line segment of the first group of control signal lines.

[0187] This embodiment also provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate comprises: a display area and a first frame area located to one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first frame area. The plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines include: a first group of data fan-out lines and a second group of data fan-out lines. The plurality of control signal lines include: a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with the orthographic projection of the second group of control signal lines on the substrate. Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate. The ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.1.

[0188] This embodiment adjusts the parasitic capacitance between the data fan-out lines and the overlapping control signal lines by adjusting the overlapping area between each data fan-out line and multiple control signal lines, so that the parasitic capacitance between the two groups of data fan-out lines and the control signal lines is approximately the same, thereby optimizing display defects such as low grayscale dark stripes caused by uneven overlap between the data fan-out lines and the control signal lines transmitting AC signals.

[0189] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-line segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-line segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-line segment can be smaller than the line width of the second sub-line segment. In this example, by increasing the line width of the second sub-line segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be approximately the same as the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines, and the parasitic capacitance between the second group of data fan-out lines and the overlapping lines is increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping lines is approximately the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0190] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; each data fan-out line in the second group of data fan-out lines includes a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate; the orthographic projection of the first sub-segment on the substrate can be a straight line, while the orthographic projection of the second sub-segment on the substrate can be a serpentine line. This example utilizes a serpentine routing design for some segments of the second group of data fan-out lines to increase the overlapping area between the second group of data fan-out lines and the second group of control signal lines, thereby reducing the parasitic capacitance difference between the two groups of data fan-out lines and the overlapping control signal lines.

[0191] In some exemplary embodiments, each control signal line within the first group of control signal lines includes a first control line segment that overlaps with an orthographic projection of the first group of data fan-out lines on the substrate; and each control signal line within the second group of control signal lines includes a first control line segment that overlaps with an orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control line segment of at least one control signal line within the second group of control signal lines may be greater than the line width of the first control line segment of the control signal lines within the first group of control signal lines. In this example, by increasing the line width of the first control line segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines is approximately the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap between the data fan-out lines and the control signal lines.

[0192] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0193] Figure 18 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 18 , this embodiment provides a display device 91 comprising a display panel 910 according to the aforementioned embodiment. In some examples, display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touchscreen structure. Display device 91 may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, or may be a product or component with both touchscreen and display functions.

[0194] In some examples, the display device 91 may be a wearable display device, for example, a display device that can be worn on a human body in some manner. For example, the display device 91 may be a smart watch, a smart bracelet, etc. However, this embodiment is not limited to this.

[0195] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

[0196] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0197] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display panel, comprising: The substrate comprises: a display area and a first frame area located on one side of the display area; a plurality of sub-pixels and a plurality of data lines, located in the display area, the plurality of data lines being connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; a plurality of data fan-out lines and a plurality of control signal lines, located in the first border area, the plurality of data fan-out lines being configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines comprising: a first group of data fan-out lines and a second group of data fan-out lines; the plurality of control signal lines comprising: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines being greater than the number of control signal lines in the second group of control signal lines; Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate; At least one organic insulating layer is disposed between the data fan-out line and the control signal line whose orthographic projection overlaps with the substrate.

2. The display panel according to claim 1, wherein: The control signal line includes: a first control line segment, the orthographic projection of the first control line segment on the substrate overlaps with the orthographic projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate, the first control line segment is located on a side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control line segment intersects with an extension direction of the multiple data fan-out lines.

3. The display panel according to claim 2, wherein: In a direction perpendicular to the display panel, the display panel at least comprises: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer arranged in a direction away from the substrate; at least a first planarization layer is provided between the first source / drain metal layer and the second source / drain metal layer; The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segments of the plurality of control signal lines are located in the second source-drain metal layer.

4. The display panel according to claim 2, wherein: In a direction perpendicular to the display panel, the display panel comprises at least: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer arranged in a direction away from the substrate; at least a first planarization layer is provided between the first source / drain metal layer and the second source / drain metal layer, and at least a second planarization layer is provided between the second source / drain metal layer and the third source / drain metal layer; The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segments of the plurality of control signal lines are located in the third source-drain metal layer.

5. The display panel according to claim 3 or 4, wherein: The plurality of data fan-out lines include: a plurality of first data fan-out lines located in the first gate metal layer and a plurality of second data fan-out lines located in the second gate metal layer; The plurality of first data fan-out lines and the plurality of second data fan-out lines are arranged one by one in an alternating pattern, and the orthographic projections of the plurality of first data fan-out lines and the plurality of second data fan-out lines on the substrate do not overlap. The display panel according to claim 2 , wherein: The control signal line also includes: a second control line segment and a third control line segment, the second control line segment is connected to one end of the first control line segment, and the third control line segment is connected to the other end of the first control line segment, and the orthographic projections of the second control line segment and the third control line segment on the substrate do not overlap with the orthographic projections of the multiple data fan-out lines on the substrate; the second control line segment and the third control line segment are in the same layer structure and are located on the side of the first control line segment close to the substrate.

7. The display panel according to claim 1, wherein: Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate, and the ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.

1.

8. The display panel according to claim 7, wherein: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with an orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with an orthographic projection of the second group of control signal lines on the substrate; The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

9. The display panel according to claim 8, wherein: A ratio of the line width of the second sub-line segment to the line width of the first sub-line segment is greater than 1 and less than 2.

10. The display panel according to claim 8, wherein: Each data fan-out line in the first group of data fan-out lines further includes: a third sub-segment connected to one end of the first sub-segment, and a fourth sub-segment connected to the other end of the first sub-segment; the orthographic projections of the third sub-segment and the fourth sub-segment on the substrate do not overlap with the orthographic projections of the first group of control signal lines on the substrate; the first sub-segment, the third sub-segment, and the fourth sub-segment of each data fan-out line in the first group of data fan-out lines are an integrated structure connected to each other; Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-line segment connected to one end of the second sub-line segment, and a sixth sub-line segment connected to the other end of the second sub-line segment; the orthographic projections of the fifth sub-line segment and the sixth sub-line segment on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate; The second sub-segment, the fifth sub-segment and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are an integrated structure connected to each other; The first sub-line segment, the third sub-line segment, the fourth sub-line segment, the fifth sub-line segment, and the sixth sub-line segment have the same line width.

11. The display panel according to claim 7, wherein: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with an orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with an orthographic projection of the second group of control signal lines on the substrate; The orthographic projection of the first sub-line segment on the substrate is a straight line, and the orthographic projection of the second sub-line segment on the substrate is a serpentine line.

12. The display panel according to claim 11, wherein: Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-line segment connected to one end of the second sub-line segment, and a sixth sub-line segment connected to the other end of the second sub-line segment; the orthographic projections of the fifth sub-line segment and the sixth sub-line segment on the substrate do not overlap with the orthographic projections of the second group of control signal lines on the substrate; The second sub-segment, the fifth sub-segment and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are an integrated structure connected to each other; The fifth sub-line segment or the sixth sub-line segment of at least one data fan-out line in the second group of data fan-out lines has an orthographic projection on the substrate that is a serpentine line.

13. The display panel according to claim 7, wherein: Each control signal line in the first group of control signal lines includes: a first control line segment that overlaps with an orthographic projection of the first group of data fan-out lines on the substrate; Each control signal line in the second group of control signal lines includes: a first control line segment overlapping with an orthographic projection of the second group of data fan-out lines on the substrate; A line width of a first control line segment of at least one control signal line in the second group of control signal lines is greater than a line width of a first control line segment of a control signal line in the first group of control signal lines.

14. The display panel according to claim 1, wherein: The substrate further includes: a second frame area and a third frame area located on both sides of the display area along the first direction, wherein the second frame area and the third frame area are both connected to the first frame area; The display panel further includes: a first group of gate driving circuits located in the second frame area and a second group of gate driving circuits located in the third frame area, wherein the number of gate driving circuits included in the first group of gate driving circuits is greater than the number of gate driving circuits included in the second group of gate driving circuits; The first group of control signal lines includes: a plurality of first drive control lines, the plurality of first drive control lines being configured to provide drive control signals to the first group of gate drive circuits; The second group of control signal lines includes: a plurality of second drive control lines, and the plurality of second drive control lines are configured to provide drive control signals to the second group of gate drive circuits.

15. The display panel according to claim 14, wherein: At least one sub-pixel of the plurality of sub-pixels comprises: a pixel circuit; The first group of gate driving circuits includes: a light-emitting driving circuit, a first reset driving circuit, and a second reset driving circuit; the light-emitting driving circuit is configured to provide a light-emitting control signal to the pixel circuit, the first reset driving circuit is configured to provide a first reset control signal to the pixel circuit, and the second reset driving circuit is configured to provide a second reset control signal to the pixel circuit; The second group of gate driving circuits includes: a first scanning driving circuit and a second scanning driving circuit; the first scanning driving circuit is configured to provide a first scanning signal to the pixel circuit, and the second scanning driving circuit is configured to provide a second scanning signal to the pixel circuit.

16. A display device comprising the display panel according to any one of claims 1 to 15.

17. A display panel comprising: The substrate comprises: a display area and a first frame area located on one side of the display area; a plurality of sub-pixels and a plurality of data lines, located in the display area, the plurality of data lines being connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; a plurality of data fan-out lines and a plurality of control signal lines, located in the first border area, the plurality of data fan-out lines being configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines comprising: a first group of data fan-out lines and a second group of data fan-out lines; the plurality of control signal lines comprising: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines being greater than the number of control signal lines in the second group of control signal lines; Each data fan-out line in the first group of data fan-out lines overlaps with an orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with an orthographic projection of the second group of control signal lines on the substrate; Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate, and the ratio of the first overlapping area to the second overlapping area ranges from 0.9 to 1.

1.

18. The display panel according to claim 17, wherein: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with an orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with an orthographic projection of the second group of control signal lines on the substrate; The line width of the first sub-line segment is smaller than the line width of the second sub-line segment.

19. The display panel according to claim 17, wherein: Each data fan-out line in the first group of data fan-out lines comprises: a first sub-line segment overlapping with an orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines comprises: a second sub-line segment overlapping with an orthographic projection of the second group of control signal lines on the substrate; The orthographic projection of the first sub-line segment on the substrate is a straight line, and the orthographic projection of the second sub-line segment on the substrate is a serpentine line.

20. The display panel according to claim 17, wherein Each control signal line in the first group of control signal lines includes: a first control line segment that overlaps with an orthographic projection of the first group of data fan-out lines on the substrate; Each control signal line in the second group of control signal lines includes: a first control line segment overlapping with an orthographic projection of the second group of data fan-out lines on the substrate; A line width of a first control line segment of at least one control signal line in the second group of control signal lines is greater than a line width of a first control line segment of a control signal line in the first group of control signal lines.

Images