Instruction processing method and apparatus, and device and computer-readable storage medium

Abstract

The present application belongs to the technical field of computers. Disclosed are an instruction processing method and apparatus, and a device and a computer-readable storage medium. The method comprises: acquiring first instructions to be processed; on the basis of a memory structure and a required rate for reading the first instructions, determining a compression level of a memory in the memory structure, wherein the memory structure is used for storing compressed first instructions; and using the compression level to compress the first instructions. By means of compressing first instructions, the size of a storage space occupied by the first instructions is reduced, and thus for memory structures of the same capacity, the number of first instructions that can be stored after compression is greater than that before compression, thereby increasing the number of instructions stored by the memory structure and reducing the storage overheads of same. Since the compression of the first instructions is performed on the basis of a compression level of a memory, the process of restoring the compressed first instructions meets a required rate, and thus the process of restoring the compressed first instructions does not affect the normal operation of the memory.

Description

Instruction processing method, device, equipment and computer-readable storage medium

[0001] This application claims priority to Chinese patent application No. 202410133420.0, filed on January 30, 2024, entitled “Instruction processing method, apparatus, device and computer-readable storage medium,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to instruction processing methods, devices, equipment, and computer-readable storage media. Background Art

[0003] In computer technology, a processor consists of an instruction memory (IMEM), a decoder (DEC), and arithmetic and logic units (ALUs). The IMEM stores instructions generated by compiling an application, the DEC parses multiple instructions in parallel, and the ALU computes multiple results based on the information parsed from the multiple instructions, thereby enabling the application to run based on the multiple results. As the complexity of an application increases, the number of instructions generated by compiling the application increases, and the IMEM must store even more instructions. Summary of the Invention

[0004] This application provides an instruction processing method, apparatus, device, and computer-readable storage medium to store more instructions. The technical solution is as follows:

[0005] In a first aspect, an instruction processing method is provided, the method comprising: obtaining a first instruction to be processed; determining a compression level of a memory in the memory structure based on the memory structure and a required rate for reading the first instruction, the memory structure being used to store the compressed first instruction; and compressing the first instruction using the compression level.

[0006] By compressing the first instruction to reduce the size of the storage space occupied by the first instruction, a memory structure of the same capacity can store more compressed first instructions than the number of first instructions before compression, thereby increasing the memory structure's instruction storage capacity and reducing the memory structure's storage overhead. Because the compression of the first instruction is based on the memory's compression level, which is determined based on a required rate, the process of restoring the compressed first instruction meets the required rate of the memory structure, and the process of restoring the compressed first instruction does not affect the normal operation of the memory in the memory structure.

[0007] In one possible implementation, before determining the compression level of the memory in the memory structure based on the memory structure and the required rate for reading the first instruction, the method further includes: obtaining at least one of a path attribute of a read path of each memory included in the memory structure or a read efficiency of the memory structure, where the memory read path is a path connecting the memory and a read module, the read module being used to read instructions stored in the memory and process the read instructions; and determining the required rate for reading the first instruction based on at least one of the path attribute or the read efficiency. Determining the required rate for reading the first instruction based on at least one of the path attribute or the read efficiency better conforms to the actual operating conditions of the memory structure and has a high degree of accuracy.

[0008] In one possible implementation, the compression level of the memories in the memory structure is determined based on the memory structure and the required rate for reading the first instruction, including: determining the read rate of each memory included in the memory structure; determining the restore rate of each memory based on the required rate for reading the first instruction and the read rate of each memory, the restore rate of the memory being the rate of decompressing the instructions stored in the memory on the read path of the memory; determining the compression level of each memory based on the restore rate of each memory, the compression rate corresponding to the compression level of the memory matching the restore rate corresponding to the memory.

[0009] Reading the first instruction in its entirety from the memory structure includes reading the first instruction and restoring the first instruction. Therefore, the restoration rate that can be used to restore the instruction while ensuring the normal operation of the memory can be determined based on the required rate of reading the first instruction from the memory structure and the reading rate of each memory, thereby selecting a compression level that matches the restoration rate. By combining the overall memory structure with the local memory, the determined compression level has high accuracy, and the compression level matches the restoration rate of each memory. The compression based on the compression level does not affect the normal operation of each memory.

[0010] In one possible implementation, the memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, and the restoration rate of one-layer compression is higher than the restoration rate of two-layer compression; the compression level is used to compress the first instruction, including: compressing the first instruction using a one-layer compression method to obtain a second instruction; compressing the second instruction using a two-layer compression method to obtain a third instruction, and the compression rate of the two-layer compression method is higher than the compression rate of the one-layer compression method. In the case where the memory structure includes multiple memories, such as a storage module and a cache module, the first instruction can be compressed in multiple sections, and the bit width of the obtained third instruction is smaller than the bit width of the first instruction, and the storage overhead is also smaller. Different compression methods can be used for different memories, such as storage modules and cache modules, and the compression process is highly flexible.

[0011] In one possible implementation, the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. The first instruction is compressed using a one-layer compression method. Before obtaining the second instruction, the method further includes: obtaining a service characteristic of the first instruction, where the service characteristic indicates an operational quality requirement of a service executed based on the first instruction; and determining the compression ratio based on the service characteristic of the first instruction. Determining the compression ratio based on the service characteristic of the first instruction ensures the operational quality of the service executed based on the first instruction.

[0012] In one possible implementation, a first instruction is compressed using a one-layer compression method to obtain a second instruction, including: obtaining instruction characteristics of the first instruction; when it is determined based on the instruction characteristics that fixed-length compression is supported, compressing the first instruction using a fixed-length compression method to obtain a second instruction, or when it is determined based on the instruction characteristics that fixed-length compression is not supported, splitting the first instruction into multiple second instructions, each of the multiple second instructions having the same bit width. Determining whether the first instruction supports fixed-length compression based on the instruction characteristics, performing fixed-length compression on the first instruction that supports fixed-length compression, and splitting the first instruction that does not support fixed-length compression, thereby achieving flexible processing of the first instruction based on the instruction characteristics. Regardless of whether the first instruction supports fixed-length compression, the first instruction can be processed to obtain a second instruction with a uniform bit width, thereby achieving wide versatility.

[0013] In a possible implementation, the instruction feature includes at least one of an instruction type, a usage frequency, or a field utilization rate of the first instruction. The instruction features in this method are diverse and highly flexible.

[0014] In one possible implementation, compressing a first instruction using a fixed-length compression method to obtain a second instruction includes determining valid fields of the first instruction to obtain a second instruction including the valid fields, where the valid fields are fields used to execute the first instruction. Determining the second instruction based on the valid fields ensures that the fields carried by the second instruction are necessary for instruction execution, thereby improving field utilization of the second instruction and ensuring reliable execution of the second instruction.

[0015] In one possible implementation, the second instruction includes a compression flag that indicates that the second instruction was obtained through fixed-length compression or splitting. By using the compression flag to clearly identify the second instruction, the determination process is simple and efficient, and can facilitate subsequent restoration of the instruction, thereby improving the efficiency of restoration.

[0016] In one possible implementation, the second instruction is compressed using a two-layer compression method to obtain a third instruction, including: obtaining the frequency of occurrence of each field included in the second instruction; and obtaining a third instruction based on the frequency of occurrence of each field, the third instruction including a code for each field, the code for each field being determined based on the frequency of occurrence of each field, and the length of the code for each field being inversely proportional to the frequency of occurrence of each field. Because the length of the code for each field is inversely proportional to the frequency of occurrence of each field, the more frequently a field appears, the shorter the corresponding code length, effectively reducing the length of the third instruction.

[0017] In one possible implementation, before obtaining the third instruction based on the frequency of occurrence of each field, the method further includes: constructing a coding dictionary corresponding to the second instruction based on the frequency of occurrence of each field, the coding dictionary including each field and the frequency of occurrence of each field; and determining the encoding of each field based on the coding dictionary. By counting the frequency of occurrence of each field using the coding dictionary, the second instruction can be subsequently compressed by searching the coding dictionary, resulting in a simple and efficient compression process.

[0018] In one possible implementation, the third instruction includes an encoding index, which is used to locate a field corresponding to the encoding included in the third instruction during decompression of the third instruction. Because the third instruction carries the encoding index, the encoding index can be parsed during subsequent decompression of the third instruction to determine the field corresponding to the encoding included in the third instruction, thereby achieving decompression of the third instruction. This simplifies the decompression process and improves decompression efficiency.

[0019] In one possible implementation, after compressing the first instruction using the compression level, the method further includes: obtaining an instruction length of the compressed first instruction; determining a storage unit in a memory structure for storing the compressed first instruction based on the instruction length; and storing the compressed first instruction in the determined storage unit. Based on the instruction length of the compressed first instruction, the storage unit for storage is first determined, and then the compressed first instruction is stored in the storage unit, thereby achieving accurate storage of the compressed first instruction.

[0020] In a possible implementation, the first instruction includes an instruction for forwarding an application program. By compressing the first instruction, the reading efficiency of the first instruction is improved, and the forwarding efficiency based on the first instruction is higher.

[0021] In one possible implementation, obtaining a first instruction to be processed includes: obtaining at least one instruction included in an instruction bundle, wherein any instruction in the at least one instruction is a first instruction to be processed, and at least one instruction is an instruction to be executed in parallel. The first instruction to be processed may be an instruction included in the instruction bundle, and the number of instructions to be processed is not limited. It may be one first instruction or multiple first instructions, and has wide versatility. For the at least one instruction to be executed in parallel, an instruction processing method may also be used for compression, thereby reducing the storage space occupied by the instruction bundle while ensuring the efficiency of parallel processing. Furthermore, if the instruction bundle including at least one instruction is, for example, a very long instruction word, this method may also be applied to application scenarios of very long instruction words.

[0022] In a second aspect, another instruction processing method is provided, which includes: obtaining a compressed first instruction, compression of the first instruction is implemented based on a compression level, the compression level is determined based on a memory structure and a required rate for reading the first instruction, and the memory structure is used to store the compressed first instruction; and restoring the compressed first instruction.

[0023] The compressed first instruction occupies less storage space than the first instruction. A memory structure of the same memory size can store more compressed first instructions, increasing the memory structure's instruction storage capacity. The compressed first instruction can be restored, ensuring the normal implementation of subsequent related operations based on the first instruction.

[0024] In one possible implementation, a memory structure includes a storage module and a cache module. The storage module has a two-layer compression level, the cache module has a one-layer compression level, the restoration rate of the one-layer compression is higher than the restoration rate of the two-layer compression level, and the compressed first instruction includes a third instruction. Restoring the compressed first instruction includes: restoring the third instruction using a restoration method corresponding to the two-layer compression method to obtain a second instruction; restoring the second instruction using a restoration method corresponding to the one-layer compression method to obtain the first instruction, and the compression rate of the two-layer compression method is higher than the compression rate of the one-layer compression method. Even if the memory structure includes multiple memories, such as a storage module and a cache module, multi-stage restoration can be performed on the third instruction, and each stage of restoration is the restoration method corresponding to the compression level of the memory, that is, each stage of restoration does not affect the normal operation of the memory.

[0025] In one possible implementation, the third instruction includes a coding index. Restoring the third instruction using a restoration method corresponding to a two-layer compression method to obtain the second instruction includes: parsing the coding index included in the third instruction; determining, based on the coding index, respective fields corresponding to respective codes included in the third instruction; and determining the second instruction based on the respective fields corresponding to the respective codes, wherein the length of the codes of the respective fields is inversely proportional to the frequency of occurrence of the respective fields. The coding index can be used to determine the correspondence between the codes and the fields, thereby restoring the third instruction. This is a simple and efficient restoration process.

[0026] In one possible implementation, the restoration method corresponding to the compression method of a layer of compression includes decompression corresponding to fixed-length compression or concatenation corresponding to splitting. The second instruction is restored using the restoration method corresponding to the compression method of the layer of compression to obtain the first instruction, including: when the second instruction is obtained by fixed-length compression, decompression corresponding to fixed-length compression is performed on the second instruction to obtain the first instruction; or, when the second instruction is obtained by splitting, concatenation of multiple second instructions obtained by splitting the first instruction to obtain the first instruction, where each of the multiple second instructions has the same bit width. Whether fixed-length compression or splitting is used, a corresponding restoration method exists, and the types of second instructions that can be restored are numerous and highly versatile.

[0027] In one possible implementation, the second instruction includes a compression flag indicating whether the second instruction was obtained through fixed-length compression or splitting. Restoring the second instruction using a restoration method corresponding to a compression method for a layer of compression, before obtaining the first instruction, further includes parsing the compression flag included in the second instruction, and determining, based on the compression flag, the method for obtaining the second instruction from the fixed-length compression and splitting. Parsing the compression flag allows determining the compression method used for the second instruction. This determination process is simple and efficient, and facilitates subsequent restoration of the instruction, improving restoration efficiency.

[0028] In one possible implementation, obtaining the compressed first instruction includes: extracting at least one instruction stored in a row of storage cells in a memory structure; and separating the at least one instruction according to their lengths to obtain at least one instruction, wherein the at least one instruction includes the compressed first instruction. Instructions stored in a row of storage cells can be extracted at a time, resulting in a large number of extracted instructions and high instruction extraction efficiency.

[0029] In one possible implementation, after restoring the compressed first instruction, the method further includes: determining an instruction bundle corresponding to the first instruction, the instruction bundle including at least one instruction, the compression result of the at least one instruction being stored in the same row of storage units of the memory structure, the compression result of any instruction among the compression results of the at least one instruction being the compressed first instruction, and the at least one instruction being an instruction executed in parallel; and sending the at least one instruction included in the instruction bundle to a decoding module, which is used to parse the at least one instruction. After restoring the first instruction, at least one instruction is further sent to the decoding module in units of the instruction bundle, so that the decoding module performs parallel parsing on the at least one instruction included in the instruction bundle. By controlling the parallel parsing of at least one instruction, it is ensured that the at least one instruction can be smoothly executed in parallel, and the processing efficiency of the at least one instruction is improved through parallel execution. Moreover, the method can also be applied in the context of instruction bundles, and has a wide range of applications.

[0030] In a possible implementation, the first instruction includes an instruction for forwarding an application program. When the first instruction is used to forward an application program, the first instruction is compressed to improve reading efficiency of the first instruction, and forwarding efficiency based on the first instruction is higher.

[0031] In a third aspect, an instruction processing device is provided, which includes: an acquisition module for acquiring a first instruction to be processed; a determination module for determining a compression level of a memory in a memory structure based on the memory structure and a required rate for reading the first instruction, wherein the memory structure is used to store the compressed first instruction; and a compression module for compressing the first instruction using the compression level.

[0032] In one possible implementation, the acquisition module is further used to obtain at least one of the path attributes of the read paths of each memory included in the memory structure or the read efficiency of the memory structure, the read path of the memory is the path connecting the memory and the read module, and the read module is used to read the instructions stored in the memory and process the read instructions; the determination module is further used to determine the required rate for reading the first instruction based on at least one of the path attributes or the read efficiency.

[0033] In one possible implementation, a determination module is used to determine the read rate of each memory included in the memory structure; determine the restore rate of each memory based on the required rate for reading the first instruction and the read rate of each memory, the restore rate of the memory being the rate of decompressing the instructions stored in the memory on the read path of the memory; determine the compression level of each memory based on the restore rate of each memory, the compression rate corresponding to the compression level of the memory matches the restore rate corresponding to the memory.

[0034] In one possible implementation, the memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, and the restoration rate of one-layer compression is higher than the restoration rate of two-layer compression; the compression module is used to compress the first instruction using a one-layer compression method to obtain a second instruction; and compress the second instruction using a two-layer compression method to obtain a third instruction, and the compression rate of the two-layer compression method is higher than the compression rate of the one-layer compression method.

[0035] In one possible implementation, the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. The acquisition module is further used to obtain the business characteristics of the first instruction, and the business characteristics indicate the operating quality requirements of the business running based on the first instruction; the determination module is further used to determine the compression ratio based on the business characteristics of the first instruction.

[0036] In one possible implementation, a compression module is used to obtain instruction characteristics of a first instruction; when it is determined based on the instruction characteristics that fixed-length compression is supported, the first instruction is compressed using fixed-length compression to obtain a second instruction; or, when it is determined based on the instruction characteristics that fixed-length compression is not supported, the first instruction is split into multiple second instructions, and the bit width of each second instruction in the multiple second instructions is the same.

[0037] In a possible implementation, the instruction feature includes at least one of an instruction type, a usage frequency, or a field utilization rate of the first instruction.

[0038] In a possible implementation, the compression module is configured to determine a valid field of the first instruction and obtain a second instruction including the valid field, where the valid field is a field used to execute the first instruction.

[0039] In a possible implementation, the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting.

[0040] In one possible implementation, the compression module is used to obtain the frequency of occurrence of each field included in the second instruction; obtain a third instruction based on the frequency of occurrence of each field, the third instruction includes the encoding of each field, the encoding of each field is determined based on the frequency of occurrence of each field, and the length of the encoding of each field is inversely proportional to the frequency of occurrence of each field.

[0041] In a possible implementation, the determination module is further configured to construct a coding dictionary corresponding to the second instruction based on the occurrence frequency of each field, the coding dictionary including each field and the occurrence frequency of each field; and determine the coding of each field based on the coding dictionary.

[0042] In a possible implementation, the third instruction includes an encoding index, and the encoding index is used to find a field corresponding to the encoding included in the third instruction during decompression of the third instruction.

[0043] In one possible implementation, the device also includes: a storage module, used to obtain the instruction length of the compressed first instruction; determine the storage unit in the memory structure for storing the compressed first instruction based on the instruction length, and store the compressed first instruction in the determined storage unit.

[0044] In a possible implementation, the first instruction includes an instruction to forward an application.

[0045] In a possible implementation, the acquisition module is configured to acquire at least one instruction included in the instruction bundle, wherein any instruction in the at least one instruction is a first instruction to be processed, and at least one instruction is an instruction to be executed in parallel.

[0046] In a fourth aspect, another instruction processing device is provided, which includes: an acquisition module for acquiring a compressed first instruction, where compression of the first instruction is implemented based on a compression level, where the compression level is determined based on a memory structure and a required rate for reading the first instruction, and where the memory structure is used to store the compressed first instruction; and a restoration module for restoring the compressed first instruction.

[0047] In one possible implementation, the memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, the restoration rate of one-layer compression is higher than the restoration rate of two-layer compression, and the compressed first instruction includes a third instruction; a restoration module is used to restore the third instruction using a restoration method corresponding to the compression method of the two-layer compression to obtain a second instruction; and restore the second instruction using a restoration method corresponding to the compression method of the one-layer compression to obtain a first instruction, and the compression rate of the two-layer compression method is higher than the compression rate of the one-layer compression method.

[0048] In one possible implementation, the third instruction includes a coding index, and a restoration module is used to parse the coding index included in the third instruction; determine the fields corresponding to the codes included in the third instruction based on the coding index, and determine the second instruction based on the fields corresponding to the codes, and the length of the code of each field is inversely proportional to the frequency of occurrence of each field.

[0049] In one possible implementation, the restoration method corresponding to the compression method of one layer of compression includes decompression corresponding to fixed-length compression or splicing corresponding to splitting, and the restoration module is used to, when the second instruction is obtained by fixed-length compression, apply decompression corresponding to the fixed-length compression to the second instruction to obtain the first instruction; or, when the second instruction is obtained by splitting, splice multiple second instructions obtained by splitting the first instruction to obtain the first instruction, and the bit width of each second instruction in the multiple second instructions is the same.

[0050] In one possible implementation, the second instruction includes a compression flag bit, which indicates that the second instruction is obtained through fixed-length compression or splitting. The restoration module is also used to parse the compression flag bit included in the second instruction, and determine the method of obtaining the second instruction from fixed-length compression and splitting based on the compression flag bit.

[0051] In one possible implementation, an acquisition module is configured to extract at least one instruction stored in a row of storage cells of a memory structure; separate the instructions in the at least one instruction according to the instruction length of each instruction to obtain at least one instruction, wherein the at least one instruction includes a compressed first instruction.

[0052] In one possible implementation, the device also includes: a sending module, used to determine an instruction bundle corresponding to the first instruction, the instruction bundle includes at least one instruction, the compression result of the at least one instruction is stored in the same row storage unit of the memory structure, the compression result of any instruction in the compression result of the at least one instruction is the compressed first instruction, and at least one instruction is an instruction executed in parallel; sending the at least one instruction included in the instruction bundle to a decoding module, the decoding module is used to parse the at least one instruction.

[0053] In a possible implementation, the first instruction includes an instruction to forward an application.

[0054] In a fifth aspect, an instruction processing device is provided, which includes a processor, and the processor is used to load and execute at least one instruction so that the instruction processing device executes the method in the first aspect or any possible implementation of the first aspect, or executes the method in the second aspect or any possible implementation of the second aspect.

[0055] In a possible implementation, the device includes a memory coupled to a processor, and the memory stores at least one instruction.

[0056] In the sixth aspect, a computer-readable storage medium is provided, in which at least one instruction is stored. The instruction is loaded and executed by a processor to implement the instruction processing method in the first aspect or any possible implementation of the first aspect, or to implement the instruction processing method in the second aspect or any possible implementation of the second aspect.

[0057] In the seventh aspect, a computer program (product) is provided, which includes a computer program / instructions, and the computer program / instructions are executed by a processor to enable the computer to implement the instruction processing method in the first aspect or any possible implementation of the first aspect, or to implement the instruction processing method in the second aspect or any possible implementation of the second aspect.

[0058] In an eighth aspect, a communication device is provided, comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other via an internal connection path; the memory is used to store instructions; the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and to control the transceiver to send signals; and when the processor executes the instructions stored in the memory, the processor executes the method according to the first aspect or any possible implementation of the first aspect, or executes the method according to the second aspect or any possible implementation of the second aspect. Optionally, the communication device may be a chip.

[0059] Optionally, there are one or more processors and one or more memories.

[0060] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0061] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.

[0062] In a ninth aspect, a chip is provided, comprising a processor for calling and executing program instructions or codes stored in a memory, so that a communication device equipped with the chip executes the methods in the above aspects.

[0063] In the tenth aspect, another chip is provided, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the methods in the above aspects.

[0064] It should be understood that the instruction processing device mentioned in the third and fourth aspects above may be the device mentioned in the fifth aspect, or may be the chip mentioned in the ninth or tenth aspect. The beneficial effects achieved by the technical solutions and corresponding possible implementations of the third to tenth aspects of this application can be referred to the technical effects of the first aspect and its corresponding possible implementations or the second aspect and its corresponding possible implementations above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG1 is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0066] FIG2 is a schematic diagram of another implementation environment provided by an embodiment of the present application;

[0067] FIG3 is a flow chart of an instruction processing method provided in an embodiment of the present application;

[0068] FIG4 is a schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0069] FIG5 is a schematic diagram of an instruction processing process provided by an embodiment of the present application;

[0070] FIG6 is a schematic diagram of the structure of a first instruction and a second instruction provided in an embodiment of the present application;

[0071] FIG7 is a schematic diagram of a two-stage compression process provided by an embodiment of the present application;

[0072] FIG8 is a flowchart of an instruction compression method provided by an embodiment of the present application;

[0073] FIG9 is a flowchart of an instruction processing method provided in an embodiment of the present application;

[0074] FIG10 is a schematic diagram of a process of reading an instruction provided by an embodiment of the present application;

[0075] FIG11 is a schematic diagram of a decompression process provided in an embodiment of the present application;

[0076] FIG12 is a schematic diagram of the effect of a fixed-length reduction method provided in an embodiment of the present application;

[0077] FIG13 is a flowchart of a fixed-length restoration method provided in an embodiment of the present application;

[0078] FIG14 is a flowchart of another fixed-length restoration method provided in an embodiment of the present application;

[0079] FIG15 is a diagram comparing the effects of an instruction storage provided by an embodiment of the present application;

[0080] FIG16 is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present application;

[0081] FIG17 is a schematic diagram of the structure of another instruction processing device provided in an embodiment of the present application;

[0082] FIG18 is a schematic diagram of the structure of a network device provided in an embodiment of the present application;

[0083] FIG19 is a schematic structural diagram of another network device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0084] The terms used in the embodiments of this application are only used to explain the specific embodiments of this application and are not intended to limit this application. To make the purpose, technical solutions and advantages of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0085] In the field of computer technology, a processor is the computing and control core of a network device, used to run applications. Exemplarily, a processor includes an instruction storage module, a decoding module, and a parallel computing module. The instruction storage module stores compiled instructions from the application, achieving programmability. The decoding module parses the instructions stored in the instruction storage module, generates parsed results, and sends these results to the parallel computing module. The parallel computing module then computes the results of the parsed instructions in parallel to generate multiple result data, which are then used to run the application.

[0086] In the related art, for a run-to-complete (RTC) architecture forwarding processor, the RTC architecture forwarding processor includes multiple processor cores and multiple instruction cache modules, one processor core is connected to one instruction cache module, and multiple instruction cache modules are connected to one instruction storage module. Among them, the hardware overhead of the instruction cache module is less than the hardware overhead of the instruction storage module. Using multiple small-capacity instruction cache modules to replace multiple large-capacity instruction storage modules can reduce the hardware overhead of the processor. However, in high-performance business scenarios with a large amount of stored instructions, the above method still needs to provide a large capacity for the instruction cache module, the hardware overhead of the instruction cache module increases, and the storage overhead is still high.

[0087] An embodiment of the present application provides an instruction processing method. Please refer to Figure 1, which shows a schematic diagram of the implementation environment of the instruction processing method provided by the embodiment of the present application. The implementation environment includes a compression module 01, a memory structure 02, and a restoration module 03. The compression module 01, the memory structure 02, and the restoration module 03 can establish a communication connection relationship as shown in Figure 1 via a wired or wireless network. In one possible implementation, the compression module 01 is used to compress the first instruction to be processed using the method provided by the embodiment of the present application, and store the compressed first instruction in the memory structure 02. The restoration module 03 can use the method provided by the embodiment of the present application to perform a restoration operation on the compressed first instruction stored in the memory structure 02 to obtain the first instruction.

[0088] Exemplarily, the memory included in the memory structure 02 in Figure 1 can be one or more memories, and Figure 2 is another implementation environment schematic diagram provided by an embodiment of the present application. Referring to Figure 2, the processor includes a storage module, a cache module and a decoding module. Among them, the storage module and the cache module can be used to store instructions (inst). In this case, the memory included in the memory structure 02 in Figure 1 is the storage module and the cache module in the left and right figures in Figure 2. In one possible case, the cache module can be called an instruction cache module (instruction cache, ICACHE), which is used to cache instructions to be processed by the decoding module to increase the rate at which the decoding module reads instructions, thereby increasing the instruction parsing rate. In the left figure of Figure 2, the instruction interaction between the storage module, the cache module and the decoding module is based on the instruction word as a whole. The instruction word refers to a plurality of instructions located in the same row of storage cells. The same row of storage cells can be storage cells in the storage module or cache cells in the cache module.

[0089] In the case where the memory structure 02 shown in Figure 1 includes multiple memories, the restoration module 03 can establish communication connections with each memory included in the memory structure 02. Referring to the right figure of Figure 2, the storage module and the cache module in Figure 2 are respectively connected to the restoration module 03. The multiple restoration modules 03 in the right figure of Figure 2 refer to different operating units of the restoration module 03, and the restoration operations performed by different operating units are different. Optionally, the number of storage modules and cache modules can be the same, that is, the storage modules and cache modules have a one-to-one correspondence. The number of storage modules and cache modules can also be different. For example, multiple cache modules share one storage module. This embodiment of the present application does not limit this.

[0090] Optionally, the compression module 01, memory structure 02 and restoration module 03 in Figure 1 can be integrated on the same network device, which can be any network device configured with a processor. The configured processor can be a programmable processor of any structure, such as an RTC architecture forwarding processor, or other types of processors. Exemplarily, the network device can be a server, such as a central server, an edge server, or a local server in a local data center. The server can be a physical server, or a cloud server that provides cloud computing services in a cloud scenario. In some embodiments, the network device can also be a terminal device such as a desktop, a laptop or a smart phone, or a switch, a router and a gateway (GW). The instruction processing operation performed by the compression module 01 can be implemented based on a compiler, and the compression module 01 is, for example, a compiler. The instruction processing operation performed by the restoration module 03 can be implemented based on hardware operation, and the restoration module 03 is, for example, a decoder.

[0091] An embodiment of the present application provides an instruction processing method, which can be applied to the implementation environment shown in Figure 1 or Figure 2 above. Taking the method executed by the compression module as an example, the flowchart of the method is shown in Figure 3, including S301-S303.

[0092] S301: Obtain a first instruction to be processed.

[0093] Exemplarily, an instruction refers to a command obtained after compiling an application program to instruct a network device to work, and the network device is, for example, a personal terminal or a server. The first instruction to be processed may be an instruction obtained by compiling any application program, for example, an instruction for forwarding an application program, and the application program includes but is not limited to a game application program, a video playback software application program, or a social application software program. Optionally, the compression module may obtain the code to be run, convert the obtained code into an instruction, and obtain the first instruction to be processed. The code to be run may be a code input manually, or may be a code obtained by accessing a code library based on manually input operation requirements. The compression module may also receive the first instruction to be processed sent from other devices or modules. The embodiment of the present application does not limit the method for obtaining the first instruction.

[0094] The embodiments of the present application do not limit the number of first instructions to be processed; the number of first instructions to be processed can be one. For example, the compression module determines, based on the code, that executing a move (mov) instruction can command the network device to operate, and determines the one mov instruction as the first instruction to be processed. Optionally, the number of first instructions to be processed can be multiple, and the multiple first instructions can belong to the same instruction bundle or different instruction bundles, such as very long instruction words (VLIWs). The instructions included in the instruction bundle can be divided according to the function corresponding to the instruction, the application corresponding to the instruction, or other methods. By connecting multiple instructions together through instruction bundles, the multiple instructions included in an instruction bundle are executed in parallel, thereby improving the computing speed of executing multiple instructions. Parallel execution of multiple instructions can mean executing multiple instructions in parallel once. For example, an instruction bundle includes three instructions, and the three instructions are executed in parallel within a beat to achieve synchronous execution of the three instructions. Parallel execution of multiple instructions can also mean executing multiple instructions in parallel multiple times, that is, the method adopted is a combination of parallel and serial methods. For example, an instruction bundle includes eight instructions. Since at most four instructions can be executed in one beat, the first four instructions are executed in parallel first, and then after the first four instructions are completed, the last four instructions are executed in parallel.

[0095] Exemplarily, the compression module obtains at least one instruction included in the instruction bundle, wherein the at least one instruction is an instruction to be executed in parallel, and any one of the at least one instructions is a first instruction to be processed. That is, each instruction included in the instruction bundle is processed as a first instruction using the instruction processing method provided in the embodiments of the present application. Since the process of processing a first instruction is similar to the process of processing multiple first instructions, the processing of a first instruction will be described below using any one of the instructions included in the instruction bundle as an example of a first instruction to be processed. The processing of other instructions included in the instruction bundle, other than any one of the instructions, can refer to a similar description and will not be repeated here.

[0096] S302 : Determine a compression level of a memory in the memory structure according to the memory structure and a required rate for reading the first instruction, where the memory structure is used to store the compressed first instruction.

[0097] In one possible scenario, the network device directed by the first instruction includes a memory structure for storing the first instruction to be processed, so as to achieve a programmable effect. Taking the network device configured with the RTC architecture forwarding processor as shown in Figure 4 as an example, the RTC forwarding architecture processor includes a scheduler (input scheduler), a processor core (RTC core), and a storage module, etc., and the storage module is also the memory included in the memory structure. Optionally, a communication connection is established between the processor core and the storage module. The established communication connection can be a direct connection or an indirect connection based on a restoration module, that is, the processor core is connected to the restoration module, and the restoration module is connected to the storage module. Optionally, there can be one restoration module, that is, one restoration module is connected to multiple storage modules and multiple processor cores respectively. There can also be multiple restoration modules, and the number of multiple restoration modules can be the same as the number of storage modules, that is, the restoration modules correspond to the processor cores and the storage modules one by one as shown in Figure 4, and one restoration module is used to connect one processor core and one storage module. The number of multiple restoration modules can also be less than the number of storage modules, that is, there is a situation where one restoration module is connected to multiple storage modules, and there is also a situation where one restoration module is connected to one storage module.

[0098] In the process of storing the first instruction in the memory structure, the compression module may compress the first instruction according to the memory structure and the required rate for reading the first instruction. Optionally, the rate appearing in the present application can be understood as a time delay or a clock cycle, and the required rate for reading the first instruction refers to the clock cycle required to read the first instruction from the memory structure, and the unit of measurement of the clock cycle is, for example, beat, or other time unit. In one possible case, reading the first instruction from the memory structure includes multiple processes of reading the first instruction from the memory included in the memory structure and processing the read first instruction, and the processing is, for example, an operation such as restoration.

[0099] The embodiments of the present application do not limit the process of the compression module obtaining the required rate for reading the first instruction, including but not limited to: obtaining at least one of the path attributes of the read paths of each memory included in the memory structure or the read efficiency of the memory structure, the read path of the memory is the path connecting the memory and the read module, the read module is used to read the instructions stored in the memory and process the read instructions; determining the required rate for reading the first instruction based on at least one of the path attributes or the read efficiency.

[0100] Exemplarily, a memory read module refers to a read module connected to the memory for reading instructions stored in the memory. Taking the memory structure shown in the left figure of FIG. 2 as an example, when the memory is a storage module, the read module is a cache module; when the memory is a cache module, the read module is a decoding module. Taking the memory structure shown in the right figure of FIG. 2 as an example, when the memory is a storage module, the read module is a restore module 03 connected to the storage module; when the memory is a cache module, the read module is a restore module 03 connected to the memory.

[0101] Optionally, the compression module may determine a read path connecting each memory and the read module, and determine path attributes of the read path, wherein the path attributes are characteristics that affect the read latency of the read path, and the path attributes include, but are not limited to, the length or width of the read path. In one possible implementation, read efficiency is related to a network processor (NP) corresponding to the memory structure. The compression module may obtain the processing performance of the NP corresponding to the memory structure, determine the read efficiency of the memory structure based on the processing performance, and determine the required rate for reading the first instruction stored in the memory structure based on the read efficiency and the path attributes of the read path of each memory.

[0102] Exemplarily, the required rate for reading the first instruction stored in the memory structure refers to the overall rate required to completely read the first instruction from the memory structure. When the memory structure includes one memory, the required rate for reading the first instruction refers to the rate of reading the first instruction from the memory and the rate of restoring the read first instruction. When the memory structure includes multiple memories, such as the storage module and cache module shown in Figure 2, the required rate for reading the first instruction from the memory structure includes rate 1 for reading the first instruction from the storage module, rate 2 for restoring the read first instruction, rate 3 for sending the first instruction stored in the storage module to the cache module, rate 4 for reading the first instruction stored in the cache module, and rate 5 for restoring the read first instruction. Optionally, the required rate for reading the first instruction can also be set based on experience. For example, the compression module provides an information input control, and the operation and maintenance personnel set the required rate for reading the first instruction based on experience and the implementation environment, and input the required rate through the information input control, so that the compression module obtains the required rate for reading the first instruction. The implementation environment can refer to the hardware configuration of the memory structure, such as the type of NP used or the model of the memory structure.

[0103] Regardless of the method by which the compression module obtains the required rate for reading the first instruction, the compression level of the memories in the memory structure can be determined based on the memory structure and the required rate for reading the first instruction. Exemplarily, the compression module determines the read rate of each memory included in the memory structure; determines the restore rate of each memory based on the required rate for reading the first instruction and the read rate of each memory, where the restore rate of the memory is the rate at which instructions stored in the memory are decompressed on the read path of the memory; and determines the compression level of each memory based on the restore rate of each memory, where the restore rate corresponding to the compression level of the memory matches the restore rate of the corresponding memory.

[0104] Optionally, the compression module determines the memory in the memory structure where the first instruction is to be stored. Taking the memory structure as an example, the memory structure includes a storage module and multiple cache modules. Multiple cache modules share one storage module. In this case, a first instruction will first be stored by the storage module and then stored by any cache module in the multiple cache modules. Therefore, the memory in the memory structure where the first instruction is to be stored is a storage module and a cache module.

[0105] Afterwards, the compression module can determine the read rate required to read instructions from each memory based on the hardware structure of each memory. Since the required rate for reading the first instruction is the overall rate for completing the reading of the first instruction from the memory included in the memory structure, that is, the required rate includes the read rate for reading the first instruction from the memory and the processing rate for processing the read first instruction, and processing the first instruction includes restoring the first instruction, etc. Therefore, the sum of the restoration rate and the read rate of each memory is not greater than the required rate for reading the first instruction. The required rate and the sum of the read rates of each memory can be subtracted, and the difference obtained represents the maximum value of the sum of the restoration rates of each memory. Then, based on the hardware structure of each memory, such as the read path of each memory and the read rate required for the read module of each memory to read instructions, the restoration rate of each memory is determined. The restoration rate of any memory indicates the rate for restoring instructions stored in any memory, and the restoration rate does not affect the original forwarding performance of the memory.

[0106] Since the restoration rate and compression complexity are negatively correlated, the higher the compression complexity, the lower the corresponding restoration rate. Therefore, the corresponding compression complexity can be determined based on the restoration rate, and the compression level can be determined based on the compression complexity. Optionally, the higher the compression level, the higher the compression complexity, the lower the restoration rate, and the higher the compression ratio. The compression ratio refers to the ratio of compressed instructions to uncompressed instructions.

[0107] Optionally, the compression module can also obtain the rate range corresponding to each compression level, and determine the compression level of each memory according to the restoration rate of each memory and the rate range corresponding to each compression level. Taking the compression level including one layer of compression and two layers of compression as an example, the rate range corresponding to one layer of compression is range A, and the rate range corresponding to two layers of compression is range B. Since the restoration rate of the storage module is the rate included in range B, the compression module determines that the compression level of the storage module is two-layer compression. Based on the fact that the restoration rate of the cache module is the rate included in range A, the compression module determines that the compression level of the cache module is one-layer compression.

[0108] In one possible scenario, the compression module can also directly determine the compression level of each memory based on the read rate of each memory. Continuing with the example of a memory including a cache module and a storage module, since the read rate of the storage module is lower than the read rate of the cache module, the compression level of the storage module is higher than that of the cache module. For example, if the compression level of the storage module is two layers and the compression level of the cache module is one layer, the restoration rate of the one layer of compression is higher than the restoration rate of the two layers of compression.

[0109] S303 , compress the first instruction using a compression level.

[0110] Exemplarily, the compression module determines the compression method of the compression level of each memory, and compresses the first instruction according to the determined compression method. The compression methods of different compression levels may be different. For example, the compression method of one-layer compression is fixed-length processing, and the compression method of two-layer compression is variable-length compression. The compression methods of different compression levels may also be the same, that is, the number of compressions indicated by different compression levels is different. For example, the compression method of one-layer compression is to use compression algorithm 1 for compression, and the compression method of two-layer compression is to use compression algorithm 1 for compression once to obtain compression result 1, and compress compression result 1 twice to obtain compression result 2. Compression result 2 is also the result obtained by compression using the compression method of two-layer compression.

[0111] When a memory structure includes multiple memories, the multiple memories have a compression order. Continuing with the example of a memory structure including a storage module and a cache module, as shown in Figure 5, after a first instruction is compressed using compression algorithm 1 and compression algorithm 2, respectively, to obtain a third instruction, the third instruction is stored in the storage module. After reading the third instruction stored in the storage module, it is sent to the cache module for caching. During transmission, the third instruction is restored by executing decompression logic 2 corresponding to compression algorithm 2, restoring the third instruction to the second instruction, which is then cached in the cache module. Subsequently, after reading the second instruction stored in the cache module, it is sent to the decoding module for parsing. During transmission, the second instruction is restored by executing decompression logic 1 corresponding to compression algorithm 1, restoring the second instruction to the first instruction, which is then decoded by the decoding module. In this case, since the decompression corresponding to the compression method of the storage module is performed first, followed by the decompression corresponding to the compression method of the cache module, the decompression order is opposite to the compression order, i.e., the later the compression is, the earlier the corresponding restoration is performed. Therefore, the compression module first executes the compression method of the cache module, and then performs the compression method of the storage module.

[0112] Optionally, for a memory structure including multiple memories, the compression module may first determine the compression method for each memory and then determine the compression order for each memory, or may first determine the compression order for each memory and then determine the compression method for each memory. Alternatively, the compression order and compression method may be determined in parallel based on multiple threads. Regardless of the method used by the compression module to determine the compression order and compression method, the first instruction may be compressed using the compression method of each memory according to the compression order to obtain a compressed first instruction.

[0113] Since the processes of compressing the first instruction once and multiple times are similar, the following takes the memory structure including a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, and the restoration rate of one-layer compression is higher than the restoration rate of two-layer compression as an example to introduce the process of compressing the first instruction.

[0114] In one possible implementation, the compression module compresses the first instruction using a one-layer compression method to obtain a second instruction; and compresses the second instruction using a two-layer compression method to obtain a third instruction, and the compression rate of the two-layer compression method is greater than the compression rate of the one-layer compression method. Exemplarily, the one-layer compression method is fixed-length processing, and the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. The compression ratio is, for example, an arbitrary integer set based on experience and implementation environment. The compression ratio can also be determined based on business characteristics. Optionally, the compression module obtains the business characteristics of the first instruction, and the business characteristics indicate the operating quality requirements of the business running based on the first instruction; the compression ratio is determined according to the business characteristics of the first instruction. Among them, the business characteristics can be determined based on a service-level agreement (SLA), and the business characteristics include but are not limited to the business's operating delay, packet loss rate, etc. The compression module obtains the business characteristics and determines the compression ratio that can be performed without affecting the business's operating quality based on the business characteristics. For example, the compression ratio determined based on the business characteristics can be 2. When the first instruction is 64 bits, the second instruction obtained by fixed-length processing is 32 bits. When the first instruction is 8 bits, the second instruction obtained by fixed-length processing is 4 bits. In this case, the second instruction obtained by fixed-length processing of the first instruction can also be called a half-width instruction.

[0115] In one possible case, fixed-length processing includes fixed-length compression or splitting. In this case, the compression module can obtain the instruction characteristics of the first instruction; when it is determined based on the instruction characteristics that fixed-length compression is supported, the first instruction is compressed using fixed-length compression to obtain a second instruction; or, when it is determined based on the instruction characteristics that fixed-length compression is not supported, the first instruction is split into multiple second instructions, and the bit width of each second instruction in the multiple second instructions is the same.

[0116] Exemplarily, the instruction feature of the first instruction includes at least one of the instruction type, usage frequency or field utilization of the first instruction. The instruction type may be a functional classification of the instruction, for example, the instruction type includes a transfer instruction or a memory access instruction, etc. The instruction type may also be classified according to the instruction format, for example, the instruction type includes a dual-operand instruction, a single-operand instruction or a program transfer instruction, etc. Optionally, the usage frequency of the first instruction may reflect the number of times instructions with the same function are used within a reference time. The reference time may be any time unit set based on experience and the implementation environment. For example, the reference time is 1 second. Taking the first instruction as a move (mov) instruction as an example, the compression module counts the number of mov instructions executed within 1 second and counts the usage frequency of the mov instruction. The usage frequency may also refer to the proportion of functional instructions corresponding to the first instruction among multiple instructions for running an application. In one possible case, the field utilization is used to reflect the number of blank fields included in the first instruction.

[0117] The compression module may select to determine whether fixed-length compression can be performed on the first instruction based on at least one of instruction type, usage frequency, or field utilization. Next, implementations of determining whether fixed-length compression can be performed on the first instruction based on three instruction characteristics are described.

[0118] Implementation method 1: Obtain an instruction type that supports fixed-length compression; when the obtained instruction type includes the instruction type of the first instruction, determine to perform fixed-length compression on the first instruction.

[0119] Exemplarily, the instruction types that support fixed-length compression can be input manually, for example, the network device where the compression module is located provides an information input control, and the operation and maintenance personnel input the instruction types that support fixed-length compression according to the information input control, and the compression module thereby obtains a set of instruction types that support fixed-length compression. Taking the instruction types including mov instruction and add instruction as an example, since the size of the unused blank field in the mov instruction is greater than the first threshold value set based on experience, the mov instruction has more unused space and can be fixed-length compressed. However, the size of the unused blank field in the add instruction is less than the first threshold value set based on experience, the add instruction has less unused space and cannot be fixed-length compressed. Based on this, the operation and maintenance personnel input the instruction types that support fixed-length compression including the mov instruction through the information input control. In one possible case, the compression module can also obtain a set of instruction types that support fixed-length compression by learning from historical data, where the historical data is, for example, the compression results of each instruction type using fixed-length compression, and the success rate of fixed-length compression of different instruction types is statistically analyzed through machine learning to determine the instruction types that support fixed-length compression.

[0120] Implementation method 2: when the usage frequency is greater than the second threshold, determine to use fixed-length compression for the first instruction; or when the usage frequency is not greater than the second threshold, determine not to use fixed-length compression for the first instruction.

[0121] Optionally, the second threshold value can be an arbitrary value set based on experience, such as 70% or 50%. When the usage frequency of the first instruction is greater than the second threshold value, the first instruction is a frequently used instruction, the first instruction is cached in the cache module many times, and the storage overhead occupied is large. Therefore, the first instruction is compressed to a fixed length to reduce the cache space occupied by the first instruction in the cache module, thereby reducing the storage overhead of the first instruction. However, the usage frequency of the first instruction is not greater than the second threshold value, which means that the first instruction is not a frequently used instruction, and the first instruction is cached in the cache module few times. If fixed-length compression is used for the first instruction, the first instruction after fixed-length compression must be restored later. Even if the storage overhead is reduced, the increased restoration overhead of the compressed first instruction is higher than the reduced storage overhead, and the instruction overhead is still large.

[0122] Implementation method three: when the field utilization rate is less than the third threshold, determine to use fixed-length compression for the first instruction; or when the field utilization rate is not less than the third threshold, determine not to use fixed-length compression for the first instruction.

[0123] Optionally, the third threshold value can be set according to the compression ratio. When fixed-length compression is used to compress the first instruction into a half-width instruction with half the bit width, the third threshold value can be 50%. When the field utilization rate is less than 50%, it means that there are many unused free fields in the first instruction. The first instruction can be compressed into a half-width instruction by deleting the free fields. When the field utilization rate is greater than 50%, since there are few unused free fields in the first instruction, even if all the free fields are deleted, a half-width instruction cannot be obtained. Instead, further processing is required. The processing process is redundant, complex, and inefficient. Therefore, fixed-length compression is not performed on the first instruction.

[0124] The compression module can adopt any one of implementation methods 1, 2 and 3 to determine whether the first instruction can be fixed-length compressed according to the instruction characteristics. It can also combine multiple implementation methods, for example, combine the instruction type and field utilization to determine whether the first instruction can be fixed-length compressed. In this case, one instruction feature corresponds to one judgment result. When the judgment results are different, for example, it is determined that the first instruction cannot be fixed-length compressed according to the instruction type, and it is determined that the first instruction can be fixed-length compressed according to the field utilization. The judgment result can be determined based on the weights of different instruction types. The weight of the instruction type set according to experience is lower than the weight of the field utilization. Since the field utilization indicates that the first instruction can be fixed-length compressed, the compression module determines to use fixed-length compression for the first instruction.

[0125] Regardless of the method by which the compression module determines whether the first instruction can be compressed to a fixed length, the first instruction can be compressed to a fixed length based on the determination result. For example, the process of compressing the first instruction to a fixed length includes: determining a valid field of the first instruction, and obtaining a second instruction including the valid field. The valid field refers to a field used to execute the first instruction. This field may be, for example, a non-blank field, a repeated field, or a required field that is indispensable for executing the instruction.

[0126] FIG6 is a schematic diagram of a valid field provided in an embodiment of the present application, wherein four instructions are shown in FIG6 , namely, a mov instruction, a merge (mrg) instruction, a compare (cmp) instruction, and a jump (jmp) instruction. Referring to FIG6 , the mov instruction includes an opcode (opcode) field, an ineffective condition (cond) field, a destination (destination, Dst) operand field, and a source (source, Src) 1 operand / immediate number (IMM) field, and the oblique line shading in FIG6 indicates a blank field. In FIG6 , the non-blank fields in the mov instruction include the opcode field, the ineffective cond field, the Dst field, and the Src1 / IMM field. Since the mov instruction only needs to use the opcode field, the Dst field, and the Src1 field, and does not need to use the ineffective cond field, the valid fields in the mov instruction are the opcode field, the Dst field, and the Src1 field. The valid fields in the mrg instruction, cmp instruction and jmp instruction can be determined by combining the mrg instruction, cmp instruction and jmp instruction in Figure 6 with the mrg instruction after fixed-length compression, the cmp instruction after fixed-length compression and the jmp instruction after fixed-length compression.

[0127] After the compression module determines the valid field of the first instruction, it can determine the second instruction based on the valid field. Optionally, the compression module can extract the valid field included in the first instruction and splice the valid field to obtain the second instruction. The valid field can also be reduced and the reduced valid field can be spliced ​​to obtain the second instruction. Among them, reducing the valid field refers to reducing the bits occupied by the valid field, determining the first bit occupied by the information carried in the valid field, determining the second bit occupied by the valid field, and adjusting the bits occupied by the valid field from the second bit to the first bit. For example, the field size of the valid field is 6 bits, and the information carried in the valid field occupies 4 bits. Therefore, the valid field can be reduced to 4 bits. In Figure 6, the compression module extracts the opcode field, Dst field, and Src1 field, reduces the opcode field, Dst field, and Src1 field, and splices the reduced opcode field, Dst field, and Src1 field to form the fixed-length compressed mov instruction shown in Figure 6, which is the second instruction. In one possible scenario, the compression module can also narrow the data selection range of the valid field. For example, it determines a commonly used selection range in the valid field whose usage frequency is greater than a reference threshold, and uses the commonly used selection range as the data selection range indicated by the valid field. For example, in the mrg instruction in Figure 6, since the data selection uses a low address space and a small immediate value, wherein the small immediate value index value is less than the immediate value of the fourth threshold, and the low address space index value is less than the address space of the fifth threshold, the fourth threshold and the fifth threshold can be values ​​set based on experience and implementation environment. In this case, the small immediate value can be modified to a field to achieve a narrowing of the data selection range. In one possible scenario, the above-mentioned fixed-length compression process can also be referred to as instruction set architecture compression (ISA compression) or instruction set compression.

[0128] For the first instruction that cannot be compressed to a fixed length, the compression module will also split the first instruction, splitting the first instruction into second instructions with the same compression ratio and bit width. The above splitting process can be based on the instruction structure of the first instruction. For example, the splitting position of the first instruction is determined in the instruction structure of the first instruction according to the compression ratio, and the first instruction is split at the splitting position to obtain multiple second instructions. Taking the compression ratio of 2 and the first instruction of 8 bits as an example, based on the fact that 8 divided by 2 is equal to 4, the splitting position of the first instruction is determined to be the midpoint of the instruction structure, that is, the position of the 4th bit, and the first 4-bit field of the first instruction is split into the first second instruction, and the last 4 bits of the first instruction are split into the second second instruction. By splitting or compressing the first instruction to a fixed length, the instruction size of the second instruction is unified. By normalizing the bit width ratio of the instruction, the subsequent compression process of the second instruction with the unified bit width ratio is simpler and the compression efficiency is higher.

[0129] Since the compression module may perform fixed-length compression on the first instruction to obtain the second instruction, or may split the first instruction to obtain the second instruction, the second instruction includes a compression flag bit, which indicates that the second instruction is obtained by fixed-length compression or splitting. Referring to Figure 7, Figure 7 includes 8 first instructions to be processed. Among them, the number after inst is used to distinguish different first instructions, and the English in brackets is the instruction type of the first instruction, that is, mov indicates that the first instruction is a mov instruction, add indicates that the first instruction is an add instruction, and jmp indicates that the first instruction is a jmp instruction. The 0 and 1 after each first instruction in Figure 7 are used as the boundary bit of the instruction bundle. When the boundary bit is equal to 0, it is determined that the instruction is not the last instruction in the instruction bundle. When the boundary bit is equal to 1, it is determined that the instruction is the last instruction in the instruction bundle. That is, in Figure 7, inst0, inst1, inst2, and inst3 belong to the same instruction bundle, inst4 and inst5 belong to the same instruction bundle, and inst6 and inst7 belong to the same instruction bundle.

[0130] The compression module performs fixed-length processing on the eight first instructions in FIG7 to obtain a plurality of second instructions. The second instruction in FIG7 includes a compression flag bit. By assigning a value to the compression flag bit, different fixed-length processing can be indicated. For example, when the compression flag bit is a first value, it is determined that the method for obtaining the second instruction is fixed-length compression. When the compression flag bit is a second value, it is determined that the method for obtaining the second instruction is splitting. The first value and the second value can be any different values ​​set according to experience, such as 1 for the first value and 0 for the second value.

[0131] In Figure 7, the second instruction of the mov instruction is obtained through fixed-length compression, with the compression flag bit before inst0_C set to the first value of 1. The second instruction of the add instruction is obtained through splitting, with the compression flag bit before inst2(add) set to the second value of 0. In Figure 7, the compression module splits the add instruction, resulting in two second instructions corresponding to the add instruction. In Figure 7, the C in the second instructions of the mov and jmp instructions indicates a single compression.

[0132] After the first instruction is processed to a fixed length to obtain a second instruction, the second instruction can be compressed using a two-layer compression method to reduce the size of the second instruction. Because the restoration method corresponding to the two-layer compression is executed on the read path from the storage module to the cache module, and the cache module has a low instruction read rate requirement, the restoration rate of the two-layer compression method used by the compression module can be lower than the restoration rate of the single-layer compression method. The two-layer compression method includes but is not limited to variable-length compression, which means that the length of the compressed instruction is not fixed.

[0133] Exemplarily, the compression module can perform variable-length compression on each second instruction sequentially according to the instruction position of each second instruction, or can perform variable-length compression on each second instruction randomly, or can perform variable-length compression on each second instruction from high to low or from low to high according to the frequency of occurrence of each second instruction. Referring to Figure 8, after a plurality of first instructions are fixed-length processed according to the instruction characteristics, some of the first instructions are selected for fixed-length compression, compressed into the original half-width, and an instruction compression mark is added to obtain the second instruction. For the uncompressed full-width instruction, that is, the first instruction, the first instruction is split into two segments according to the half-width to obtain two second instructions. For the processed second instructions, the compression module will count the high-frequency second instructions, that is, the frequency of occurrence is higher than the frequency threshold, and give priority to variable-length compression of the high-frequency second instructions.

[0134] Optionally, the variable-length compression process includes but is not limited to: obtaining the frequency of occurrence of each field included in the second instruction; obtaining a third instruction based on the frequency of occurrence of each field, the third instruction including the encoding of each field, the encoding of each field is determined based on the frequency of occurrence of each field, and the length of the encoding of each field is inversely proportional to the frequency of occurrence of each field.

[0135] Exemplarily, the frequency of occurrence of a field may refer to the frequency of occurrence of the field in a full instruction, where the full instruction refers to all instructions to be stored in the memory structure, and the full instruction includes the second instruction. In one possible case, different instructions include the same field, and the same field may refer to a field with exactly the same index value, or a field with the same function, or a field with similar functions. For any field included in the second instruction, the compression module counts the first number of any field and the second number of fields included in the full instruction, divides the first number by the second number, and the quotient obtained is the frequency of occurrence of any field.

[0136] After determining the frequency of occurrence of each field, the compression module can encode the fields according to the frequency of occurrence of each field. In one possible case, the compression module can construct a coding dictionary corresponding to the second instruction according to the frequency of occurrence of each field, and the coding dictionary includes each field and the frequency of occurrence of each field; the coding of each field is determined according to the coding dictionary. The compression module can use the frequency of occurrence of each field as the index of the field and store the field and the index together in the coding dictionary. It can also determine the storage location of each field in the compression dictionary according to the frequency of occurrence of each field. Taking the compression dictionary as a multi-branch tree as an example, the field with the highest frequency of occurrence is used as the root node, and then the leaf nodes are constructed from bottom to top according to the frequency of occurrence of each field from high to low.

[0137] Regardless of the method by which the compression module constructs the coding dictionary, the second instruction can be variable-length compressed based on the constructed coding dictionary to obtain the third instruction as shown in Figure 8. Optionally, the compression module determines the frequency of occurrence of each field according to the coding dictionary, and determines the code corresponding to the field according to the frequency of occurrence. Among them, the higher the frequency of occurrence of the field, the shorter the length of the code. For example, the fields include field A, field B and field C. The frequency of occurrence of field A is higher than the frequency of occurrence of field B, and the frequency of occurrence of field B is higher than the frequency of occurrence of field C. In this case, the code of field A is 0, the code of field B is 1, and the code of field C is 01. In one possible implementation, the above variable-length compression can be called Huffman compression.

[0138] By determining the encoding corresponding to each field according to the frequency of occurrence, the field with a higher frequency of occurrence has a greater number of fields in the full amount of instructions. Therefore, the fields with a large number of fields are encoded with a small length, and then the encodings corresponding to multiple fields are spliced ​​into a third instruction, which effectively reduces the overall length of the full amount of instructions. In addition, the second instruction may include one or more fields, which is not limited in the embodiment of the present application. When the second instruction includes a field, the above-mentioned process of encoding according to the frequency of occurrence of the field can be understood as encoding the second instruction as a whole according to the frequency of occurrence of the second instruction in the full amount of instructions, that is, one second instruction corresponds to one encoding, which is the third instruction.

[0139] In one possible implementation, the third instruction includes a coding index, which is used to search for a field corresponding to the coding included in the third instruction during decompression of the third instruction. When the coding utilizes a compression dictionary, the coding index can be referred to as dictionary index search information. Continuing with FIG. 7 , the coding index is information carried in a tag, which in some cases can also be referred to as a fixed-length code compression tag.

[0140] In one possible scenario, after compressing the first instruction, the compression module may store the compressed first instruction in a memory structure, so that the compressed first instruction achieves a programmable effect, facilitates subsequent parsing by the decoding module and calculation by the parallel computing module, and thereby ensures the smooth execution of the application corresponding to the first instruction. Exemplarily, the compression module obtains the instruction length of the compressed first instruction; determines a storage unit in the memory structure for storing the compressed first instruction based on the instruction length; and stores the compressed first instruction in the determined storage unit.

[0141] Optionally, continuing with the example of the compressed first instruction being the third instruction in the above embodiment, the third instruction, in addition to including an encoding index, also includes a length field for the third instruction. The encoding module can determine the instruction length of the third instruction by parsing the length field of the third instruction and then, based on the memory size of free cells in the storage cells of the storage module, store the third instruction in a storage cell with free memory size not less than the instruction length. In one possible scenario, when the third instruction is an instruction obtained by compressing the first instruction included in the instruction bundle, the compression module will store multiple third instructions belonging to the same instruction bundle in the same row of storage cells. Optionally, the compression module can determine multiple third instructions belonging to the same instruction bundle based on the boundary bits of each third instruction, or can determine third instructions with the same instruction bundle identifier as belonging to the same instruction bundle based on the instruction bundle identifier carried by each third instruction. Since the instructions in the storage module are subsequently parsed in units of a row of storage cells, by storing multiple third instructions belonging to the same instruction bundle in the same row, it is ensured that the third instructions belonging to the same instruction bundle can be processed in parallel at the same time. Continuing with FIG. 7 , FIG. 7 , the compression module stores multiple third instructions obtained by variable-length compression in the same row of storage cells. In FIG7 , the uncompressed first instruction occupies two rows of storage units. By compressing the first instruction, the storage space occupied by the first instruction is effectively reduced, thereby reducing storage overhead.

[0142] In summary, the instruction processing method provided by the embodiment of the present application compresses the first instruction before storing the first instruction to reduce the size of the first instruction. The memory structure of the same capacity can store more compressed first instructions than the number of first instructions before compression, thereby increasing the instruction storage capacity of the memory structure and reducing the storage overhead of the memory structure. In addition, more instructions are stored in the same row of storage units. Subsequently, in the process of reading instructions in units of rows, the number of instruction reads is small and the reading overhead is small. Since the compression of the first instruction is based on the compression level of the memory, and the compression level of the memory is determined according to the required rate of reading the first instruction from the memory structure, the process of restoring the compressed first instruction meets the required rate of the memory structure. Even if the compressed first instruction needs to be restored during the process of reading the compressed first instruction, it does not affect the normal operation of the memory in the memory structure, and also ensures the smooth operation of the application program running based on the first instruction.

[0143] An embodiment of the present application provides an instruction processing method, which can be applied to the implementation environment shown in Figure 1 or Figure 2 above. Taking the method executed by the restoration module as an example, the flowchart of the method is shown in Figure 9, including S901-S902.

[0144] S901, obtaining a compressed first instruction, where compression of the first instruction is implemented based on a compression level, where the compression level is determined based on a memory structure and a required rate for reading the first instruction, and the memory structure is used to store the compressed first instruction.

[0145] Exemplarily, the restoration module obtains an identifier of an instruction to be processed and determines the compressed first instruction to be processed based on the identifier. The restoration module can determine the identifiers of the instructions currently allowed for calculation based on the program loading status within the device, or it can receive manually input instruction identifiers. The instruction identifier can be the identifier of the instruction bundle to which the compressed first instruction belongs, or it can be the location identifier of the storage unit where the instruction is located, such as the row of the storage unit. The instruction identifier can also be other identifiers that can distinguish different instructions.

[0146] Regardless of the method by which the restoration module obtains the identifier of the instruction to be processed, the restoration module can determine the compressed first instruction to be processed based on the instruction identifier, and extract the compressed first instruction from the memory structure. In one possible implementation, the restoration module can extract at least one instruction stored in a row of storage cells of the storage module; separate the instructions in the at least one instruction based on their instruction lengths to obtain at least one instruction, wherein the at least one instruction includes the compressed first instruction.

[0147] At least one instruction stored in a row of storage cells is 0100001110101, where 0 is a compression mark bit and the beginning of the first instruction is 1. Since the instruction length of the first instruction is 3, the first instruction is 100, and the 0 after 100 is a boundary bit. Therefore, the compression mark bit of the second instruction is determined to be 0, and then the second instruction is determined according to the instruction length of the second instruction, thereby realizing the separation of multiple instructions.

[0148] FIG10 is a schematic diagram of an instruction processing process provided by an embodiment of the present application. Referring to FIG10 , multiple compressed instructions are stored in a storage module in units of instruction words. In FIG10 , one instruction word includes eight half-width instructions (half inst) because a row of storage cells in the cache module can only store eight half-width instructions. The lengths of the instruction words corresponding to the eight half-width instructions in FIG10 are different because the lengths of the instructions obtained by performing variable-length compression on the half-width instructions included in different instruction words are different.

[0149] FIG10 uses the example of reading instruction word IW_C4 to illustrate the process. The restoration module locates instruction word IW_C4 using the program counter (PC), extracts the located instruction word IW_C4, and separates each instruction according to the instruction length of each instruction included in instruction word IW_C4. Regarding the instruction length of the instruction shown in FIG7 , which is information included in the instruction tag, the restoration module can determine the instruction length of each instruction through tag parsing to achieve the separation of multiple instructions. For example, a tag parser is used in FIG10 . Since the separation of multiple instructions is performed sequentially, the tag parsing process can be referred to as serial parsing in some cases. After separating multiple instructions, the restoration module can determine the first compressed instruction to be processed from the multiple instructions. Continuing with FIG10 as an example, the first five instructions of the eight instructions separated in FIG10 are instructions included in instruction bundle 1. Since the instruction identifier indicates that the current instruction bundle to be processed is instruction bundle 1, the restoration module thus determines that the first five instructions are the first compressed instructions to be processed. Optionally, the first instruction includes an instruction to forward the application.

[0150] In one possible implementation, the restoration module can also receive the compressed first instruction sent by the memory structure to obtain the compressed first instruction to be restored. Continuing with the example of the memory structure shown in FIG4 including the storage module, the processor core sends an instruction read request to the storage module, and the storage module determines that the instruction to be read is the compressed first instruction based on the instruction read request, and reads the compressed first instruction. Since the instruction format that the processor core can process is an uncompressed instruction format, the compressed first instruction must be restored to the uncompressed first instruction before returning the instruction to the processor core. Based on this, the storage module sends the extracted compressed first instruction to the restoration module, and the restoration module thereby obtains the compressed first instruction.

[0151] S902, restore the compressed first instruction.

[0152] Exemplarily, the restoration module obtains the compression method corresponding to the compressed first instruction, and restores the compressed first instruction using the restoration method corresponding to the compression method. The compression method corresponding to the first instruction matches the compression level of the memory storing the first instruction. The restoration module can determine the compression method adopted by the compression module for the first instruction based on the communication connection with the compression module. In the case where the compressed first instruction is obtained by compressing the first instruction using multiple compression methods, the restoration module can determine the restoration order corresponding to each memory according to the reading order of each memory, and execute the restoration method corresponding to the compression method on the compressed first instruction in sequence according to the restoration order.

[0153] In the embodiment shown in Figure 3, the memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, the restoration rate of one-layer compression is higher than the restoration rate of two-layer compression, and the compressed first instruction includes the third instruction. The process of restoring the compressed first instruction includes but is not limited to: restoring the third instruction using the restoration method corresponding to the compression method of the two-layer compression to obtain the second instruction; restoring the second instruction using the restoration method corresponding to the compression method of the one-layer compression to obtain the first instruction, and the compression rate of the two-layer compression method is greater than the compression rate of the one-layer compression method.

[0154] Exemplarily, when the compression method of the two-layer compression is variable-length compression, the restoration method corresponding to the variable-length compression includes: the restoration module parses the encoding index included in the third instruction; determines the various fields corresponding to the various codes included in the third instruction according to the encoding index, and determines the second instruction according to the various fields corresponding to the various codes, and the length of the code of each field is inversely proportional to the frequency of occurrence of each field.

[0155] In one possible implementation, the third instruction includes a coding index. For example, the third instruction includes a tag field, and the restoration module parses the tag field to determine the coding index carried in the tag field. Alternatively, the coding index may directly indicate the correspondence between the coding and the field. When the compression module encodes based on a coding dictionary, the coding index may indicate the coding dictionary used in the process of encoding to obtain the third instruction, and the restoration module determines the correspondence between the coding and the field based on the coding dictionary.

[0156] In one possible scenario, the second instruction obtained by the compression module from compressing the first instruction has different situations, namely, situation one of the second instruction obtained by fixed-length compression of the first instruction, situation two of the high-order portion of the second instruction obtained by splitting the first instruction, and situation three of the low-order portion of the second instruction obtained by splitting the first instruction. The encoding dictionaries used to encode the second instructions of different situations are stored in different locations. In this case, the restoration module first determines the situation of the second instruction corresponding to the third instruction based on the compression flag bit carried by the third instruction, and sends the encoding index to the storage location of the encoding dictionary corresponding to the determined situation, thereby obtaining the encoding dictionary.

[0157] Exemplarily, the restoration module parses the compression mark bit, determines the storage location of the encoding dictionary of the third instruction based on the compression mark bit and the information carried by the third instruction, accesses the determined storage location, and obtains the encoding dictionary of the third instruction based on the encoding index. When the value of the compression mark bit is the first value, it is determined that the second instruction corresponding to the third instruction is case one, and the encoding dictionary for decompressing the third instruction is determined from multiple fixed-length compressed encoding dictionaries based on the encoding index of the third instruction. When the value of the compression mark bit is the second value, it is determined whether the second instruction corresponding to the third instruction belongs to the high-order part or the low-order part based on the information carried by the second instruction. When the second instruction corresponding to the third instruction belongs to the high-order part, it is determined that the second instruction corresponding to the third instruction is case two, and the encoding dictionary for decompressing the third instruction is determined from the high-order width encoding dictionary based on the encoding index. When the second instruction corresponding to the third instruction belongs to the low-order part, it is determined that the second instruction corresponding to the third instruction is case three, and the encoding dictionary for decompressing the third instruction is determined from the low-order width encoding dictionary based on the encoding index.

[0158] Figure 11 is a process for restoring a third instruction provided by an embodiment of the present application, and Figure 11 shows the process of decompressing the third instruction included in the instruction word to obtain the second instruction. Among them, the instruction word includes 9 third instructions, and the restoration module determines the fixed-length processing corresponding to each third instruction according to the compression mark bit of each third instruction. When the fixed-length processing corresponding to the third instruction is fixed-length compression, the encoding index carried in the tag is parsed, and the encoding index is sent to the storage space for storing the encoding dictionary for fixed-length compression, and the encoding dictionary for decompressing the third instruction returned according to the encoding index search is received. When the fixed-length processing corresponding to the third instruction is split, for the third instruction obtained by compressing the second instruction with high bit width, the encoding index is sent to the storage space for storing the encoding dictionary with high bit width, and the encoding dictionary for decompressing the third instruction returned according to the encoding index search is received. For the third instruction obtained by compressing the second instruction with low bit width, the encoding index is sent to the storage space for storing the encoding dictionary with low bit width, and the encoding dictionary for decompressing the third instruction returned according to the encoding index search is received.

[0159] Regardless of the method used by the restoration module to obtain the encoding dictionary used to decompress the third instruction, the corresponding relationship between the encoding and the field can be obtained based on the encoding dictionary. Taking the example of the encoding dictionary constructing the storage location of each field based on the frequency of occurrence of each field, the restoration module determines the frequency of occurrence of each field based on the storage location of each field in the encoding dictionary, and determines the corresponding relationship between each field and the encoding based on the corresponding relationship between the frequency of occurrence of each field and the encoding. Afterwards, the restoration module searches for the fields corresponding to each encoding included in the third instruction based on the corresponding relationship between the field and the encoding, and splices the corresponding fields to obtain the second instruction.

[0160] Exemplarily, after restoring the third instruction to obtain the second instruction, the restoration module may send the second instruction to the cache module for caching. Optionally, because the restoration module uses instruction words as a dimension when restoring the third instruction, and an instruction word refers to at least one instruction stored in a row of cache cells of the cache module, the multiple restored second instructions may be stored in the same row of the cache module. For example, as shown in FIG10 , in FIG10 , the decompressed instruction word IW_4 including the multiple second instructions is stored in a row of the cache module.

[0161] After restoring the third instruction to obtain the second instruction, the restoration module may further restore the second instruction. For example, the second instruction may be extracted from the cache module and restored using a restoration method corresponding to the compression method of the first-layer compression. For example, when the compression method of the first-layer compression is fixed-length processing, restoration method two corresponding to the fixed-length processing includes: determining a method for obtaining the second instruction from fixed-length compression or splitting; and performing a restoration operation corresponding to the determined method on the second instruction.

[0162] In one possible implementation, when the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained through fixed-length compression or splitting, the restoration module can parse the compression flag bit included in the second instruction, thereby determining the manner in which the second instruction is obtained from fixed-length compression and splitting based on the compression flag bit, and then selecting the restoration operation for restoring the second instruction.

[0163] Exemplarily, the restoration module reads the compression flag bit, and when the compression flag bit is a first value, determines that the method for obtaining the second instruction is fixed-length compression, and when the compression flag bit is a second value, determines that the method for obtaining the second instruction is splitting. Figure 12 is a schematic diagram of restoring the second instruction provided by an embodiment of the present application. In Figure 12, an instruction word includes eight second instructions. The restoration module parses the compression flag bit before inst0_C. Since the value of the compression flag bit is the first value 1, it determines that the fixed-length processing corresponding to the second instruction is fixed-length compression. Parse the compression flag bit before inst2. The value of the compression flag bit is the second value 0. It determines that the fixed-length processing corresponding to the second instruction is splitting.

[0164] After determining the fixed-length processing corresponding to the second instruction, the restoration module may perform fixed-length restoration corresponding to the fixed-length processing. In one possible scenario, the restoration method corresponding to the compression method of one layer of compression includes decompression corresponding to fixed-length compression or concatenation corresponding to splitting. Performing restoration method two on the second instruction includes, but is not limited to, the following two restoration operations.

[0165] Restoration operation 1: When the second instruction is obtained by fixed-length compression, the second instruction is subjected to decompression corresponding to the fixed-length compression to obtain the first instruction. For the second instruction obtained by fixed-length compression, the second instruction can be subjected to decompression corresponding to the fixed-length compression. Continuing with the second instruction shown in FIG6 as an example, the instruction structure corresponding to the second instruction is determined, the invalid field corresponding to the second instruction is restored according to the instruction structure, and the invalid field and the valid field included in the second instruction are spliced ​​to obtain the first instruction. Among them, the restoration module can determine the instruction structure according to the instruction type of the second instruction. For example, based on the fact that the second instruction belongs to the mov instruction, it is determined that the non-blank field of the second instruction also includes an invalid cond field. The restoration module determines the information carried by the invalid cond field based on the valid field carried by the second instruction, and splices the invalid cond field and other blank fields and valid fields to obtain the first instruction shown in FIG6.

[0166] Restoration operation 2: When the second instruction is obtained by splitting, multiple second instructions obtained by splitting the first instruction are spliced ​​together to obtain the first instruction, and the bit width of each second instruction in the multiple second instructions is the same. For the second instructions obtained by splitting, the restoration module determines the multiple second instructions obtained by splitting the same first instruction, splices the multiple second instructions, and obtains the first instruction. Optionally, the restoration module can be based on the storage location of the second instruction, for example, multiple second instructions obtained by splitting the same first instruction are stored adjacently, and the restoration module thereby determines that the second instruction whose adjacent storage and compression mark bits are all the second value is the second instruction obtained by splitting the same first instruction. Alternatively, the restoration module can also determine the second instruction belonging to the same first instruction based on the information carried by the second instruction.

[0167] In one possible implementation, after restoring the first instruction, the restoration module also sends the first instruction to the decoding module, which then parses the first instruction. Because the decoding module uses instruction bundles as processing units when parsing instructions, the restoration module's process of sending the first instruction includes, but is not limited to, determining an instruction bundle corresponding to the first instruction, the instruction bundle including at least one instruction, the compression result of the at least one instruction being stored in a same row of storage cells in a memory structure, the compression result of any instruction in the compression result of the at least one instruction being the compressed first instruction, and the at least one instruction being an instruction executed in parallel; and sending the at least one instruction included in the instruction bundle to the decoding module, which is configured to parse the at least one instruction.

[0168] FIG13 is a schematic diagram of an instruction processing process provided by an embodiment of the present application. In FIG13 , after performing fixed-length restoration on multiple second instructions to obtain multiple first instructions, the first instruction included in the instruction bundle is extracted from the multiple first instructions. For example, based on the boundary bit included in the first instruction, when the boundary bit is 0, it is determined that the first instruction is not the last instruction included in the instruction bundle, and the search continues backward until the first instruction with the boundary bit being 1 is read, and the first instruction and the previous first instruction are determined to be the first instructions included in the same instruction bundle. In FIG13 , the four first instructions included in the extracted instruction bundle are inst0, inst1, inst2, and inst3, and the decoding module receives the multiple first instructions included in the instruction bundle.

[0169] Optionally, the restoration module may first perform a fixed-length restoration on the second instruction as shown in FIG13 , and then determine the instruction bundle to which the restored first instruction belongs. Alternatively, the restoration module may first determine the instruction bundle to which each second instruction belongs, and then perform a fixed-length restoration on the second instructions included in each instruction bundle to obtain the first instructions included in each instruction bundle. Taking the multiple second instructions shown in FIG14 as an example, the restoration module extracts instruction bundle 1 including inst0, inst1, inst2, and inst3, and instruction bundle 2 including inst4 and inst5 based on the boundary bits of the multiple second instructions. Instruction bundle decompression is then used to perform a fixed-length restoration on each second instruction included in the instruction bundle to obtain multiple first instructions. The multiple first instructions included in an instruction bundle are synchronously sent to the decoding module. In addition, the embodiment of the present application does not limit the method for determining the instructions included in the instruction bundle. It may be based on the boundary bits in the above embodiment, or other methods may be used, such as based on the instruction bundle identifier.

[0170] In summary, the instruction processing method provided in the embodiments of the present application is such that the storage space occupied by the compressed first instruction is smaller than the storage space occupied by the original first instruction. A memory structure of the same memory size can store more compressed first instructions, and the memory structure has a high instruction storage capacity. Because the number of instructions stored in the same row of the memory structure is greater, when instructions stored in the memory structure are read in units of rows, instruction reading efficiency is high, saving power consumption for instruction reading.

[0171] As shown in FIG15 , in the case where multiple RTC cores in the RTC processor architecture share a cache module, each RTC core reads instructions stored in the cache module quickly. For example, the upper figure in FIG15 shows the case where the uncompressed first instruction is stored in the cache module. The multiple first instructions occupy four rows of cache units. The RTC core reads the instructions four times to retrieve the multiple first instructions. The lower figure in FIG15 shows the case where the compressed first instruction is stored in the cache module. The compressed multiple first instructions occupy two rows of cache units. The RTC core reads the instructions twice to retrieve the multiple first instructions. The reading rate of the RTC core is improved, and the probability of conflict when the RTC core accesses the cache module at the same time is small. More RTC cores can share the cache module, saving more cache modules. In addition, the method for restoring the compressed first instruction meets the processing requirements of the read modules of each memory in the memory structure. Even if the compressed first instruction is decompressed, it will not affect the normal operation of the read module, thereby ensuring the processing performance of the read module and the normal operation of the business corresponding to the first instruction.

[0172] The above describes the instruction processing method of the embodiment of the present application. Corresponding to the above method, the embodiment of the present application also provides an instruction processing device. Figure 16 is a structural diagram of an instruction processing device provided by the embodiment of the present application. Based on the following multiple modules shown in Figure 16, the instruction processing device shown in Figure 16 can perform all or part of the operations shown in Figure 3 above. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiment of the present application does not limit this. As shown in Figure 16, the device includes:

[0173] An acquisition module 1601 is configured to acquire a first instruction to be processed;

[0174] a determining module 1602 for determining a compression level of a memory in a memory structure according to the memory structure and a required rate for reading the first instruction, the memory structure being used to store the compressed first instruction;

[0175] The compression module 1603 is configured to compress the first instruction using a compression level.

[0176] In one possible implementation, the acquisition module 1601 is also used to obtain at least one of the path attributes of the read paths of each memory included in the memory structure or the read efficiency of the memory structure, where the read path of the memory is the path connecting the memory and the read module, and the read module is used to read the instructions stored in the memory and process the read instructions; the determination module 1602 is also used to determine the required rate for reading the first instruction based on at least one of the path attributes or the read efficiency.

[0177] In one possible implementation, the determination module 1602 is used to determine the read rate of each memory included in the memory structure; determine the restoration rate of each memory based on the required rate of reading the first instruction and the read rate of each memory, and the restoration rate of the memory is the rate of decompressing the instructions stored in the memory on the read path of the memory; determine the compression level of each memory based on the restoration rate of each memory, and the compression rate corresponding to the compression level of the memory matches the restoration rate corresponding to the memory.

[0178] In one possible implementation, the memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, and the restoration rate of one-layer compression is higher than the restoration rate of two-layer compression; the compression module 1603 is used to compress the first instruction using a one-layer compression method to obtain a second instruction; and compress the second instruction using a two-layer compression method to obtain a third instruction, and the compression rate of the two-layer compression method is greater than the compression rate of the one-layer compression method.

[0179] In one possible implementation, the ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio. The acquisition module 1601 is also used to obtain the business characteristics of the first instruction, and the business characteristics indicate the operating quality requirements of the business running based on the first instruction; the determination module 1602 is also used to determine the compression ratio based on the business characteristics of the first instruction.

[0180] In one possible implementation, the compression module 1603 is used to obtain the instruction characteristics of the first instruction; when it is determined based on the instruction characteristics that fixed-length compression is supported, the first instruction is compressed using a fixed-length compression method to obtain a second instruction; or, when it is determined based on the instruction characteristics that fixed-length compression is not supported, the first instruction is split into multiple second instructions, and the bit width of each second instruction in the multiple second instructions is the same.

[0181] In a possible implementation, the instruction feature includes at least one of an instruction type, a usage frequency, or a field utilization rate of the first instruction.

[0182] In a possible implementation, the compression module 1603 is configured to determine a valid field of the first instruction and obtain a second instruction including the valid field, where the valid field is a field used to execute the first instruction.

[0183] In a possible implementation, the second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting.

[0184] In one possible implementation, the compression module 1603 is used to obtain the frequency of occurrence of each field included in the second instruction; obtain a third instruction based on the frequency of occurrence of each field, the third instruction includes the encoding of each field, the encoding of each field is determined based on the frequency of occurrence of each field, and the length of the encoding of each field is inversely proportional to the frequency of occurrence of each field.

[0185] In a possible implementation, the determination module 1602 is further configured to construct a coding dictionary corresponding to the second instruction according to the occurrence frequency of each field, the coding dictionary including each field and the occurrence frequency of each field; and determine the coding of each field according to the coding dictionary.

[0186] In a possible implementation, the third instruction includes an encoding index, and the encoding index is used to find a field corresponding to the encoding included in the third instruction during decompression of the third instruction.

[0187] In one possible implementation, the device also includes: a storage module, used to obtain the instruction length of the compressed first instruction; determine the storage unit in the memory structure for storing the compressed first instruction based on the instruction length, and store the compressed first instruction in the determined storage unit.

[0188] In a possible implementation, the first instruction includes an instruction to forward an application.

[0189] In a possible implementation, the acquisition module 1601 is configured to acquire at least one instruction included in the instruction bundle, wherein any instruction in the at least one instruction is a first instruction to be processed, and at least one instruction is an instruction to be executed in parallel.

[0190] The above-described device compresses the first instruction to reduce the amount of storage space occupied by the first instruction. A memory structure of the same capacity can store more compressed first instructions than uncompressed first instructions, thereby increasing the memory structure's instruction storage capacity and reducing the memory structure's storage overhead. Because the compression of the first instruction is based on the memory's compression level, which is determined based on a required rate, the process of restoring the compressed first instruction meets the required rate of the memory structure and does not affect the normal operation of the memory in the memory structure.

[0191] The embodiment of the present application also provides another instruction processing device. Figure 17 is a schematic diagram of the structure of an instruction processing device provided by the embodiment of the present application. Based on the following multiple modules shown in Figure 17, the instruction processing device shown in Figure 17 can perform all or part of the operations shown in Figure 9 above. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiment of the present application is not limited to this. As shown in Figure 17, the device includes:

[0192] An acquisition module 1701 is configured to acquire a compressed first instruction, where compression of the first instruction is implemented based on a compression level, where the compression level is determined based on a memory structure and a required rate for reading the first instruction, where the memory structure is configured to store the compressed first instruction.

[0193] The restoration module 1702 is configured to restore the compressed first instruction.

[0194] In one possible implementation, the memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, the restoration rate of one-layer compression is higher than the restoration rate of two-layer compression, and the compressed first instruction includes a third instruction; the restoration module 1702 is used to restore the third instruction using a restoration method corresponding to the compression method of the two-layer compression to obtain a second instruction; and restore the second instruction using a restoration method corresponding to the compression method of the one-layer compression to obtain a first instruction, and the compression rate of the two-layer compression method is greater than the compression rate of the one-layer compression method.

[0195] In one possible implementation, the third instruction includes a coding index, and the restoration module 1702 is used to parse the coding index included in the third instruction; determine the fields corresponding to the codes included in the third instruction based on the coding index, and determine the second instruction based on the fields corresponding to the codes, and the length of the code of each field is inversely proportional to the frequency of occurrence of each field.

[0196] In one possible implementation, the restoration method corresponding to the compression method of one layer of compression includes decompression corresponding to fixed-length compression or splicing corresponding to splitting, and the restoration module 1702 is used to, when the second instruction is obtained by fixed-length compression, apply decompression corresponding to the fixed-length compression to the second instruction to obtain the first instruction; or, when the second instruction is obtained by splitting, splice multiple second instructions obtained by splitting the first instruction to obtain the first instruction, and the bit width of each second instruction in the multiple second instructions is the same.

[0197] In one possible implementation, the second instruction includes a compression flag bit, which indicates that the second instruction is obtained through fixed-length compression or splitting. The restoration module 1702 is also used to parse the compression flag bit included in the second instruction, and determine the method of obtaining the second instruction from fixed-length compression and splitting based on the compression flag bit.

[0198] In one possible implementation, the acquisition module 1701 is configured to extract at least one instruction stored in a row of storage cells of a memory structure; separate the instructions in the at least one instruction according to the instruction length of each instruction to obtain at least one instruction, wherein the at least one instruction includes the compressed first instruction.

[0199] In one possible implementation, the device also includes: a sending module, used to determine an instruction bundle corresponding to the first instruction, the instruction bundle includes at least one instruction, the compression result of the at least one instruction is stored in the same row storage unit of the memory structure, the compression result of any instruction in the compression result of the at least one instruction is the compressed first instruction, and at least one instruction is an instruction executed in parallel; sending the at least one instruction included in the instruction bundle to a decoding module, the decoding module is used to parse the at least one instruction.

[0200] In a possible implementation, the first instruction includes an instruction to forward an application.

[0201] The compressed first instruction occupies less storage space than the first instruction. A memory structure of the same memory size can store more compressed first instructions, increasing the memory structure's instruction storage capacity. The compressed first instruction can be restored, ensuring the normal implementation of subsequent related operations based on the first instruction.

[0202] It should be understood that the device provided in FIG. 16 or FIG. 17 only uses the division of the above-mentioned functional modules as an example to illustrate when implementing its functions. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here. In addition, the instruction processing device provided in FIG. 16 or FIG. 17 can be a chip or a communication device. For example, the instruction processing device can be the network device described below.

[0203] Referring to FIG. 18 , FIG. 18 illustrates a schematic diagram of the structure of a network device 1800 provided in accordance with an exemplary embodiment of the present application. The network device 1800 shown in FIG. 18 is configured to execute the operations described in the instruction processing method shown in FIG. 3 or FIG. 9 . The network device 1800 is, for example, a switch or router, and may be implemented using a general bus architecture.

[0204] As shown in FIG. 18 , the network device 1800 includes at least one processor 1801 , a memory 1803 , and at least one communication interface 1804 .

[0205] The processor 1801 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 1801 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute the various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0206] Optionally, network device 1800 also includes a bus. The bus is used to transmit information between the various components of network device 1800. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Buses can be categorized as address buses, data buses, control buses, and the like. For ease of illustration, FIG18 shows only one thick line, but this does not imply that there is only one bus or only one type of bus.

[0207] The memory 1803 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1803 is, for example, independent and connected to the processor 1801 via a bus. The memory 1803 can also be integrated with the processor 1801.

[0208] The communication interface 1804 uses any transceiver-like device for communicating with other devices or communication networks. The communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). The communication interface 1804 can include a wired communication interface or a wireless communication interface. Specifically, the communication interface 1804 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In an embodiment of the present application, the communication interface 1804 can be used for the network device 1800 to communicate with other devices.

[0209] In a specific implementation, as an embodiment, the processor 1801 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG18 . Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0210] In a specific implementation, as an embodiment, network device 1800 may include multiple processors, such as processor 1801 and processor 1805 shown in FIG18 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0211] In a specific implementation, as an embodiment, the network device 1800 may further include an output device and an input device. The output device communicates with the processor 1501 and can display information in a variety of ways. For example, the output device can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 1801 and can receive user input in a variety of ways. For example, the input device can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0212] In some embodiments, the memory 1803 is used to store program code 1810 for executing the solution of the present application, and the processor 1801 can execute the program code 1810 stored in the memory 1803. In other words, the network device 1800 can implement the instruction processing method provided by the method embodiment through the processor 1801 and the program code 1810 in the memory 1803. The program code 1810 may include one or more software modules. Optionally, the processor 1801 itself may also store program code or instructions for executing the solution of the present application.

[0213] In a specific embodiment, the network device 1800 of the embodiment of the present application may correspond to the computing device in the above-mentioned various method embodiments.

[0214] Among them, each step of the instruction processing method shown in Figure 3 or Figure 9 is completed by the hardware integrated logic circuit or software instruction in the processor of the network device 1800. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware. To avoid repetition, it will not be described in detail here.

[0215] Referring to FIG. 19 , FIG. 19 shows a schematic diagram of the structure of a network device 1900 provided in another exemplary embodiment of the present application. The network device 1900 shown in FIG. 19 is configured to execute all or part of the operations involved in the instruction processing method shown in FIG. 3 or FIG. 9 . The network device 1900 is, for example, a switch or router, and can be implemented using a general bus architecture.

[0216] As shown in FIG. 19 , the network device 1900 includes a main control board 1910 and an interface board 1930 .

[0217] The main control board (MCB), also known as the main processing unit (MPU) or route processor card, is used to control and manage various components in network device 1900, including routing calculations, device management, device maintenance, and protocol processing. MCB 1910 includes a central processing unit (CPU) 1911 and memory 1912.

[0218] Interface board 1930 is also known as a line processing unit (LPU), line card, or service board. It provides various service interfaces and implements data packet forwarding. Service interfaces include, but are not limited to, Ethernet interfaces and POS (Packet over SONET / SDH) interfaces. Ethernet interfaces, for example, are Flexible Ethernet Clients (FlexE Clients). Interface board 1930 includes a central processing unit (CPU) 1931, a network processor (NPU) 1932, a forwarding table memory 1934, and a physical interface card (PIC) 1933.

[0219] The central processing unit 1931 on the interface board 1930 is used to control and manage the interface board 1930 and communicate with the central processing unit 1911 on the main control board 1910 .

[0220] The network processor 1932 is used to implement packet forwarding processing. The network processor 1932 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 1932 is used to forward received packets based on the forwarding table stored in the forwarding entry memory 1934. If the destination address of the packet is the address of the network device 1900, the packet is sent to the CPU (such as the central processing unit 1631) for processing. If the destination address of the packet is not the address of the network device 1900, the next hop and outgoing interface corresponding to the destination address are searched in the forwarding table based on the destination address, and the packet is forwarded to the outgoing interface corresponding to the destination address. Processing of uplink packets can include processing the packet's inbound interface and forwarding table lookup; processing of downlink packets can include forwarding table lookup, etc. In some embodiments, the central processing unit can also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, thereby eliminating the need for a forwarding chip in the interface board.

[0221] Physical interface card 1933 implements the physical layer interconnection function. Raw traffic enters interface board 1930 through this card, and processed packets are sent out from this physical interface card 1933. Physical interface card 1933, also known as a daughter card, can be installed on interface board 1930. It is responsible for converting optical and electrical signals into packets, performing a validity check on these packets, and forwarding them to network processor 1932 for processing. In some embodiments, central processing unit 1931 can also perform the functions of network processor 1932, such as implementing software forwarding based on a general-purpose CPU, thus eliminating the need for network processor 1932 in physical interface card 1933.

[0222] Optionally, network device 1900 includes multiple interface boards. For example, network device 1900 further includes interface board 1940. Interface board 1940 includes a central processing unit 1941, a network processor 1942, a forwarding table entry memory 1944, and a physical interface card 1943. The functions and implementation of each component in interface board 1940 are the same as or similar to those of interface board 1930 and are not further described here.

[0223] Optionally, network device 1900 also includes a switching fabric board 1920. Switching fabric board 1920 may also be referred to as a switch fabric unit (SFU). If network device 1900 has multiple interface boards, switching fabric board 1920 is used to exchange data between the interface boards. For example, interface board 1930 and interface board 1940 can communicate via switching fabric board 1920.

[0224] The main control board 1910 is coupled to the interface board. For example, the main control board 1910, the interface board 1930, the interface board 1940, and the switching network board 1920 are connected to the system backplane via a system bus to achieve intercommunication. In one possible implementation, an inter-process communication (IPC) channel is established between the main control board 1910 and the interface boards 1930 and 1940, and communication is performed between the main control board 1910 and the interface boards 1930 and 1940 via the IPC channel.

[0225] Logically, network device 1900 includes a control plane and a forwarding plane. The control plane includes a main control board 1910 and a central processing unit 1911. The forwarding plane includes various components that perform forwarding, such as a forwarding table entry memory 1934, physical interface cards 1933, and a network processor 1932. The control plane performs routing functions, generates forwarding tables, processes signaling and protocol messages, and configures and maintains the network device's status. The control plane sends the generated forwarding tables to the forwarding plane. On the forwarding plane, the network processor 1932 forwards messages received by the physical interface card 1933 based on the forwarding tables sent by the control plane. The forwarding tables sent by the control plane can be stored in the forwarding table entry memory 1934. In some embodiments, the control plane and forwarding plane can be completely separate and not located on the same network device.

[0226] It's worth noting that there may be one or more main control boards (SPUs), which can include both active and standby SPUs. There may also be one or more interface boards. The higher the network device's data processing capabilities, the more interface boards it provides. Interface boards can also have one or more physical interface cards. There may be no SPUs, one or more SPUs, and multiple SPUs can provide load balancing and redundancy. In a centralized forwarding architecture, network devices may not require SPUs; the interface boards handle service data processing for the entire system. In a distributed forwarding architecture, network devices may have at least one SPU, which enables data exchange between multiple interface boards, providing high-capacity data exchange and processing capabilities. Therefore, network devices with distributed architectures have greater data access and processing capabilities than those with centralized architectures. Alternatively, a network device can consist of a single card, without a switching fabric board (SFB), integrating the functions of the interface board and the main control board. In this case, the central processing unit (CPU) on the interface board and the CPU on the main control board can be combined into a single CPU on this card, performing the combined functions of the two. This type of network device has lower data exchange and processing capabilities (for example, low-end network devices such as switches or routers). The specific architecture used depends on the specific network deployment scenario and is not specified here.

[0227] In a specific embodiment, the network device 1900 corresponds to the instruction processing apparatus shown in Figure 16 or Figure 17. In some embodiments, the compression module 1602 in the instruction processing apparatus shown in Figure 16 corresponds to the central processing unit 1911 or the network processor 1932 in the network device 1900.

[0228] An embodiment of the present application further provides a communication device, comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other via an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals. When the processor executes the instructions stored in the memory, the processor executes the instruction processing method.

[0229] It should be understood that the processor may be a CPU, or other general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the Advanced Reduced Instruction Set Machine (ARM) architecture.

[0230] Furthermore, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store device type information.

[0231] The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an EEPROM, or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0232] An embodiment of the present application further provides an instruction processing device, comprising a processor configured to load and execute at least one instruction, so that the instruction processing device implements the instruction processing method shown in either Figure 3 or Figure 9. Optionally, the device further comprises a memory coupled to the processor, the memory configured to store the at least one instruction.

[0233] An embodiment of the present application also provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor to enable the computer to implement the instruction processing method shown in either Figure 3 or Figure 9.

[0234] The embodiments of the present application further provide a computer program (product), which, when executed by a computer, can enable a processor or computer to execute the corresponding steps and / or processes in the above method embodiments.

[0235] An embodiment of the present application also provides a chip, which includes a processor for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes the instruction processing method shown in either Figure 3 or Figure 9.

[0236] An embodiment of the present application also provides another chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the instruction processing method shown in either Figure 3 or Figure 9.

[0237] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive).

[0238] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, storage, display, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the first instruction involved in this application was obtained with full authorization.

[0239] Those skilled in the art will appreciate that the various method steps and modules described in conjunction with the embodiments disclosed herein can be implemented in software, hardware, firmware, or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0240] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0241] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target. Generally speaking, a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure. In various embodiments, the function of the program module can be merged or split between the described program modules. The machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.

[0242] The computer program code for realizing the method for the embodiment of the application can be written in one or more programming languages.These computer program codes can be provided to the processor of general-purpose computer, special-purpose computer or other programmable instruction processing device, so that program code, when being executed by computer or other programmable instruction processing device, causes the function / operation specified in flow chart and / or block diagram to be implemented.Program code can be executed completely on computer, partly on computer, as an independent software package, partly on computer and partly on remote computer or completely on remote computer or server.

[0243] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like.

[0244] Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0245] A machine-readable medium may be any tangible medium that contains or stores a program for or in connection with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0246] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0247] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or can be electrical, mechanical or other forms of connection.

[0248] Modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0249] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0250] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0251] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items that have substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on quantity or order of execution. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described examples, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image. Both the first image and the second image may be images, and in some cases, may be separate and different images.

[0252] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0253] In this application, the term "at least one" means one or more, and the term "plurality" means two or more. For example, "plurality of second messages" means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0254] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0255] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items. The term "and / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this application generally indicates that the associated objects are in an "or" relationship.

[0256] It will also be understood that the term “comprise” (also known as “includes,” “including,” “comprises,” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0257] It should also be understood that the terms “if” and “if” may be interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting.” Similarly, the phrases “if it is determined that ” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining ” or “in response to determining ” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event],” depending on the context.

[0258] It should be understood that determining B based on A does not mean determining B based solely on A. B can also be determined based on A and / or other information.

[0259] It should also be understood that references throughout this specification to "one embodiment," "an embodiment," or "one possible implementation" mean that specific features, structures, or characteristics associated with that embodiment or implementation are included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "one possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. A method for processing an instruction, characterized in that: The method comprises: Get the first instruction to be processed; determining a compression level of a memory in the memory structure according to a memory structure and a required rate for reading the first instruction, the memory structure being used to store the compressed first instruction; The first instruction is compressed using the compression level.

2. The method according to claim 1, characterized in that Before determining the compression level of the memory in the memory structure according to the memory structure and the required rate of reading the first instruction, the method further includes: Obtaining at least one of a path attribute of a read path of each memory included in the memory structure or a read efficiency of the memory structure, wherein the read path of the memory is a path connecting the memory and a read module, the read module being configured to read instructions stored in the memory and process the read instructions; A required rate for reading the first instruction is determined according to at least one of the path attribute or the read efficiency.

3. The method according to claim 1 or 2, characterized in that The determining, based on the memory structure and the required rate for reading the first instruction, a compression level of a memory in the memory structure, comprises: Determining a read rate of each memory included in the memory structure; determining a restoration rate of each memory according to a demand rate for reading the first instruction and a read rate of each memory, wherein the restoration rate of the memory is a rate at which instructions stored in the memory are decompressed on a read path of the memory; The compression level of each memory is determined according to the restoration rate of each memory, and the compression rate corresponding to the compression level of the memory matches the restoration rate corresponding to the memory.

4. The method according to any one of claims 1 to 3, characterized in that: The memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, and the restoration rate of the one-layer compression is higher than the restoration rate of the two-layer compression; The compressing the first instruction using the compression level includes: compressing the first instruction using the first-layer compression method to obtain a second instruction; The second instruction is compressed using the two-layer compression method to obtain a third instruction, and the compression rate of the two-layer compression method is greater than the compression rate of the one-layer compression method.

5. The method according to claim 4, characterized in that The ratio between the bit width of the first instruction and the bit width of the second instruction is equal to the compression ratio, and the compressing the first instruction using the compression method of the first layer of compression to obtain the second instruction further includes: Acquire a service characteristic of the first instruction, where the service characteristic indicates an operation quality requirement of a service executed based on the first instruction; The compression ratio is determined according to the service characteristics of the first instruction.

6. The method according to claim 4 or 5, characterized in that The compressing the first instruction using the first-layer compression method to obtain a second instruction includes: Acquiring an instruction feature of the first instruction; When it is determined based on the instruction characteristics that fixed-length compression is supported, the first instruction is compressed using fixed-length compression to obtain the second instruction; or, when it is determined based on the instruction characteristics that fixed-length compression is not supported, the first instruction is split into multiple second instructions, and the bit width of each second instruction in the multiple second instructions is the same.

7. The method according to claim 6, characterized in that The instruction feature includes at least one of an instruction type, a usage frequency, or a field utilization rate of the first instruction.

8. The method according to claim 6 or 7, characterized in that The compressing the first instruction by using a fixed-length compression method to obtain the second instruction includes: A valid field of the first instruction is determined, and a second instruction including the valid field is obtained, where the valid field is a field used to execute the first instruction.

9. The method according to any one of claims 4 to 8, characterized in that: The second instruction includes a compression flag bit, and the compression flag bit indicates that the second instruction is obtained by fixed-length compression or splitting.

10. The method according to any one of claims 4 to 9, characterized in that: The compressing the second instruction using the two-layer compression method to obtain a third instruction includes: Obtaining the occurrence frequency of each field included in the second instruction; A third instruction is obtained according to the frequency of occurrence of each field, wherein the third instruction includes the encoding of each field, the encoding of each field is determined based on the frequency of occurrence of each field, and the length of the encoding of each field is inversely proportional to the frequency of occurrence of each field.

11. The method according to claim 10, characterized in that Before acquiring the third instruction according to the occurrence frequency of each field, the method further includes: Building a coding dictionary corresponding to the second instruction according to the occurrence frequencies of the respective fields, the coding dictionary including the respective fields and the occurrence frequencies of the respective fields; The encoding of each field is determined according to the encoding dictionary.

12. The method according to claim 10 or 11, characterized in that The third instruction includes an encoding index, and the encoding index is used to find a field corresponding to the encoding included in the third instruction during the process of decompressing the third instruction.

13. The method according to any one of claims 1 to 12, characterized in that: After compressing the first instruction using the compression level, the method further includes: Obtaining the instruction length of the compressed first instruction; A storage unit in the memory structure for storing the compressed first instruction is determined according to the instruction length, and the compressed first instruction is stored in the determined storage unit.

14. The method according to any one of claims 1 to 13, characterized in that: The first instruction includes an instruction to forward an application program.

15. The method according to any one of claims 1 to 14, characterized in that: The obtaining of a first instruction to be processed includes: At least one instruction included in the instruction bundle is acquired, wherein any instruction in the at least one instruction is a first instruction to be processed, and the at least one instruction is an instruction to be executed in parallel.

16. A method for processing an instruction, characterized in that: The method comprises: Obtaining a compressed first instruction, wherein compression of the first instruction is implemented based on a compression level, wherein the compression level is determined based on a memory structure and a required rate of reading the first instruction, the memory structure being used to store the compressed first instruction; The compressed first instruction is restored.

17. The method according to claim 16, characterized in that The memory structure includes a storage module and a cache module, the compression level of the storage module is two-layer compression, the compression level of the cache module is one-layer compression, the restoration rate of the one-layer compression is higher than the restoration rate of the two-layer compression, and the compressed first instruction includes a third instruction; The restoring the compressed first instruction includes: Restoring the third instruction using a restoration method corresponding to the two-layer compression method to obtain a second instruction; The second instruction is restored using a restoration method corresponding to the compression method of the one-layer compression to obtain a first instruction, and the compression rate of the compression method of the two-layer compression is greater than the compression rate of the compression method of the one-layer compression.

18. The method according to claim 17, characterized in that The third instruction includes a coding index, and restoring the third instruction using a restoration method corresponding to the compression method of the two-layer compression to obtain the second instruction includes: Parsing the encoding index included in the third instruction; The fields corresponding to the codes included in the third instruction are determined according to the coding index, and the second instruction is determined according to the fields corresponding to the codes. The length of the code of each field is inversely proportional to the frequency of occurrence of each field.

19. The method according to claim 17 or 18, characterized in that The restoration method corresponding to the compression method of the first layer of compression includes decompression corresponding to fixed-length compression or splicing corresponding to splitting, and restoring the second instruction using the restoration method corresponding to the compression method of the first layer of compression to obtain the first instruction includes: In a case where the second instruction is obtained by fixed-length compression, decompressing the second instruction by performing the corresponding decompression operation on the fixed-length compression to obtain the first instruction; Alternatively, when the second instruction is obtained by splitting, multiple second instructions obtained by splitting the first instruction are spliced together to obtain the first instruction, and the bit widths of the multiple second instructions are the same.

20. The method according to claim 19, characterized in that The second instruction includes a compression flag bit, the compression flag bit indicating that the second instruction is obtained by fixed-length compression or splitting, and the second instruction is restored using a restoration method corresponding to the compression method of the first layer of compression, before obtaining the first instruction, further comprising: Parse the compression flag bit included in the second instruction, and determine a method for obtaining the second instruction from fixed-length compression and splitting according to the compression flag bit.

21. The method according to any one of claims 16 to 20, characterized in that: The obtaining of the compressed first instruction includes: fetching at least one instruction stored in a row of memory cells of the memory structure; The instructions in the at least one instruction are separated according to their instruction lengths to obtain the at least one instruction, where the at least one instruction includes the compressed first instruction.

22. The method according to any one of claims 16 to 21, characterized in that: After restoring the compressed first instruction, the method further includes: determining an instruction bundle corresponding to the first instruction, the instruction bundle including at least one instruction, compression results of the at least one instruction being stored in a same row of storage units of the memory structure, a compression result of any instruction among the compression results of the at least one instruction being the compressed first instruction, and the at least one instruction being an instruction executed in parallel; At least one instruction included in the instruction bundle is sent to a decoding module, and the decoding module is used to parse the at least one instruction.

23. The method according to any one of claims 16 to 22, characterized in that: The first instruction includes an instruction to forward an application program.

24. An instruction processing device, characterized in that: The device comprises: An acquisition module, configured to acquire a first instruction to be processed; a determining module, configured to determine a compression level of a memory in the memory structure according to the memory structure and a required rate for reading the first instruction, the memory structure being configured to store the compressed first instruction; A compression module is configured to compress the first instruction using the compression level.

25. An instruction processing device, characterized in that: The device comprises: an acquisition module configured to acquire a compressed first instruction, wherein compression of the first instruction is implemented based on a compression level, wherein the compression level is determined based on a memory structure and a required rate of reading the first instruction, wherein the memory structure is configured to store the compressed first instruction; A restoration module is used to restore the compressed first instruction.

26. An instruction processing device, characterized in that: The device includes a processor, which is used to load and execute at least one instruction, so that the instruction processing device implements the instruction processing method according to any one of claims 1 to 15, or implements the instruction processing method according to any one of claims 16 to 23.

27. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one instruction, which is loaded and executed by a processor to implement the instruction processing method according to any one of claims 1 to 15, or the instruction processing method according to any one of claims 16 to 23.

28. A chip, characterized in that: The chip includes a processor, which is used to run program instructions or codes, so that the device containing the chip executes the instruction processing method described in any one of claims 1-15, or executes the instruction processing method described in any one of claims 16-23.

29. A computer program product, characterized in that The computer program product includes a computer program / instructions, and the computer program / instructions are executed by a processor to enable a computer to execute the instruction processing method according to any one of claims 1 to 15, or the instruction processing method according to any one of claims 16 to 23.

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